JP2008177618A - Flexible wiring board, semiconductor device and electronic equipment using the wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flexible wiring board which can make a wiring pattern shape after etching more excellent than that of the conventional tape carrier for a COF semiconductor device, can make a connection state between the wiring pattern and a semiconductor element satisfactory, and can make the mechanical strength of the wiring pattern of an nonconnected part more improved than in the conventional types, and to provide a semiconductor device and electronic equipment that use the wiring board. <P>SOLUTION: A flexible wiring board is provided with an insulating tape 6 and a wiring pattern 57, formed on the insulating tape 6. The wiring pattern 57 is formed into a predetermined pattern and has a connecting part for connecting a semiconductor element 2 thereto, in a mounting region which the semiconductor element 2 is connected to and mounted on. Only the thickness of the wiring pattern 57 in the connection part is made thinner than that of a wiring layer in the nonconnected part. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a flexible wiring board, a semiconductor device and an electronic device using the same, and a method for manufacturing the flexible wiring board. More specifically, the present invention relates to a flexible wiring board on which a semiconductor element is mounted, a semiconductor device and an electronic device using the same, and a method for manufacturing the flexible wiring board.

  As a semiconductor device in which a semiconductor element is bonded and mounted on a flexible wiring board, there are TCP (Tape Carrier Package), COF (Chip On Film) and the like. Examples of the differences between TCP and COF include the following points.

  First, the TCP is provided with an opening for mounting a semiconductor element on an insulating tape in advance, and is formed in a state where the wiring pattern protrudes in a cantilever shape. It is joined. On the other hand, the COF is different in that it does not have an opening for mounting a semiconductor element, and the semiconductor element is bonded and mounted on a wiring pattern formed on the surface of a thin film insulating tape. .

  Further, since TCP has a wiring pattern protruding in a cantilever shape, the wiring pattern has a thickness of 18 μm or more, and it is difficult to manufacture a wiring pattern with a wiring pitch of less than 45 μm. In contrast, since COF forms a wiring pattern on the surface of a thin film insulating tape, the thickness of the wiring pattern can be 8 μm or less, and it is easy to manufacture a wiring pattern with a wiring pitch of 35 μm or less. There are some differences.

  In addition, a slit is provided in advance in a portion where the TCP is bent after being mounted on a liquid crystal panel or the like. On the other hand, the COF is different in that it does not have a bending slit and can be freely bent anywhere in the thin film insulating tape.

  Further, TCP is formed by laminating copper foil on an insulating tape made of polyimide using an adhesive. On the other hand, COF is formed by applying and curing polyimide or the like on the back surface of the copper foil (casting method), or by laminating copper on a thin film insulating tape made of polyimide or the like by sputtering (sputtering method, meta Rising method) is different.

  As the COF, a thin film insulating tape that can be bent freely from its intended use is used. In addition, each wiring of the wiring pattern arranged on the surface of the thin film insulating tape is electrically connected to a corresponding terminal of the semiconductor element, and the external connection connector portion is connected to a liquid crystal panel or a printed board. . The wiring pattern exposed portion other than the above is coated with a solder resist to ensure an insulating state.

  As described above, COF is a technique that facilitates the fine pitching (miniaturization) of the wiring pattern, but actually, the thickness of the wiring pattern is 8 to 18 μm according to the wiring pitch of 35 to 50 μm or more. in use. However, there is no patent document describing a technique related to the thickness of the wiring pattern. On the other hand, in the case of TCP, Patent Document 1 is cited as a document describing a technique related to the thickness of a wiring pattern.

  A conventional COF will be described with reference to FIGS. FIG. 11 is a cross-sectional view showing a schematic configuration of a conventional COF 101. FIG. 12 is a cross-sectional view illustrating a schematic configuration of the COF 101 when cut along the line C-C ′ illustrated in FIG. 11. As shown in FIGS. 11 and 12, the COF 101 has a configuration in which a semiconductor element 102 is connected and mounted on a tape carrier 103.

In the tape carrier 103 of the COF 101 shown in FIGS. 11 and 12, the wiring pattern 105 is formed on the insulating tape 104. The wiring pattern 105 is formed of a copper foil or sputtered copper having a thickness of 8 to 18 μm by a casting method or a sputtering method (metalizing method). As shown in FIGS. 11 and 12, the wiring pattern 105 is formed with the same thickness in all regions including a region where the semiconductor element 102 is connected and mounted and other regions.
Japanese Patent Laid-Open No. 10-32227 (published February 3, 1998)

  In Patent Document 1, the thickness of the wiring pattern of the opening portion for mounting the semiconductor element and the slit portion for bending is increased (26 μm) in order to increase the mechanical strength. The thickness of the wiring pattern of the (Outer Lead Bonding) portion is made thin (18 μm) in order to increase the top width of the wiring pattern and secure a connection area.

  However, in practice, the wiring pattern in the opening portion on which the semiconductor element is mounted has the finest pitch, and thus it is necessary to reduce the thickness of the wiring pattern. Further, even if all the portions are formed with the same thickness of 18 μm, there is no problem in mechanical strength, and a wiring pattern with a thickness of 18 μm is adopted in an actual mass-produced product. That is, the technique described in Patent Document 1 is not realistic and is not necessary. As described above, in actual TCP, it is difficult to make the wiring pattern fine pitch.

  On the other hand, compared with TCP, COF makes it easy to make finer wiring patterns (inner leads). As for the wiring pitch of the wiring pattern (inner leads) in mass production, the limit of TCP is 45 μm, whereas 35 μm of COF is mass-produced, and it is considered that 30 μm or less is possible.

  However, according to the inventor's investigation, the following problems have been found when the COF is fine pitch.

  For example, as one of the problems when making the fine pitch of COF, when the wiring pattern (inner leads) is made finer, especially when the wiring pitch is 30 μm or less, the wiring pattern thickness is 8 μm at present. It may be difficult to pattern-etch the pattern (inner lead) into a good shape.

  That is, with the fine pitch of the wiring pattern (inner leads), it is necessary to reduce the width of the wiring pattern (inner leads), and it becomes difficult to perform pattern etching into a trapezoid having a good cross-sectional shape of the wiring pattern. For this reason, the cross-sectional shape of the wiring pattern becomes a cross-sectional shape closer to a triangle, and the thickness variation of the wiring pattern (inner lead) may increase.

  This point will be specifically described with reference to FIG. FIG. 13 shows a fine pitch of the wiring pattern 105 of the conventional COF 101 shown in FIGS. 11 and 12. For example, when the wiring pitch exceeds 35 μm, there is almost no problem. However, when the wiring pitch is less than 35 μm, it becomes difficult to perform an etching process so that the wiring pattern 105 has a trapezoidal shape having a good cross-sectional shape. In this case, as shown in FIG. 13, the cross-sectional shape of the wiring pattern 105 is closer to a triangle. Further, it can be seen that the thickness variation of the wiring pattern 105 after the etching process is increased, and the connection state between the semiconductor element 102 and the wiring pattern 105 is deteriorated.

  As a method for solving this, there is a thin film of copper foil or sputtered copper (wiring pattern). If the thickness of the copper foil or sputtered copper (wiring pattern) is reduced, it becomes possible to pattern-etch the wiring pattern into a good shape. For example, even when the wiring pitch of the wiring pattern (inner lead) is 30 μm, if the thickness of the copper foil or sputtered copper (wiring pattern) is reduced to about 5 μm, the wiring pattern is pattern-etched into a trapezoid having a good cross-sectional shape. It becomes easy.

  However, there is a problem that the mechanical strength of the wiring pattern is reduced due to the thinning of the wiring pattern accompanying the fine pitch of the wiring pattern (inner leads). For this reason, the wiring pattern may be disconnected or separated between the connection / mounting process of the semiconductor element and the module mounting process of the COF semiconductor device.

  This point will be specifically described with reference to FIGS. 14 and 15. FIG. 14 shows a thinned copper foil or sputtered copper for forming the wiring pattern 105 of the conventional COF 101 shown in FIGS. FIG. 15 is a cross-sectional view showing a schematic configuration of the COF 101 when cut along the line D-D ′ shown in FIG. 14. As shown in FIGS. 14 and 15, if the thickness of the copper foil or sputtered copper is reduced, the wiring pattern can be etched to have a good cross-sectional shape. However, since the mechanical strength of the wiring pattern is reduced, disconnection or peeling of the wiring pattern is likely to occur between the connection / mounting process of the semiconductor element to the module mounting process.

  Currently, as one of the requirements for COF, there is a response to the increase in the number of pins. Another requirement is a reduction in size and thickness. In order to satisfy these requirements at the same time, it is necessary to reduce the fine pitch of the connection portion with the semiconductor element and the connector portion for external connection of the wiring pattern, and to reduce the thickness of the insulating tape, the wiring pattern, and the like. For this purpose, it is necessary to reduce the width and thickness of the wiring pattern (inner lead). However, while COF can be bent freely, it is necessary to improve the mechanical strength as the wiring pattern becomes thinner. As described above, it is difficult to achieve fine pitch with the conventional technology. have.

  The present invention solves the above-described problems, and can improve the shape of a wiring pattern after etching as compared with a conventional tape carrier for a COF type semiconductor device. The connection state with the element can be made good, and the mechanical strength of the wiring pattern at the non-connection part can be improved as compared with the conventional one. It is an object of the present invention to provide a flexible wiring board that can be reduced to 50% or less of the above, and a positional deviation that occurs when connected to a semiconductor element, and a semiconductor device and an electronic apparatus using the flexible wiring board.

  In order to solve the above problems, a flexible wiring board according to the present invention is a flexible wiring board including an insulating layer and a wiring layer formed on the insulating layer. The wiring layer is formed in a predetermined pattern. And a connecting portion for connecting to the electronic component in the mounting area for connecting and mounting the electronic component, and only the thickness of the wiring layer of only the connecting portion is It is characterized by being thinner than the thickness of the wiring layer.

  According to said structure, the wiring layer is formed in the predetermined pattern, and has a some wiring by this. The predetermined pattern is a pattern composed of a plurality of wirings arbitrarily determined according to the usage of the flexible wiring board. In addition, the plurality of wirings in the wiring layer have connection portions for connecting to electronic components. This connecting portion is provided in a mounting area for connecting and mounting electronic components. That is, the wiring layer has a mounting area as an area where electronic components are mounted, and has a configuration having a connection portion connected to the electronic components in the mounting area. In the wiring layer formed on the insulating layer, the thickness of the wiring layer in the connection portion is thinner than the thickness of the wiring layer in the non-connection portion. For this reason, the process of a connection part becomes easy. Note that the non-connection portion is a region other than the connection portion in the wiring layer.

  Therefore, for example, when etching a wiring, the wiring can be etched to have a favorable shape, and variations in the thickness of each wiring can be reduced. For this reason, it is possible to make the pattern of the wiring layer finer (fine pitch).

  Moreover, since the thickness of the wiring layer in the non-connection portion is thicker than the thickness of the wiring layer in the connection portion, the mechanical strength of the wiring layer can be improved. For this reason, even when the flexible wiring board is bent, the wiring layer pattern can be prevented from being disconnected or peeled off.

  In the flexible wiring board according to the present invention, it is preferable that the wiring layer has the same thickness of the non-connection portion in the mounting region as that of the non-connection portion in the non-mounting region. According to the above configuration, since the non-connection portion has the same thickness over the entire region, the mechanical strength of the wiring layer can be further improved, and even when the flexible wiring board is bent, the pattern It is possible to prevent disconnection or peeling.

  The flexible wiring board according to the present invention is more effective when the interval between at least one pair of adjacent wirings in the pattern is less than 35 μm. According to said structure, the fine pitch of the pattern of a wiring layer is attained.

  In the flexible wiring board according to the present invention, it is preferable that the thickness of the wiring layer in the mounting region or the connection portion is in the range of 3 to 6 μm. According to said structure, even if it is a case where the wiring of a mounting area | region or a connection part is etched, it becomes possible to etch so that a cross section may become a favorable shape. In addition, it is possible to reduce the thickness variation of each wiring of the pattern, and to improve the connection state with the electronic component.

  In the flexible wiring board according to the present invention, the thickness of the wiring layer in the non-mounting region or the non-connecting portion is preferably 8 μm or more. According to said structure, since the mechanical strength of a wiring layer can be improved, it becomes possible to prevent generation | occurrence | production of the disconnection of a pattern, or peeling even when the flexible wiring board is bent.

  In the flexible wiring board according to the present invention, the connection portion is an inner lead portion. According to said structure, it has a connection part in a mounting area | region, While being able to make a connection state with an electronic component favorable, the mechanical strength of a wiring layer can be improved.

  In order to solve the above problems, a semiconductor device according to the present invention includes any one of the flexible wiring boards described above and a semiconductor element connected to a connection portion of the flexible wiring board. According to the above configuration, a fine pitch of wiring can be achieved and a semiconductor device with improved mechanical strength can be obtained.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the semiconductor device. According to said structure, while being able to make fine pitch of wiring, it can be set as the electronic device which improved mechanical strength.

  As described above, in the flexible wiring board according to the present invention, the wiring layer is formed in a predetermined pattern and has a mounting area for connecting and mounting an electronic component. The thickness is smaller than the thickness of the wiring layer in the non-mounting area. In addition, as described above, the method for manufacturing a flexible wiring board according to the present invention includes a wiring layer forming step of forming a wiring layer on the insulating layer, and a pattern forming step of forming the wiring layer in a predetermined pattern. The method for producing a flexible wiring board further includes a thinning step for reducing the thickness of the wiring layer connected to the electronic component. In addition, as described above, the method for manufacturing a flexible wiring board according to the present invention includes a wiring layer forming step of forming a wiring layer on the insulating layer, and a pattern forming step of forming the wiring layer in a predetermined pattern. In the method for manufacturing a flexible wiring board, the wiring layer forming step includes a first wiring layer forming step for forming the first wiring layer and a first wiring layer other than a portion where the first wiring layer and the electronic component are connected. And a second wiring layer forming step of forming a second wiring layer. For this reason, it is possible to reduce the fineness (fine pitch) and improve the mechanical strength of the wiring layer by improving the etching shape of the wiring layer pattern and the connection state with the electronic component. Also, it is possible to prevent connection failure and to prevent the wiring layer pattern from being disconnected or peeled when the flexible wiring board is bent.

[Reference Form 1]
Reference Embodiment 1 of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the present embodiment. 2 is a cross-sectional view showing a schematic configuration of the semiconductor device when cut along the line AA ′ shown in FIG.

  As shown in FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor element (electronic component) 2 and a tape carrier (flexible wiring board) 3. The semiconductor element 2 is connected to the tape carrier 3 and is mounted on the tape carrier 3. An insulating resin 4 is sealed in a gap existing between the tape carrier 3 and the semiconductor element 2. As described above, in this embodiment, a COF type semiconductor device in which the semiconductor element 2 is mounted on the tape carrier 3 will be described as an example.

  Examples of the semiconductor element 2 include an integrated circuit (LSI: Large Scaled Integrated circuit) such as a CPU (Central Processing Unit) and a memory. The semiconductor element 2 is provided with a plurality of protruding electrodes 5.

  The protruding electrode 5 is an electrode protruding in a substantially vertical direction from the surface facing the tape carrier 3 when the semiconductor element 2 is mounted on the tape carrier 3, and electrically connects the semiconductor element 2 and the tape carrier 3. It is an electrode used for connection. For this reason, the protruding electrode 5 should just consist of an electroconductive material, and the shape is not limited. However, a shape that facilitates connection with the tape carrier 3 is preferable. As the protruding electrode 5, for example, a cylindrical, prismatic, or ball-shaped electrode made of Au or solder can be used.

  The tape carrier 3 is for connecting and mounting the semiconductor element 2 and includes an insulating tape (insulating layer) 6, a wiring pattern (wiring layer, pattern) 7, and a solder resist 8.

  The insulating tape 6 is a base material for arranging the wiring pattern 7 on the surface. Since the insulating tape 6 is used in various shapes as well as having an insulating property, the insulating tape 6 needs to have high flexibility (flexibility) that can be bent freely. For this reason, as a material for forming the insulating tape 6, for example, a resin material such as polyimide, glass epoxy, or polyester is used. In this reference embodiment, the insulating tape 6 using a polyimide resin will be described as an example.

  The insulating tape 6 is preferably a thin-film tape-like base material in order to facilitate bending and to make the semiconductor device 1 smaller and thinner. The thickness of the insulating tape 6 may be appropriately set according to the purpose of use, but is preferably in the range of 15 to 40 μm, for example.

  The wiring pattern 7 is a wiring formed in a pattern on the surface of the insulating tape 6. The wiring pattern 7 is formed by forming copper foil or sputtered copper (hereinafter simply referred to as “copper foil”) on the insulating tape 6 by a casting method or a sputtering method (metalizing method), and the copper foil is formed into a desired pattern. It is formed by etching. In this reference embodiment, copper will be described as an example of the material used for the wiring pattern 7, but the present invention is not limited to this, and a conductive metal such as silver can be used.

  In order to connect the semiconductor device 1 to other electronic components, the wiring pattern 7 is provided with an external connection terminal (not shown). The surface of the wiring pattern 7 is subjected to tin plating or gold plating (not shown). The detailed configuration of the wiring pattern 7 will be described later.

  The solder resist 8 is a resist formed on the wiring pattern 7. The solder resist 8 is made of, for example, a heat-resistant coating material, and prevents exposure of parts other than the connection part. Therefore, the solder resist 8 is formed on the wiring pattern 7 in a portion other than the region where the semiconductor element 2 is mounted or a portion where no external connection terminal is provided. That is, the solder resist 8 is formed on the wiring pattern 7 that is exposed when the semiconductor element 2 or the like is connected and mounted on the tape carrier 3.

  The insulating tape 6 is not provided with an opening for mounting the semiconductor element 2. For this reason, the semiconductor element 2 is connected and mounted on the insulating tape 6 by bonding the protruding electrode 5 provided on the semiconductor element 2 and the wiring pattern 7 formed on the surface of the insulating tape 6. That is, this connection is performed by connecting each wiring of the wiring pattern 7 disposed on the surface of the insulating tape 6 and the protruding electrode 5 of the semiconductor element 2 corresponding to each wiring. Thereby, the wiring pattern 7 and the semiconductor element 2 are electrically connected.

  The wiring pattern 7 is partially different in thickness. Specifically, the thickness of the region (mounting region; connection part) where the semiconductor element 2 is connected / mounted in the wiring pattern 7 is larger than the thickness of the region (non-mounted region) where the semiconductor element 2 is not connected / mounted. It is getting thinner. As a result, the wiring pattern 7 can be fine pitched in the mounting area, the mechanical strength of the wiring pattern 7 can be improved in the non-mounting area, and the strength of the semiconductor device 1 is also improved.

  The mounting area is an area where the wiring pattern 7 and the semiconductor element 2 are connected and mounted. That is, the mounting region indicates a portion where the protruding electrode 5 and the wiring pattern 7 are connected, but indicates a region occupied by the semiconductor element 2 when the semiconductor element 2 is mounted on the tape carrier 3. Accordingly, the wiring pattern 7 connected to the semiconductor element 2 in the mounting region is a so-called inner lead. In addition, the non-mounting area is an area other than the mounting area.

  Further, the connection portion indicates a portion of the wiring pattern 7 that is actually connected to the semiconductor element 2, and the non-connection portion is a region other than the connection portion. In this reference embodiment, the connection portion is included in the mounting area.

  The thickness of the wiring pattern 7 in the mounting region is preferably in the range of 3 to 6 μm, for example. When the thickness of the wiring pattern 7 is less than 3 μm, a problem that the protruding electrode 5 comes into contact with the surface of the insulating tape 6 may occur. Moreover, when the thickness of the wiring pattern 7 exceeds 6 μm, it becomes difficult to improve the shape of the wiring pattern 7 by etching and the connection state with the semiconductor element 2.

  However, the thickness of the wiring pattern 7 in the mounting region is not limited to the above thickness. That is, the thickness of the wiring pattern 7 in the mounting area is a thickness for enabling the wiring pattern 7 to have a fine pitch, that is, a thickness for enabling the wiring pattern 7 to have a favorable shape by pattern etching. Any thickness may be used as long as the protruding electrode 5 does not come into contact with the insulating tape 6.

  The wiring pattern 7 is more effective when the wiring pitch, which is the interval between the wirings, is less than 35 μm. When the wiring pitch is less than 35 μm, a so-called fine pitch tape carrier 3 can be obtained.

  The semiconductor device 1 may be a semiconductor module (electronic device) 9 by connecting to another electronic component. In the semiconductor module 9, for example, the semiconductor device 1 can drive and control other electronic components. FIG. 3 is a cross-sectional view showing a schematic configuration of the semiconductor module 9 in the present embodiment. FIG. 3 shows a case where the semiconductor device 1 is used for a liquid crystal display device. In this case, examples of the other electronic components include the liquid crystal panel 10 and other printed boards 11. In the semiconductor module 9, the external connection terminal of the wiring pattern 7 in the semiconductor device 1 is connected to the liquid crystal panel 10, other printed circuit board 11, and the like.

  Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described with reference to FIG. FIG. 4 is a cross-sectional view illustrating a schematic configuration of the method for manufacturing the semiconductor device 1. The manufacturing method of the semiconductor device 1 in the present embodiment is such that the thickness of the copper foil in the mounting region is not mounted by half etching before the wiring pattern 7 is formed by etching the copper foil formed on the surface of the insulating tape 6. This is a method of making the area thinner than the thickness of the copper foil.

  First, as shown in FIG. 4A, a copper foil (wiring layer) 12 is formed on the surface of the insulating tape 6 by a casting method or a sputtering method (metalizing method) so as to have a thickness of 8 to 18 μm. To do. Here, the casting method is a method of curing after applying polyimide to a copper foil. On the other hand, the sputtering method (metalizing method) is a method in which a metal seed layer is formed by sputtering on a film such as polyimide or Kapton, and then copper plating is deposited on the metal seed layer by electroplating, and the copper plating is stacked. is there.

  Next, as shown in FIG. 4B, the surface of the copper foil 12 corresponding to the mounting region is etched. This etching process is performed so that the thickness of the copper foil 12 in the mounting region is thinner than the thickness of the copper foil 12 in the non-mounting region. In the following, this etching process is sometimes referred to as half etching.

  Half etching is performed by adjusting the temperature, time, speed, etc., for example, using a tape surface coating device so that the thickness of the copper foil 12 in the mounting region becomes a desired thickness. Can be controlled.

  And as shown in FIG.4 (c), the etching process with respect to the copper foil 12 is performed so that the copper foil 12 may become a predetermined pattern, and the desired wiring pattern 7 is formed. The wiring pattern 7 is formed in all regions where the wiring pattern 7 in the mounting region and the non-mounting region is to be formed. Thereafter, as shown in FIG. 4D, a solder resist 8 is applied on the wiring pattern 7 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 3 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 3 manufactured as described above. This connection is performed by arranging the semiconductor element 2 and the tape carrier 3 so that the protruding electrode 5 and the wiring pattern 7 correspond to each other and connecting the protruding electrode 5 and the wiring pattern 7. This connection can be performed by, for example, Au—Sn eutectic bonding. As a result, the semiconductor element 2 is connected and mounted on the tape carrier 3.

  After the semiconductor element 2 is connected and mounted on the tape carrier 3, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 3. By injecting and sealing the insulating resin 4, it is possible to ensure an insulation state from the outside at the connection portion between the semiconductor element 2 and the wiring pattern 7. Thereby, the semiconductor device 1 of the present embodiment is manufactured.

  When the semiconductor device 1 is connected to other electronic components, for example, a liquid crystal panel or a printed board may be connected to the external connection terminals of the wiring pattern 7.

  As described above, in the tape carrier 3 for the COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 7 in the mounting region is thinner than the thickness of the wiring pattern 7 in the non-mounting region. In particular, the thickness of the wiring pattern 7 in the non-mounting area is 8 to 18 μm, whereas the thickness of the wiring pattern 7 in the mounting area is 3 to 6 μm.

  Thereby, the shape of the wiring pattern 7 after etching can be improved and the connection state between the wiring pattern 7 and the semiconductor element 2 can be improved as compared with the tape carrier for the conventional COF type semiconductor device. can do. In addition, the mechanical strength of the wiring pattern 7 in the non-mounting region can be improved as compared with the conventional case, and defects due to disconnection or peeling of the wiring pattern 7 can be reduced to 50% or less of the conventional case.

[Reference form 2]
The second embodiment of the present invention will be described with reference to FIGS. 1 to 3 and FIG. FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the present embodiment. 2 is a cross-sectional view showing a schematic configuration of the semiconductor device when cut along the line AA ′ shown in FIG.

  As shown in FIG. 1, the semiconductor device 1 includes a semiconductor element 2 and a tape carrier 3. In this embodiment, the manufacturing method of the semiconductor device 1 is different from that of the embodiment 1, and the configuration of the semiconductor device 1 is the same. For this reason, the members described in Reference Embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a method for manufacturing the semiconductor device 1 will be mainly described. Unless otherwise specified, terms used in the present reference form also have the same meaning as in the first reference form.

  Here, the manufacturing method of the semiconductor device 1 in the present embodiment will be specifically described with reference to FIG. FIG. 5 is a cross-sectional view illustrating a schematic configuration of a method for manufacturing the semiconductor device 1 according to the present embodiment.

  In the manufacturing method of the semiconductor device 1 according to the present embodiment, after the wiring pattern 7 is formed by etching the copper foil formed on the surface of the insulating tape 6, the thickness of the copper foil in the mounting region is reduced by half etching. It is the method of making it thinner than the thickness of copper foil.

  First, as shown in FIG. 5A, a copper foil 12 is formed on the surface of the insulating tape 6 so as to have a thickness of 8 to 18 μm by a casting method or a sputtering method (metalizing method).

  Next, as shown in FIG. 5B, the copper foil 12 is etched so that the copper foil 12 has a predetermined pattern, and a desired wiring pattern 7 is formed. The wiring pattern 7 is formed in all regions where the wiring pattern 7 in the mounting region and the non-mounting region is to be formed.

  Then, as shown in FIG. 5C, the surface of the wiring pattern 7 corresponding to the mounting area is etched. This etching process is performed by half etching. That is, the thickness of the wiring pattern 7 in the mounting area is made smaller than the thickness of the wiring pattern 7 in the non-mounting area. Thereafter, as shown in FIG. 5D, a solder resist 8 is applied on the wiring pattern 7 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 3 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 3 in the same manner as in the first embodiment. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 3, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 3. Thereby, the semiconductor device 1 of the present embodiment is manufactured.

  When the semiconductor device 1 is connected to other electronic components to form the semiconductor module 9, as shown in FIG. 3, for example, a liquid crystal panel 10 or a printed board 11 is connected to an external connection terminal of the wiring pattern 7. Etc. may be connected.

  As described above, in the tape carrier 3 for the COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 7 in the mounting region is thinner than the thickness of the wiring pattern 7 in the non-mounting region. In particular, the thickness of the wiring pattern 7 in the non-mounting area is 8 to 18 μm, whereas the thickness of the wiring pattern 7 in the mounting area is 3 to 6 μm.

  Thereby, the shape of the wiring pattern 7 after etching can be improved and the connection state between the wiring pattern 7 and the semiconductor element 2 can be improved as compared with the tape carrier for the conventional COF type semiconductor device. can do. In addition, the mechanical strength of the wiring pattern 7 in the non-mounting region can be improved as compared with the conventional case, and defects due to disconnection or peeling of the wiring pattern 7 can be reduced to 50% or less of the conventional case.

  Further, in the tape carrier 3 in the present embodiment, after the wiring pattern 7 is formed by etching, the thickness of the wiring pattern 7 in the mounting region is reduced by half etching. For this reason, compared with the tape carrier 3 of the reference form 1, it becomes possible to make the thickness of the wiring pattern 7 in the mounting region more uniform.

[Reference form 3]
The third embodiment of the present invention will be described below with reference to FIGS. FIG. 6 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment. FIG. 7 is a cross-sectional view showing a schematic configuration of the semiconductor device when cut along the line BB ′ shown in FIG.

  As shown in FIGS. 6 and 7, the semiconductor device 21 includes a semiconductor element 2 and a tape carrier (flexible wiring board) 23. The semiconductor element 2 is connected to the tape carrier 23 and is mounted on the tape carrier 23. An insulating resin 4 is sealed in a gap that exists between the tape carrier 23 and the semiconductor element 2. Also in this reference embodiment, a COF type semiconductor device in which the semiconductor element 2 is mounted on the tape carrier 23 will be described as an example. In addition, about the member same as the member demonstrated in the reference forms 1 and 2, the same code | symbol is attached | subjected and the description is abbreviate | omitted. Further, the terms used in the present embodiment are the same as those in the embodiment 1 unless otherwise specified.

  The semiconductor element 2 is provided with a plurality of protruding electrodes 5. The tape carrier 23 is for connecting and mounting the semiconductor element 2 and includes an insulating tape 6, a wiring pattern (wiring layer, pattern) 27, and a solder resist 8.

  The wiring pattern 27 is a wiring formed in a pattern on the surface of the insulating tape 6. As the wiring pattern 27, copper foil or sputtered copper (hereinafter simply referred to as “copper foil”) is formed on the insulating tape 6 by a casting method or a sputtering method (metalizing method), and this copper foil is formed into a desired pattern. It is formed by etching. In the reference embodiment, copper is taken as an example of the material used for the wiring pattern 7, but the material is not limited to this. For example, a conductive metal such as silver can be used.

  The wiring pattern 27 includes a first wiring layer 27a and a second wiring layer 27b. The first wiring layer 27a is a layer made of copper foil provided on the insulating tape 6, and the second wiring layer 27b is a layer made of copper foil provided on the first wiring layer 27a.

  The second wiring layer 27b is provided in a part on the first wiring layer 27a. In the present embodiment, the second wiring layer 27b is provided in a non-mounting area on the first wiring layer 27a. That is, the thickness of the wiring pattern 27 in the non-mounting area is larger than the thickness of the wiring pattern 27 in the mounting area. Thereby, the fine pitch of the wiring pattern 27 can be achieved by controlling the thickness of the first wiring layer 27a. In addition, the mechanical strength of the wiring pattern 27 can be improved by controlling the thickness of the second wiring layer 27b.

  The thickness of the first wiring layer 27a is preferably in the range of 3 to 6 μm, for example. When the thickness of the first wiring layer 27a is less than 3 μm, a problem that the protruding electrode 5 comes into contact with the surface of the insulating tape 6 may occur. Further, when the thickness of the first wiring layer 27a exceeds 6 μm, it becomes difficult to make the shape of the wiring pattern 27 by etching and to make the connection state with the semiconductor element 2 good.

  Further, the thickness of the second wiring layer 27b may be appropriately set according to the thickness of the first wiring layer 27a. For example, when the thickness of the first wiring layer 27a is in the range of 3 to 6 μm, the thickness of the second wiring layer 27b is within the range of 8 to 18 μm in total with the thickness of the first wiring layer 27a. It is preferable that the thickness is as follows.

  However, the thickness of the first wiring layer 27a is not limited to the above thickness. That is, the thickness of the first wiring layer 27a is a thickness for enabling the wiring pattern 27 to have a fine pitch, that is, a thickness for enabling the wiring pattern 27 to have a good shape by pattern etching. Any thickness may be used as long as the protruding electrode 5 does not contact the insulating tape 6.

  Further, the thickness of the second wiring layer 27b is not limited to the above thickness, and the thickness is sufficient to obtain sufficient mechanical strength by the total thickness of the first wiring layer 27a and the second wiring layer 27b. I just need it.

  The wiring pattern 27 is more effective when the wiring pitch that is the interval between the wirings is less than 35 μm. When the wiring pitch is less than 35 μm, a so-called fine pitch tape carrier 23 can be obtained.

  Note that an external connection terminal (not shown) is provided on the wiring pattern 27 in order to connect the semiconductor device 21 to other electronic components. The surface of the wiring pattern 27 is subjected to tin plating or gold plating (not shown).

  The insulating tape 6 is not provided with an opening for mounting the semiconductor element 21. For this reason, the semiconductor element 21 is connected to and mounted on the insulating tape 6 by bonding the protruding electrode 5 provided on the semiconductor element 21 and the wiring pattern 27 formed on the surface of the insulating tape 6. That is, this connection is performed by connecting each wiring of the wiring pattern 27 arranged on the surface of the insulating tape 6 and the protruding electrode 5 of the semiconductor element 21 corresponding to each wiring. Thereby, the wiring pattern 27 and the semiconductor element 21 are electrically connected.

  The semiconductor device 21 may be a semiconductor module (electronic device) 29 by connecting to another electronic component. In the semiconductor module 29, for example, the semiconductor device 21 can drive and control other electronic components. FIG. 8 is a cross-sectional view showing a schematic configuration of the semiconductor module 29 in the present embodiment. FIG. 8 shows a case where the semiconductor device 21 is used for a liquid crystal display device. In this case, examples of the other electronic components include the liquid crystal panel 10 and other printed boards 11. In the semiconductor module 29, the external connection terminal of the wiring pattern 27 in the semiconductor device 21 is connected to the liquid crystal panel 10, the other printed circuit board 11, and the like.

  Next, a method for manufacturing the semiconductor device 21 having the above configuration will be described with reference to FIG. FIG. 9 is a cross-sectional view illustrating a schematic configuration of a method for manufacturing the semiconductor device 21. In the manufacturing method of the semiconductor device 21 in the present embodiment, before the wiring pattern 27 is formed by etching the copper foil formed on the surface of the insulating tape 6, the thickness of the copper foil in the non-mounting region is determined by electroplating or the like. This is a method in which the thickness of the mounting area is greater than that of the copper foil.

  First, as shown in FIG. 9A, the first copper foil layer 32 is formed on the surface of the insulating tape 6 so as to have a thickness of 3 to 6 μm by a casting method or a sputtering method (metalizing method). . Then, as shown in FIG. 9B, a second copper foil layer 33 is further formed on the portion of the first copper foil layer 32 corresponding to the non-mounting region.

  The second copper foil layer 33 is formed, for example, by depositing copper plating by electroplating and stacking on the first copper foil layer 32. Thereby, the thickness of the copper foil of a mounting area | region and a non-mounting area | region can be varied. Moreover, when forming the 2nd copper foil layer 33 by electroplating, the thickness of the 2nd copper foil layer 33 is arbitrarily controllable. For this reason, according to the thickness of the 1st copper foil layer 32, it becomes possible to change the thickness of the 2nd copper foil layer 33 suitably. Therefore, for example, it is also easy to form the second copper foil layer 33 so that the total thickness of the first copper foil layer 32 and the second copper foil layer 33 is 8 to 18 μm.

  And as shown in FIG.9 (c), the etching process with respect to the 1st copper foil layer 32 and the 2nd copper foil layer 33 so that the 1st copper foil layer 32 and the 2nd copper foil layer 33 may become a predetermined pattern. The desired wiring pattern 27 is formed. Thereby, the wiring pattern 27 composed of the first wiring layer 27a and the second wiring layer 27b is formed. The wiring pattern 27 is formed in all regions where the wiring pattern 27 in the mounting region and the non-mounting region is to be formed.

  Thereafter, as shown in FIG. 9D, the solder resist 8 is applied on the wiring pattern 27 in a portion exposed when the semiconductor element 22 is mounted in a later step. Thereby, the tape carrier 23 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 23 manufactured as described above. This connection is performed by arranging the semiconductor element 2 and the tape carrier 23 so that the protruding electrode 5 and the wiring pattern 27 correspond to each other and connecting the protruding electrode 5 and the wiring pattern 27. This connection can be performed by, for example, Au—Sn eutectic bonding. Thereby, the semiconductor element 22 is connected and mounted on the tape carrier 23.

  After the semiconductor element 2 is connected and mounted on the tape carrier 23, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 23. By injecting and sealing the insulating resin 4, it is possible to ensure an insulation state from the outside at the connection portion between the semiconductor element 2 and the wiring pattern 27. Thereby, the semiconductor device 21 of the present embodiment is manufactured.

  When the semiconductor device 21 is connected to other electronic components, for example, a liquid crystal panel or a printed board may be connected to the external connection terminal of the wiring pattern 27.

  As described above, in the tape carrier 23 for the COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 27 in the non-mounting area is larger than the thickness of the wiring pattern 7 in the mounting area. In particular, the thickness of the wiring pattern 27 in the mounting area is 3 to 6 μm, whereas the thickness of the wiring pattern 27 in the non-mounting area is 8 to 18 μm.

  As a result, the shape of the wiring pattern 27 after etching can be improved and the connection state between the wiring pattern 27 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, the mechanical strength of the wiring pattern 27 in the non-mounting region can be improved as compared with the conventional case, and defects due to disconnection or peeling of the wiring pattern 27 can be reduced to 50% or less of the conventional case.

[Reference form 4]
Reference embodiment 4 of the present invention will be described below with reference to FIGS. 6 to 8 and FIG. FIG. 6 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment. FIG. 7 is a cross-sectional view showing a schematic configuration of the semiconductor device when cut along the line BB ′ shown in FIG.

  As shown in FIG. 6, the semiconductor device 21 includes a semiconductor element 2 and a tape carrier 23. In the present embodiment, the manufacturing method of the semiconductor device 21 is different from that of the above embodiment 3, and the configuration of the semiconductor device 21 is the same. For this reason, the members described in the reference embodiment 3 are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a method for manufacturing the semiconductor device 21 will be mainly described. Unless otherwise specified, terms used in the present reference form also have the same meaning as in the third embodiment.

  Here, the manufacturing method of the semiconductor device 21 in the present embodiment will be specifically described with reference to FIG. FIG. 10 is a cross-sectional view showing a schematic configuration of a method for manufacturing the semiconductor device 21 according to the present embodiment.

  In the manufacturing method of the semiconductor device 21 of the present embodiment, after the wiring pattern 27 is formed by etching the copper foil formed on the surface of the insulating tape 6, the thickness of the copper foil in the non-mounting region is mounted by electroplating or the like. This is a method of making the area thicker than the thickness of the copper foil in the region.

  First, as shown in FIG. 10A, the first copper foil layer 32 is formed on the surface of the insulating tape 6 by a casting method or a sputtering method (metalizing method) so as to have a thickness of 3 to 6 μm. .

  Next, as shown in FIG. 10B, the first copper foil layer 32 is etched so that the first copper foil layer 32 has a predetermined pattern, and the first wiring layer 27a having a desired pattern is formed. Form. The first wiring layer 27a is formed in all regions where the wiring pattern 27 in the mounting region and the non-mounting region is to be formed.

  Then, as shown in FIG. 10C, a copper foil is further stacked on the first wiring layer 27a corresponding to the non-mounting region to form the second wiring layer 27b. Thereby, the wiring pattern 27 composed of the first wiring layer 27a and the second wiring layer 27b etched into a desired pattern shape is formed. The second wiring layer 27b is formed, for example, by depositing copper plating by electroplating and stacking on the first wiring layer 27a.

  Thereby, the thickness of the wiring pattern 27 can be varied between the mounting area and the non-mounting area. Further, when the second wiring layer 27b is formed by electroplating, the thickness of the second wiring layer 27b can be arbitrarily controlled. For this reason, the thickness of the second wiring layer 27b can be appropriately changed according to the thickness of the first wiring layer 27a. Therefore, for example, the second wiring layer 27b can be easily formed so that the total thickness of the first wiring layer 27a and the second wiring layer 27b is 8 to 18 μm.

  Thereafter, as shown in FIG. 10 (d) 2, a solder resist 8 is applied on the wiring pattern 27 in a portion exposed when the semiconductor element is mounted in a later step. Thereby, the tape carrier 23 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 23 in the same manner as in the above Reference Mode 3. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 23, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 23. Thereby, the semiconductor device 21 of the present embodiment is manufactured.

  As in the case of the third embodiment, when the semiconductor device 21 is connected to other electronic components to form a semiconductor module, as shown in FIG. What is necessary is just to connect the panel 10, the printed circuit board 11, etc. FIG.

  As described above, in the tape carrier 23 for the COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 27 in the non-mounting area is larger than the thickness of the wiring pattern 27 in the mounting area. In particular, the thickness of the wiring pattern 27 in the mounting area is 3 to 6 μm, whereas the thickness of the wiring pattern 27 in the non-mounting area is 8 to 18 μm.

  As a result, the shape of the wiring pattern 27 after etching can be improved and the connection state between the wiring pattern 27 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, the mechanical strength of the wiring pattern 27 in the non-mounting region can be improved as compared with the conventional case, and defects due to disconnection or peeling of the wiring pattern 27 can be reduced to 50% or less of the conventional case.

[Embodiment 1]
The following describes the first embodiment of the present invention with reference to FIGS. FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment.

  As shown in FIG. 16, the semiconductor device 51 includes a semiconductor element 2 and a tape carrier (flexible substrate) 53. The semiconductor element 2 is connected to the tape carrier 53 and is mounted on the tape carrier 53. An insulating resin 4 is sealed in a gap that exists between the tape carrier 53 and the semiconductor element 2. Also in this embodiment, a COF type semiconductor device in which the semiconductor element 2 is mounted on the tape carrier 53 will be described as an example. In addition, about the member same as the member demonstrated in the reference form 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted. Further, terms used in the present embodiment that are the same as those in Reference Embodiment 1 have the same meanings unless otherwise specified.

  The semiconductor element 2 is provided with a plurality of protruding electrodes 5. The tape carrier 53 is for connecting and mounting the semiconductor element 2 and includes an insulating tape 6, a wiring pattern 57, and a solder resist 8.

  The wiring pattern 57 is a wiring formed in a pattern on the surface of the insulating tape 6. The wiring pattern 57 is formed by forming a copper foil on the insulating tape 6 by a casting method or a sputtering method (metalizing method) and etching the copper foil into a desired pattern. In this embodiment, copper is described as an example of a material used for the wiring pattern 57, but the material is not limited to this, and a conductive metal such as silver can be used. .

  The wiring pattern 57 is partially different in thickness. Specifically, only the thickness (connection portion) where the wiring pattern 57 and the semiconductor element 2 are connected is thinner than the thickness of the other portion (non-connection portion). As a result, the wiring pattern 57 can be fine pitched at the connecting portion, the mechanical strength of the wiring pattern 57 can be improved at the non-connecting portion, and the strength of the semiconductor device 51 is also improved.

  Moreover, in this Embodiment, only the thickness of a connection part is thin, and it is thick on the outer side and the inner side (the mounting area outer side and the mounting area inner side rather than a connection part). Furthermore, in the present embodiment, the thickness of the wiring pattern 57 outside the connection portion and the thickness of the wiring pattern 57 inside the connection portion are the same.

  The connection portion is a portion where the protruding electrode 5 of the semiconductor element 2 and the wiring pattern 57 are connected, and is included in the mounting region. That is, in the mounting region, a portion where the protruding electrode 5 of the semiconductor element 2 and the wiring pattern 57 are connected is a connection portion.

  The connecting portion is formed so that the length of the connecting portion is about 40 μm larger than the length of the protruding electrode (connecting member) 5. The “length of the connecting portion” is the length of the portion where the thickness of the wiring pattern 57 in the connecting portion is thin, and the “length of the protruding electrode 5” is the design of the protruding electrode 5. It is a long thing. That is, in this case, when the protruding electrode 5 is connected to the central portion of the connecting portion, the distance between the side end portion of the protruding electrode 5 and the end portion of the connecting portion is about 20 μm. By forming in this way, for example, even when the connection accuracy of the semiconductor element 2 to the tape carrier 53 is ± 15 μm and the manufacturing size tolerance of the protruding electrode 5 is ± 10 μm, the semiconductor element 2 is connected to the connection portion. It is possible to avoid being connected to the tape carrier 53 in a state of being disconnected. However, the size is not limited to 40 μm. Moreover, it is preferable that the thickness of the wiring pattern 57 of the connection portion is within a range of 3 to 6 μm, for example. However, the thickness of the wiring pattern 57 is not limited to this, and may be any thickness that allows the wiring pattern 57 to have a fine pitch. The protruding electrode 5 may be in contact with the insulating tape 6. Any thickness is acceptable.

  The wiring pattern 57 is more effective when the wiring pitch, which is the interval between the wirings, is less than 35 μm. When the wiring pitch is less than 35 μm, a so-called fine pitch tape carrier can be obtained.

  Note that an external connection terminal (not shown) is provided on the wiring pattern 57 in order to connect the semiconductor device 51 to other electronic components. Further, the surface of the wiring pattern 57 is subjected to tin plating or gold plating (not shown).

  The insulating tape 6 is not provided with an opening for mounting the semiconductor element 2. For this reason, the semiconductor element 2 is connected and mounted on the insulating tape 6 by bonding the protruding electrode 5 provided on the semiconductor element 2 and the wiring pattern 57 formed on the surface of the insulating tape 6. That is, this connection is performed by connecting each wiring of the wiring pattern 57 arranged on the surface of the insulating tape 6 and the protruding electrode 5 of the semiconductor element 2 corresponding to each wiring. Thereby, the wiring pattern 57 and the semiconductor element 2 are electrically connected.

  The semiconductor device 51 can be a semiconductor module by connecting to other electronic components. In this semiconductor module, for example, the semiconductor device 51 can drive and control other electronic components. FIG. 17 is a cross-sectional view showing a schematic configuration of the semiconductor module 59 in the present embodiment. FIG. 17 shows the case where the semiconductor device 51 is used for a liquid crystal display device. In this case, examples of the other electronic components include the liquid crystal panel 10 and other printed boards 11. In the semiconductor module 59, the external connection terminal of the wiring pattern 57 in the semiconductor device 51 is connected to the liquid crystal panel or other printed circuit board.

  Next, a method for manufacturing the semiconductor device 51 having the above configuration will be described with reference to FIG. FIG. 18 is a cross-sectional view illustrating a schematic configuration of a method for manufacturing the semiconductor device 51. In the manufacturing method of the semiconductor device 51 in the present embodiment, the thickness of the copper foil corresponding to the connection portion is formed before the wiring pattern 57 is formed by etching the copper foil formed on the surface of the insulating tape 6. In this method, the thickness of the copper foil in the non-connection portion is made thinner by half etching.

  First, as shown in FIG. 18A, a copper foil 62 is formed on the surface of the insulating tape 6 so as to have a thickness of 8 to 18 μm by a casting method or a sputtering method (metalizing method).

  Next, as shown in FIG. 18B, etching processing (half etching) is performed on the surface of the copper foil 62 in a portion (line) corresponding to the connection portion. This etching process is performed so that the thickness of the copper foil 62 in the connection portion is thinner than the thickness of the copper foil 62 in the non-connection portion. Further, this etching process is performed so that the length of the connecting portion is about 40 μm larger than the length of the protruding electrode 5 of the semiconductor element 2 to be connected later.

  Then, as shown in FIG. 18C, the copper foil 62 is etched to form a desired wiring pattern 57 so that the copper foil 62 has a predetermined pattern. The formation of the wiring pattern 57 is performed in all regions where the wiring pattern 57 of the connection portion and the non-connection portion is to be formed. Thereafter, as shown in FIG. 18D, a solder resist 8 is applied on the wiring pattern 57 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 53 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 53 in the same manner as in the first embodiment. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 53, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 53. Thereby, the semiconductor device 51 of the present embodiment is manufactured.

  When the semiconductor device 51 is connected to other electronic components to form the semiconductor module 59, the external connection terminal of the wiring pattern 57 is connected to, for example, the liquid crystal panel 10 or the printed board 11 as shown in FIG. Etc. may be connected.

  As described above, in the tape carrier 53 for a COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 57 in the connection portion is thinner than the thickness of the wiring pattern 57 in the non-connection portion. In particular, the thickness of the wiring pattern 57 in the non-connection portion is 8 to 18 μm, whereas the thickness of the wiring pattern 57 in the connection portion is 3 to 6 μm.

  As a result, the shape of the wiring pattern 57 after etching can be improved and the connection state between the wiring pattern 57 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, it is possible to improve the mechanical strength of the wiring pattern 57 in the non-connection portion as compared with the conventional case, and it is possible to reduce defects due to disconnection or peeling of the wiring pattern 57 to 50% or less of the conventional case.

  Further, only the thickness of the wiring pattern 57 in the connection portion is reduced, and the thickness of the wiring pattern 57 in the non-connection portion is equivalent to that of a conventional tape carrier for a COF type semiconductor device. It is possible to improve the mechanical strength of the wiring pattern 57 at the same level as compared to the conventional case, and it is possible to further reduce defects due to disconnection or peeling of the wiring pattern 57 and to generate a position generated when connecting to the semiconductor element 2. Deviation can also be reduced.

[Embodiment 2]
The following describes the second embodiment of the present invention with reference to FIG. 16, FIG. 17, and FIG.

  FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device 51 according to the present embodiment. In the present embodiment, the manufacturing method of the semiconductor device 51 is different from that of the first embodiment, and the configuration of the semiconductor device 51 is the same. For this reason, the members described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a method for manufacturing the semiconductor device 51 will be mainly described. The terms used in the present embodiment also have the same meaning as in the first embodiment.

  A method for manufacturing the semiconductor device 51 in the present embodiment will be specifically described with reference to FIG. FIG. 19 is a cross-sectional view showing a schematic configuration of a method for manufacturing semiconductor device 51 in the present embodiment. In the manufacturing method of the semiconductor device 51 of the present embodiment, after the wiring pattern 57 is formed by etching the copper foil formed on the surface of the insulating tape 6, the thickness of the copper foil at the connection portion is disconnected by half etching. It is a method of making it thinner than the thickness of the copper foil of the part.

  First, as shown in FIG. 19A, a copper foil 62 is formed on the surface of the insulating tape 6 so as to have a thickness of 8 to 18 μm by a casting method or a sputtering method (metalizing method).

  Next, as shown in FIG. 19B, the copper foil 62 is etched to form a desired wiring pattern 57 so that the copper foil 62 has a predetermined pattern. The formation of the wiring pattern 57 is performed in all regions where the wiring pattern 57 of the connection portion and the non-connection portion is to be formed.

  Then, as shown in FIG. 19C, the surface of the wiring pattern 57 corresponding to the connection portion is etched. This etching process is performed by half etching. That is, the thickness of the wiring pattern 57 in the connection portion is made smaller than the thickness of the wiring pattern 57 in the non-connection portion. Further, this etching process is performed so that the length of the connecting portion is about 40 μm larger than the length of the protruding electrode 5 of the semiconductor element 2 to be connected later.

  Thereafter, as shown in FIG. 19D, a solder resist is applied on the wiring pattern 57 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 53 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 53 in the same manner as in the first embodiment. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 53, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 53. Thereby, the semiconductor device 51 of the present embodiment is manufactured.

  When the semiconductor device 51 is connected to other electronic components to form the semiconductor module 59, the external connection terminal of the wiring pattern 57 is connected to, for example, the liquid crystal panel 10 or the printed board 11 as shown in FIG. Etc. may be connected.

  As described above, in the tape carrier 53 for a COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 57 in the connection portion is thinner than the thickness of the wiring pattern 57 in the non-connection portion. In particular, the thickness of the wiring pattern 57 in the non-connection portion is 8 to 18 μm, whereas the thickness of the wiring pattern 57 in the connection portion is 3 to 6 μm.

  As a result, the shape of the wiring pattern 57 after etching can be improved and the connection state between the wiring pattern 57 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, it is possible to improve the mechanical strength of the wiring pattern 57 in the non-connection portion as compared with the conventional case, and it is possible to reduce defects due to disconnection or peeling of the wiring pattern 57 to 50% or less of the conventional case. Furthermore, it is possible to reduce the positional deviation that occurs when the semiconductor element 2 is connected.

[Embodiment 3]
The following describes the third embodiment of the present invention with reference to FIGS. 16, 17, and 20. FIG.

  FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device 51 according to the present embodiment. In the semiconductor device 51 of the present embodiment, the wiring pattern 57 is composed of two layers (a first wiring layer and a second wiring layer), and the basic configuration compared to the first embodiment is as follows. Are the same. For this reason, the members described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a method for manufacturing the semiconductor device 51 will be mainly described. The terms used in the present embodiment also have the same meaning as in the first embodiment.

  A method for manufacturing the semiconductor device 51 in the present embodiment will be specifically described with reference to FIG. FIG. 20 is a cross-sectional view showing a schematic configuration of a method for manufacturing the semiconductor device 51 in the present embodiment. In the manufacturing method of the semiconductor device 51 of the present embodiment, the thickness of the copper foil at the non-connection portion is electroplated before the wiring pattern 57 is formed by etching the copper foil formed on the surface of the insulating tape 6. Thus, the thickness is made thicker than the thickness of the copper foil of the connecting portion.

  First, as shown in FIG. 20A, a first copper foil layer 72 is formed on the surface of the insulating tape 6 by a casting method or a sputtering method (metalizing method) so as to have a thickness of 3 to 6 μm. . Then, as shown in FIG. 20B, a second copper foil layer 73 is further formed on the first copper foil layer 72 corresponding to the non-connection portion. The second copper foil layer 73 is formed so that the total thickness of the first copper foil layer 72 and the second copper foil layer 73 is 8 to 18 μm. The second copper foil layer 73 is formed so that the length of the connection portion is about 40 μm larger than the length of the protruding electrode 5 of the semiconductor element 2 to be connected later.

  And as shown in FIG.20 (c), the etching process with respect to the 1st copper foil layer 72 and the 2nd copper foil layer 73 so that the 1st copper foil layer 72 and the 2nd copper foil layer 73 may become a predetermined pattern. The desired wiring pattern 57 is formed. As a result, a wiring pattern 57 including the first wiring layer 57a and the second wiring layer 57b is formed. The formation of the wiring pattern 57 is performed in all regions where the wiring pattern 57 of the connection portion and the non-connection portion is to be formed.

  After that, as shown in FIG. 20D, a solder resist 8 is applied on the wiring pattern 57 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 53 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 53 in the same manner as in the first embodiment. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 53, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 53. Thereby, the semiconductor device 51 of the present embodiment is manufactured.

  When the semiconductor device 51 is connected to other electronic components to form the semiconductor module 59, the external connection terminal of the wiring pattern 57 is connected to, for example, the liquid crystal panel 10 or the printed board 11 as shown in FIG. Etc. may be connected.

  As described above, in the tape carrier 53 for a COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 57 in the connection portion is thinner than the thickness of the wiring pattern 57 in the non-connection portion. In particular, the thickness of the wiring pattern 57 in the non-connection portion is 8 to 18 μm, whereas the thickness of the wiring pattern 57 in the connection portion is 3 to 6 μm.

  As a result, the shape of the wiring pattern 57 after etching can be improved and the connection state between the wiring pattern 57 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, it is possible to improve the mechanical strength of the wiring pattern 57 in the non-connection portion as compared with the conventional case, and it is possible to reduce defects due to disconnection or peeling of the wiring pattern 57 to 50% or less of the conventional case. Furthermore, it is possible to reduce the positional deviation that occurs when the semiconductor element 2 is connected.

[Reference Form 5]
Reference embodiment 5 of the present invention will be described below with reference to FIGS. 16, 17, and 21. FIG.

  FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device 51 according to the present embodiment. The semiconductor device 51 according to the present embodiment has a wiring pattern 57 composed of two layers (a first wiring layer and a second wiring layer), and the basic configuration is the same as that of the fifth embodiment. It is. For this reason, the members described in the fifth embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a method for manufacturing the semiconductor device 51 will be mainly described. Also, the terms used in this reference form have the same meaning as in the fifth embodiment.

  A method for manufacturing the semiconductor device 51 according to the present embodiment will be specifically described with reference to FIG. FIG. 21 is a cross-sectional view showing a schematic configuration of a method for manufacturing the semiconductor device 51 in the present embodiment. In the manufacturing method of the semiconductor device 51 of the present embodiment, after the wiring pattern 57 is formed by etching the copper foil formed on the surface of the insulating tape 6, the thickness of the copper foil in the non-connection portion is connected by electroplating or the like. It is a method of making it thicker than the thickness of the copper foil of the part.

  First, as shown in FIG. 21A, the first copper foil layer 72 is formed on the surface of the insulating tape 6 by a casting method or a sputtering method (metalizing method) so as to have a thickness of 3 to 6 μm. .

  Next, as shown in FIG. 21B, the first copper foil layer 72 is etched so that the first copper foil layer 72 has a predetermined pattern, and the first wiring layer 57a having a desired pattern is formed. Form. The formation of the first wiring layer 57a is performed in all regions where the wiring patterns 57 of the connection part and the non-connection part are to be formed.

  Then, as shown in FIG. 21C, a second wiring layer 57b is formed by further stacking copper foil on the portion of the first wiring layer 57a corresponding to the non-connection portion. As a result, a wiring pattern 57 including the first wiring layer 57a and the second wiring layer 57b etched into a desired pattern shape is formed. The second wiring layer 57b is formed, for example, by depositing copper plating by electroplating and stacking on the first wiring layer 57a. The second wiring layer 57 is formed so that the total thickness of the first wiring layer 57a and the second wiring layer 57b is 8 to 18 μm. Further, the second copper foil layer 73 is formed so that the length of the connecting portion is about 40 μm larger than the length of the protruding electrode 5 of the semiconductor element 2 to be connected later.

  Thereafter, as shown in FIG. 21D, a solder resist 8 is applied on the wiring pattern 57 in a portion exposed when the semiconductor element 2 is mounted in a later step. Thereby, the tape carrier 53 is produced.

  Next, the semiconductor element 2 is connected and mounted on the tape carrier 53 in the same manner as in the fifth embodiment. Then, after the semiconductor element 2 is connected and mounted on the tape carrier 53, the insulating resin 4 is injected and sealed in a gap formed between the semiconductor element 2 and the tape carrier 53. Thereby, the semiconductor device 51 of the present embodiment is manufactured.

  When the semiconductor device 51 is connected to other electronic components to form the semiconductor module 59, the external connection terminal of the wiring pattern 57 is connected to, for example, the liquid crystal panel 10 or the printed board 11 as shown in FIG. Etc. may be connected.

  As described above, in the tape carrier 53 for the COF type semiconductor device according to the present embodiment, the thickness of the wiring pattern 57 in the connection portion is thinner than the thickness of the wiring pattern 57 in the non-connection portion. In particular, the thickness of the wiring pattern 57 in the non-connection portion is 8 to 18 μm, whereas the thickness of the wiring pattern 57 in the connection portion is 3 to 6 μm.

  As a result, the shape of the wiring pattern 57 after etching can be improved and the connection state between the wiring pattern 57 and the semiconductor element 2 can be improved as compared with a tape carrier for a conventional COF type semiconductor device. can do. In addition, it is possible to improve the mechanical strength of the wiring pattern 57 in the non-connection portion as compared with the conventional case, and it is possible to reduce defects due to disconnection or peeling of the wiring pattern 57 to 50% or less of the conventional case. Furthermore, it is possible to reduce the positional deviation that occurs when the semiconductor element 2 is connected.

  The tape carrier of the present invention is a thin insulating tape that becomes a COF semiconductor device by electrically connecting a plurality of wiring patterns arranged on the surface and protruding electrodes of a semiconductor element and sealing with an insulating resin. In the insulating tape in which the wiring pitch of the wiring pattern in the region where the semiconductor element is connected / mounted is less than 35 μm, the semiconductor element is more than the thickness of the wiring pattern other than the region where the semiconductor element is connected / mounted. This can also be expressed as a tape carrier for a COF semiconductor device in which the wiring pattern in the region to be connected and mounted has a small thickness. In the above tape carrier, the thickness of the wiring pattern in the region where the semiconductor element is connected and mounted may be 3 to 6 μm.

  In addition, the tape carrier manufacturing method of the present invention is configured such that, before the wiring pattern is formed by pattern etching, the thickness of the wiring pattern forming region to which the semiconductor element is connected and mounted later is half-etched to obtain other regions. It can also be expressed as a method of forming the wiring pattern by pattern etching after making it thinner, including other regions.

  In the above manufacturing method, after the wiring pattern is formed by pattern etching, the thickness of the wiring pattern in a region where the semiconductor element is later connected and mounted is formed by half etching to be thinner than the wiring pattern in other regions. It may be.

  The tape carrier of the present invention is a thin film insulating tape that becomes a COF semiconductor device by electrically connecting a plurality of wiring patterns arranged on the surface and protruding electrodes of a semiconductor element and sealing with an insulating resin. In the insulating tape in which the wiring pitch of the wiring pattern in the region where the semiconductor element is connected / mounted is less than 35 μm, the semiconductor element is connected rather than the thickness of the wiring pattern in the region where the semiconductor element is connected / mounted. -It can also be expressed as a tape carrier for a COF semiconductor device in which the wiring pattern other than the area to be mounted is formed thick. In the above tape carrier, the thickness of the wiring pattern other than the region where the semiconductor element is connected and mounted may be 8 μm or more.

  Further, the tape carrier manufacturing method of the present invention is characterized in that the thickness of the wiring pattern forming region other than the region where the semiconductor element is connected and mounted later is sputtered (metalizing method) before patterning the wiring pattern. Thus, it can be expressed as a method of forming the wiring pattern by pattern etching after being stacked thicker than the wiring pattern forming region for connecting and mounting the semiconductor element.

  In the above manufacturing method, after the wiring pattern is formed by pattern etching, the thickness of the wiring pattern other than the region where the semiconductor element is connected and mounted later is connected by sputtering (metalizing method). -You may form it piled up thickly rather than the said wiring pattern of the area | region to mount.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

[Reference form]
In order to solve the above problems, a flexible wiring board according to this reference example is a flexible wiring board including an insulating layer and a wiring layer formed on the insulating layer. The wiring layer has a predetermined pattern. It is formed and has a mounting region for connecting and mounting electronic components, and the thickness of the wiring layer in the mounting region is smaller than the thickness of the wiring layer in the non-mounting region.

  According to said structure, the wiring layer is formed in the predetermined pattern, and has a some wiring by this. The predetermined pattern is a pattern composed of a plurality of wirings arbitrarily determined according to the usage of the flexible wiring board. The wiring layer has a mounting area for connecting and mounting electronic components. The mounting region is a region where an electronic component is mounted in the wiring layer, and specifically, a region covered with the electronic component. Since the thickness of the wiring layer in the mounting region is thinner than the thickness of the wiring layer in the non-mounting region, the connection portion can be easily processed. The non-mounting area is an area other than the mounting area in the wiring layer.

  Therefore, for example, when etching a wiring, the wiring can be etched to have a favorable shape, and variations in the thickness of each wiring can be reduced. For this reason, it is possible to make the pattern of the wiring layer finer (fine pitch).

  Moreover, since the thickness of the wiring layer in the non-mounting region is thicker than the thickness of the wiring layer in the mounting region, the mechanical strength of the wiring layer can be improved. For this reason, even when the flexible wiring board is bent, the wiring layer pattern can be prevented from being disconnected or peeled off.

  In order to solve the above problems, a flexible wiring board according to this reference example is a flexible wiring board including an insulating layer and a wiring layer formed on the insulating layer. The wiring layer has a predetermined pattern. It is formed and has a connection part for connecting to an electronic component, and the thickness of the wiring layer in the connection part is thinner than the thickness of the wiring layer in the non-connection part (part other than the connection part) It is characterized by that.

  In the flexible wiring board according to this reference example, the electronic component has a connection member for connecting to the connection portion, and the wiring layer in the connection portion has a connection accuracy between the connection portion and the connection member, and It is preferable that the thickness of the connecting member is reduced in consideration of the manufacturing size tolerance. Further, when the connection accuracy is ± 15 μm and the manufacturing size tolerance of the connection member is ± 10 μm, the wiring layer in the connection portion is thin at least in the range of the design length of the connection member + 40 μm. It is preferable.

  According to said structure, the thin area | region of the wiring layer in a connection part is the range which considered the tolerance of the connection precision and the manufacturing size of the connection member. For example, when the connection accuracy of the electronic component to the connection part is about 15 μm and the manufacturing size tolerance of the connection member is ± 10 μm, the wiring layer in the connection part is at least in the range of the design length of the connection member +40 μm. It is getting thinner. Thereby, it becomes possible to connect without connecting the connection member of an electronic component from a connection part, and it can avoid that it becomes a connection failure. The connection accuracy is the accuracy of positional deviation when connecting the connection portion and the connection member. In addition, the manufacturing size tolerance of the connecting member refers to a range of size error that occurs when the connecting member is manufactured. The design length of the connecting member is the target value (design value) at the time of manufacturing before considering the tolerance of the manufacturing size. The actual finished size is obtained by adding or subtracting the manufacturing size tolerance to the design length. Become.

  In order to solve the above problems, a method for manufacturing a flexible wiring board according to this reference example includes a wiring layer forming step of forming a wiring layer on an insulating layer, and a pattern forming step of forming the wiring layer in a predetermined pattern. In the method for manufacturing a flexible wiring board having the above-described structure, the method further includes a thinning step of reducing the thickness of the portion of the wiring layer connected to the electronic component.

  According to said structure, since the thickness of the part connected to an electronic component of a wiring layer can be made thin by a thinning process, the process of the connection part with an electronic component becomes easy. Therefore, for example, when etching a wiring, the wiring can be etched to have a favorable shape, and variations in the thickness of each wiring can be reduced. For this reason, it is possible to make the pattern of the wiring layer finer (fine pitch).

  Further, since the thickness of the wiring layer other than the connection portion with the electronic component is thicker than the thickness of the wiring layer at the connection portion, the mechanical strength of the wiring layer can be improved. For this reason, even when the flexible wiring board is bent, it is possible to manufacture a flexible wiring board in which the pattern of the wiring layer does not break or peel off.

  In the method for manufacturing a flexible wiring board according to this reference example, the thinning step is preferably performed between the wiring layer forming step and the pattern forming step. According to said structure, after thinning the connection part with an electronic component of a wiring layer, a pattern formation process is performed. In this case, since a relatively large region is thinned, the thinning can be easily performed without using a highly accurate method.

  In the method for manufacturing a flexible wiring board according to this reference example, it is preferable that the thinning step is performed after the pattern forming step. According to said structure, since it forms in a thin layer after forming a pattern, the variation in the thickness of a pattern can be reduced.

  In the method for manufacturing a flexible wiring board according to the present invention, the thinning step is preferably performed using an etching method. According to said structure, thinning of a wiring layer can be performed easily.

  In order to solve the above problems, a method for manufacturing a flexible wiring board according to this reference example includes a wiring layer forming step of forming a wiring layer on an insulating layer, and a pattern forming step of forming the wiring layer in a predetermined pattern. In the method for manufacturing a flexible wiring board, the wiring layer forming step includes a first wiring layer forming step of forming a first wiring layer, and a first wiring other than a portion where the first wiring layer and the electronic component are connected. And a second wiring layer forming step of forming a second wiring layer on the layer.

  According to said structure, the 2nd wiring layer is formed on the 1st wiring layer other than the part which a 1st wiring layer and an electronic component connect. That is, in the wiring layer, the thickness of the portion connected to the electronic component is thinner than the thickness of the other portions. For this reason, the process of the part connected with an electronic component becomes easy.

  Therefore, for example, when etching a wiring, the wiring can be etched to have a favorable shape, and variations in the thickness of each wiring can be reduced. For this reason, it is possible to make the pattern of the wiring layer finer (fine pitch).

  Further, since the thickness of the wiring layer other than the connection portion with the electronic component is thicker than the thickness of the wiring layer at the connection portion, the mechanical strength of the wiring layer can be improved. For this reason, even when the flexible wiring board is bent, it is possible to manufacture a flexible wiring board in which the pattern of the wiring layer does not break or peel off.

  In the method for manufacturing a flexible wiring board according to this reference example, it is preferable that the second wiring layer forming step is performed between the first wiring layer forming step and the pattern forming step. According to said structure, after forming a 2nd wiring layer on 1st wiring layers other than a connection part with an electronic component, a pattern formation process is performed. In this case, since the second wiring layer in a relatively large region is formed, the second wiring layer can be easily stacked without using a highly accurate method.

  In the method for manufacturing a flexible wiring board according to this reference example, it is preferable that the second wiring layer forming step is performed after the pattern forming step. According to said structure, since a wiring layer is thickened after forming a pattern, the variation in the thickness of a pattern can be reduced.

  In the method for manufacturing a flexible wiring board according to this reference example, it is preferable that the second wiring layer forming step is performed using a sputtering method (metalizing method). According to said structure, it can carry out easily making thickness of wiring layers other than the connection part with an electronic component thicker than the thickness of the wiring layer of a connection part.

  As described above, by using the method for manufacturing a flexible wiring board according to the present invention, the resulting flexible wiring board can have a fine pitch in the wiring pattern and can improve the mechanical strength. The electrical connection with the element can be made favorable. Therefore, the flexible wiring board according to the present invention can be particularly suitably used as a wiring board or the like of an electronic device that is reduced in size and thickness.

  Therefore, the present invention can be suitably used not only in the industrial field for manufacturing flexible wiring boards but also in the industrial field for manufacturing various electronic / electrical devices and components thereof.

1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a schematic configuration of a semiconductor device in a case where the semiconductor device is cut along a line A-A ′ illustrated in FIG. 1, illustrating one embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor module according to one embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 25 is a cross-sectional view illustrating a schematic configuration of a semiconductor device manufacturing method according to another embodiment of the present invention. FIG. 24 is a sectional view showing a schematic configuration of a semiconductor device according to still another reference embodiment of the present invention. FIG. 17 is a sectional view showing a schematic configuration of a semiconductor device when it is cut along a B-B ′ line shown in FIG. 6, showing still another reference embodiment of the present invention. FIG. 24 is a cross-sectional view illustrating a schematic configuration of a semiconductor module according to still another reference embodiment of the present invention. FIG. 24 is a sectional view showing a schematic configuration of a method for manufacturing a semiconductor device, showing still another reference embodiment of the present invention. FIG. 24 is a sectional view showing a schematic configuration of a method for manufacturing a semiconductor device, showing still another reference embodiment of the present invention. It is sectional drawing which shows schematic structure of the conventional semiconductor device. It is sectional drawing which shows schematic structure of the conventional semiconductor device. It is sectional drawing which shows schematic structure of the conventional semiconductor device. It is sectional drawing which shows schematic structure of the conventional semiconductor device. It is sectional drawing which shows schematic structure of the conventional semiconductor device. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to Embodiments 1, 2, and 3 of the present invention. FIG. BRIEF DESCRIPTION OF THE DRAWINGS Embodiment 1, 2, and 3 of this invention are shown, and it is sectional drawing which shows schematic structure of a semiconductor module. BRIEF DESCRIPTION OF THE DRAWINGS It is Embodiment 1 of this invention, and is sectional drawing which shows schematic structure of the manufacturing method of a semiconductor device. FIG. 9 is a sectional view illustrating a schematic configuration of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 24 is a sectional view illustrating a third embodiment of the present invention and illustrating a schematic configuration of a method for manufacturing a semiconductor device. FIG. 24 is a sectional view showing a schematic configuration of a method for manufacturing a semiconductor device, showing still another reference embodiment of the present invention.

Explanation of symbols

1.21 51 Semiconductor device 2 Semiconductor element (electronic component)
3, 23, 53 Tape carrier (flexible wiring board)
6 Insulating tape (insulating layer)
7.27.57 Wiring pattern (wiring layer, pattern)
9.29.59 Semiconductor module (electronic equipment)
12.62 Copper foil (wiring layer)
32.72 First copper foil layer (wiring layer)
33.73 Second copper foil layer (wiring layer)

Claims (8)

In a flexible wiring board comprising an insulating layer and a wiring layer formed on the insulating layer,
The wiring layer is formed in a predetermined pattern, and has a connection portion for connecting to the electronic component in a mounting region for connecting and mounting the electronic component,
A flexible wiring board characterized in that only the thickness of the wiring layer of only the connecting portion is thinner than the thickness of the wiring layer of the non-connecting portion.   The flexible wiring board according to claim 1, wherein the wiring layer has the same thickness of the non-connection portion in the mounting region as that of the non-connection portion in the non-mounting region.   The flexible wiring board according to claim 1, wherein an interval between at least one pair of adjacent wirings in the pattern is less than 35 μm.   4. The flexible wiring board according to claim 1, wherein a thickness of the wiring layer in the connection portion is in a range of 3 to 6 μm.   5. The flexible wiring board according to claim 1, wherein a thickness of the wiring layer in the non-connecting portion is 8 μm or more.   The flexible wiring board according to claim 1, wherein the connection portion is an inner lead portion.   A semiconductor device comprising: the flexible wiring board according to claim 1; and a semiconductor element connected to a connection portion of the flexible wiring board.   An electronic apparatus comprising the semiconductor device according to claim 7.

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