KR0151898B1 - Multichip package of center pad type - Google Patents
Multichip package of center pad typeInfo
- Publication number
- KR0151898B1 KR0151898B1 KR1019950023689A KR19950023689A KR0151898B1 KR 0151898 B1 KR0151898 B1 KR 0151898B1 KR 1019950023689 A KR1019950023689 A KR 1019950023689A KR 19950023689 A KR19950023689 A KR 19950023689A KR 0151898 B1 KR0151898 B1 KR 0151898B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- substrate
- bonding
- chips
- multichip package
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 멀티칩 패키지에 관한 것으로, 더욱 상세하게는 센터 본딩패드들을 갖는 복수개의 칩들이 패턴닝(patterning)된 기판에 의해 그 칩들에 대응하는 내부리드들이 각기 전기적 연결됨으로써, 대칭칩을 새로이 제작하거나 멀티칩 패키지를 제작하기 위한 패키지의 조립장치를 도입하는 단점을 극복한 것이다.The present invention relates to a multi-chip package, and more particularly, a symmetric chip is newly manufactured by internally connecting internal leads corresponding to the chips by a substrate in which a plurality of chips having center bonding pads are patterned. Or to overcome the disadvantage of introducing a package assembly device for manufacturing a multi-chip package.
Description
제1도는 종래 기술의 일실시예에 의한 대칭칩(mirror chip)을 이용한 멀티칩 패키지를 나타내는 단면도.1 is a cross-sectional view showing a multi-chip package using a symmetric chip (mirror chip) according to an embodiment of the prior art.
제2도는 종래 기술의 다른 실시예에 의한 기판을 이용한 멀티칩 패키지를 나타내는 단면도.2 is a cross-sectional view showing a multichip package using a substrate according to another embodiment of the prior art.
제3도는 본 발명에 의한 기판을 이용한 센터 패드(center pad)형태의 칩이 적용된 멀티칩 패키지를 나타내는 평면도.3 is a plan view showing a multi-chip package to which a chip in the form of a center pad using a substrate according to the present invention is applied.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
116, 118 : 폴리이미드 테이프 120, 130 : 칩116, 118: polyimide tape 120, 130: chip
122, 132 : 칩 본딩패드 140 : 기판122, 132: chip bonding pad 140: substrate
141, 143 : 연결단자(기판 본딩패드) 142, 144 : 기판 접속패드141, 143: connection terminal (substrate bonding pad) 142, 144: board connection pad
150, 152 : 와이어 160, 170 : 내부리드150, 152: Wire 160, 170: Internal lead
162, 172 : 도금막 180, 190 : 범프162, 172: plating film 180, 190: bump
200 : 멀티칩 패키지200: multichip package
본 발명은 멀티칩 패키지에 관한 것으로, 더욱 상세하게는 센터 패드(center pad)를 갖는 칩을 패턴닝(patterning)된 기판을 이용하여 멀티칩 패키지를 제작함으로써, 새로운 대칭칩(mirror chip)의 설계 및 제작이 필요없게 되며, 주로 에지패드(Edge pad)형태의 칩에만 적용되는 멀티칩 패키지를 센터 패드 형태의 칩에도 적용할 수 있도록 구성한 멀티칩 패키지이다.The present invention relates to a multichip package, and more particularly, to design a new symmetric chip by fabricating a multichip package using a substrate patterned with a chip having a center pad. And it does not need to manufacture, it is a multi-chip package configured to be applied to a multi-chip package mainly applied to the chip of the edge pad (edge pad) type.
전자 산업이 발전함에 따라 보다 적은 면적에 보다 고밀도한 칩을 실장하려는 기술이 꾸준히 개발되고 있다. 이러한 기술 발전에 의해 TSOP(thin small outline package) 또는 적층형 패키지와 같은 고밀도 패키지가 개발되었으며, 이중에서도 가장 간단하며, 수율이 높고, 적용 범위가 넓은 2칩 1패키지를 중심으로 기술 개발이 진행되고 있다.As the electronics industry develops, technologies are increasingly being developed to mount denser chips in smaller areas. These advances have led to the development of high density packages such as thin small outline packages (TSOPs) or stacked packages. Among them, the development of technologies is focused on two-chip single packages, which are the simplest, higher yield, and broadest applicable. .
제1도는 종래 기술의 일실시예에 의한 대칭칩(mirror chip)을 이용한 멀티칩 패키지를 나타내는 단면도이다.1 is a cross-sectional view showing a multi-chip package using a mirror chip according to an embodiment of the prior art.
제1도를 참조하면, 종래 기술에 의한 멀티칩 패키지(100)는 상부칩(10) 및 그(10)에 대칭되는 하부칩(20)이 서로 마주보며 적층되어 있으며, 그 사이에 공통 리드(30)가 삽입·배치되어 범프(40)에 의해 전기적 연결되어 있으며, 상기 공통 리드(30)와 범프(40)의 사이 및 범프(40)와 칩들(10),(20)의 본딩패드(도시 안됨) 사이에는 전기 전도성이 양호한 도금막(45)이 형성되어 있는 구조를 가지고 있다.Referring to FIG. 1, in the multi-chip package 100 according to the related art, the upper chip 10 and the lower chip 20 symmetrical to the 10 are stacked to face each other, and a common lead ( 30 is inserted and arranged and electrically connected by the bump 40, and bonding pads between the common lead 30 and the bump 40 and between the bump 40, the chips 10, and 20. (Not used) has a structure in which a plating film 45 having good electrical conductivity is formed.
이와 같은 구조를 갖는 멀티칩 패키지는, 그 구성에 있어서 대칭칩을 새로이 설계·제작하여야 하는 어려움이 상존하기 때문에 실제 적용되지는 않는다.The multichip package having such a structure is not practically applied because of the difficulty in designing and manufacturing a symmetric chip in the configuration.
제2도는 종래 기술의 다른 실시예에 의한 기판을 이용한 멀티칩 패키지를 나타내는 단면도이다.2 is a cross-sectional view showing a multichip package using a substrate according to another embodiment of the prior art.
제2도를 찹조하면, 종래 기술에 의한 멀티칩 패키지(110)는 서로 마주보고 적층된 상부칩(12)과 그(12)에 대칭되는 하부칩(22)이 상기 칩들(12),(22)들의 사이에 삽입된 리드프레임(60)와 접착제(70)에 의해 접착되어 있으며, 또한 상기 칩들(12),(22)의 본딩패드들(도시 안됨)은 그들에 대응되는 공통 리드(52)와 와이어(80)에 의해 전기적 연결되어 있는 구조를 갖는다.Referring to FIG. 2, the multi-chip package 110 according to the related art includes the upper chips 12 stacked on the other side and the lower chips 22 symmetrical to the chips 12, 22. The bonding pads (not shown) of the chips 12 and 22 are bonded to each other by the lead frame 60 and the adhesive 70 inserted therebetween. And wires 80 are electrically connected.
이와 같은 구조를 갖는 멀티칩 패키지는 그 칩들 간에 연결되는 상호접속(interconnection)을 진행하는 데에 특별한 조립장치가 요구되며 공통리드(52)에 상호접속하기 때문에 대칭칩(mirror chip)이 필요하다.A multichip package having such a structure requires a special assembly device for the interconnection between the chips and requires a symmetric chip because it interconnects to the common lead 52.
따라서 본 발명의 목적은 별도의 대칭칩을 제작하거나 새로운 패키지 조립장치의 도입이 요구되지 않도록 패턴닝된 기판을 이용하는 동시에 센터 패드(center pad)를 갖는 칩을 멀티칩 패키지로 구성하기에 곤란한 단점을 극복할 수 있는 기판을 이용한 센터 패드(center pad)형태의 칩을 적용한 멀티칩 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to make it difficult to construct a chip having a center pad into a multichip package while using a patterned substrate so that a separate symmetric chip or a new package assembly device is not required. An object of the present invention is to provide a multichip package in which a chip in a center pad form using a substrate that can be overcome is applied.
상기 목적을 달성하기 위하여, 센터 패드(center pad)를 갖는 칩이 복수개 탑재된 멀티칩 패키지에 있어서, 센터 본딩패드들을 갖는 복수개의 칩들과; 그 칩 상면에 내부리드에 연결되는 접속 pad와 전기적 회로가 형성된 기판 본딩 패드를 갖는 기판과 ; 칩 본딩패드에 대응하여 기판 본딩패드와 각기 전기적 연결된 연결단자들과 ; 상기 칩들의 상면과 상기 기판의 하면을 접착하는 접착수단과 ; 그 기판의 접속패드들에 대응하여 전기적 연결된 내부리드들을 포함하는 것을 특징으로 하는 기판을 이용하여 센터 패드(center pad)형태의 칩에 적용한 멀티칩 패키지를 제공한다.In order to achieve the above object, there is provided a multichip package having a plurality of chips having a center pad, comprising: a plurality of chips having center bonding pads; A substrate having a connection pad connected to an internal lead on the upper surface of the chip and a substrate bonding pad on which an electrical circuit is formed; Connecting terminals electrically connected to the substrate bonding pads in correspondence with the chip bonding pads; Bonding means for bonding an upper surface of the chips and a lower surface of the substrate; The present invention provides a multichip package applied to a chip having a center pad type by using a substrate including internal leads electrically connected to connection pads of the substrate.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제3도는 본 발명에 의한 기판을 이용하여 센터 패드(center pad)형태의 칩에 적용한 멀티칩 패키지를 나타내는 평면도이다.3 is a plan view illustrating a multichip package applied to a chip in a center pad form using a substrate according to the present invention.
제3도를 찹조하면, 본 발명에 의한 멀티칩 패키지(200)는 2개의 칩(120),(130)이 패턴닝(patterning)된 기판(140)에 폴리이미드 테이프(양면 접착 테이프)(116),(118)에 접착되어 있으며, 그 기판의 좌우 말단부에 형성되어 있는 접속패드들(142),(144)과 그들에 대응되는 내부리드들(160),(170)이 각각의 범프들(180),(190) 또는 열압착 방법에 의해 전기적 연결되어 있으며, 또한 기판(140)의 상면에 형성되어 있는 기판본딩패드(141),(143)와 그에 대응되는 기판 접속패드(142),(144)는 회로 패턴(도시 안됨)에 의해 각기 전기적 연결되어 있으며, 기판본딩패드(141),(143)는 그에 대응되는 칩 본딩패드(122),(132)에 각기 와이어(150),(152)에 의해 전기적 연결되어 있는 구조를 가지고 있다.Referring to FIG. 3, the multichip package 200 according to the present invention is a polyimide tape (double-sided adhesive tape) 116 on a substrate 140 on which two chips 120 and 130 are patterned. Are connected to the bumps 118 and 118, and the connection pads 142 and 144 formed on the left and right ends of the substrate and the inner leads 160 and 170 corresponding thereto are respectively bumps. 180, 190, or the substrate bonding pads 141 and 143 which are electrically connected by a thermocompression bonding method and are formed on the upper surface of the substrate 140, and the substrate connection pads 142 corresponding thereto (( 144 is electrically connected to each other by a circuit pattern (not shown), and the substrate bonding pads 141 and 143 are wired 150 and 152 to chip bonding pads 122 and 132 corresponding thereto. It has a structure that is electrically connected by).
좀 더 상세히 언급하면, 상기 범프(180),(190)의 상하면에는 전기전도성이 양호한 도금막(162),(172)이 형성되어 열압착(thermo-compression) 기술에 의해 본딩이 되어지며 따라서, 칩 본딩패드(122),(132)와 기판 본딩패드(141),(143)와 기판접속패드(142),(144)와 내부리드(160),(170)가 전기적 연결되어 있는 것이다.In more detail, the upper and lower surfaces of the bumps 180 and 190 are plated films 162 and 172 having good electrical conductivity to be bonded by thermo-compression technology. The chip bonding pads 122, 132, the substrate bonding pads 141, 143, the substrate connection pads 142, 144, and the inner leads 160, 170 are electrically connected to each other.
상기의 제3도에서 상기 칩들(120),(130)을 기판(140)의 하면에 접착시키는 폴리이미드 테이프(116),(118)의 면적은 그 칩들(120),(130)을 고정시킬 수 있는 최소의 면적이 바람직하다. 또한, 제3도에서는 2개의 칩에 대하여 기술을 하였지만 이에 국한되지 않고 복수개의 칩이 병렬로 패키징되는 멀티칩 패키지로 확장될 수 있다.In FIG. 3, the area of the polyimide tapes 116 and 118 that bonds the chips 120 and 130 to the bottom surface of the substrate 140 may be used to secure the chips 120 and 130. The smallest area that is possible is desirable. In addition, although FIG. 3 describes two chips, the present invention is not limited thereto and may be extended to a multichip package in which a plurality of chips are packaged in parallel.
따라서, 본 발명에 따른 구조에 따르면, 멀티칩 패키지를 구성하는 데에 있어서 대칭칩이 요구되지 않으며, 또한 기존의 패키지 조립장치에 의해 제작이 가능한 동시에 센터 패드를 갖는 칩들을 패키징할 수 있는 이점(利點)이 있다.Therefore, according to the structure according to the present invention, there is no need for a symmetrical chip in constructing a multichip package, and it is possible to manufacture a chip by an existing package assembly apparatus and simultaneously package chips having a center pad ( I)
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950023689A KR0151898B1 (en) | 1995-08-01 | 1995-08-01 | Multichip package of center pad type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950023689A KR0151898B1 (en) | 1995-08-01 | 1995-08-01 | Multichip package of center pad type |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970013233A KR970013233A (en) | 1997-03-29 |
| KR0151898B1 true KR0151898B1 (en) | 1998-10-01 |
Family
ID=19422588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950023689A KR0151898B1 (en) | 1995-08-01 | 1995-08-01 | Multichip package of center pad type |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0151898B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100537893B1 (en) * | 1998-11-04 | 2006-02-28 | 삼성전자주식회사 | Leadframe and multichip package using the same |
| KR100702970B1 (en) * | 2005-07-06 | 2007-04-03 | 삼성전자주식회사 | semiconductor package having dual interconnection form and manufacturing method thereof |
-
1995
- 1995-08-01 KR KR1019950023689A patent/KR0151898B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970013233A (en) | 1997-03-29 |
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