KR940010535B1 - Package of semiconductor device and manufacturing method thereof - Google Patents

Package of semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR940010535B1
KR940010535B1 KR1019910016778A KR910016778A KR940010535B1 KR 940010535 B1 KR940010535 B1 KR 940010535B1 KR 1019910016778 A KR1019910016778 A KR 1019910016778A KR 910016778 A KR910016778 A KR 910016778A KR 940010535 B1 KR940010535 B1 KR 940010535B1
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South Korea
Prior art keywords
chips
leads
package
chip
semiconductor package
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KR1019910016778A
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Korean (ko)
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KR930006869A (en
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송영재
이충우
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삼성전자 주식회사
김광호
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Priority to KR1019910016778A priority Critical patent/KR940010535B1/en
Publication of KR930006869A publication Critical patent/KR930006869A/en
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Publication of KR940010535B1 publication Critical patent/KR940010535B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

The semiconductor package can simply make more than 2 chips get assemled in a package unit so that it can realize a high integration of the semiconductors and a minimiztion of electronic devices. The semiconductor package includes leads getting in contact with a multiple of chips; a bump formed in one among the chips, and connected with the leads via a wire. The manufacturing method comprises a step of forming the bump in a bonding pad; a step of glueing a polyamid tape to the leads, and mounting another chip to the tape; a step of bonding the leads with a wire; a step of sealing up the chips with a resin; a step of bending the exteror leads.

Description

반도체 패키지 및 그 제조방법Semiconductor package and manufacturing method

제 1a~e 도는종래의 반도체패키지의 제조공정을 설명하기 위한도면,1a to e or a diagram for explaining a manufacturing process of a conventional semiconductor package,

제 2 도는 제 1 도의 제조공정에 의한 다른 실시예를 설명하기 위한 단면도,2 is a cross-sectional view for explaining another embodiment by the manufacturing process of FIG.

제 3a~e 도는 이 발명에 따른 반도체 패키지의 제조공정을 설명하기 위한 도면.3A to 3E are views for explaining the manufacturing steps of the semiconductor package according to the present invention.

제 4a,b 도는 제 3 도의 제조공정에 의한 다른 실시예를 설명하기 위한 단면도,4a, b or sectional view for explaining another embodiment by the manufacturing process of FIG.

제 5a,b 도는 이 발명에 따른 리드프레임에 칩이 접착되는 상태를 설명하기 위한 도면이다.5A and 5B are views for explaining a state in which a chip is bonded to a lead frame according to the present invention.

이 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 하나의 패키지내에 2개 이상의 칩을 간단히 실장할 수 있도록 하여 반도체 패키지의 고집적화 및 전자기기의 소형화를 이룰 수 있도록 한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, it is possible to easily mount two or more chips in one package to achieve high integration of a semiconductor package and miniaturization of an electronic device.

일반적으로, 반도체 패키지의 소형화 및 고집적화 추세에 따라 고용량의 메모리에 대한 수요에 대응하기 위하여 하나의 패키지내에 2개이상의 칩을 실장할 수 있는 패키지 기술에 개발되어 오고 있는데, 종래의 이와 같은 패키지를 제조함에 있어서는 제 1a~e 도에 나타낸 바와 같이, 먼저 회로패턴이 형성된 칩(1)상의 본딩패드에 범프(Bump)(1a)를 각각 형성하고 이 범프(1a)상에 두께가 대략 35㎛ 정도인 보조리드(2)를 열압착 방식에 의해 접착시킨다.In general, in accordance with the trend of miniaturization and high integration of semiconductor packages, package technologies capable of mounting two or more chips in one package have been developed. As shown in Figs. 1A to 1E, bumps 1a are formed on the bonding pads on the chip 1 on which the circuit patterns are formed, respectively, and the thicknesses are approximately 35 mu m on the bumps 1a. The auxiliary lead 2 is bonded by a thermocompression bonding method.

상기와 같은 방법으로 또 다른 1쌍의 보조리드(3)가 범프(4a)에 의해 접착된 칩(4)을 1조로 하여 리드(5)를 중심으로 서로 대칭되도록 상하로 정렬한 후 보조리드(2), (3)들을 굽힘성형하여 각 리드(5)에 연결시킨다.In the same manner as above, another pair of auxiliary leads 3 are arranged in a pair with the chips 4 bonded by the bumps 4a so as to be symmetrical with each other about the leads 5, and then the auxiliary leads ( 2) and (3) are bent and connected to each lead 5.

다음에, 상기 칩(1)(4)과 보조리드(2), (3)들을 수지(6)로 몰딩하고, 이 수지(6) 외부의 리드(5)를 굽힘성형함으로써 반도체 패키지(7)를 제조할 수 있게 된다. 또한, 제 2 도에 나타낸 바와 같이 상기한 바와 같은 방법으로 제조되는 1쌍의 칩(1), (4)과 보조리드(2), (3)들을 1조로 하여 하나의 패키지(8)내에 리드(5)를 중심으로 하여 상하측에 2조의 칩(1), (4)과 보조리드(2), (3)들을 실장할 수 있게 된다.Next, the semiconductor package 7 is formed by molding the chips 1, 4, auxiliary leads 2, and 3 with a resin 6, and bending the leads 5 outside the resin 6. It can be prepared. In addition, as shown in FIG. 2, a pair of chips 1, 4, auxiliary leads 2, and 3, which are manufactured by the method described above, is used as a pair and leads into one package 8 It is possible to mount two sets of chips (1), (4) and auxiliary leads (2) and (3) on the upper and lower sides with the center of (5).

그러나, 상기한 바와 같은 제조방법에 의하여 제조되는 반도체 패키지(7), (8)들을 2개의 칩(2), (4)이 서로 반대방향으로 적층되므로 회로패턴이 서로 대칭인 칩(1), (4)을 사용하여야만 하며, 35㎛정도의 보조리드(2), (3)에 의해 리드(5)와 접촉되어 있으므로 칩(1), (4)을 지지하는 보조리드(2), (3)의 범프(1a), (4a)의 취약함으로 인하여 본딩불량을 일으킬 염려가 있다. 더욱이, 상기한 바와 같은 반도체 패키지(7), (8)는 보조리드(2), (3)와 칩(1), (4)을 접착하기 위한 공정과, 보조리드(2), (3)를 리드(5)와 상, 하부에 접속하기 위한 공정 등의 복잡한 과정을 거쳐야만 하며, 보조리드(2), (3)를 리드(5)에 접속하기 위한 포밍(Forming)공정시에 보조리드(2), (3)와 칩(1), (4)의 접속부가 쇼트(Short)될 위험이 있는 것이었다.However, since the two chips 2 and 4 are stacked in opposite directions to the semiconductor packages 7 and 8 manufactured by the manufacturing method as described above, the chips 1 having a symmetrical circuit pattern, (4) must be used, and the auxiliary leads (2) and (3) supporting the chips (1) and (4) are in contact with the leads (5) by the auxiliary leads (2) and (3) of about 35 μm. Due to the weakness of bumps (1a) and (4a) of), there is a risk of bonding failure. Furthermore, the semiconductor packages 7 and 8 as described above are bonded to the auxiliary leads 2 and 3 and the chips 1 and 4, and the auxiliary leads 2 and 3, respectively. Must be subjected to a complex process such as a process for connecting the lead 5 to the upper and lower parts, and the auxiliary lead during the forming process for connecting the auxiliary leads 2 and 3 to the lead 5. 2), (3) and the chip (1), (4) the connection was a risk of short.

이 발명은 상기한 바와 같은 종래의 문제점을 감안하여 이루어진 것으로서, 이 발명의 목적은 하나의 패키지내에 2개이상의 칩을 연속제조공정을 실장할 수 있도록 함으로써 제조공정을 단순화하고 코스트를 절감시킬 수 있는 반도체 패키지 및 그 제조방법을 제공함에 있다.The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to simplify the manufacturing process and reduce the cost by enabling the continuous manufacturing process of two or more chips in one package. A semiconductor package and a method of manufacturing the same are provided.

상기한 바와 같은 목적을 달성하기 위한 이 발명의 특징은, 하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하양측에 형성되는 범프와 각각의 리드들을 연결하여 수지로 밀봉하여서 된 반도체 패키지의 제조 방법에 있어서, 상기 회로패턴이 형성된 칩상의 본딩패드를 범프를 향상하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또 다른 칩을 탑재하여 접착시킨 후 리드들과 와이어 본딩하는 단계와, 상기 칩들을 수지로 밀봉하여 패키지를 성형한 후 외부 리드들을 굽힘성형하는 단계로 이루어지는 반도체 패키지의 제조방법에 있다.A feature of the present invention is to stack a plurality of chips in one package, connect bumps formed on the upper and lower sides of the chips, and seal each of the leads with a resin. A manufacturing method comprising the steps of: improving a bump on a chip-shaped bonding pad on which a circuit pattern is formed and adhering leads on the bump; attaching a polyimide tape on the lead and mounting another chip on the tape; And bonding the leads to wires after bonding, and sealing the chips with a resin to form a package, and then bending external leads.

이 발명의 또 다른 특징은, 하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하양측에 형성되는 범프와 리드들을 연결하여 수지로 밀봉하여서 된 반도체 패키지에 있어서, 상기 리드들을 사이에 두고 상하양측에 복수의 칩을 적층하여 상기 리드에 접착되도록 하고, 어느 하나의 칩에 범프를 형성하여 상기 리드들과 각각 와이어로 연결한 후 수지로 밀봉하여서 된 반도체 패키지에 있다.A further feature of the present invention is a semiconductor package in which a plurality of chips are stacked in one package, and bumps and leads formed on the upper and lower sides of the chips are connected and sealed with a resin. The semiconductor package is formed by stacking a plurality of chips on both sides so as to be bonded to the leads, and forming bumps on any one of the chips, connecting the leads with wires, and sealing the resin with resins.

이하, 이 발명의 실시예를 첨부도면에 따라 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 3 도 내지 제 5 도는 이 발명에 따른 반도체 패키지 및 그 제조방법을 설명하기 위한 도면으로서, 먼저 이 발명에 따른 반도체 패키지는 제 3e 도에 나타낸 바와 같이 2개의 칩(11)(14) 사이에 리드(12)들이 위치하여 이 리드(12)들을 사이에 두고 상기 칩(11), (14)들이 접착되도록 하며, 상기 어느 하나의 칩(14)상에 범프를 형성하여 각각의 리드(12)들과 와이어(15)로 연결한후에 수지(16)로 밀봉한 후에 패키지(17) 외부에 리드(12)들을 굽힘성형함으로써 이루어진다.3 to 5 illustrate a semiconductor package and a method of manufacturing the same according to the present invention. First, the semiconductor package according to the present invention is formed between two chips 11 and 14 as shown in FIG. Leads 12 are positioned so that the chips 11, 14 are bonded to each other with the leads 12 interposed therebetween, and bumps are formed on any one chip 14 so that each lead 12 By connecting the wires with the wires 15 and sealing with the resin 16 and then bending the leads 12 outside the package 17.

또한, 상기 리드(12)에 접착되는 칩(11), (14)은 그 어느 하나의 칩, 예를 들면 리드(12)의 하측에 접착되는 칩(11)은 이 칩(11)상의 본딩패드(도시생략)에 범프(11a)를 형성하여 리드(12)에 접착되도록 하고, 상기 리드(12)의 상측에 접착되는 칩(14)은 리드(12)와의 사이에 폴리아미드 테이프(13)를 개재하여 상기 리드(12)와 접착되도록 하고 있다.In addition, the chips 11 and 14 bonded to the lead 12 are any one chip, for example, the chip 11 bonded to the lower side of the lead 12 is a bonding pad on the chip 11. A bump 11a is formed on the lead 12 so as to be bonded to the lead 12, and the chip 14 adhered to the upper side of the lead 12 has a polyamide tape 13 between the lead 12. It interposes with the said lead 12 through it.

그리고, 제 4a,b 도에 나타낸 바와 같이, 리드(12)를 사이에 두고 상하양측에 접착된 2개의 칩(11), (14)을 1조로 하여 또 다른 1쌍의 칩(11), (14)을 대칭으로 접착하여 수지(16)로 밀봉함으로써 하나의 패키지(18)내에 4개의 칩을 실장할 수 있다.As shown in Figs. 4A and 4B, another pair of chips 11 and (2) are used as a pair of two chips 11 and 14 bonded to the upper and lower sides with the lead 12 therebetween. Four chips can be mounted in one package 18 by symmetrically bonding 14 and sealing them with resin 16.

다음에, 이 발명에 따른 반도체 패키지의 제조방법에 대하여 설명한다. 제 3a~e 도에 나타낸 바와 같이, 회로패턴이 형성된 칩(11)상의 본딩패드에 범프(11a)를 형성하고, 이 범프(11a)상에 리드(12)들을 열압착방식에 의해 접착시킨다.Next, the manufacturing method of the semiconductor package which concerns on this invention is demonstrated. As shown in Figs. 3A to E, bumps 11a are formed on the bonding pads on the chip 11 on which the circuit patterns are formed, and the leads 12 are bonded to the bumps 11a by thermocompression bonding.

상기와 같은 상태에서 리드(12)의 폴리이미드 테이프(13)를 접촉시키고, 이 테이프(13)상에 또 다른 칩(14)을 실장한다.In the above state, the polyimide tape 13 of the lead 12 is contacted, and another chip 14 is mounted on the tape 13.

그 후에, 상기 칩(14)과 리드(12)들을 와이어(15)로 연결한 후 수지(16)로 몰딩하여 패키지(17)를 성형하고 패키지(17)외부의 리드(12)들을 굽힘성형함으로써 연속 제조공정으로 반도체 패키지(17)를 제조한다. 한편, 제 4a,b 도는 이 발명에 따른 반도체 패키지의 제조방법의 다른 실시예를 나타낸 도면으로서, 상술한 바와 같이 하여 제조되는 반도체 패키지의 몰딩전에 다른 1조의 칩(11), (14)들을 동시에 몰딩하여 하나의 패키지(18)내에 4개의 칩을 실장할 수 있는 것이다.Thereafter, the chip 14 and the leads 12 are connected by a wire 15 and then molded with a resin 16 to form a package 17 and by bending the leads 12 outside the package 17. The semiconductor package 17 is manufactured by a continuous manufacturing process. 4A and 4B show another embodiment of a method of manufacturing a semiconductor package according to the present invention, in which different sets of chips 11 and 14 are simultaneously placed before molding a semiconductor package manufactured as described above. By molding, four chips can be mounted in one package 18.

즉, 제 3d 도와 같이 진행된 상태의 제조공정후에 또 다른 1쌍의 칩(11), (14)들을 대칭으로 접촉시킨 후 수지(16)로 몰딩하여 하나의 패키지(18)내에 4개의 칩들을 실장할 수 있도록 하고, 상기 수지(16)의 외부로 패키지(18)내에 4개의 칩들을 실장할 수 있도록 하고, 상기 수지(16)의 외부로 노출된 리드(12)들을 굽힘성형하면 되는데, 이때 제 4b 도에서와 같이 상측의 리드(12)와 하측의 리드(12)가 서로 연결되도록 한다. 또한, 제 5a,b 도는 리드 프레임(19)상에 각각의 칩(11), (14)들이 부착되는 상태를 나타낸 것으로서, 하단의 칩(11)에는 범프(도시생략)가 형성되어 리드프레임(19)이 칩(11)과 열압착 방식에 의해 접착되고, 이 리드프레임(11)상에는 폴리이미드 테이프(13)가 접착되어 이 테이프(13)와 또 다른 칩(14)이 접착되며, 이 칩(14)과 리드프레임(19)이 와이어(15)로 연결되는 것이다.That is, after the manufacturing process in the state of the 3d diagram, another pair of chips 11 and 14 are symmetrically contacted, and then molded with resin 16 to mount four chips in one package 18. It is possible to mount the four chips in the package 18 to the outside of the resin 16, and to bend the leads 12 exposed to the outside of the resin 16. As shown in FIG. 4B, the upper lead 12 and the lower lead 12 are connected to each other. In addition, as shown in the 5a, b or the lead frame 19, each chip 11, 14 is attached to the state, the lower chip 11 is formed with a bump (not shown) lead lead ( 19 is bonded to the chip 11 by a thermocompression bonding method, and a polyimide tape 13 is attached to the lead frame 11 to bond the tape 13 to another chip 14. 14 and the lead frame 19 are connected by a wire 15.

이상에서와 같이 이 발명에 따른 반도체 패키지 및 그의 제조방법에 의하면, 하나의 패키지내에 2개이상의 칩을 연속제조공정으로 실장할 수 있도록 함으로써 제조공정을 단순화하고 코스트를 절감시킬 수 있는 것이다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, by allowing two or more chips to be mounted in a continuous manufacturing process in one package, it is possible to simplify the manufacturing process and reduce the cost.

Claims (4)

하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하 양측에 형성되는 범프와 각각의 리드들을 연결하여 수지로 밀봉하여서된 반도체 패키지의 제조방법에 있어서; 상기 회로패턴이 형성된 칩상의 본딩패드에 범프를 형성하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또 다른 칩을 탑재하여 접착시킨후, 리드들과 와이어 본딩하는 단계와; 상기 칩들을 수지로 밀봉하여 패키지를 성형한 후, 외부리드들을 굽힘성형하는 단계로 이루어지는 반도체 패키지의 제조방법.A method for manufacturing a semiconductor package, comprising: stacking a plurality of chips in one package, connecting bumps formed on the upper and lower sides of the chips, and sealing the leads with resins; Forming bumps on the bonding pads on the chip on which the circuit pattern is formed and adhering the leads on the bumps, attaching a polyimide tape on the leads and mounting and bonding another chip on the tapes, Wire bonding with the fields; Forming a package by sealing the chips with a resin and then bending the outer leads. 하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하 양측에 형성되는 범프와 리드들을 연결하여 수지로 밀봉하여서 된 반도체 패키지에 있어서, 상기 리드들을 사이에 두고 상하 양측에 복수의 칩을 적층하여 상기 리드에 접착되도록 하고, 어느 하나의 칩에 범프를 형성하여 상기 리드들과 각각 와이어로 연결한 후, 수지로 밀봉하여서 된 반도체 패키지.In a semiconductor package in which a plurality of chips are stacked in one package, and bumps and leads formed on the upper and lower sides of the chips are connected and sealed with a resin, a plurality of chips are stacked on both upper and lower sides with the leads interposed therebetween. And a bump formed on any one chip to connect the wires to the leads, and then sealed with a resin. 제 2 항에 있어서, 상기 리드에 접착되는 각각의 칩이 범프와 폴리이미드 테이프에 의해 접착되도록 한 반도체 패키지.The semiconductor package according to claim 2, wherein each chip bonded to the lead is bonded by bumps and polyimide tape. 제 2 항 또는 제 3 항에 있어서, 상기 2개의 칩과 이들 사이에 위치한 리드를 한쌍으로 하여 또 다른 1쌍의 칩과 리드들을 대칭으로 적층한 후, 수지로 밀봉하여 하나의 패키지 내에 4개의 칩을 실장하여서 된 반도체 패키지.The chip of claim 2 or 3, wherein the two chips and the leads located therebetween are paired, and another pair of chips and the leads are symmetrically stacked, and then sealed with resin and four chips in one package. The semiconductor package was mounted.
KR1019910016778A 1991-09-26 1991-09-26 Package of semiconductor device and manufacturing method thereof KR940010535B1 (en)

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Publication number Priority date Publication date Assignee Title
KR100687066B1 (en) * 2000-07-10 2007-02-27 삼성전자주식회사 Manufacturing method for multi chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100687066B1 (en) * 2000-07-10 2007-02-27 삼성전자주식회사 Manufacturing method for multi chip package

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