KR930006869A - Manufacturing method of semiconductor package - Google Patents
Manufacturing method of semiconductor package Download PDFInfo
- Publication number
- KR930006869A KR930006869A KR1019910016778A KR910016778A KR930006869A KR 930006869 A KR930006869 A KR 930006869A KR 1019910016778 A KR1019910016778 A KR 1019910016778A KR 910016778 A KR910016778 A KR 910016778A KR 930006869 A KR930006869 A KR 930006869A
- Authority
- KR
- South Korea
- Prior art keywords
- chips
- package
- leads
- manufacturing
- bump
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000011347 resin Substances 0.000 claims abstract 5
- 229920005989 resin Polymers 0.000 claims abstract 5
- 238000000034 method Methods 0.000 claims abstract 4
- 239000004642 Polyimide Substances 0.000 claims abstract 3
- 238000005452 bending Methods 0.000 claims abstract 3
- 229920001721 polyimide Polymers 0.000 claims abstract 3
- 238000007789 sealing Methods 0.000 claims abstract 3
- 238000000465 moulding Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
이 발명은 반도체 패키지의 제조방법에 관한 것으로서, 회로패턴이 형성된 칩상의 본딩패드에 범프를 형성하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또다른 칩을 탑재하여 접착시킨후 리드들과 와이어 본딩하는 단계와, 상기 칩들을 수지로 밀봉하여 패키지를 형성한 후 외부 리드들을 굽힘성형하는 단계들로 하여 하나의 패키지내에 2개 이상의 칩을 실장할수 있도록 함으로써 패키지이 고접적화 및 전자기기의 소형화를 이룰수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, the method comprising: forming a bump on a bonding pad on a chip on which a circuit pattern is formed and adhering leads on the bump, attaching a polyimide tape on the lead, Mounting two or more chips in one package by mounting and bonding another chip, wire bonding with leads, and sealing the chips with resin to form a package, and then bending external leads. The package enables high integration and miniaturization of electronics.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도의 (가)∼(마)는 이발명에 따른 반도체 패키지의 제조공정을 설명하기 위한 도면,3A to 3E are views for explaining a manufacturing process of a semiconductor package according to the present invention;
제4도의 (가),(나)는 이발명에 따른 반도체 패키지를 이중으로 적층한 상태를 설명하기 위한 도면,(A) and (b) of FIG. 4 are diagrams for explaining a state in which the semiconductor packages according to the present invention are stacked in duplicate,
제5도의 (가),(나)는 이 발명에 따른 리드프레임에 칩이 접착되는 것을 설명하기 위한 도면이다.(A) and (b) of FIG. 5 are diagrams for explaining the bonding of the chip to the lead frame according to the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910016778A KR940010535B1 (en) | 1991-09-26 | 1991-09-26 | Package of semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910016778A KR940010535B1 (en) | 1991-09-26 | 1991-09-26 | Package of semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930006869A true KR930006869A (en) | 1993-04-22 |
KR940010535B1 KR940010535B1 (en) | 1994-10-24 |
Family
ID=19320366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910016778A KR940010535B1 (en) | 1991-09-26 | 1991-09-26 | Package of semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940010535B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100687066B1 (en) * | 2000-07-10 | 2007-02-27 | 삼성전자주식회사 | Manufacturing method for multi chip package |
-
1991
- 1991-09-26 KR KR1019910016778A patent/KR940010535B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940010535B1 (en) | 1994-10-24 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
AMND | Amendment | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application | ||
J2X1 | Appeal (before the patent court) |
Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL |
|
G160 | Decision to publish patent application | ||
B701 | Decision to grant | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060928 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |