KR930006869A - Manufacturing method of semiconductor package - Google Patents

Manufacturing method of semiconductor package Download PDF

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Publication number
KR930006869A
KR930006869A KR1019910016778A KR910016778A KR930006869A KR 930006869 A KR930006869 A KR 930006869A KR 1019910016778 A KR1019910016778 A KR 1019910016778A KR 910016778 A KR910016778 A KR 910016778A KR 930006869 A KR930006869 A KR 930006869A
Authority
KR
South Korea
Prior art keywords
chips
package
leads
manufacturing
bump
Prior art date
Application number
KR1019910016778A
Other languages
Korean (ko)
Other versions
KR940010535B1 (en
Inventor
송영재
이충우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910016778A priority Critical patent/KR940010535B1/en
Publication of KR930006869A publication Critical patent/KR930006869A/en
Application granted granted Critical
Publication of KR940010535B1 publication Critical patent/KR940010535B1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

이 발명은 반도체 패키지의 제조방법에 관한 것으로서, 회로패턴이 형성된 칩상의 본딩패드에 범프를 형성하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또다른 칩을 탑재하여 접착시킨후 리드들과 와이어 본딩하는 단계와, 상기 칩들을 수지로 밀봉하여 패키지를 형성한 후 외부 리드들을 굽힘성형하는 단계들로 하여 하나의 패키지내에 2개 이상의 칩을 실장할수 있도록 함으로써 패키지이 고접적화 및 전자기기의 소형화를 이룰수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, the method comprising: forming a bump on a bonding pad on a chip on which a circuit pattern is formed and adhering leads on the bump, attaching a polyimide tape on the lead, Mounting two or more chips in one package by mounting and bonding another chip, wire bonding with leads, and sealing the chips with resin to form a package, and then bending external leads. The package enables high integration and miniaturization of electronics.

Description

반도체 패키지의 제조방법Manufacturing method of semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도의 (가)∼(마)는 이발명에 따른 반도체 패키지의 제조공정을 설명하기 위한 도면,3A to 3E are views for explaining a manufacturing process of a semiconductor package according to the present invention;

제4도의 (가),(나)는 이발명에 따른 반도체 패키지를 이중으로 적층한 상태를 설명하기 위한 도면,(A) and (b) of FIG. 4 are diagrams for explaining a state in which the semiconductor packages according to the present invention are stacked in duplicate,

제5도의 (가),(나)는 이 발명에 따른 리드프레임에 칩이 접착되는 것을 설명하기 위한 도면이다.(A) and (b) of FIG. 5 are diagrams for explaining the bonding of the chip to the lead frame according to the present invention.

Claims (4)

하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하양측에 형성되는 범프와 각각의 리드들을 연결하여 수지로 밀봉하여서된 반도체 패키지의 제조방법에 있어서, 상기 회로패턴이 형성된 칩상의 본딩패드에 범프를 형성하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또다른 칩을 탑재하여 접착시킨 후 리드들과 와이어 본딩하는 단계와, 상기 칩들을 수지로 밀봉하여 패키지를 성형한후 외부리드들을 굽힘성형하는 단계로 이루어지는 반도체 패키지의 제조방법.A method of manufacturing a semiconductor package in which a plurality of chips are stacked in one package, and bumps formed on the upper and lower sides of the chips and respective leads are sealed to each other to seal the resin with a bonding pad on a chip on which the circuit pattern is formed. Forming a bump and adhering the leads on the bump, attaching a polyimide tape on the lead and mounting another chip on the tape to bond, followed by wire bonding with the leads; A method of manufacturing a semiconductor package comprising the step of bending the outer leads after molding the package by sealing with a resin. 제1항에 있어서, 상기 2개의 칩이 동일방향으로 위치하도록 된 반도체 패키지의 제조방법.The method of claim 1, wherein the two chips are positioned in the same direction. 하나의 패키지내에 복수의 칩을 적층하고, 이 칩들의 상하 양측에 형성되는 범프와 각각의 리드들을 연결하고 수지로 밀봉하여서된 반도체 패키지의 제조방법에 있어서, 상기 회로패턴이 형성된 칩상의 본딩패드에 범프를 형성하고 이 범프상에 리드들을 접착시키는 단계와, 상기 리드상에 폴리이미드 테이프를 부착시키고 이 테이프상에 또다른 칩을 탑재하여 접착시킨 후 리드들과 와이어 본딩하는 단계와, 상기 2개의 칩과 이들사이에 위치한 리드를 1쌍으로 하여 또다른 1쌍의 칩들을 대칭으로 적층하여 하나의 패키지내에 4개의 칩을 적층시키는 단계와, 상기 칩들을 수지로 밀봉하여 패키지를 성형한후 외부 리드들을 굽힘 성형하는 단계로 이루어지는 반도체 패키지의 제조방법.A method of manufacturing a semiconductor package in which a plurality of chips are stacked in one package, bumps formed on the upper and lower sides of the chips, and respective leads are connected and sealed with a resin, wherein the bonding pattern on the chip on which the circuit pattern is formed is provided. Forming a bump and adhering the leads on the bump, attaching a polyimide tape on the lead and mounting another chip on the tape to bond, followed by wire bonding with the leads; Stacking four chips in one package by symmetrically stacking another pair of chips with a pair of chips and a lead located between them, and sealing the chips with resin to form a package, followed by an external lead Method of manufacturing a semiconductor package comprising the step of bending the mold. 제3항에 있어서, 상기 다른 쌍을 이루는 리드들이 패키지 외부에서 서로 연결되도록 한 반도체 패키지의 제조방법.The method of claim 3, wherein the other pair of leads are connected to each other outside the package. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016778A 1991-09-26 1991-09-26 Package of semiconductor device and manufacturing method thereof KR940010535B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910016778A KR940010535B1 (en) 1991-09-26 1991-09-26 Package of semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910016778A KR940010535B1 (en) 1991-09-26 1991-09-26 Package of semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR930006869A true KR930006869A (en) 1993-04-22
KR940010535B1 KR940010535B1 (en) 1994-10-24

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Publication number Priority date Publication date Assignee Title
KR100687066B1 (en) * 2000-07-10 2007-02-27 삼성전자주식회사 Manufacturing method for multi chip package

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