TWI772672B - Chip packaging method and chip packaging structure - Google Patents

Abstract

A chip packaging method and a chip packaging structure are disclosed. The chip packaging method includes: providing a wafer and forming a protective layer on an wafer active surface; sawing the wafer into several dies; providing a metal structure which includes at least one metal unit; mounting the dies and the metal structure on the carrier; forming a plastic encapsulating layer. The chip structure includes: at least one die; a protective layer; a metal unit which includes at least one metal feature; a plastic encapsulating layer used to encapsulate the dies and the metal unit; wherein the chip structure is capable of connecting to an external circuit through the at least one metal feature. The disclosure improves the packaging performance by using multiple metal features of the metal unit. In addition, the protective layer is formed on the wafer active surface, which makes a step of applying insulating layer can be omitted after implementing the step of forming the plastic encapsulating layer.

Description

Chip packaging method and chip structure

The present disclosure relates to the field of semiconductor technology, and in particular, to a chip packaging method and a chip structure.

Panel-level package is to cut the wafer to separate many dies, arrange and paste the dies on the carrier board, and package the many dies simultaneously in the same process flow. As a technology emerging in recent years, panel-level packaging has received widespread attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and suitable for mass production.

The present disclosure aims to provide a chip packaging method, the chip packaging method includes: providing a wafer, forming a protective layer on the active surface of the wafer; cutting and separating the wafer to form crystal grains; providing a metal structure, the metal structure includes at least A metal unit; mounting the die and metal structure on a carrier board; forming a plastic encapsulation layer.

The present disclosure also provides a wafer structure including: at least one die; a protective layer; a metal unit, the metal unit including at least one metal feature; a plastic encapsulation layer for encapsulating the die and the metal unit; Wherein the chip structure is connected with the external circuit through at least one metal feature.

The present disclosure achieves the enhancement of packaging performance due to different metal features by utilizing multiple metal features of a metal unit.

The metal features may include a connection structure and a heat dissipation structure. The connection structure is connected to the electrical connection points on the active surface of the die in the wafer through the conductive structure. The packaged wafer structure passes through the connection structure and external circuit elements, such as PCB boards. connection, thereby replacing the structure of wire bonding. Compared with the wire bonding package structure, the present disclosure has a simple packaging process, avoids the mutual interference of signals between the leads in the wire bonding structure, and avoids the noise generated by the leads due to vibration when the chip is working. In addition, the connection structure is used to replace the lead structure, which is more suitable for chip packaging with large electric flux.

Further, the die arranged on the carrier board together with the metal structure is the die with a protective layer. Since in the present disclosure, the die arranged on the carrier already has a protective layer, so in the forming step of the plastic sealing layer After that, the step of forming the panel-level conductive layer can be directly performed without the step of applying the insulating layer first. Especially in large-sized panels, if an insulating layer is formed on the entire panel, first of all, the process difficulty is much greater than that of forming a small-area protective layer, and secondly, forming an insulating layer on the entire panel will also reduce the amount of insulating layer materials used. increase.

Furthermore, the protective layer and the plastic encapsulation layer used in the present disclosure have certain material properties, and the material properties can help reduce the warpage during the encapsulation of the panel and enable the encapsulated chip structure to have a durable life cycle, especially It is suitable for large panel level packaging and packaging of high current flux and thin chips.

100: Wafer

1001: Wafer Active Surface

1002: Wafer backside

103: Electrical connection point

105: Insulation layer

106: Wafer Conductive Traces

107: Protective layer

109: Protective layer opening

109a: Lower surface of protective layer opening

109b: upper surface of protective layer opening

109c: Protective layer opening sidewall

111: conductive bump

113: Die

113a: grain

113b: grain

1131: Grain Active Surface

1132: Die backside

117: carrier board

1171: front side of carrier board

1172: Back of carrier board

121: Adhesive layer

123: Plastic layer

1231: Front of plastic layer

1232: The back of the plastic layer

124: Conductive Filled Vias

125: Conductive traces

129: Dielectric layer

130: Wafer Conductive Layer

131: Surface treatment layer

150: Panel Module

200: Metal Frame

201: Connection Pad

202: vacancy

203: connecting rod

205: Backside heat sink

207: Thermal Pad

209: Thermally Conductive Materials

210: Metal Layer

211: Conductive glue

300: Temporary support plate

301: Adhesive layer

500: Wafer

S1~S9: Steps

FIG. 1 is a flowchart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure; 2 to 15 are schematic flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure; FIGS. 16 to 20 are schematic flowcharts of a chip packaging method proposed according to another exemplary embodiment of the present disclosure; Fig. 25 is a schematic flowchart of a chip packaging method proposed according to still another exemplary embodiment of the present disclosure; Figs. 26 to 28 are schematic flowcharts of a chip packaging method proposed according to still another exemplary embodiment of the present disclosure; Figs. 29a, 29b, 29c, 29d, and 29e are schematic diagrams of the chip structure obtained by the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; FIG. 30 is a schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure.

In order to make the technical solutions of the present disclosure clearer and the technical effects clearer, the preferred embodiments of the present disclosure will be described and explained in detail below with reference to the accompanying drawings. public restrictions.

FIG. 1 is a flowchart of a chip packaging method according to Embodiment 1 of the present disclosure. 1, the method of the present disclosure includes the steps of:

In step S1, the wafer 100 is provided.

As shown in FIG. 2, at least one wafer 100 is provided, the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002, the wafer 100 includes a plurality of die 113, wherein the active surface of each die constitutes a die The circular active surface 1001, the active surface of each die in the wafer 100 forms a series of active components and passive components through a series of processes such as doping, deposition, and etching. Components include diodes, triodes, etc., and passive components include voltages, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits to achieve various functions. The active surface 1001 of the wafer further includes an electrical connection point 103 for drawing out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103 .

In step S2, a protective layer 107 is applied on the active surface 1001 of the wafer.

FIGS. 3a-3b show optional process steps of applying the protective layer 107 on the active surface 1001 of the wafer: as shown in FIG. 3a, the protective layer 107 is applied on the active surface 1001 of the wafer.

Preferably, the protective layer 107 is applied on the active surface 1001 of the wafer by lamination.

Optionally, before the step of applying the protective layer 107 on the active surface of the wafer 1001, physical and/or chemical treatment is performed on the active surface 1001 of the wafer and/or the protective layer 107 applied to the wafer 100, so that the protective layer 107 can be protected. The bond between layer 107 and wafer 100 is tighter. Optionally, the treatment method is plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, and introduce promotion modification groups between the wafer 100 and the protective layer 107, for example, with an affinity Surface modifier with organic and inorganic affinity groups to increase the adhesion between organic/inorganic interface layers.

As shown in FIG. 3 b , a protective layer opening 109 is formed on the surface of the protective layer 107 .

A protective layer opening 109 is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the wafer active surface 1001 to expose the electrical connection point 103 on the wafer active surface 1001 .

Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, each protective layer opening 109 in at least a part of the protective layer openings 109 corresponds to a plurality of electrical connection points 103 .

Optionally, at least a part of the electrical connection points 103 corresponds to a plurality of protective layer openings 109 .

Optionally, at least a part of the protective layer openings 109 do not have corresponding electrical connection points 103 , or at least a part of the electrical connection points 103 do not have corresponding protective layer openings 109 .

The protective layer openings are formed by laser patterning or photolithography patterning.

If laser patterning is used to form the protective layer opening, preferably, before the protective layer 107 is applied to the active surface of the wafer 1001 , an electroless plating process step is performed on the active surface of the wafer 1001 to form a conductive layer on the electrical connection point 103 . overlay. Optionally, the conductive cover layer is one or more layers of Cu, Ni, Pd, Au, and Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive cover layer is not shown in the figures. The conductive cover layer can protect the electrical connection points 103 on the active surface 1001 of the wafer from laser damage during the subsequent steps of forming the protective layer openings.

Preferably, as shown in the partial enlarged view in FIG. 3b, there is a gap between the lower surface 109a of the protective layer opening and the insulating layer 105. Preferably, the lower surface 109a of the protective layer opening is at a position close to the center of the electrical connection point 103.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening, and the ratio of the area of the lower surface 109a of the protective layer opening to the area of the upper surface 109b of the protective layer opening 60%~90%.

At this time, the inclination of the sidewall 109c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the sidewall.

Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier plate.

Optionally, a conductive medium is filled in the protective layer openings 109 , so that the protective layer openings 109 become conductive filled vias 124 . At least a portion of the conductive filled vias 111 are connected to the electrical connection points 103 on the active surface 1001 of the wafer. The conductively filled vias 111 are made to extend the electrical connection points 103 on the wafer active surface 1001 to the surface of the protective layer unilaterally, and the protective layer is formed around the conductively filled vias 111 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or combinations thereof, or can be other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metals A deposition process is formed to form conductive filled vias 111 in the protective layer openings 109 .

FIGS. 4a-4c show another optional process step of applying the protective layer 107 on the active surface of the wafer 1001 : as shown in FIG. 4a , the conductive layer 130 of the wafer is formed on the active surface 1001 of the wafer.

The wafer conductive layer 130 is the wafer trace 106 . The wafer conductive traces 106 can be made of materials such as copper, gold, silver, tin, aluminum, or combinations thereof, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electroless plating, or Other suitable metal deposition processes are formed.

At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, the conductive traces 106 of the wafer interconnect and lead out the plurality of electrical connection points 103 in at least a portion of the active surface 1001 of the wafer to each other, and the die thus formed is shown in schematic diagram A of the die in FIG. 6b.

The formation of the wafer conductive traces 106 can reduce the number of protective layer openings 109 formed in the subsequent process. The wafer conductive traces 106 are used to first interconnect the plurality of electrical connection points 103 according to the circuit design, eliminating the need for each electrical connection. Requirement of forming protective layer openings 109 on the connection points 103 .

Optionally, at least a part of the electrical connection points 103 on the active surface 1001 of the wafer are independently drawn out by the conductive traces 106 of the wafer, and the die formed by this is shown in the schematic diagram B of the die in FIG. 6b.

The formation of the wafer conductive traces 106 helps to reduce the difficulty of the subsequent formation of the protective layer opening 109. Due to the existence of the wafer conductive traces 106, the lower surface 109a of the protective layer opening can have a larger area, corresponding to , the protective layer opening 109 can have a larger area, especially on the wafer 100 with smaller exposed electrical connection points 103 , making the formation of the protective layer opening possible.

Although not shown in the figure, it can be understood that the conductive traces 106 of the wafer lead out a part of the electrical connection points 103 on the active surface of the wafer 1001 individually and connect another part of the electrical connection points 103 on the active surface of the wafer 1001 to each other. Interconnect and lead out.

As shown in FIG. 4b, a protective layer 107 is applied on the active surface 1001 of the wafer and the conductive layer 130 of the wafer.

In one embodiment, the protective layer 107 is applied by lamination.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the active surface 1001 of the wafer and/or the surface of the protective layer 107 applied on the wafer 100, so that the protective layer 107 is protected. The bond between the protective layer 107 and the wafer 100 is tighter. Optionally, the treatment method is plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, and introduce promotion modification groups between the wafer 100 and the protective layer 107, for example, with an affinity Surface modifier with organic and inorganic affinity groups to increase the adhesion between organic/inorganic interface layers.

As shown in FIG. 4 c , a protective layer opening 109 is formed on the surface of the protective layer 107 .

At least a part of the protective layer opening 109 is located corresponding to the wafer conductive layer 130, and the wafer conductive layer 130 is exposed through the protective layer opening 109; the protective layer opening 109 has a protective layer opening lower surface 109a and a protective layer opening upper surface 109b.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening. It is easy to perform, and the conductive material is formed uniformly and continuously on the sidewalls during the filling process.

Preferably, the contact area between the wafer conductive layer 130 and the single contact area of the electrical connection point 103 is smaller than the contact area between the wafer conductive layer 130 and the single contact area of the protective layer opening 109 .

When the type of the wafer 100 is that the exposed electrical connection points 103 have a small area, a conductive layer is formed on the active surface 1001 of the wafer, and then a protective layer opening is formed, which can effectively reduce the difficulty of forming the protective layer opening and avoid the protective layer opening. The opening lower surface 109a is too small, making it difficult to form the protective layer opening 109 .

The protective layer openings are formed by laser patterning or photolithography patterning.

Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier plate.

Optionally, a conductive medium is filled in the protective layer opening 109 , so that the protective layer opening 109 becomes a conductively filled through hole 124 , at least a part of the conductively filled through hole 124 is connected to the wafer conductive layer 130 , and the protective layer surrounds the conductively filled through hole 124 . all around.

FIGS. 5 a to 5 c illustrate yet another optional process step of applying the protective layer 107 on the active surface 1001 of the wafer.

As shown in FIG. 5a, wafer traces 106 are formed on the active surface 1001 of the wafer.

The wafer conductive traces 106 can be made of materials such as copper, gold, silver, tin, aluminum, or combinations thereof, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electroless plating, or Other suitable metal deposition processes are formed.

The at least a portion of the wafer conductive traces 106 may be for interconnecting and leading out a plurality of the electrical connection points 103 in at least a portion.

The at least a part of the conductive traces 106 on the wafer can also be independently drawn out of at least a part of the electrical connection points 103 , and the die formed therefrom is shown in the schematic diagram B of the die in FIG. 6 c .

As shown in FIG. 5b , wafer conductive studs 111 are formed on the pads or connection points of the wafer conductive traces 106 .

The shape of the conductive bumps 111 on the wafer may be round, or may be other shapes such as oval, square, line, and the like. The conductive bumps 111 on the wafer can be made of one or more layers of copper, gold, silver, tin, aluminum, etc., or a combination of materials, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electrodeless Electroplating process, or other suitable metal deposition process.

Optionally, the conductive bumps 111 of the wafer can also be directly formed at the electrical connection points 103 on the active surface 1001 of the wafer, and the electrical connection points 103 are drawn out.

Wafer conductive traces 106 and/or wafer conductive bumps 111 are referred to as wafer conductive layer 130 .

As shown in FIG. 5c , a protective layer 107 is applied on the wafer conductive layer 130 .

The protective layer 107 is applied on the wafer conductive layer 130 to cover the wafer conductive layer 130 .

In one embodiment, the protective layer is applied by lamination.

In one embodiment, the protective layer 107 is applied so that the protective layer 107 completely covers the conductive layer 130 of the wafer. In this case, after the protective layer 107 is applied, a thickness of the protective layer 107 is thinned to expose the conductive layer 130 . The surface of the wafer conductive layer.

In another embodiment, the thickness of the applied protective layer 107 is just enough to expose the surface of the conductive layer 130 of the wafer.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the active surface 1001 of the wafer on which the conductive layer 130 of the wafer is formed and/or the surface of the protective layer 107 applied on the wafer 100 to The bonding between the protective layer 107 and the wafer 100 is made tighter. Optionally, the treatment method is plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, and introduce promotion modification groups between the wafer 100 and the protective layer 107, for example, with an affinity Surface modifier with organic and inorganic affinity groups to increase the adhesion between organic/inorganic interface layers.

In step S2, during the process of applying the protective layer 107 to the active surface 1001 of the wafer, the protective layer 107 can protect the active surface 1131 of the die from infiltrating the plastic sealing material during the plastic sealing process, thereby protecting the active surface 1131 of the die from damage; at the same time, during the plastic sealing process , the plastic sealing pressure is not easy to cause the position movement of the die 113 on the carrier board 117 ; in addition, the alignment accuracy requirement in the subsequent panel-level conductive layer formation process can also be reduced.

The protective layer 107 adopts an insulating material, such as BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), polymer matrix dielectric film, organic polymer film, or Other materials with similar insulating and structural properties are formed by lamination, coating, printing, etc.

Preferably, the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000-10000 MPa; further preferred Young's modulus of the protective layer 107 It is 1000-7000, 4000-7000 or 4000-8000MPa; in the preferred embodiment, the Young's modulus of the protective layer 107 is 5500MPa.

Preferably, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably, the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; In a preferred embodiment, the thickness of the protective layer 107 is 45 μm; in another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus value of the protective layer 107 is in the range of 1000-20000MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; 107 has sufficient support for the conductive layer formed on its surface. Meanwhile, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffer and support.

Especially in some types of chips, it is necessary to use thin die for packaging, and the conductive layer needs to reach a certain thickness to form a large electric flux. The value of the Young's modulus of the layer 107 ranges from 1000 to 10000 MPa. The soft and flexible protective layer 107 can form a buffer layer between the die 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the wafer, the conductive layer on the surface of the protective layer will not excessively press the crystal. The die 113 is prevented from being broken by the pressure of the thick conductive layer. Meanwhile, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the material properties of the protective layer 107, The protective layer 107 can effectively protect the die against the ejector pressure of the die transfer equipment in the subsequent die transfer process.

The die transfer process is a process of rearranging and adhering the diced and separated die 113 to the carrier plate 117 (reconstruction process). The die transfer process requires the use of a bonder machine, which includes an ejector pin. , using an ejector pin to lift up the die 113 on the wafer 100 , and use a bonder head to suck up the lifted die 113 and transfer and bond it to the carrier board 117 .

During the process of ejecting the crystal grains 113 by the ejector pins, the crystal grains 113, especially the thin crystal grains 113, are brittle and easily broken by the ejection pressure of the ejector pins. The protective layer 107 with material characteristics can protect the brittle crystal grains in this process. The grains 113 can maintain the integrity of the crystal grains 113 even under a relatively large jacking pressure.

Preferably, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO ₂ particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, For example _SiO2 mixed with _TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, are spherical or spherical-like. In a preferred embodiment, the filling amount of filler particles, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, in the protective layer 107 is more than 50%.

The organic material has the advantages of easy operation and application. The die 113 to be encapsulated is made of an inorganic material such as silicon. When the protective layer 107 is made of an organic material alone, due to the difference between the material properties of the organic material and the material properties of the inorganic material , it will make the packaging process difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials can modify the material properties of organic materials, so that the materials have both the characteristics of organic materials and inorganic materials.

Especially the coefficient of thermal expansion (CTE) of the material, the silicon crystal grains 113 have a low coefficient of thermal expansion, usually about 3 ppm/K, and the protective layer 107 is an organic/inorganic composite material layer including filler particles, which can make the thermal expansion coefficient of the protective layer The reduction reduces the property difference between the organic layer and the inorganic layer in the encapsulation structure.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; In a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the following plastic sealing process, the die 113 on which the protective layer 107 is applied will expand and contract correspondingly during the heating and cooling process of the plastic sealing process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K, The degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, and the interface between the protective layer 107 and the die 113 is not easy to generate interface stress, and it is not easy to destroy the bond between the protective layer 107 and the die 113, so that the packaged The wafer structure is more stable.

In the process of using the packaged chip, it is often necessary to go through cold and heat cycles. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the cold and heat cycle, the protective layer 107 and the The die 113 maintains a relatively uniform degree of expansion and contraction, which prevents the interface fatigue from accumulating at the interface between the protective layer 107 and the die 113 , so that the packaged chip has durability and prolongs the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the protective layer 107 with too many filler particles, which will further reduce the thermal expansion coefficient and also increase the Young's modulus of the material, so that the protective layer material is The flexibility is reduced, the stiffness is too strong, and the buffering effect of the protective layer 107 is not good. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10 ppm/k.

When the step of forming the opening of the protective layer by means of laser patterning is included, preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, have a diameter of less than 3 μm, preferably the filler in the protective layer 107 The diameter of the particles, such as inorganic oxide particles, such as SiO2 particles, is between 1 and 2 μm.

The diameter of the filler particles is controlled to be less than 3 μm, which is beneficial to forming a protective layer opening with smooth sidewalls on the protective layer 107 in the laser patterning process, so that the material can be fully filled in the conductive material filling process to avoid having a large size Concave and convex protective layer open side The wall 109c cannot be filled with the conductive material on the rear side of the sidewall shielded by the protrusions, which affects the conductivity of the conductively filled via 124 .

At the same time, the filling size of 1-2 μm will expose the filler with small particle size during the laser patterning process, so that the sidewall 109c of the opening of the protective layer has a certain roughness. The contact surface is larger and the contact is tighter, and the conductive filled vias 124 with good conductivity are formed.

The diameter size of the above-mentioned filler is the average value of the particle diameter.

Optionally, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, grinding the back surface 1002 of the wafer to thin the wafer 100 to a desired thickness.

Modern electronic devices are small and lightweight, and the wafers tend to be thinner. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 are difficult, and the grinding and thinning are reduced. The process technology is difficult, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has the protective layer 107 , the protective layer 107 with material properties will support the wafer 100 , thereby reducing the difficulty of processing, transferring and thinning the wafer 100 .

In step S3 , the wafer 100 with the protective layer 109 applied is cut to form the die 113 with the protective layer 109 .

As shown in FIG. 6 a , the wafer 100 on which the protective layer 107 has been applied is diced along the dicing lines to obtain a plurality of die 113 formed with the protective layer. The die 113 has a die active surface 1131 and a die back surface 1132 .

As shown in FIG. 6b, the wafer 100 formed with the wafer conductive layer 130 and the protective layer opening 109 formed by applying the protective layer 107 is cut along the dicing road to obtain a plurality of die 113, and the die 113 has die Active side 1131 and die back side 1132.

The schematic diagram A of the die in FIG. 6b shows that the conductive traces 106 of the wafer interconnect and lead out the plurality of electrical connection points 103 on the active surface 1131 of the die.

The schematic diagram B of the die in FIG. 6b shows that the conductive traces 106 of the wafer lead out the electrical connection points 103 on the active surface 1131 of the die independently.

As shown in FIG. 6c , the wafer 100 on which the wafer conductive layer 130 and the protective layer 107 are applied is cut along the dicing road to obtain a plurality of die 113 . The die 113 has a die active surface 1131 and a die 1132 on the back.

The schematic diagram A of the die in FIG. 6c shows that the conductive traces 106 of the wafer interconnect and lead out the plurality of electrical connection points 103 on the active surface 1131 of the die.

The schematic diagram B of the die in FIG. 6c shows that the conductive traces 106 of the wafer independently lead out the electrical connection points 103 on the active surface 1131 of the die.

The schematic diagram C of the die in FIG. 6c shows that the conductive bumps 111 of the wafer are directly formed at the electrical connection points 103 on the active surface 1001 of the wafer, and the electrical connection points 103 are led out.

Optionally, before the step of dicing the wafer 100 to separate the die 113, it also includes performing a plasma surface treatment on the side with the protective layer 107 of the wafer 100 to which the protective layer 107 is applied to increase the surface roughness, so that the subsequent steps can be improved. During the process, the adhesion of the die 113 on the carrier plate 117 is increased, and it is difficult to cause the die movement of the die 113 under the molding pressure.

Due to the material properties of the protective layer, in the dicing process of the wafer 100 , the separated dies 113 are free of burrs and die chips.

It can be understood that, if the process allows, after the wafer 100 is selectively cut into the die 113 to be packaged according to the specific actual situation, a wafer conductive surface is formed on the die active surface 1131 of each die 113. layer 130 and/or protective layer 107 . The wafer conductive layer 130 refers to a conductive layer formed before the dies 113 cut from the wafer 100 are mounted on the carrier.

Step S4, providing a metal structure.

According to the embodiment shown in FIG. 7 , the metal structure is a metal frame 200 composed of an array of metal cells. The metal frame 200 may use an existing lead frame in the industry, or may be formed by etching or mechanical stamping a piece or/or a piece of metal according to actual requirements. The metal to be patterned can be a single metal, such as copper, or an alloy. Part or all of the metal surface may be coated with a second metal, such as nickel and/or gold, to protect the metal sheet from environmental attack, such as oxidation. The thickness of the metal is not less than the thickness of the crystal grains 113 . The metal to be engraved can be rectangular, square or other shapes. As shown in FIG. 7, the metal is engraved to include the same 4 metal units, and the outer contour of each metal unit is rectangular, which is also here. Exemplarily, the number of metal units is not limited to 4, and can be set according to actual needs. The shape of the metal unit can also be a rectangle or other shapes. The blank area in the metal unit indicates that the metal is completely etched away, and the remaining metal part includes metal features. , different metal characteristics can bring different performance improvements.

In FIG. 7 , the metal feature includes at least one connection pad 201. These connection pads 201 are arranged inside the contour edge of the metal frame 200, and can also be arranged at other positions according to actual needs. 203 connect. The connection pads 201 are equivalent to the pins of the packaged die. According to the present disclosure, after the die 113 is packaged, the connection pads 201 are exposed, and the packaged die 113 is soldered to the circuit board through these connection pads 201 , realize the connection with other circuit components. Keep the connecting rods 203 when the metal is engraved to ensure that the connection pads 201 and other features formed by engraving are connected to the outer contour of the metal frame 200, so that the engraving can be guaranteed when the metal frame 200 is transferred. The features on it will not drop. Optionally, the metal sheet can be attached to the temporary support for engraving first, and after the engraving is completed, the position of the metal frame can be transferred by means of the support. This method does not require engraving connecting lines/connecting rods.

As shown in FIG. 7 , each metal unit in the metal frame 200 includes a vacancy 202 . The vacancy 202 is shown as a blank area in the figure. The blank area is formed by completely etching part of the metal, and its area is larger than that of the die 113 . surface area, so that the die 113 and the metal frame 200 are pasted to the carrier board in a later step without touching the die 113 . According to the example in the figure, each metal unit includes one vacancy 202 , in another example, one metal unit may also include two or more vacancies 202 , each vacancy 202 accommodates one or more die 113 . Adjacent metal frames 200 have a common outline edge. As shown in FIG. 7 , the metal frame 200 in the upper left corner has a common outline edge with its right and lower metal frames 200, so that all the metal frames 200 have a common outline edge. 200 connected into one.

The metal frame 200 of the present disclosure as shown in FIG. 7 is only exemplary, the area of a single piece of metal may be the same as the surface area of the carrier plate 117, and the shape is also the same as the shape of the carrier plate 117, preferably a rectangle or a rectangle, but Other shapes can also be designed according to actual needs. However, during the experiment, it was found that when the area of the carrier plate 117 is relatively large, if the metal frame 200 is etched with the same metal as the carrier plate 117, since the metal is relatively thin, when the area of the carrier plate 117 is relatively large, during the transfer process It is easy to cause deformation and difficult to operate. Therefore, preferably, two or more pieces of metal having the same sum of area as the surface area of carrier plate 117 may be used, and one piece of metal may be etched on each piece of metal During the manufacturing process of the one or more metal frames 200 , each piece of metal after etching is sequentially arranged on the carrier plate 117 , and the surface area of the carrier plate 117 is the same when assembled together.

In step S5 , the die 113 with the protective layer 107 and the metal structure are arranged on the carrier board 117 .

Figures 8a-9 show a preferred embodiment of disposing the metal frame on the carrier in step S5.

Since the metal material used for the metal frame 200 is relatively thin, especially when the area is relatively large, the surface is easily deformed when being picked and placed. Therefore, in order to more conveniently adhere the metal frame 200 to the carrier plate 117 while maintaining a flat surface. , you can use the following methods: As shown in Figures 8a and 8b, a temporary support plate 300 is provided, an adhesive layer 301 is formed on its surface, and the engraved metal frame 200 is attached to the temporary support plate 300 by means of pasting. Optionally, Instead of using the temporary support plate 300 , the patterned metal frame 200 may be transported by directly using the thick adhesive layer 301 as the temporary support plate 300 . Preferably, the shape and size of the temporary support plate 300 , the adhesive layer 301 and the carrier plate 117 are the same.

Preferably, as shown in FIG. 8 a , after the metal frame 200 is pasted on the temporary support plate 300 , the connecting rods 203 are cut to separate the metal frame 200 . Optionally, each connecting rod 203 connecting each metal unit is cut, so that each metal unit pasted on the temporary support plate 300 is separated from each other; The metal frame 200 on the support plate 300 is separated into two parts, four parts, six parts, or any other number of parts. Preferably, the cutting line is along the center line of the connecting rod 203 . The advantages of this method are: in the packaging process, it is often necessary to undergo heating and cooling steps to separate an entire metal frame 200 into units with smaller areas, or directly into metal units separated from each other. In the heating and cooling step, the metal frame 200 or the metal units with smaller area expand and contract independently of each other. Due to the smaller area, the degree of expansion and contraction of each unit or unit is smaller, which makes the packaging process easier to control and operate.

Preferably, as shown in FIG. 8b, after the metal frame 200 is pasted on the temporary support plate 300, the connecting rod 203 is separated and removed from the metal frame 200, so as to separate the metal units in the metal frame 200, as shown in FIG. 8b The pads 201 are connected into separate parts. Since the features on the metal frame can be independent of each other, board-level testing can be performed before cutting, which can greatly reduce testing costs and time.

As shown in FIG. 9, a carrier board 117 is provided, the carrier board 117 having a carrier board front side 1171 and a carrier board back side 1172. The shape of the carrier board 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier board 117 can be a wafer substrate of small size, or a rectangular carrier board of various sizes, especially a large size. The material of 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-sized quadrilateral panel made of stainless steel.

The carrier board 117 has a carrier board front surface 1171 and a carrier board back surface 1172, and the carrier board front surface 1171 is a plane.

The die 113 is bonded and fixed on the carrier board 117 by the adhesive layer 121 .

The adhesive layer 121 can be formed on the front surface 1171 of the carrier board by means of lamination, printing, spraying, coating or the like. In order to facilitate the separation of the carrier board 117 and the back-molded die 113 in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, for example, a thermal separation material is used as the adhesive layer 121 .

The side of the temporary support plate 300 on which the metal frame 200 is attached faces the front surface 1171 of the carrier plate. The surface area of the temporary support plate 300 is the same as that of the carrier plate 117, and the shape is also the same. By aligning and contacting the two, the metal frame 200 can be attached to the adhesive layer 121 , then the temporary support plate 300 is peeled off, and the adhesive layer 301 on the metal frame 200 is removed, that is, the attachment of the metal frame 200 is completed.

In this step, preferably, the metal frame 200 is aligned on the carrier board 117 through the pre-formed alignment marks (the marks are not shown in the figure) on the carrier board 117 and the metal frame 200, Layer 301 adheres metal frame 200 to carrier plate 117 .

In addition, the metal foil or metal sheet can also be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300 , and then the metal foil or metal sheet can be etched into a desired pattern to form the engraved metal frame 200 , and then transfer the metal frame 200 to the carrier board 117 .

The side of the metal frame 200 facing the carrier board 117 is defined as the front side of the metal frame, and the side facing away from the carrier board 117 is defined as the back side of the metal frame. Metal Structure Front and Metal Structure Back, Metal Unit Front and Metal Unit Back, Metal Feature Front and Metal Feature Back are also defined accordingly.

FIG. 10 shows an embodiment of disposing the die 113 on the carrier plate 117 in step S5.

Since the metal frame 200 has already been pasted on the adhesive layer 121 on the front side 1171 of the carrier board, which is shown as the connection pad 201 in FIG. , in the present disclosure, the die 113 is pasted in the vacancy 202 of the metal frame 200 , and optionally one vacancy 202 corresponds to one die 113 or one vacancy 202 corresponds to multiple die 113 . Preferably, a position mark for the arrangement of the die 113 is set on the carrier board 117, and the mark can be formed on the carrier board 117 by means of laser, mechanical engraving, etc. When pasting, it is aligned with the pasting position on the carrier plate 117 . Figure 10 It is only an example diagram, and FIG. 10 only shows that the die 113 pasted on the adhesive layer 121 of the carrier board 117 is in the form of the die 113 having the protective layer 107 and the protective layer opening as shown in FIG. 6a; The die pasted on the adhesive layer 121 of the carrier board 117 may also be in the form of a die having the wafer conductive layer 130, the protective layer 107 and the protective layer opening 109 as shown in FIG. 6b, or the die in FIG. 6c. The die form is shown with wafer conductive layer 130 and protective layer 107 . Meanwhile, the metal frame 200 pasted on the adhesive layer 121 may also be a metal frame 200 with only the connecting rod 203 cut but not removed as shown in FIG. 8 a , or a metal frame 200 with a complete connecting rod 203 .

As shown in FIG. 10 , one metal unit corresponds to one die 113 , the number of die 113 on the carrier 117 is the same as the number of metal units on the carrier 117 , and the arrangement of the die 113 is the same as that of the metal units on the carrier 117 The arrangement corresponds to. The number and arrangement of metal units are not limited to those shown in FIG. 10 , but can be customized according to actual needs.

In addition, one metal unit can correspond to a plurality of die 113, and the plurality of die 113 are placed in the predetermined vacancy 202, especially the plurality of die is a plurality of die with different functions, which are arranged according to the requirements of the actual product The metal unit on the carrier board 117 is packaged, and after the package is completed, it is cut into a plurality of packages; thus, one package includes a plurality of dies to form a multi-chip module (MCM). ), and the positions of multiple dies can be freely set according to the needs of the actual product.

The installation sequence shown in FIGS. 9-10 is that the metal frame 200 is firstly mounted on the carrier board 117, and then the die 113 is mounted on the carrier board 117, but this is only an example, and the die 113 can also be mounted first. The pellets 113 are mounted on the carrier plate 117 , and then the metal frame 200 is mounted on the carrier plate 117 .

In step S6 , a plastic sealing layer 123 is formed on the carrier board 117 .

As shown in FIG. 11 , the plastic encapsulation layer 123 covers the entire carrier board 117 for encapsulating all the die 113 and the metal frame 200 , and is embodied as the connection pads 201 in FIG. After the carrier plate 117 is peeled off, the next encapsulation step can be continued on the reconstituted flat structure.

The surface of the plastic sealing layer 123 in contact with the front surface 1171 of the carrier or the adhesive layer 121 is defined as the front surface 1231 of the plastic sealing layer. The side of the plastic sealing layer 123 facing away from the front surface 1171 of the carrier or the adhesive layer 121 is defined as the back surface 1232 of the plastic sealing layer.

Preferably, the front surface 1231 of the plastic sealing layer and the back surface 1232 of the plastic sealing layer are substantially flat and parallel to the front surface 1171 of the carrier board.

The plastic sealing layer 123 may adopt paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic encapsulation layer 123 may be an organic composite material, a resin composite material, a polymer composite material, or a polymer composite material, such as epoxy resin with filler, ABF (Ajinomoto buildup film) or other polymers with suitable filler.

In one embodiment, the plastic sealing layer 123 is formed by using an organic/inorganic composite material by molding.

Optionally, before forming the plastic encapsulation layer 123, some pre-processing steps, such as chemical cleaning and plasma cleaning, may be performed to remove impurities on the surface of the die 113 and the metal frame 200, so that the plastic encapsulation layer 123 and the die 113 and the metal frame can be removed. 200 and the carrier board 117 can be connected more closely without delamination or cracking.

Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3-10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm/K; in another preferred embodiment The thermal expansion coefficient of the middle plastic sealing layer 123 is 7 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm/K.

Preferably, the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected to be 3~10ppm/K and the thermal expansion coefficient of the selected protective layer 107 is the same or similar. During the heating and cooling process of the plastic sealing process, the degree of expansion and contraction between the protective layer 107 and the plastic sealing layer 123 Keeping the same, the two materials are not easy to produce interface stress. The low thermal expansion coefficient makes the thermal expansion coefficient of the plastic sealing layer, the protective layer and the die close to each other, so that the interface of the plastic sealing layer 123, the protective layer 107 and the die 113 is tightly combined to avoid the generation of an interface layer. separation.

In the process of using the packaged chip, it is often necessary to go through cold and heat cycles. Since the thermal expansion coefficients of the protective layer 107 , the plastic sealing layer 123 and the die 113 are similar, during the cold and heat cycle, the protective layer 107 , the plastic sealing layer 123 and the die 113 have similar thermal expansion coefficients. The interface fatigue is small, and the interface gap is not easy to appear between the protective layer 107 , the plastic sealing layer 123 and the die 113 , so that the service life of the chip is prolonged, and the chip can be applied in a wide range of fields.

The difference in thermal expansion coefficient between the die 113 and the plastic sealing layer 123 will also cause warping of the panel module after plastic sealing. Due to the warping phenomenon, it is difficult to locate the die 113 in the panel module in the subsequent conductive layer forming process. The precise position of the conductive layer has a great influence on the formation process of the conductive layer.

In particular, in the large-panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the die of the outer and surrounding parts of the panel far from the center to have a larger size than before molding. position changes, so, in the large panel packaging process Among them, solving the warpage problem has become one of the keys to the entire process. The warpage problem even limits the enlargement of the panel size and becomes a technical barrier in the packaging of large-size panels.

The thermal expansion coefficients of the protective layer 107 and the plastic sealing layer 123 are limited within the range of 3-10 ppm/K, and preferably the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively avoid the warpage of the panel module. Enabling packaging processes using large panels.

At the same time, during the plastic sealing process, since the plastic sealing pressure will generate a pressure on the back of the die 113 toward the carrier plate 117 , the pressure is easy to press the die 113 into the adhesive layer 121 , so that the die 113 is formed during the process of forming the plastic sealing layer 123 . After the plastic sealing layer 123 is formed, the die 113 and the front surface 1231 of the plastic sealing layer are not in the same plane, and the surface of the die 113 protrudes beyond the front surface 1231 of the plastic sealing layer, forming a stepped structure. In the subsequent formation process of the panel-level conductive layer, the panel-level conductive layer will also have a stepped structure correspondingly, which makes the package structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the plastic sealing pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure on the front surface 1231 of the plastic sealing layer.

In order to expose the metal frame 200 , the plastic encapsulation layer 123 needs to be thinned, which can be thinned by mechanically grinding or polishing the back side 1232 of the plastic encapsulation layer, and the thickness of the plastic encapsulation layer 123 is reduced to the back of the metal frame 200 , thereby exposing the metal frame 200 features of the surface. As shown in FIG. 12 , when the thickness of the metal frame 200 is thicker than that of the die 113 , the plastic encapsulation layer can be further thinned to the backside of the die 113 , so that both the metal frame 200 and the backside of the die 113 are exposed.

In step S7 , the carrier plate 117 is peeled off to form the panel module 150 .

After the carrier plate 117 is peeled off, the protective layer 107 on the active surface 1131 of the die, the lower surface of the metal frame 200 and the front surface 1231 of the plastic sealing layer are exposed.

After the carrier 117 is separated, the structure of the plastic encapsulation layer 123 covered with the die 113 and the metal frame 200 is defined as the panel module 150 .

In step S8, a panel-level conductive layer and a dielectric layer 129 are formed.

A panel-level conductive layer is formed on the surface of the protective layer 107 , and the panel-level conductive layer is connected to the electrical connection points 103 on the active surface 1131 of the die through the wafer conductive layer 130 and/or the conductive filled vias 124 , and is connected to the metal frame 200 . A dielectric layer 129 is formed on the panel-level conductive layer, and the dielectric layer 129 is used to cover and protect the panel-level conductive layer. The panel-level conductive and dielectric layers 129 may be one layer or multiple layers.

As shown in FIG. 13 , the panel-level conductive layer is embodied as panel-level conductive traces 125 (panel level traces) in the figure. Since the conductive filled vias 124 have not been formed in the process flow shown in the figure, optional, conductive Filling vias 124 and panel-level conductive traces 125 occurs in the same conductive layer formation step. The conductive filled vias 124 and the panel-level conductive traces 125 are formed using a method of forming a patterned conductive layer. The conductive filled vias 124 and the panel conductive traces 125 can be made of materials such as copper, gold, silver, tin, aluminum or a combination thereof, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, non- Electrode plating process, or other suitable metal deposition process.

At least a portion of the panel-level conductive traces 125 are connected to the electrical connection points 103 on the active surface 103 of the die through the conductively filled vias 124 and are connected to the connection pads 201 , and the die is connected through the panel-level conductive traces 125 and the conductively filled vias 124 Electrical connection points 103 on the active surface lead to connection pads 201 .

The pattern traces of the panel-level conductive traces 125 in FIG. 13 are merely exemplary, and the pattern traces of the panel-level conductive traces 125 are connected according to specific circuit designs.

Optionally, the conductively filled vias 124 and the panel-level conductive traces 125 may also be formed in steps, and the conductively-filled vias 124 are formed first and then the panel-level conductive traces 125 are formed.

When the conductive filled vias 124 have been formed in the previous step of applying the protective layer, the step of forming the panel-level conductive layer can be directly performed.

When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 also needs to be included.

As shown in FIG. 14 , a dielectric layer 129 is formed on the panel-level conductive traces 125 .

The dielectric layer 129 is formed on the surface of the panel-level conductive layer using lamination, coating, spraying, printing, molding, and other suitable methods.

The dielectric layer 129 can be BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), ABF (Ajinomoto Build up Film), silicon dioxide, silicon nitride, oxynitride Silicon, tantalum pentoxide, alumina, polymer matrix dielectric film, organic polymer film; also organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with fillers Resin, ABF, or other polymers with suitable fillers; other materials with similar insulating and structural properties are also possible. Dielectric layer 129 is ABF in a preferred embodiment. The dielectric layer 129 functions to protect the conductive layer and to insulate.

As shown in FIG. 14 , the height of the dielectric layer 129 is higher than that of the panel-level conductive traces 125 , and the dielectric layer 129 completely encapsulates the panel-level conductive traces 125 .

Due to the existence of the protective layer 107 , the panel-level conductive layer formation step can be performed directly after the plastic sealing process is completed, avoiding the need to form the panel-level conductive layer formation step after forming the insulating layer after the plastic sealing process.

The panel-level conductive and dielectric layers 129 shown in FIGS. 13 and 14 have only one layer, but alternatively, the panel-level conductive and dielectric layers may be multiple layers.

When the panel-level conductive layer and the dielectric layer are multi-layered, the steps of forming the multi-layer panel-level conductive layer and the dielectric layer are: forming a first layer of panel-level conductive traces on the surface of the protective layer; The first-layer panel-level conductive bumps are formed on the electrical connection points for connecting with the first-layer panel-level conductive traces and leading them out; forming the first-layer panel-level conductive traces and the first-layer panel-level conductive bumps The first layer of dielectric layer covers the first layer of panel-level conductive traces and the first layer of panel-level conductive bumps and exposes the surface of the first-layer panel-level conductive bumps; A second-layer panel-level conductive trace connected to the first-layer panel-level conductive bump is formed on the surface, and the second-layer panel-level conductive trace is completely covered by the second-layer dielectric layer.

At this point, a package structure with two panel-level conductive and dielectric layers is formed.

By analogy, a package structure of multi-layer panel-level conductive layers and dielectric layers can be formed.

When the panel-level conductive layer and the dielectric layer are multi-layered, the step of forming the multi-layer panel-level conductive layer and the dielectric layer may also be: forming a first layer of panel-level conductive traces on the surface of the protective layer; A first layer of dielectric layer is formed on the first layer of panel-level conductive traces, and the thickness of the first layer of dielectric layer is greater than the thickness of the first layer of panel-level conductive traces, and it is completely covered; on the first layer of dielectric layer Laser patterning or photolithography is used to form openings on the layer, the openings are formed on the electrical connection points of the panel-level conductive traces of the first layer, and the electrical connection points of the panel-level conductive traces of the first layer are exposed; The material fills the openings and forms a second layer of panel-level conductive traces on the first layer of dielectric layer and at corresponding locations of the filled openings; and forms a second layer of dielectric layer on the second layer of panel-level conductive traces, the second layer of The thickness of the layer dielectric layer is thicker than that of the panel-level conductive traces of the second layer, and the panel-level conductive traces of the second layer are completely covered by the second-layer dielectric layer.

At this point, a package structure with two panel-level conductive and dielectric layers is formed.

By analogy, a package structure of multi-layer panel-level conductive layers and dielectric layers can be formed.

When each metal unit of the metal frame 200 corresponds to multiple dies 113 , especially multiple dies with different functions, the package becomes a multi-chip package module with metal features, and the panel-level conductive layers of the multiple dies are packaged. The pattern design is designed according to the electrical connection needs of the actual product. The packaged chip structure is shown in Figure 29e.

In step S8, in the step of forming a panel-level conductive layer and a dielectric layer 129 on the surface of the protective layer 107 of the die 113, as shown in FIG. 13 and FIG. 14, the die 113 as shown in FIG. 6a is used for encapsulation, It can be understood that the die shown in FIG. 6b can also be used for packaging, and the openings 109 of the protective layer are filled with conductive materials to form conductive filled vias 124, and at least a part of the conductive filled vias 124 are connected to the wafer conductive traces 106, Remove wafer conductive traces 106 from protective layer 107 Lead out, and form panel-level conductive traces 125 on the surface of the protective layer 107 . Preferably, the conductive filled vias 124 and the panel-level conductive traces 125 are formed in the same metal layer forming step. At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the conductive filled vias 124, and are connected to at least a portion of the connection pads 201 of the metal frame 200. The electrical connection points 103 on the active surface 1131 of the die pass through the wafer conductive layer 130 and conduct electricity. The filled vias 124 and the panel-level conductive traces 125 are led to the connection pads 201 of the metal frame 200 , and then electrically connected to the outside world through the connection pads 201 . It can be understood that the die shown in FIG. 6c can also be used for packaging, and the panel-level conductive traces 125 are formed on the surface of the protective layer 107, and at least a part of the panel-level conductive traces 125 are connected to the wafer conductive bumps 111, and Connected to at least a part of the metal frame 200 , the electrical connection points 103 on the die active surface 1131 lead to the connection pads 201 of the metal frame 200 through the wafer conductive layer 130 and the panel-level conductive layer to achieve electrical connection with the outside world.

In step S9, a plurality of wafers 500 are formed by dicing.

As shown in FIG. 15 , the packaged monomers are diced and separated to form a packaged wafer, which can be diced by machine or laser.

When the plastic-encapsulated metal frame 200 is the metal frame 200 including the connecting rods 203 as shown in FIG. 8a, when cutting and separating, it is necessary to cut the periphery of the connecting rods 203 to remove the connecting rods 203, so that the packaging can be completed. Links are not included in wafer 500 so that each metal feature in the metal unit of metal frame 200 is independent.

Preferably, before or after the cutting and separating step, a surface treatment layer 131 is optionally formed on the backside 1132 of the die and/or the surface of the exposed metal frame by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and tin plating (Tin) are used.

Optionally, the surface treatment layer 131 may also be configured to enable back grounding of the wafer 500 , that is, the surface treatment layer 131 electrically connects the backside 1132 of the die and the connection pad 201 specifically connected to the backside grounding on the backside according to the specific design of the circuit. together (specifically connecting the backside grounded connection pad is: the connection pad is connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure).

The difference between the second embodiment of the present disclosure and the first embodiment is mainly the structure of the metal frame 200 , and other identical parts will not be repeated, and only the different parts from the first embodiment will be described in this embodiment.

FIG. 16 shows a structural diagram of the metal frame 200 in Embodiment 2 of the present disclosure. On the basis that the metal features of the metal frame 200 in Embodiment 1 are the connection pads 201 , in Embodiment 2, the metal features of the metal frame 200 also include The heat dissipation structure is used for heat dissipation. The heat dissipation structure is embodied as a heat dissipation pad 207 in FIG. 16. The heat dissipation pad 207 can be as large as possible to improve the heat dissipation effect when conditions permit, and its shape is not limited to the rectangle shown in the figure. It can also be a square or other shapes, and the number of the heat dissipation pads 207 is not limited to one, and can be two or more as required. In order to keep the heat dissipation pad 207 from being separated from the metal frame 200 , the heat dissipation pad 207 and the outer contour of the metal frame 200 retain one or more connecting rods 203 to ensure that the heat dissipation pad 207 and the metal frame 200 are connected together during the process of transferring the metal frame 200 . If the metal frame 200 is formed after fixing the metal to the temporary support plate 300 in the manner described in Embodiment 1, it is not necessary to form the connecting rod 203, which is also applicable in this embodiment.

When transferring the metal frame 200 , the metal frame 200 may be transported using the temporary support plate 300 and/or the adhesive layer 301 in the manner described in Embodiment 1. After the metal frame 200 is pasted to the temporary support plate 300, the connecting rods 203 can be cut to separate the metal frame 200 open, or the connecting rod 203 is separated and removed from the metal frame 200 , so as to separate the metal units in the metal frame 200 .

The steps of forming the protective layer in Embodiment 2 are: referring to FIGS. 3 a to 3 b , applying a protective layer 107 on the active surface 1001 of the wafer; forming a protective layer opening 109 on the surface of the protective layer 107 . At least a part of the protective layer opening 109 is formed at a position corresponding to the electrical connection point 103 on the active surface of the wafer 1001 and/or at a heat dissipation position on the active surface of the wafer 1001 to expose the electrical connection point 103 and the heat dissipation position. The heat dissipation location can be at the electrical connection point 103, because there is often accumulated heat at the electrical connection point that needs to be dissipated. FIG. 3b only shows the case where the heat dissipation location is at the electrical connection point 103, but FIG. 3b is only an example Yes, the heat dissipation position may also be at other positions requiring heat dissipation except the electrical connection point 103 .

Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 and/or heat dissipation positions on the active surface 1001 of the wafer.

Optionally, each protective layer opening 109 in at least a part of the protective layer openings 109 corresponds to a plurality of electrical connection points 103 and/or heat dissipation positions.

Optionally, at least a part of the electrical connection points 103 and/or heat dissipation positions correspond to a plurality of protective layer openings 109 .

Optionally, a conductive material is filled in the protective layer opening 109 to form a conductive filled via 124, and this step can also be performed after the plastic sealing process.

The forming step of the protective layer opening can also be performed after the plastic sealing process.

Another optional process step of applying the protective layer 107 on the active surface 1001 of the wafer is shown in FIGS. 4a-4c: As shown in FIG. 4a, a wafer conductive layer 130 is formed on the active surface 1001 of the wafer. Wafer conductive layer 130 is embodied as wafer conductive traces 106 in FIG. 4a.

At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of wafer active surface 1001 to each other.

Optionally, at least a part of the electrical connection points 103 on the active surface 1001 of the wafer are independently drawn out by the conductive traces 106 of the wafer.

Although not shown in the figure, it can be understood that the conductive traces 106 of the wafer lead out a part of the electrical connection points 103 on the active surface of the wafer 1001 individually and connect another part of the electrical connection points 103 on the active surface of the wafer 1001 to each other. Interconnect and lead out.

At least a portion of the wafer conductive traces 106 corresponds to at least a portion of the heat dissipation locations on the wafer active surface 1001 .

FIG. 4 a only shows the case where the heat dissipation position is at the electrical connection point 103 , however, FIG. 4 a is only an example, and the heat dissipation position may also be at other positions requiring heat dissipation besides the electrical connection point 103 .

As shown in FIG. 4b, a protective layer 107 is applied over the active surface 1001 of the wafer and the conductive traces 106 of the wafer.

As shown in FIG. 4 c , a protective layer opening 109 is formed on the surface of the protective layer 107 .

At least a part of the protective layer openings 109 are located corresponding to the wafer conductive traces 106 , and the wafer conductive traces 106 are exposed through the protective layer openings 109 .

Optionally, a conductive material is filled in the protective layer opening 109 to form a conductive filled via 124, and this step can also be performed after the plastic sealing process.

The forming step of the protective layer opening can also be performed after the plastic sealing process.

Another optional process step of applying the protective layer 107 on the wafer active surface 1001 is shown in FIGS. 5 a to 5 c .

A wafer conductive layer 130 is formed on the wafer active surface 1001 , and the wafer conductive layer 130 is the wafer conductive traces 106 and/or the wafer conductive bumps 111 .

As shown in FIG. 5a, wafer conductive traces 106 are formed on the active surface 1001 of the wafer.

At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of wafer active surface 1001 to each other.

Optionally, at least a part of the electrical connection points 103 on the active surface 1001 of the wafer are independently drawn out by the conductive traces 106 of the wafer.

Although not shown in the figure, it can be understood that the conductive traces 106 of the wafer lead out a part of the electrical connection points 103 on the active surface of the wafer 1001 individually and connect another part of the electrical connection points 103 on the active surface of the wafer 1001 to each other. Interconnect and lead out.

At least a portion of the wafer conductive traces 106 corresponds to at least a portion of the heat dissipation locations on the wafer active surface 1001 .

Fig. 5a only shows the case where the heat dissipation position is at the electrical connection point 103, however, Fig. 5a is only exemplary, As shown in FIG. 5b , wafer conductive bumps 111 are formed on the pads or connection points of the wafer conductive traces 106 .

As shown in FIG. 5c , a protective layer 107 is applied on the wafer conductive layer 130 .

In the protective layer forming step in Embodiment 2, the conductive layer, the forming method and material of the protective layer, the shape and the forming method of the protective layer opening are the same as those in Embodiment 1, and are not repeated here.

Die 113 is formed by dicing the wafer 100 to which the protective layer has been applied as described above.

FIG. 17 shows that the crystal grains 113 and the metal frame 200 are arranged on the carrier board 117 , and the arrangement steps are similar to the method described in the first embodiment. The connecting rod 203 of the metal frame 200 in FIG. 17 is cut to separate the metal frame 200 into several parts, but the connecting rod 203 of the metal frame 200 is not removed. Optionally, the connecting rod 203 can also be cut from the metal frame 200 removed. The form of the die 113 shown in FIG. 17 is the form of the die 113 including the wafer conductive layer 130 and the protective layer opening 109 in FIG. 6b. However, FIG. 17 is only an example, and the crystal grains 113 arranged on the carrier board 117 may also be in the form of crystal grains as shown in FIG. 6a or 6c.

FIG. 18 shows that the plastic sealing layer 123 is formed on the carrier board 117 to encapsulate all the die 113 and the metal frame 200, and a flat plate structure is reconstructed, and then the plastic sealing layer 123 is thinned to expose the metal frame 200, and the carrier board 117 is peeled off to form a The method and steps of the panel module 150 are also similar to those described in the first embodiment.

FIG. 19 shows the formation of panel-level conductive and dielectric layers 129 .

A panel-level conductive layer is formed on the surface of the protective layer 107. In FIG. 19, the panel-level conductive layer is embodied as panel-level conductive traces 125. Since the conductive filled vias 124 have not been formed in the process shown in the figure, it is necessary to use the The conductive filling material fills the protective layer opening 109 to form The conductively filled vias 124 connected to the wafer conductive traces 106, optionally, the conductively filled vias 124 and the panel-level conductive traces 125 are formed in the same conductive layer formation step.

At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the wafer conductive traces 106 through the conductive filled vias 124 to connect to the electrical connection points 1131 on the die active surface 1131 and to the connection pads 201 in the metal unit , the electrical connection points 103 on the active surface of the die are connected to the connection pads 201 through the panel-level conductive traces 125 and the conductive filled vias 124 and the wafer conductive layer 130 .

At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the wafer conductive traces 106 through the conductive filled vias 124 to connect to heat dissipation locations on the die active surface 1131 and to the heat dissipation pads 207 in the metal unit, Since the conductive material of metal is also a good conductor of heat, the heat can be transferred to the heat dissipation pad 207 through the wafer conductive layer 130 , the conductive filled vias 124 and the panel-level conductive layer, and then dissipated to the outside through the heat dissipation pad 207 . Of course, it can be understood that the heat-dissipating position can also be provided with only thermally conductive material, and the thermally conductive material can be used to transfer heat to the heat-dissipating pad 207 .

The pattern traces of the panel-level conductive traces 125 in FIG. 19 are merely exemplary, and the pattern traces of the panel-level conductive traces 125 are connected according to specific circuit designs.

When the conductive filled vias 124 have been formed in the previous step of applying the protective layer, the step of forming the panel-level conductive layer can be directly performed.

When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 also needs to be included.

Next, a dielectric layer 129 is formed on the panel-level conductive layer.

The panel-level conductive and dielectric layers 129 may be one layer or multiple layers.

The materials and forming methods of the panel-level conductive layer and the dielectric layer 129 are similar to those in Embodiment 1.

FIG. 19 shows that in the steps of forming the panel-level conductive layer and the dielectric layer 129, the die 113 shown in FIG. 6b is used for encapsulation. It can be understood that the die 113 shown in FIG. 6a can also be used. encapsulate the particles, fill the protective layer openings 109 with conductive materials to form conductive filled vias 124 connected to the electrical connection points 103 and/or heat dissipation positions; form panel-level conductive traces 125 on the surface of the protective layer 107, at least a part of the panel-level conductive traces The lines 125 are connected to the conductive filled vias 124 corresponding to the electrical connection points 103, and are connected to at least a part of the connection pads 201 of the metal frame 200. The electrical connection points 103 on the active surface 1131 of the die pass through the conductive filled vias 124 and the panel-level conductive The traces 125 lead to the connection pads 201 of the metal frame 200 , and are then electrically connected to the outside through the connection pads 201 . At least a part of the panel-level conductive traces 125 is connected to at least a part of the conductive filled vias 124 corresponding to the heat dissipation position, and the heat dissipation position may be the position of the electrical connection point 103, or other positions other than the electrical connection point 103, and at least a part The heat dissipation pads 207 of the metal frame 200 are connected to dissipate heat to the outside through the heat dissipation pads 207 . It can be understood that the die shown in FIG. 6c can also be used for packaging.

As shown in FIG. 20 , the packaged monomers are separated by dicing to form a packaged wafer, which can be diced by machine or laser.

The metal frame 200 in FIG. 20 includes the connecting rods 203. When cutting and separating, it is necessary to cut the periphery of the connecting rods 203 to remove the connecting rods 203, so that the packaging wafer 500 formed after packaging does not include the connecting rods, so that the metal frame 200 Each metal feature in the metal unit is independent.

Preferably, before or after the cutting and separating step, a surface treatment layer 131 is optionally formed on the backside 1132 of the die and/or the surface of the exposed metal frame by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and tin plating (Tin) are used.

Optionally, the surface treatment layer 131 may also be configured to enable back grounding of the wafer 500 , that is, the surface treatment layer 131 electrically connects the backside 1132 of the die and the connection pad 201 specifically connected to the backside grounding on the backside according to the specific design of the circuit. together (specifically connecting the backside grounded connection pad is: the connection pad is connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure).

Compared with the solution of Embodiment 1, since the heat dissipation pad 207 of the heat dissipation structure is added, the heat generated during the use of the chip can be dissipated in time by means of the heat dissipation pad 207 .

The difference between Embodiment 3 of the present disclosure and Embodiment 1 is mainly the structure of the metal frame 200 , and other identical parts will not be repeated here, and only the parts different from Embodiment 1 will be described in this embodiment.

The formation steps of the protective layer 107 are similar to those in Embodiment 1, and are not repeated here.

FIG. 21 shows a structural diagram of the metal frame 200 in Embodiment 3 of the present disclosure. On the basis that the metal features of the metal frame 200 in Embodiment 1 are the connection pads 201, in Embodiment 3, the metal features of the metal frame 200 also include The heat dissipation structure for heat dissipation is shown in FIG. 21 as a backside heat sink 205, although not shown in the figure, but optionally, the heat dissipation structure may also be embodied as a backside heat sink and a heat dissipation pad. As shown in FIG. 21 , the backside heat sink 205 is connected to the metal frame 200 by connecting rods 203 as a whole, so as to ensure that the backside heat sink 205 and the metal frame 200 are connected together during the process of transferring the metal frame 200 . The backside heat sink 205 is formed by half-etching (or stamping) the metal, which can also be understood as being thinned from the lower surface of the metal. During the etching (or stamping) process, the upper surface, that is, the backside heat sink 507 is retained, and the lower surface is removed to form a blank area, and the blank area is the vacancy 202 for placing the die 113 . The connecting rod 203 connecting the back heat sink 205 and the metal frame 200 is not half-etched (or punched), and its thickness is the same as the thickness of the metal sheet. In addition, it can also play a supporting role for the backside heat dissipation surface 205 when the backside heat sink 205 is applied to the backside 1132 of the die, so that it can be kept level and not easy to tilt. 21 shows that the number of connecting rods 203 connected to the back heat sink 205 is 2, but the optional number can also be 4, that is, the four corners of the back heat sink 205 are connected to the connecting rod 203, or other any quantity. When the die 113 is accommodated in the vacancy 202, the backside 1002 of the die is in contact with the backside heat sink 205 for heat dissipation.

FIG. 22 shows the arrangement of the die 113 on the carrier board 117, the thermal conductive material 209 is applied on the back surface 1132 of the die, the die 113 is connected to the heat sink on the back side through the thermal conductive material 209, and the thermal conductive material 209 is preferably a liquid substance or paste This position reduces the interface resistance of heat transfer.

FIG. 23 shows that the metal frame 200 is bonded to the carrier board 117, the backside 1132 of the die is connected to the backside heat sink 205 through the thermally conductive material 209, and the heat generated during the use of the chip formed after packaging passes through the thermally conductive material 209 and the heat sink 205. The backside heat sink 205 radiates to the outside. The process of applying the metal frame 200 to the carrier plate 117 can also be transferred through the temporary support plate as in Example 1.

FIG. 24 shows the steps of applying the plastic encapsulation layer 123 and the steps of forming the panel-level conductive layer and the dielectric layer 129 . The steps are similar to those described in Embodiment 1 and will not be repeated here.

Optionally, according to the specific design of the circuit, a conductive structure can be used, which is embodied as a wafer-level conductive layer and a panel-level conductive layer in FIG. The electrical connection point 103 of (back grounding) is electrically connected to the backside heat sink 20 , and the backside grounding is realized by using the backside heat sink 205 .

FIG. 25 shows the dicing to separate the packaged monomers to form the packaged wafer.

Preferably, before or after the cutting and separating step, a surface treatment layer 131 is optionally formed on the backside 1132 of the die and/or the surface of the exposed metal frame by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and tin plating (Tin) are used.

When the conductive structure is not used to realize the back grounding of the wafer, optionally, the surface treatment layer 131 can also be configured to be able to realize the back grounding of the wafer 500 , that is, the surface treatment layer 131 can connect the back surface of the wafer 500 according to the specific design of the circuit. The heat sink 205 and the connection pad 201 specifically connected to the backside ground are electrically connected together (the connection pad specifically connected to the backside ground is: the connection pad connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure). At this time, the thermally conductive material 209 applied on the backside of the die by the backside heat sink 205 through the thermally conductive material 209 is a material that can conduct electricity, such as a metal thermally conductive adhesive.

The difference between Embodiment 4 of the present disclosure and Embodiment 1 is that a metal layer is formed on the backside of the wafer before the plastic sealing step.

FIG. 26 shows the formation of a metal layer 210 on the wafer back surface 1002 of the wafer 100 in Embodiment 4 of the present disclosure, and the metal layer 210 may optionally be one or more layers of aluminum, tin, nickel, gold, silver, lead, bismuth, Copper, and combinations thereof, preferably copper, are formed by electroplating, electroless plating, sputtering, or other suitable means.

A protective layer is formed on the wafer active surface 1001 of the wafer 100 , and the steps of forming the protective layer 107 are similar to those in Embodiment 1, and are not repeated here. The wafer 100 on which the metal layer 210 and the protective layer 107 are formed is cut and separated into dies 113 having the metal layer 210 and the protective layer 107 .

Optionally, the step of forming the metal layer 210 is performed after the step of forming the protective layer 107 or the step of cutting and separating.

Next, the die 113 and the metal frame 200 are arranged on the carrier board 117 , and the plastic sealing layer 123 is formed on the carrier board 117 .

27 shows the formation of the plastic encapsulation layer 123 for encapsulating the die 113 on the carrier board 117 and the metal frame 200, and the formation of the panel-level conductive and dielectric layers 129, the steps are similar to those described in Embodiment 1 ,No longer. FIG. 27 is only an example diagram, and FIG. 27 only shows that the die 113 is in the form of a die 113 with a protective layer 107 and an opening in the protective layer as shown in FIG. 6a; the die 113 can also be as shown in FIG. 6b The illustrated die form with the wafer conductive layer 130 and the protective layer 107 and the protective layer opening 109 may also be in the form of a die with the wafer conductive layer 130 and the protective layer 107 as shown in FIG. 6c. Meanwhile, the metal frame 200 may also be a metal frame with heat dissipation pads 207 . The metal layer surface and the metal feature backside of the die backside 1132 are exposed from the backside of the plasticizer layer by thinning the plasticizer layer.

Preferably, according to the design, the metal layer on the backside 1132 of the die and at least one metal feature are electrically connected through a conductive material, and the material can be optionally the conductive glue 211 . At this time, the metal layer of the backside 1132 of the die and the entire metal frame are in an electrical connection state. In the next step, when electroplating is used to form the surface treatment layer, the metal layer and the metal frame can form a current conducting electrical connection path, so that the surface treatment layer can be formed on the surface of the metal layer and the back of the metal frame without the need for a seed layer. In this case, the link 203 should remain in the metal frame.

In some embodiments, the conductive adhesive 211 can also be configured to enable back grounding of the chip 500 , that is, the conductive adhesive 211 can specifically connect the metal layer 210 on the backside of the die to the connection pad 201 on the backside grounding according to the specific design of the circuit. Electrically connected together (specifically connecting the backside grounded connection pads is: the connection pads are connected to the backside grounded electrical connection points on the active surface of the die through the conductive structure).

As shown in FIG. 28 , the packaged monomers are separated by dicing to form a packaged wafer.

Preferably, before or after the cutting and separating step, a surface treatment layer 131 is optionally formed on the backside 1132 of the die and/or the surface of the exposed metal frame by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and tin plating (Tin) are used. When the surface treatment layer 131 is formed by electroplating, due to the existence of the conductive adhesive 211, the metal layer on the backside of the die and the metal frame are electrically connected as a whole, forming a whole that the electroplating current is conducting during electroplating, so it can be directly Carry out the plating step.

Compared with the solution of Embodiment 1, the metal layer 210 is added on the back of the die 113, and the metal layer can strengthen the heat dissipation, so that the heat generated during the use of the chip can be dissipated in time; and the conductive adhesive 211 is combined to make the surface treatment The formation steps of the layers are simpler.

According to another aspect of the present disclosure, there is also provided a wafer structure, which is preferably fabricated by the method of the present disclosure described above, but is not limited to the above method.

29a, 29b, 29c, 29d, and 29e are schematic diagrams of chip structures obtained by the packaging method provided by the exemplary embodiments of the present disclosure. As shown in the figure, a wafer 500 includes: at least one die 113; a protective layer 107; a metal unit, where the metal unit includes at least one metal feature; a plastic encapsulation layer 123 for encapsulating the die 113 and the metal unit; wherein the wafer structure Connections to external circuits are made through at least one metal feature.

In some embodiments, the wafer 500 further includes a conductive structure, and at least one metal feature on the metal unit is connected to the die 113 through the conductive structure. In some embodiments, the metal features include connection structures and/or heat dissipation structures.

Specifically, as shown in FIG. 29a , the metal feature is a connection structure, and the connection structure is embodied as a connection pad 201 , and the chip 500 is connected to an external circuit through at least one connection pad 201 .

As shown in FIG. 29a, the conductive structure includes conductive filled vias 124 and a panel-level conductive layer, embodied as panel-level conductive traces 125 in the figure, and the panel-level conductive layer may also be panel-level conductive traces 125 and panel-level conductive bumps The column, the panel-level conductive layer can be one layer as shown in the figure, or it can be a multi-layer; the conductive filled through holes 124 are formed by filling the openings of the protective layer with conductive materials, and at least a part of the conductive filled through holes 124 are connected to the electrical connection points 103. The panel-level conductive layer is formed on the surface of the protective layer 107 and the front surface 1231 of the plastic sealing layer, at least a part of the panel-level conductive layer is connected to the conductive filling via 124 and connected to the connection pad 201, the surface of the protective layer 107, the front surface of the plastic sealing layer 1231 and the connection pad 201 Front flush.

In some embodiments, the conductively filled via 124 has a conductively filled via lower surface and a conductively filled via upper surface, and the area ratio of the conductively filled via lower surface to the conductively filled via upper surface is 60%-90%.

In some embodiments, there is a gap between the lower surface of the conductively filled via and the insulating layer 105 . Preferably, the lower surface of the conductively filled via is at a position close to the center of the electrical connection point 103 .

In some embodiments, a conductive cap layer is formed on the electrical connection points 103 .

29a is only an example, the conductive structure may also include the wafer conductive layer 130, the conductively filled vias 124 and the panel-level conductive layer, and the conductive structure may also include the wafer conductive layer 130 and the panel-level conductive layer.

The backside 1132 of the die and the backside of the metal unit, specifically the backside of the connection pad, are exposed from the backside 1232 of the plastic sealing layer, and the part exposed from the backside 1232 of the plastic sealing layer has a surface treatment layer 131 . Optionally, the surface treatment layer 131 may also be configured to enable back grounding of the wafer 500 , that is, the surface treatment layer 131 electrically connects the backside 1132 of the die and the connection pad 201 specifically connected to the backside grounding on the backside according to the specific design of the circuit. together (specifically connecting the backside grounded connection pad is: the connection pad is connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure).

The wafer 500 further includes a dielectric layer 129 covering the panel-level conductive layer, and the outermost dielectric layer 129 completely covers the panel-level conductive layer.

As shown in FIG. 29b , the metal features are a connection structure and a heat dissipation structure. The connection structure is embodied as a connection pad 201 , and the chip 500 is connected to an external circuit through at least one connection pad 201 ; the heat dissipation structure is embodied as a heat dissipation pad 207 .

29b, the conductive structure includes a wafer conductive layer 130, represented in the figure as wafer conductive traces 106, conductively filled vias 124, and a panel-level conductive layer, represented in the figure as panel-level conductive layers The traces 125, the panel-level conductive layer can also be the panel-level conductive traces 125 and the panel-level conductive bumps, the panel-level conductive layer can be one layer as shown in the figure, or can be multiple layers; at least a part of the wafer conductive layer 130 connected to the electrical connection point 103 and/or the heat dissipation position; the conductive filled via 124 is formed by filling the protective layer opening 109 with a conductive material; at least a part of the conductive filled via 124 is connected to the wafer conductive layer; the panel-level conductive layer is formed on the protective layer The surface of the layer 107 is connected to the front surface 1231 of the plastic sealing layer, at least a part of the panel-level conductive layer is connected to the conductive filled vias 124 and connected to the metal unit. The surface of the protective layer 107, the front surface 1231 of the plastic sealing layer and the front surface of the metal unit are flush.

In some embodiments, at least a portion of the wafer conductive layer 130 interconnects and draws out the plurality of electrical connection points 103 , and in other embodiments, at least a portion of the wafer conductive layer 130 separates out the electrical connection points 103 .

Optionally, the contact area between the wafer conductive layer 130 and the single contact area of the electrical connection point 103 is smaller than the contact area between the wafer conductive layer 130 and the single contact area of the conductive filled via 124 .

The conductively filled through hole has a lower surface of the conductively filled through hole and an upper surface of the conductively filled through hole. Optionally, the area of the lower surface of the conductively filled through hole is smaller than that of the upper surface of the conductively filled through hole.

29b is only an example, the conductive structure may also include conductive filled vias 124 and a panel-level conductive layer; the conductive structure may also include a wafer conductive layer 130 and a panel-level conductive layer.

The backside of the die 1132 and the backside of the metal unit, specifically the backside of the connection pad and the backside of the heat dissipation pad, are exposed from the backside 1232 of the plastic sealing layer, and the part exposed from the backside 1232 of the plastic sealing layer has a surface treatment layer 131 . Optionally, the surface treatment layer 131 may also be configured to enable back grounding of the wafer 500 , that is, the surface treatment layer 131 electrically connects the backside 1132 of the die and the connection pad 201 specifically connected to the backside grounding on the backside according to the specific design of the circuit. together (specifically connecting the backside grounded connection pad is: the connection pad is connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure).

The wafer 500 further includes a dielectric layer 129 covering the panel-level conductive layer, and the outermost dielectric layer 129 completely covers the panel-level conductive layer.

As shown in FIG. 29c, the metal features are a connection structure and a heat dissipation structure. The connection structure is embodied as a connection pad 201, and the heat dissipation structure is embodied as a backside heat sink 205. Optionally, the backside heat sink 205 is applied to the back of the die through a thermally conductive material 209. The chip 500 is connected to external circuits through at least one connection pad 201 . In some embodiments, the heat dissipation structures may be heat dissipation pads 207 and backside heat sinks 205 .

As shown in FIG. 29c, the conductive structure includes a wafer conductive layer 130 and a panel-level conductive layer, which is embodied as panel-level conductive traces 125 in the figure, and the panel-level conductive layer can also be panel-level conductive traces 125 and panel-level conductive bumps The column, the panel-level conductive layer can be a layer as shown in the figure, or can be a multi-layer; the wafer conductive layer includes wafer conductive traces 106 and wafer conductive bumps 111; at least a part of wafer conductive traces 106 and electrical The connection point 103 and/or the heat dissipation position are connected; at least a part of the wafer conductive bumps 111 are formed on the wafer conductive traces 106; the panel level conductive layer is formed on the surface of the protective layer 107 and the front side 1231 of the plastic sealing layer, and at least a part of the panel level conductive layer is formed It is connected to the conductive bumps 111 of the wafer and connected to the metal unit, and the surface of the protective layer 107, the front surface 1231 of the plastic sealing layer and the front surface of the metal unit are flush.

In some embodiments, at least a portion of the wafer conductive traces 106 lead out the electrical connection points 103 individually; in other embodiments, at least a portion of the wafer conductive traces 106 interconnect and lead out the plurality of electrical connection points 103 to each other.

Optionally, the wafer conductive layer is a wafer conductive bump 111, and at least a part of the wafer conductive bump is connected to the electrical connection point 103 and/or the heat dissipation position.

29c is only an example, the conductive structure may also include conductive filled vias 124 and a panel-level conductive layer, and the conductive structure may also include a wafer conductive layer 130, conductively-filled vias 124 and a panel-level conductive layer.

Optionally, according to the specific design of the circuit, a conductive structure may be used to electrically connect the back grounding electrical connection point 103 on the active surface of the die to the backside heat sink 20 to achieve back grounding using the backside heat sink 205 .

The backside 1132 of the die and the backside of the metal unit, specifically the backside of the backside heat sink 205 , are exposed from the backside 1232 of the plastic sealing layer, and the part exposed from the backside 1232 of the plastic sealing layer has a surface treatment layer 131 . When the conductive structure is not used to realize the back grounding of the wafer, optionally, the surface treatment layer 131 can also be configured to be able to realize the back grounding of the wafer 500 , that is, the surface treatment layer 131 can connect the back surface of the wafer 500 according to the specific design of the circuit. The heat sink 205 and the connection pad 201 specifically connected to the backside ground are electrically connected together (the connection pad specifically connected to the backside ground is: the connection pad connected to the backside grounded electrical connection point on the active surface of the die through the conductive structure). At this time, the thermally conductive material 209 applied on the backside of the die by the backside heat sink 205 through the thermally conductive material 209 is a material that can conduct electricity, such as a metal thermally conductive adhesive.

The wafer 500 further includes a dielectric layer 129 covering the panel-level conductive layer, and the outermost dielectric layer 129 completely covers the panel-level conductive layer.

According to the structures shown in, for example, FIGS. 29 a and 29 b , optionally, the backside 1132 of the die may also have a metal layer 210 , and the surface of the metal layer 210 is exposed from the backside 1232 of the plastic encapsulation layer. The metal features have metal feature backsides that are exposed from the overmolding layer backside 1232 . Preferably, the surface of the metal layer 201 and the back surface of at least one metal feature are connected through conductive glue 211 .

In some embodiments, the conductive adhesive 211 can also be configured to enable back grounding of the chip 500 , that is, the conductive adhesive 211 can specifically connect the metal layer 210 on the backside of the die to the connection pad 201 on the backside grounding according to the specific design of the circuit. electrically connected together (special The connection pads that are connected to the ground on the back side are: the connection pads are connected to the electrical connection points on the active surface of the die through the conductive structure.

Some embodiments of the package structure with metal layer 210 and conductive paste 211 are shown in FIG. 29d.

According to the structures shown in, for example, Fig. 29a, Fig. 29b and Fig. 29c, optionally, the wafer structure has a plurality of die 113, preferably, the plurality of die 113 are die 113 with different functions, and a plurality of The dies 113 are electrically connected according to product design. One embodiment of a package structure with multiple dies 113 is shown in Figure 29e.

In the wafer structure, preferably, the Young's modulus of the protective layer 107 is any one of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

The protective layer 107 is soft, has good flexibility and elasticity, and has sufficient support for the panel conductive layer formed on the surface thereof, and is especially suitable for the packaging of thin die with large electric flux.

In some embodiments, the material of the protective layer 107 is an organic/inorganic composite material. Preferably, the organic/inorganic composite material in which inorganic particles are added to the organic material is used to modify the material properties of the organic material, so that the material has the characteristics of both organic and inorganic materials.

In some embodiments, the thickness of the protective layer 107 is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm. This thickness range ensures that the protective layer 107 can provide sufficient buffering and support.

In some embodiments, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the thermal expansion coefficient of the plastic sealing layer 123 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the protective layer 107 and the molding layer 123 have the same or similar thermal expansion coefficients. It avoids the accumulation of interface fatigue at the interface between the protective layer 107 , the plastic sealing layer 123 and the die 113 , so that the packaged chip has durability and prolongs the service life of the chip.

30 is an exemplary schematic view of the wafer 500 in use, during use, the wafer 500 is connected to the circuit board or substrate 400 through at least one metal feature, represented in the figure as a connection pad 201 .

The wafer structure in the present disclosure may replace the wire bonding structure. Compared with the wire bonding package structure, the present disclosure has a simple packaging process, avoids the mutual interference of signals between the leads in the wire bonding structure, and avoids the noise generated by the leads due to vibration when the chip is working. In addition, the connection structure is used to replace the lead structure, which is more suitable for chip packaging with large electric flux.

The specific embodiments described above are intended to further describe the technical solutions and technical effects of the present disclosure in detail, but those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure should be included within the protection scope of the present disclosure.

S1~S9: Steps

Claims (13)

A chip structure, comprising: at least one die, the die has a die active surface and a die back surface; a protective layer, including a protective layer first surface and a protective layer second surface, wherein the protective layer first Two surfaces are formed on the active surface of the die; a metal unit, the metal unit includes at least one metal feature, the metal feature has a front side of the metal feature and a back side of the metal feature, the front side of the metal feature is flush with the first side of the protective layer flat, and the backside of the metal feature is located on the same side as the backside of the die and is flush with the backside of the die; a plastic encapsulation layer is used to encapsulate the die and the metal unit, the plastic encapsulation layer includes a front side of the plastic encapsulation layer and a The back side of the plastic sealing layer, the front side of the plastic sealing layer is flush with the front side of the metal feature, and the back side of the plastic sealing layer is flush with the back side of the metal feature; a conductive structure, at least one of the metal features on the metal unit passes through the conductive structure and the crystal feature. The conductive structure includes a conductive filled through hole and a panel-level conductive layer; the conductive filled through hole is formed by filling the opening of the protective layer with a conductive material, and at least a part of the conductive filled through hole is connected to an electrical connection point and/or a heat dissipation position ; The panel-level conductive layer is formed on the surface of the protective layer and the front side of the plastic sealing layer, at least a part of the panel-level conductive layer is connected with the conductive filling through holes and connected with the metal unit, and the surface of the protective layer, the front side of the plastic sealing layer and the front side of the metal unit are flush and a dielectric layer covering the panel-level conductive layer, the outermost dielectric layer completely covering the panel-level conductive layer without openings; wherein the chip structure is connected to an external circuit through at least one of the metal features . The chip structure of claim 1, wherein the metal feature includes a connection structure and/or a heat dissipation structure; the connection structure includes a connection pad; and the heat dissipation structure includes a heat dissipation pad. The chip structure according to claim 2, wherein the heat dissipation structure further comprises a backside heat sink, and the backside heat sink is applied on the backside of the die through a thermally conductive material. The wafer structure according to claim 1, a metal layer is applied on the back side of the die, and the surface of the metal layer is exposed from the back side of the plastic sealing layer. The chip structure of claim 4, wherein the metal feature has a backside of the metal feature, the backside of the metal feature is exposed from the backside of the plastic encapsulation layer, and the surface of the metal layer and the backside of at least one of the metal features are connected through conductive glue. The wafer structure according to claim 1, wherein the backside of the die and the backside of the metal unit are exposed from the backside of the plastic sealing layer, and the portion exposed from the backside of the plastic sealing layer has a surface treatment layer. According to the wafer structure of claim 1, the at least one die is a plurality of die, the plurality of die are die with different functions, and the plurality of die are electrically connected according to product design. A chip packaging method, comprising: providing a wafer, forming a protective layer on an active surface of the wafer, the protective layer comprising a first surface of the protective layer and a second surface of the protective layer, wherein the second surface of the protective layer is formed on the active surface of the wafer; cutting and separating the wafer to form a die, the die having an active surface of the die and a back surface of the die; providing a metal structure, the metal structure includes at least one metal unit, and the metal unit includes at least one a metal feature, the metal feature has a metal feature front side and a metal feature back side, the metal feature front side is flush with the first side of the protective layer, and the metal feature back side is on the same side as the die back side and the die back flush; The die and the metal structure are mounted on a carrier board; a plastic encapsulation layer is formed, the plastic encapsulation layer includes a front side of the plastic encapsulation layer and a back side of the plastic encapsulation layer, the front side of the plastic encapsulation layer is flush with the front side of the metal feature, and the plastic encapsulation layer The backside of the layer is flush with the backside of the metal feature; a conductive structure is formed, and the die and at least one metal feature of the metal unit are connected through the conductive structure; wherein the step of forming the conductive structure includes: on the active surface of the wafer A protective layer opening is formed in the protective layer, and at least a part of the protective layer opening is formed at an electrical connection point and/or a heat dissipation position; a conductive material is filled in the protective layer opening to form a conductive filled through hole and a panel-level conductive layer is formed. The first-level conductive layer is formed on the surface of the protective layer and the front surface of the plastic sealing layer, at least a part of the panel-level conductive layer is connected with the conductive filling through hole and connected with the metal unit, and the surface of the protective layer, the front surface of the plastic sealing layer and the front surface of the metal unit are flush; and forming a dielectric layer covering the panel-level conductive layer, the outermost dielectric layer completely covering the panel-level conductive layer without openings. The chip packaging method according to claim 8, wherein the metal feature includes a connection structure and/or a heat dissipation structure; the connection structure includes a connection pad; and the heat dissipation structure includes a heat dissipation pad. According to the chip packaging method of claim 9, the heat dissipation structure further includes a backside heat sink, and the backside heat sink is applied on the backside of the die through a thermally conductive material. The chip packaging method according to claim 8, further comprising the step of applying a metal layer on the backside of the die, and connecting the surface of the metal layer and the backside of at least one of the metal features through conductive glue. The chip packaging method according to claim 8, wherein the metal structure is a metal frame, the metal frame is transferred to the carrier board through a temporary support plate, and the metal frame is arranged on the temporary support plate. The time support plate also includes a step of cutting and separating the connecting rods so that the metal units in the metal frame are independent of each other. The chip packaging method according to claim 8, wherein the metal structure is a metal frame, the metal frame is transferred to the carrier board through a temporary support plate, and after the metal frame is set on the temporary support plate, the metal frame also includes removing the metal frame from the metal frame The step of removing the links so that the metal units in the metal frame are independent of each other.

Images