CN111883437B - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN111883437B
CN111883437B CN202010635571.8A CN202010635571A CN111883437B CN 111883437 B CN111883437 B CN 111883437B CN 202010635571 A CN202010635571 A CN 202010635571A CN 111883437 B CN111883437 B CN 111883437B
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metal
chip
encapsulation
metal fixing
rewiring
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CN111883437A (en
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霍炎
涂旭峰
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing an encapsulation structural member encapsulating a chip to be encapsulated and a metal fixing member, wherein the metal fixing member is positioned at the outer side of the chip to be encapsulated; a rewiring structure is formed on the first surface of the encapsulation structure and a metal protector rewiring structure is located over the metal fixture. The semiconductor packaging structure is manufactured by the semiconductor packaging method. According to the semiconductor packaging structure, the metal protection piece is arranged, so that the stress of the edge can be effectively absorbed, the rewiring structure beside the metal protection piece is protected, and the reliability of the semiconductor packaging structure is improved; through setting up the metal mounting, can reach the dispersion and lie in the stress purpose that the rewiring structure of edge received, simultaneously, can improve the cohesion between metal protection piece and the plastic envelope material.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor packaging method and a semiconductor packaging structure.
Background
At present, for a packaged product, the pins at different positions are subjected to different stresses due to different thermal expansion coefficients when heating or cooling, and the outermost pins (edge pins) of the package are subjected to the stresses most greatly.
In addition, in the packaged product, edge pins led out through copper wiring have risks of falling off from solder contact portions during drop tests and temperature cycle reliability capability tests due to stress concentration, and even cause cracking in severe cases.
Therefore, how to distribute the stress to the edge pins is a problem to be solved in the art.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, including the steps of:
providing an encapsulation structural member for encapsulating a chip to be encapsulated and a metal fixing member, wherein the metal fixing member is positioned on the outer side of the chip to be encapsulated, the encapsulation structural member comprises a first surface and a second surface which are opposite, and the front surface of the chip to be encapsulated corresponds to the first surface of the encapsulation structural member;
and forming a rewiring structure on the first surface of the encapsulation structural member and a metal protection member positioned above the metal fixing member, wherein the rewiring structure is electrically connected with a welding pad on the front surface of the chip to be packaged, and the metal protection member is connected with the metal fixing member.
Optionally, before forming a rewiring structure on the first surface of the encapsulation structure and a metal protector located outside the rewiring structure, the semiconductor packaging method includes:
attaching the chip to be packaged and the metal fixing piece to a carrier plate, wherein the back surface of the chip to be packaged faces upwards, and the front surface of the chip to be packaged faces towards the carrier plate;
the encapsulation structure is formed by covering the chip to be encapsulated, the metal fixing piece and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structural member.
Optionally, after forming the encapsulation structure, before peeling the carrier plate, the semiconductor packaging method includes:
and thinning the second surface of the encapsulation structure to expose one end of the metal fixing piece.
Optionally, the rewiring structure is formed in the same process step as the metal guard, and an upper surface of the metal guard is flush with an upper surface of the rewiring structure.
Optionally, after forming a rewiring structure on the first surface of the encapsulation structure and a metal protector located outside the rewiring structure and above the metal fixture, the semiconductor packaging method further comprises:
a heat sink is formed on the second surface of the encapsulation structure, the heat sink being coupled to the metal fixture.
Yet another aspect of the present application provides a semiconductor package structure, including:
the packaging structure comprises a first surface and a second surface which are opposite to each other, a chip and a metal fixing piece are packaged in the packaging structure, two ends of the metal fixing piece are respectively exposed out of the first surface and the second surface of the packaging structure, the metal fixing piece is positioned on the outer side of the chip, and the front face of the chip corresponds to the first surface of the packaging structure;
the rewiring structure and the metal protection piece are both positioned on the first surface of the encapsulation structural part, the metal protection piece is positioned above the metal fixing part, the rewiring structure is electrically connected with the welding pad on the front face of the chip, and the metal protection piece is connected with the metal fixing part.
Optionally, the metal fixing piece includes a first portion, a connecting portion, and a second portion connected in sequence in a thickness direction; the width of the connecting portion of the metal fixing member is smaller than the width of the first portion of the metal fixing member and the width of the second portion.
Optionally, an upper surface of the metal guard is flush with an upper surface of the rewiring structure.
Optionally, the metal protector is located outside the rewiring structure.
Optionally, the first surface of the encapsulating structure is rectangular, and the metal protector is located at a corner of the rectangle.
Optionally, the semiconductor package further includes a heat sink located on the second surface of the encapsulation structure and connected to the metal fixture.
According to the semiconductor packaging method and the semiconductor packaging structure, the metal protection piece is arranged, so that the stress of the edge can be effectively absorbed, the rewiring structure beside the metal protection piece is protected, and the reliability of the semiconductor packaging structure is improved; by arranging the metal fixing piece, the purpose of dispersing the stress suffered by the rewiring structure positioned at the edge can be achieved, and meanwhile, the binding force between the metal protecting piece and the plastic packaging material (the packaging layer of the packaging structural part) can be improved; and moreover, the strength of the rewiring structure of the packaged product on the PCB can be improved, so that the board-level reliability of the product is improved.
It should be noted that, because the material of the metal protection member is metal, and the encapsulation layer of the encapsulation structural member is plastic encapsulation material, the thermal expansion coefficient of the metal is greatly different from that of the plastic encapsulation material, and the lattice constants of the two materials are different, so that the binding force is poor. In the application, the metal fixing piece is preset in the encapsulation structural member, and the metal protecting piece is fixedly connected to the metal fixing piece, so that better binding force between the encapsulation layer of the encapsulation structural member and the metal protecting piece formed on the encapsulation layer can be helped, and the risk that the metal protecting piece falls off due to poor binding force in the manufacturing process is reduced.
In addition, the electrical extraction of the front surface of the chip is realized through a rewiring structure, and compared with the conventional electrical connection through a lead wire in the prior art, the rewiring structure requires smaller space, particularly the space in the thickness direction; and, because the pin that is concentrated at the lead frame at last is not used for connecting the electricity, the overall arrangement of rewiring structure is more nimble.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method proposed according to embodiment 1 of the present application.
Fig. 2 (a) -2 (m) are process flow diagrams of the semiconductor packaging method in embodiment 1 according to the present application.
Fig. 3 is a schematic structural diagram of a semiconductor obtained by the above semiconductor packaging method according to embodiment 1 of the present application.
Fig. 4 (a) -4 (b) are process flow diagrams of the semiconductor packaging method in embodiment 2 according to the present application.
Fig. 5 is a schematic structural diagram of a semiconductor obtained by the above-described semiconductor packaging method according to embodiment 2 of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "a" or "an" and the like as used in the description and the claims do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper" and/or "lower" and the like are used for ease of description only and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
Example 1
As shown in fig. 1, 2 (a) -2 (m) and 3, the present application provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 100: the chip to be packaged and the metal fixing piece are attached to a carrier plate, the metal fixing piece is located on the outer side of the chip to be packaged, the back face of the chip to be packaged faces upwards, and the front face of the chip to be packaged faces towards the carrier plate;
step 200: the packaging structure is formed by covering the chip to be packaged, the metal fixing piece and the exposed carrier plate with a packaging layer, wherein the packaging structure comprises a first surface and a second surface which are opposite, and the front surface of the chip to be packaged corresponds to the first surface of the packaging structure;
step 300: stripping the carrier plate to expose the first surface of the encapsulation structure;
step 400: forming a rewiring structure on the first surface of the encapsulation structural member and a metal protection member positioned above the metal fixing member, wherein the rewiring structure is electrically connected with a welding pad on the front surface of the chip to be packaged, and the metal protection member is connected with the metal fixing member;
step 500: a dielectric layer is formed over the rewiring structure, the metal guard, and the exposed first surface of the encapsulation structure.
According to the semiconductor packaging method, the metal protection piece is arranged, so that the stress of the edge can be effectively absorbed, the rewiring structure beside the metal protection piece is protected, and the reliability of the semiconductor packaging structure is improved; by arranging the metal fixing piece, the purpose of dispersing stress born by the rewiring structure positioned at the edge can be achieved, and meanwhile, the binding force between the metal protecting piece and the plastic packaging material can be improved; and moreover, the strength of the rewiring structure of the packaged product on the PCB can be improved, so that the board-level reliability of the product is improved.
In addition, the electrical extraction of the front surface of the chip is realized through a rewiring structure, and compared with the conventional electrical connection through a lead wire in the prior art, the rewiring structure requires smaller space, particularly the space in the thickness direction; and, because the pin that is concentrated at the lead frame at last is not used for connecting the electricity, the overall arrangement of rewiring structure is more nimble.
Before step 100, as shown in fig. 2 (a), a protective layer 12 is formed on the front surface of the chip 11 to be packaged. The chip 11 to be packaged includes a front surface and a back surface which are oppositely disposed, and the front surface of the chip 11 to be packaged is an active surface.
As shown in fig. 2 (b), first protection layer openings 121 are formed on the protection layer 12 at positions corresponding to the bonding pads of the chip 11 to be packaged, and each first protection layer opening 121 is located at least on the bonding pad of the chip 11 to be packaged or the line led out from the bonding pad, so that the bonding pad on the front surface of the chip 11 to be packaged or the line led out from the bonding pad is exposed from the first protection layer opening 121.
In step 100, as shown in fig. 2 (c), the chip 11 to be packaged with the protective layer 12 formed on the front surface and the metal fixing member 13 are attached to the carrier plate 2 through an adhesive layer, the back surface of the chip 11 to be packaged faces upward, and the front surface faces toward the carrier plate 2, wherein the metal fixing member 13 is located on the outer side of the chip 11 to be packaged.
The metal fixture 13 includes a first portion 131, a connection portion 132, and a second portion 133 connected in this order along a thickness direction T of the semiconductor package structure; the width w2 of the connecting portion 132 of the metal fixing member 13 is smaller than the width w1 of the first portion 131 and the width w3 of the second portion 133 of the metal fixing member 13, that is, the metal fixing member 13 having an i-shaped structure with wider ends, which is advantageous in that, on one hand, the metal fixing member 13 is stably attached to the carrier plate 2, and on the other hand, in a later step, a larger area of support can be provided for the metal protecting member when the metal protecting member is formed above the metal fixing member 13.
In other embodiments, the metal fixing member 13 may be formed into a T-shaped structure, that is, the metal fixing member 13 includes a first portion 131 and a connecting portion 132 connected in sequence, and the width of the connecting portion 132 of the metal fixing member 13 is smaller than the width of the first portion 131 of the metal fixing member 13, and the first portion 131 provides a larger area support for the metal protection member formed in the later step.
The adhesive layer is used to bond the chip 11 to be packaged and the metal fixing member 13, and the adhesive layer may be made of a material that is easy to peel, so that the carrier plate 2, the chip 11 to be packaged and the metal fixing member 13 are peeled off in a subsequent process, for example, a thermal separation material that can lose its adhesiveness by heating may be used.
In other embodiments, the adhesive layer may be a two-layer structure, and the thermal separation material layer and the chip attach layer are adhered to the carrier plate 2, so that the thermal separation material layer loses adhesion when heated and can be peeled off from the carrier plate 2, and the chip attach layer is an adhesive material layer and can be used for adhering the chip 11 to be packaged. After the packaged chip 11 is peeled off from the carrier plate 2, the chip attachment layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier plate 2 by lamination, printing, or the like.
The number of chips 11 to be packaged may be one or a plurality. The number of chips 11 to be packaged may be adjusted according to design requirements, and is not limited herein.
In step 200, as shown in fig. 2 (d), the whole carrier 2 is covered by the encapsulating layer 14, and the chip 11 to be encapsulated and the metal fixing member 13 are encapsulated by plastic to form the encapsulating structure 10. The encapsulating structure 10 is a flat structure on which rewiring and packaging can continue after the carrier plate 2 has been peeled off.
The encapsulating structure 10 comprises a first surface 10a and a second surface 10b arranged opposite to each other, and the second surface 10b of the encapsulating structure 10 is arranged opposite to the carrier plate 2, is substantially flat and parallel to the surface of the carrier plate 2. The first surface 10a of the encapsulation structure 10 is exposed with the protective layer 12 formed on the front surface of the chip 11 to be packaged, and one end of the metal fixture 13 (the first portion 131 of the metal fixture 13).
By pre-arranging the metal fixing member 13 in the encapsulating structural member 10, the metal protecting member formed later is fixedly connected to the metal fixing member 13, so that the encapsulating layer 14 of the encapsulating structural member 10 and the metal protecting member formed thereon can be assisted to have better binding force, and the risk of dropping the metal protecting member due to poor binding force in the manufacturing process is reduced.
In one embodiment, the encapsulation layer 14 may be formed by laminating an epoxy resin film or a Molding film, or may be formed by injection Molding (Injection Molding), compression Molding (Compression Molding) or Transfer Molding (Transfer Molding) an epoxy resin compound.
Before proceeding to step 300, as shown in fig. 2 (e), the second surface 10b of the encapsulating structure 10 is further polished to reduce the thickness of the encapsulating structure 10, so that the end of the metal fixing member 13 away from the carrier plate 2 is exposed on the second surface 10b of the encapsulating structure 10. In this way, on the one hand, it is convenient to connect the metal fixing member 13 with the metal heat sink formed later; on the other hand, the overall volume of the final semiconductor package 1 can be further reduced by the method of thinning the encapsulation structure 10.
Further optionally, before proceeding to step 300, the packaging method further comprises attaching a support plate 30 to the second surface 10b of the encapsulation structure 10.
The support plate 30 is attached at least in a partial region of the second surface 10b of the enclosing structure 10. As shown in fig. 2 (f), in one embodiment, the support plate 30 is mounted on the second surface 10b of the encapsulation structure 10, and the support plate 30 covers the entire area of the second surface 10b of the encapsulation structure 10.
The material strength of the supporting plate 30 is greater than that of the encapsulation layer, so that the mechanical strength of the encapsulation structure in the encapsulation process can be effectively improved and ensured, adverse effects caused by deformation of each structure can be effectively restrained, and the effect of product encapsulation can be improved. In other embodiments, the support plate may also be formed on the second surface 10b of the encapsulation structure 10 by Spraying, printing, coating, or the like.
In step 300, as shown in fig. 2 (g), the carrier plate 2 is peeled off to expose the first surface 10a of the encapsulation structure 10. The first surface 10a of the encapsulation structure 10 is exposed with the protective layer 12 formed on the front surface of the chip 11 to be packaged, and one end of the metal fixture 13 (the first portion 131 of the metal fixture 13).
Because the bonding layer is a thermal separation film between the carrier plate 2 and the chip to be packaged and the metal fixing piece 13, the bonding layer can be reduced in viscosity after being heated in a heating mode, and then the carrier plate 2 is peeled. By peeling the carrier plate 2 by heating the adhesive layer, damage to the chip 11 to be packaged during peeling can be minimized. In other embodiments, the carrier plate 2 may also be peeled off directly mechanically.
After the carrier plate 2 is peeled off, the first surface 10a of the encapsulation structure 10 facing the carrier plate 2, the front surface of the chip 11 to be packaged, and one end of the metal fixture 13 (the first portion 131 of the metal fixture 13) are exposed. After peeling the carrier plate 2, a first encapsulating structure 10 is obtained comprising the chip 11 to be encapsulated, the metal fixture 13 and an encapsulating layer 14 encapsulating the chip 11 to be encapsulated and the metal fixture 13. On the encapsulation structure 10 formed, rewiring and the like may be performed according to actual conditions, so that the chip 11 to be packaged is electrically connected to the outside.
In addition, since the thickness of the metal fixing member 13 is not smaller than the thickness of the chip 11 to be packaged along the thickness direction T of the semiconductor package structure, when the thickness of the package structure 10 is reduced, the end of the metal fixing member 13 away from the carrier 2 is exposed on the second surface 10b of the package structure 10, the chip 11 to be packaged is still in the encapsulation layer 16 and is not exposed on the second surface 10b of the package structure 10. The thickness of the chip 11 to be packaged refers to the thickness including the protective layer 12. In addition, after the thickness of the encapsulating structure 10 is reduced, one end of the metal fixing member 13, which is far away from the carrier plate 2, is exposed to the second surface 10b of the encapsulating structure 10, it is realized that both ends of the metal fixing member 13 are respectively exposed to the first surface 10a of the encapsulating structure 10 and the second surface 10b of the encapsulating structure 10, so that the double-sided interconnection of the encapsulating structure 10 can be further realized, that is, the first surface 10a of the encapsulating structure 10 and the second surface 10b of the encapsulating structure 10 are communicated through the metal fixing member 13, and heat on the front surface of the chip 11 to be encapsulated can be led to the back surface through the metal fixing member 13, thereby improving the heat dissipation effect.
In the embodiment of the present application, after the carrier plate 2 is peeled off, the surfaces of the protection layer 12 and the metal fixing member are exposed, and at this time, the chip attachment layer in the adhesive layer is still present on the surface of the protection layer 12, and when removed by chemical means, the protection layer 12 can also protect the surface of the chip 11 to be packaged from damage. After the bonding layer is completely removed, if the encapsulating material is permeated before, the surface can be leveled by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the protective layer 12, the surface of the chip 11 to be packaged cannot be treated chemically or by grinding, so as not to damage the circuit on the front surface of the chip 11 to be packaged.
In step 400, as shown in fig. 2 (h) and fig. 2 (i), a rewiring structure 21 is formed on the first surface 10a of the encapsulation structure 10, the rewiring structure 21 being electrically connected to the pads of the front surface of the chip 11 to be packaged; and a metal protector 22 is formed on the first surface 10a of the envelope structure 10. The metal protector 22 is located above the metal fixture 13 and is connected to the metal fixture 13.
Preferably, the metal protector 22 is located outside the rewiring structure 21, so that the edge stress can be further effectively absorbed, thereby protecting the rewiring structure 21 beside the metal protector, improving the reliability of the semiconductor package structure, and avoiding affecting the pattern layout and electrical extraction of the rewiring structure 21 on the first surface 10a of the encapsulation structure 10.
The first surface 10a of the enclosing structure 10 is rectangular, and the metal protector 22 is located at the corners of the rectangle. The metal protector 22 is located at the corners of the rectangle so as to occupy the minimum usable area of the first surface 10a of the enclosing structural member 10; in addition, since the metal protector 22 is provided at the corner where the corner is most concentrated, the stress can be dispersed most effectively, and the risk of the rewiring structure 21 (particularly, the edge position of the rewiring structure 21) falling off and cracking can be avoided.
The rewiring structure 21 is formed in the same process step as the metal guard 22, and the upper surface of the metal guard 22 is flush with the upper surface of the rewiring structure 21. That is, a surface of the metal protector away from the encapsulation structure 10 is flush with a surface of the rewiring structure 21 away from the encapsulation structure 10 to protect the rewiring structure 21 and improve the reliability of the semiconductor package.
It should be noted that although the re-wiring structure 21 and the metal protector 22 are formed in the same process step, the metal protector 22 is separated from the re-wiring structure 21, that is, the metal protector 22 has no electrical property.
Specifically, the rewiring structure 21 includes a stacked first metal layer 211 and second metal layer 212, wherein the first metal layer 211 is a conductive trace, i.e., a rewiring layer; the second metal layer 212 is a conductive stud, i.e., a lead layer. The conductive posts are preferably circular in shape, but may be rectangular, square, or other shapes.
The metal protector 22 includes a first metal protection layer 221 and a second metal protection layer 222 which are laminated. The first metal protection layer 221 and the first metal layer 211 are formed in the same process step, and the second metal protection layer 222 and the second metal layer 212 are formed in the same process step, which may be formed by photolithography and electroplating processes. Since both are formed in the same process step, the upper surface of the finally formed metal protector 22 and the upper surface of the rewiring structure 21 have the effect of being flush.
In this case, since the protective layer opening 121 is already formed on the protective layer 12, at least the protective layer opening 121 can be directly seen when the first metal layer 211 is formed, and thus the first metal layer 211 can be more accurately aligned when formed.
When the first metal layer 211 is formed, the conductive medium 23 may be filled in the protective layer opening 121 of the chip 11 to be packaged at the same time, that is, the first metal layer 211 and the conductive medium 23 are formed in the same conductive layer forming process. The conductive medium 23 forms a vertical connection structure in the protective layer opening 121, so that the bonding pad on the surface of the chip 11 to be packaged is electrically connected with the rewiring structure 21 through the vertical connection structure formed by the conductive medium 23.
The metal fixing member 13, the rewiring structure 21 and the metal protection member 22 are all made of copper.
In step 500, as shown in fig. 2 (j), a dielectric layer 24 is formed, the dielectric layer 24 being formed on the rewiring structure 21, the metal guard 22, and the exposed first surface 10a of the encapsulation structure 10. The dielectric layer 24 may be formed in a Molding film manner, or the dielectric layer 24 may be formed by Lamination (Printing) or Printing (Printing) manner. The dielectric layer 24 may be made of an insulating material such as one or more of polyimide, epoxy, PBO (Polybenzoxazole), etc., preferably an epoxy compound.
Further, in an embodiment, the re-routing may be repeated on the front side of the chip to be packaged, for example, more re-routing structures and more dielectric layers may be formed in the same manner, and may be adjusted according to design requirements. Accordingly, in order to achieve protection of the multilayer rewiring structure, the metal protector forms a structure including a plurality of metal protectors stacked so as to be flush with the final multilayer rewiring structure.
After forming the dielectric layer 24, the dielectric layer 24 is thinned to expose the second metal protection layer 222 of the metal protection part 22 and the second metal protection layer 222 of the metal protection part 22, as shown in fig. 2 (k).
After completion of step 500, the encapsulation method further includes peeling back the support plate 30, as shown in fig. 2 (l). The support plate 30 may be peeled off directly mechanically, or may be peeled off by other methods, which are not limited in this application and may be set according to the specific application environment.
Next, as shown in fig. 2 (m), a metal connection layer 40 is brushed at a predetermined position on the dielectric layer 24 to form the final semiconductor package 1. The metal connection layer 40 functions similarly to the lead frame of the related art, and the semiconductor package structure 1 is electrically connected to the outside through the metal connection layer 40 and is mounted next through the metal connection layer 40.
Specifically, the metal connection layer 40 is located on a side of the second metal layer 212 away from the first metal layer 211, and is directly connected to the second metal layer 212. The material of the metal connection layer 40 is tin, but not limited to tin, but may be nickel-gold alloy, or other metals.
In other embodiments, the semiconductor package 1 may be mounted by alignment without brushing the metal connection layer 40 on the dielectric layer 24 at a predetermined position, by forming the metal connection layer on the surface of other structures (such as PBC boards) on which the semiconductor package 1 is to be mounted.
In addition, if a plurality of semiconductor package structures are packaged together, after the packaging is completed, the whole package structure is cut into a plurality of semiconductor package structures by laser or mechanical cutting. The structure of the semiconductor package 1 formed is shown in fig. 3.
As shown in fig. 3, a schematic structural diagram of a semiconductor package structure 1 obtained by using the above-described semiconductor packaging method according to embodiment 1 of the present application is shown. The semiconductor package 1 includes: an encapsulation structure 10, a rewiring structure 21, a metal protector 22, and a dielectric layer 24.
The encapsulation structure 10 includes opposite first and second surfaces 10a, 10b, the encapsulation structure 10 having a chip 11 and a metal fixture 13 encapsulated therein.
The chip 11 includes a front surface and a back surface disposed opposite to each other, and the front surface of the chip 11 is an active surface. A protective layer 12 is formed on the front surface of the chip 11. First protection layer openings 121 are formed on the protection layer 12 at positions corresponding to the bonding pads of the chip 11, and each first protection layer opening 121 is located at least on the bonding pad of the chip 11 or a line led out from the bonding pad. The front face of the chip 11 corresponds to the first surface 10a of the encapsulation structure 10.
The thickness of the metal fixing member 13 is not smaller than the thickness of the chip 11 in the thickness direction T of the semiconductor package 1. The thickness of the chip 11 refers to the thickness including the protective layer 12. Both ends of the metal fixing member 13 are exposed to the first surface 10a of the encapsulation structure 10 and the second surface 10b of the encapsulation structure 10, respectively, and the metal fixing member 13 is located outside the chip 11. In this way, by arranging the metal fixing piece 13, the purpose of dispersing the stress suffered by the rewiring structure positioned at the edge can be achieved, and meanwhile, the binding force between the metal protecting piece and the plastic packaging material can be improved; and moreover, the strength of the rewiring structure of the packaged product on the PCB can be improved, so that the board-level reliability of the product is improved. Further, through the two ends of the metal fixing member 13 respectively exposed on the first surface 10a of the encapsulation structural member 10 and the second surface 10b of the encapsulation structural member 10, the two-sided interconnection of the encapsulation structural member 10 can be realized, that is, the first surface 10a of the encapsulation structural member 10 and the second surface 10b of the encapsulation structural member 10 are communicated through the metal fixing member 13, and the heat of the front surface of the chip 11 can be led to the back surface through the metal fixing member 13, so that the heat dissipation effect is improved.
The metal fixture 13 includes a first portion 131, a connecting portion 132, and a second portion 133 connected in sequence; the width of the connecting portion 132 of the metal fixing member 13 is smaller than the width of the first portion 131 of the metal fixing member 13 and the width of the second portion 133, that is, the metal fixing member 13 forming an i-shaped structure, and the structure having both ends being wider is advantageous in that, on the one hand, the metal fixing member 13 is stably attached to the carrier plate 2, and on the other hand, in a later step, a larger area of support can be provided for the metal protecting member when the metal protecting member is formed above the metal fixing member 13.
In other embodiments, the metal fixing member 13 may be formed into a T-shaped structure, that is, the metal fixing member 13 includes a first portion 131 and a connecting portion 132 connected in sequence, and the width of the connecting portion 132 of the metal fixing member 13 is smaller than the width of the first portion 131 of the metal fixing member 13, and the first portion 131 provides a larger area support for the metal protection member formed in the later step.
The rewiring structure 21 and the metal protection member 22 are both located on the first surface 10a of the encapsulation structure 10, the metal protection member 22 is located above the metal fixing member 13, the rewiring structure 21 is electrically connected with the bonding pad on the front surface of the chip 11, and the metal protection member 22 is connected with the metal fixing member 13. Specifically, the first protection layer opening 121 is filled with the conductive medium 23, and the conductive medium 23 forms a vertical connection structure in the protection layer opening 121, so that the bonding pad on the surface of the chip 11 is electrically connected with the rewiring structure 21 through the vertical connection structure formed by the conductive medium 23.
The upper surface of the metal protector 22 is flush with the upper surface of the rewiring structure. That is, a surface of the metal protector away from the encapsulation structure 10 is flush with a surface of the rewiring structure 21 away from the encapsulation structure 10 to protect the rewiring structure 21 and improve the reliability of the semiconductor package.
Specifically, the rewiring structure 21 includes a stacked first metal layer 211 and second metal layer 212, wherein the first metal layer 211 is a conductive trace, i.e., a rewiring layer; the second metal layer 212 is a conductive stud, i.e., a lead layer. The conductive posts are preferably circular in shape, but may be rectangular, square, or other shapes.
The metal protector 22 includes a first metal protection layer 221 and a second metal protection layer 222 which are laminated. The first metal protection layer 221 and the first metal layer 211 are formed in the same process step, and the second metal protection layer 222 and the second metal layer 212 are formed in the same process step, which may be formed by photolithography and electroplating processes. Since both are formed in the same process step, the upper surface of the finally formed metal protector 22 and the upper surface of the rewiring structure 21 have the effect of being flush.
Preferably, the metal protector 22 is located outside the rewiring structure 21, so as to further effectively absorb the stress of the edge, protect the rewiring structure 21 beside the metal protector to form protection, improve the reliability of the semiconductor package structure, and avoid affecting the pattern layout and electrical extraction of the rewiring structure 21 of the first surface 10a of the encapsulation structure 10.
The first surface 10a of the enclosing structure 10 is rectangular, and the metal protector 22 is located at the corners of the rectangle. The metal protector 22 is located at the corners of the rectangle so as to occupy the area of use of the first surface 10a of the enclosing structure 10 to a minimum extent that affects the graphical layout of the rewiring structure 21 of the first surface 10a of the enclosing structure 10; moreover, by providing the metal protector 22 where the corners are most concentrated, the dispersion of stresses can be most effectively achieved, avoiding the risk of rewiring structure falling off and cracking during drop testing and temperature cycling reliability capability testing.
A dielectric layer 24 is formed over the rewiring structure 21, the metal guard 22 and the exposed first surface 10a of the encapsulation structure 10.
In the present embodiment, the semiconductor package structure 1 further includes a metal connection layer 40, and the metal connection layer 40 is located on a side of the second metal layer 212 away from the first metal layer 211 and is directly connected to the second metal layer 212. The material of the metal connection layer 40 is tin, but not limited to tin, but may be nickel-gold alloy, or other metals.
Further, in another embodiment, the re-routing may be repeated on the front side of the chip, e.g., more re-routing structures may be formed in the same manner, and more dielectric layers may be adjusted according to design requirements. Accordingly, in order to achieve protection of the multilayer rewiring structure, the metal protector forms a structure including a plurality of metal protectors stacked so as to be flush with the final multilayer rewiring structure.
Example 2
The semiconductor packaging method of this embodiment is basically the same as that of embodiment 1, except that after step 500, that is, after the formation of the dielectric layer, it further includes: a heat sink is formed on the second surface of the encapsulation structure, the heat sink being coupled to the metal fixture.
Specifically, as shown in fig. 4 (a), a heat sink 50 is formed on the second surface 10b of the envelope structure 10, and the heat sink 50 is connected to the end of the metal fixing member 13 remote from the metal protection member 22.
Next, as shown in fig. 4 (b), a metal connection layer 40 is brushed on the dielectric layer 24 at a predetermined position to form the final semiconductor package 1.
As shown in fig. 5, a schematic structural diagram of a semiconductor package 1 obtained by the above-described semiconductor packaging method according to embodiment 2 of the present application is shown. The structure of the semiconductor package 1 is substantially the same as that of embodiment 1, except that: the semiconductor package 1 further includes a heat sink 50, and the heat sink 50 is located on the second surface 10b of the encapsulation structure 10 and is connected to the metal fixture 13.
Thus, the provision of the heat sink 50 can exert an effect of helping the chip 11 to dissipate heat; meanwhile, by connecting the heat sink 50 with the metal fixing member 13, the metal fixing member 13 can function to enhance the bonding force between the heat sink 50 and the molding material (the encapsulating layer of the encapsulating structure), so that the heat sink 50 is not easily detached from the second surface 10b of the encapsulating structure 10.
In the present application, embodiments of the semiconductor package structure and embodiments of the packaging method may be complementary without conflict.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (11)

1. A method of packaging a semiconductor, comprising the steps of:
providing an encapsulation structural member for encapsulating a chip to be encapsulated and a metal fixing member, wherein the metal fixing member is positioned on the outer side of the chip to be encapsulated, the metal fixing member is positioned on the edge part of the encapsulation structural member, the encapsulation structural member comprises a first surface and a second surface which are opposite, and the front surface of the chip to be encapsulated corresponds to the first surface of the encapsulation structural member;
and forming a rewiring structure on the first surface of the encapsulation structural member and a metal protection member positioned above the metal fixing member, wherein the rewiring structure is electrically connected with a welding pad on the front surface of the chip to be packaged, and the metal protection member is connected with the metal fixing member.
2. The semiconductor packaging method of claim 1, wherein prior to forming a rewiring structure on the first surface of the encapsulation structure and a metal guard outside the rewiring structure, the semiconductor packaging method comprises:
attaching the chip to be packaged and the metal fixing piece to a carrier plate, wherein the back surface of the chip to be packaged faces upwards, and the front surface of the chip to be packaged faces towards the carrier plate;
the encapsulation structure is formed by covering the chip to be encapsulated, the metal fixing piece and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structural member.
3. The semiconductor packaging method according to claim 2, wherein after the encapsulation structure is formed, before peeling the carrier plate, the semiconductor packaging method includes:
and thinning the second surface of the encapsulation structure to expose one end of the metal fixing piece.
4. The semiconductor packaging method of claim 1, wherein the re-wiring structure is formed in the same process step as the metal guard, and an upper surface of the metal guard is flush with an upper surface of the re-wiring structure.
5. The semiconductor packaging method of claim 1, wherein after forming a rewiring structure on the first surface of the encapsulation structure and a metal protector located outside the rewiring structure and above the metal mount, the semiconductor packaging method further comprises:
a heat sink is formed on the second surface of the encapsulation structure, the heat sink being coupled to the metal fixture.
6. A semiconductor package structure, comprising:
the packaging structure comprises a first surface and a second surface which are opposite, a chip and a metal fixing piece are packaged in the packaging structure, two ends of the metal fixing piece are respectively exposed out of the first surface and the second surface of the packaging structure, the metal fixing piece is positioned on the outer side of the chip, the metal fixing piece is positioned at the edge part of the packaging structure, and the front face of the chip corresponds to the first surface of the packaging structure;
the rewiring structure and the metal protection piece are both positioned on the first surface of the encapsulation structural part, the metal protection piece is positioned above the metal fixing part, the rewiring structure is electrically connected with the welding pad on the front face of the chip, and the metal protection piece is connected with the metal fixing part.
7. The semiconductor package according to claim 6, wherein the metal fixing member includes a first portion, a connecting portion, and a second portion connected in this order in a thickness direction; the width of the connecting portion of the metal fixing member is smaller than the width of the first portion of the metal fixing member and the width of the second portion.
8. The semiconductor package according to claim 6, wherein an upper surface of the metal protector is flush with an upper surface of the rewiring structure.
9. The semiconductor package structure of claim 6, wherein the metal guard is located outside the rewiring structure.
10. The semiconductor package according to claim 9, wherein the first surface of the encapsulation structure is rectangular, and the metal protector is located at a corner of the rectangle.
11. The semiconductor package according to claim 6, further comprising a heat sink located on the second surface of the encapsulation structure and coupled to the metal fixture.
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