CN113725099B - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN113725099B
CN113725099B CN202010231979.9A CN202010231979A CN113725099B CN 113725099 B CN113725099 B CN 113725099B CN 202010231979 A CN202010231979 A CN 202010231979A CN 113725099 B CN113725099 B CN 113725099B
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die
layer
packaged
metal
encapsulation structure
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CN113725099A (en
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周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing an encapsulation structure encapsulating a first die to be packaged and a metal heat sink; forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged; forming a first dielectric layer, and fixing a second die to be packaged, the front surface of which is provided with a second protective layer, on a second part of the metal radiating fin in the first surface of the encapsulation structure through the first dielectric layer, wherein the back surface of the second die to be packaged is closely attached to the second part of the metal radiating fin; forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure; a second dielectric layer is formed. The semiconductor packaging structure manufactured by the semiconductor packaging method has the advantages of small volume and compact structure, and can effectively dissipate heat.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor packaging method and a semiconductor packaging structure.
Background
Currently, in the packaging process, dies having different functions are often packaged in a package structure to form a specific function, which is called MCM (multi-chip module, chinese name). The MCM has the advantages of small volume, high reliability, high performance, multifunction and the like.
With miniaturization and weight reduction of electronic devices, chip packages having a compact structure and a small volume are increasingly favored in the market.
In addition, the chip can produce heat in the course of working, if the heat that produces is not in time dispelled, can produce harmful effect to work efficiency and life of chip. The heat accumulated in the chip working is effectively dissipated, and the heat dissipation device is a basis for guaranteeing continuous and efficient operation of the chip.
However, how to further reduce the volume of the chip package and to effectively dissipate heat is a problem to be solved in the art.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, including:
providing an encapsulation structure encapsulated with a first die to be encapsulated and a metal heat sink, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first die to be encapsulated, and the second part of the metal heat sink and the first protection layer of the first die to be encapsulated are exposed on the first surface of the encapsulation structure;
Forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer and the first surface of the encapsulation structure, the first protection layer of the first die to be packaged and the second part of the metal radiating fin, and fixing a second die to be packaged, the front surface of which is provided with a second protection layer, on the second part of the metal radiating fin in the first surface of the encapsulation structure through the first dielectric layer, and the back surface of the second die to be packaged is tightly attached to the second part of the metal radiating fin;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
and forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
Optionally, after forming a first dielectric layer, the first dielectric layer is formed on the first rewiring layer and the exposed first surface of the encapsulation structure, the first protection layer of the first die to be packaged and the second portion of the metal heat sink, and a second die to be packaged with a second protection layer formed on the front surface is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, and the back surface of the second die to be packaged is clung to the second portion of the metal heat sink, the semiconductor packaging method includes:
Applying the first dielectric layer over the first rewiring layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink;
after preliminary heating the first dielectric layer, applying the second die to be packaged with the second protective layer formed on the front surface to a position corresponding to the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer;
and continuing to heat the first dielectric layer, wherein the first dielectric layer is cured by heating, the second die to be packaged is cured to a position corresponding to the second part of the metal heat sink in the first surface of the encapsulation structure along with the first dielectric layer, and the back surface of the second die to be packaged is closely attached to the second part of the metal heat sink.
Optionally, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
Optionally, before forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
Forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
mounting the first to-be-packaged bare chip with the first protection layer formed on the front surface and the metal radiating fin on a carrier plate, wherein the back surface of the first to-be-packaged bare chip faces upwards, the front surface faces towards the carrier plate, a first part of the metal radiating fin is clung to the back surface of the first to-be-packaged bare chip, a second part of the metal radiating fin is mounted on the carrier plate;
forming the encapsulation structural member by covering the first die to be encapsulated, the metal heat sink and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged and the second portion of the metal heat sink.
Optionally, after forming the encapsulation structure, before peeling the carrier plate, the semiconductor packaging method includes:
and thinning the second surface of the encapsulation structure far away from the carrier plate to expose one surface of the first part of the metal radiating fin far away from the first die to be packaged.
Optionally, in mounting the first die to be packaged and the metal heat sink with the first protective layer formed on the front surface on a carrier,
the semiconductor packaging method comprises the following steps:
attaching the first die to be packaged with the first protective layer formed on the front surface to a carrier plate;
forming a first metal connection layer on the back surface of the first die to be packaged;
coating a first heat-conducting adhesive on the first metal connecting layer; the method comprises the steps of,
the metal radiating fin is attached to the carrier plate, a first part of the metal radiating fin is located on the first metal connecting layer and is connected with the first metal connecting layer through the first heat conducting adhesive, and a second part of the metal radiating fin is attached to the carrier plate; or,
the semiconductor packaging method comprises the following steps:
attaching the first die to be packaged with the first protective layer formed on the front surface to a carrier plate;
coating a first heat-conducting adhesive on the back surface of the first bare chip to be packaged; the method comprises the steps of,
and the metal radiating fin is attached to the carrier plate, a first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat conducting adhesive, and a second part of the metal radiating fin is attached to the carrier plate.
Optionally, before the first die to be packaged and the metal heat sink with the first protective layer formed on the front surface are mounted on a carrier, the semiconductor packaging method includes:
and grinding the back surface of the first die to be packaged.
Optionally, before the second die to be packaged having the second protective layer formed on the front side is secured to the second portion of the metal heat sink in the first surface of the encapsulation structure by the first dielectric layer,
the semiconductor packaging method comprises the following steps:
forming a second metal connection layer on the back surface of the second die to be packaged; the method comprises the steps of,
coating a second heat-conducting adhesive on the second metal connecting layer; or,
the semiconductor packaging method comprises the following steps:
coating a second heat-conducting adhesive on the back surface of the second bare chip to be packaged; and/or the number of the groups of groups,
in fixing a second die to be packaged, the front face of which is formed with a second protective layer, on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the second portion of the metal heat sink is connected with a second metal connection layer of the second die to be packaged through the second heat conductive glue.
Optionally, before the second die to be packaged having the second protective layer formed on the front surface is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
And grinding the back surface of the second die to be packaged.
Optionally, in forming a first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method includes:
forming a first conductive trace on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive trace being electrically connected with a bond pad of a front side of the first die to be packaged;
forming a first conductive stud on a side of the first conductive trace remote from the encapsulation structure; and/or the number of the groups of groups,
in forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure, the semiconductor packaging method comprises:
forming a second conductive trace on a surface of the first dielectric layer away from the encapsulation structure, wherein the second conductive trace is electrically connected with the first rewiring layer and a bonding pad on the front surface of the second die to be packaged;
and forming a second conductive convex column on one surface of the second conductive trace away from the first dielectric layer.
Optionally, in forming the second dielectric layer, the semiconductor packaging method includes:
the second conductive protruding columns are exposed on one surface of the second dielectric layer away from the first rewiring layer.
Optionally, before the second die to be packaged having the second protective layer formed on the front surface is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front surface of the second die to be packaged.
Another aspect of the present application provides a semiconductor package structure, including:
an encapsulation structure, which comprises a first surface and a second surface which are opposite, wherein the encapsulation structure is provided with a plurality of first cavities and metal radiating fins, each first cavity is concave, each metal radiating fin comprises a first part, a second part and a connecting part connected between the first part and the second part, a first bare chip with a first protection layer formed on the front surface is positioned in the first cavity, the front surface of the first bare chip and the second part of each metal radiating fin are exposed out of the first surface of the encapsulation structure, and the back surface of each first bare chip faces to the first part of each metal radiating fin;
A first rewiring layer located on the first surface of the encapsulation structure and the front side of the first die, the first rewiring layer being electrically connected with a bond pad of the front side of the first die;
a first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure, the first protection layer of the first die to be packaged and the second part of the metal heat sink, wherein the first dielectric layer is also provided with a plurality of second cavities which are concave inwards, the second die with the second protection layer formed on the front surface is positioned in the second cavities, and the back surface of the second die faces to the second part of the metal heat sink;
a second rewiring layer located on a side of the first dielectric layer away from the encapsulation structure, the second rewiring layer being electrically connected to both the first rewiring layer and the bonding pads on the front side of the second die;
and a second dielectric layer formed on the second rewiring layer and the exposed second protective layer of the first dielectric layer and the second die.
Optionally, a side of the first portion of the metal heat sink remote from the first die is exposed from the second surface in the encapsulation structure.
Optionally, the semiconductor package structure further includes:
a first metal connection layer formed on the back surface of the first die;
the first heat-conducting glue is coated on the first metal connecting layer, is positioned between the first metal connecting layer and the first part of the metal radiating fin and is used for connecting the first part of the metal radiating fin with the first metal connecting layer;
a second metal connection layer formed on the back surface of the second die;
and the second heat-conducting glue is coated on the second metal connecting layer, is positioned between the second metal connecting layer and the second part of the metal radiating fin and is used for connecting the second part of the metal radiating fin with the second metal connecting layer.
Optionally, the thickness of the second die is less than the thickness of the encapsulation structure.
Optionally, a side of the second protective layer remote from the second die is flush with a side of the first dielectric layer remote from the encapsulation structure.
Optionally, the first portion of the metal heat sink matches the shape and size of the back side of the first die; and/or the second portion of the metal heat sink matches the shape and size of the back side of the second die.
Optionally, the width of the connecting portion of the metal heat sink is smaller than the width of the first portion of the metal heat sink and the width of the second portion.
According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the first bare chip to be packaged with a certain function is firstly routed once in a manner of packaging and forming the conducting layer, and then the second bare chip to be packaged is fixed on the first surface of the packaging structural member through the first dielectric layer, so that the space between the first bare chip to be packaged and the second bare chip to be packaged is reduced, the formed semiconductor packaging structure is more compact, the beneficial effect of reducing the whole occupied space is realized, and on the other hand, the second bare chip is directly fixed on the first surface of the packaging structural member through the first dielectric layer, so that the first bare chip is prevented from being fixed through the bonding layer, the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further realized; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, copper metal radiating fins are applied to the back surfaces of the first die to be packaged and the second die to be packaged, so that heat accumulated in the use process of the die can be quickly radiated, and continuous and efficient operation of the die in the use process is ensured.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 2 (a) -2 (x) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 3 is a schematic structural view of a semiconductor package structure obtained by using the above semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 4 (a) -4 (d) are process flow diagrams of a method for fabricating a metal heat sink in a semiconductor packaging method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper" and/or "lower" and the like are used for ease of description only and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
As shown in fig. 1, 2 (a) -2 (x), 3 and 4 (a) -4 (d), the present application provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: providing an encapsulation structure encapsulated with a first die to be encapsulated and a metal heat sink, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first die to be encapsulated, and the second part of the metal heat sink and the first protection layer of the first die to be encapsulated are exposed on the first surface of the encapsulation structure;
step 102: forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
step 103: forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer and the first surface of the encapsulation structure, the first protection layer of the first die to be packaged and the second part of the metal radiating fin, and fixing a second die to be packaged, the front surface of which is provided with a second protection layer, on the second part of the metal radiating fin in the first surface of the encapsulation structure through the first dielectric layer, and the back surface of the second die to be packaged is tightly attached to the second part of the metal radiating fin;
Step 104: forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
step 105: and forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
According to the semiconductor packaging method and the semiconductor packaging structure, the first die to be packaged with a certain function is firstly routed once in a manner of packaging and forming the conducting layer, and then the second die to be packaged is fixed on the first surface of the packaging structural member through the first dielectric layer, so that the space between the first die to be packaged and the second die to be packaged is reduced, the structure of the formed semiconductor packaging structure is more compact, the beneficial effect of reducing the whole occupied space is achieved, and on the other hand, the second die is directly fixed on the first surface of the packaging structural member through the first dielectric layer, the first die is prevented from being fixed through the bonding layer, the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further achieved; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, copper metal radiating fins are applied to the back surfaces of the first die to be packaged and the second die to be packaged, so that heat accumulated in the use process of the die can be quickly radiated, and continuous and efficient operation of the die in the use process is ensured.
In this embodiment, in step 101, the semiconductor packaging method includes:
step 1011: forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
step 1012: mounting the first to-be-packaged bare chip with the first protection layer formed on the front surface and the metal radiating fin on a carrier plate, wherein the back surface of the first to-be-packaged bare chip faces upwards, the front surface faces towards the carrier plate, a first part of the metal radiating fin is clung to the back surface of the first to-be-packaged bare chip, a second part of the metal radiating fin is mounted on the carrier plate;
step 1013: forming the encapsulation structural member by covering the first die to be encapsulated, the metal heat sink and the exposed carrier plate with an encapsulation layer;
Step 1014: and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged and the second portion of the metal heat sink.
In step 1011, a first protection layer is formed on the front surface of the first die to be packaged, and the first protection layer may be formed on the front surface of the first semiconductor wafer before the first semiconductor wafer is cut into a plurality of first dies to be packaged, and then the first semiconductor wafer is cut to obtain the first die to be packaged with the first protection layer formed on the front surface. It will be understood, of course, that the first semiconductor wafer may be cut into first dies to be packaged, and then a first protective layer may be formed on the front surface of each first die to be packaged, as the process allows, which is specifically selected according to the actual situation.
As shown in fig. 2 (a), the front surface of the first semiconductor wafer 100, that is, the front surface corresponding to the first die 201 to be packaged, has a first insulating layer 2011 and a first bonding pad 2012, and the first bonding pad 2012 is used for electrically connecting with the outside. The front side of the first die 201 to be packaged is the active side of the first die 201 to be packaged.
As shown in fig. 2 (b), a first protection layer 202 is formed on the front surface of the first semiconductor wafer 100, i.e., the front surface corresponding to the first die 201 to be packaged.
The first protective layer 202 is made of one or more of insulating materials such as polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. Optionally, the material of the protective layer is selected to be insulating and capable of accommodating materials for chemical cleaning, polishing, etc. The first protective layer 202 may be formed on the first semiconductor wafer by Lamination (Coating), coating (Printing), printing (Printing), or the like. The temperature, pressure and time ranges are different according to the materials, and the curing conditions of different materials are different.
Next, as shown in fig. 2 (c), after the step of forming the first protective layer 202 is completed, the back surface of the first semiconductor wafer 100, that is, the back surface corresponding to the first die 201 to be packaged, is polished to thin the thickness of the first die 201 to be packaged, thereby thinning the thickness of the final overall packaging structure, and further realizing the beneficial effect of reducing the overall occupied space.
Then, as shown in fig. 2 (d), the first semiconductor wafer 100 with the first protection layer 202 formed thereon is cut along the scribe line, so as to obtain a plurality of first dies to be packaged 201 with the first protection layer 202 formed thereon. The cutting process may be mechanical cutting or laser cutting.
The first die 201 to be packaged with the first protective layer 202 is shown in fig. 2 (e), where the front surface of the first die 201 to be packaged still has the first insulating layer and the first bonding pad, but they are not labeled in the figure for convenience of subsequent process flow. The first die 201 to be packaged formed through the above steps is a die to be packaged having a specific function.
Next, as shown in fig. 2 (f), first protection layer openings 2021 are formed on the first protection layer 202 at positions corresponding to the bonding pads of the first die 201 to be packaged, and each first protection layer opening 2021 is at least corresponding to the bonding pads of the first die 201 to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the first die 201 to be packaged or the wires led out from the bonding pads are exposed from the first protection layer opening 2021.
If the first protective layer 202 material is a laser reactive material, the first protective layer opening 2021 may be formed in a laser patterning manner; if the first protective layer 202 material is a photosensitive material, then the first protective layer opening 2021 may be formed using photolithographic patterning. The shape of the first protection layer opening 2021 may be round, but may be other shapes such as oval, square, line, etc.
In this embodiment, since the first protection layer opening 2021 is already formed on the first protection layer 202, at least the first protection layer opening 2021 can be directly seen when the first rewiring layer is subsequently formed, so that the first rewiring layer can be more accurately aligned when the first rewiring layer is formed.
Also, the steps of forming a second protective layer on the front side of the second die to be packaged and forming a second protective layer opening on the second protective layer are substantially the same as the steps of forming a first protective layer on the front side of the first die to be packaged and forming a first protective layer opening on the first protective layer. The specific content is as follows:
the second protection layer may be formed on the front surface of the second semiconductor wafer before dicing the second semiconductor wafer into a plurality of second dies to be packaged, and then dicing the second semiconductor wafer to obtain the second dies to be packaged with the second protection layer formed on the front surface. It will be understood, of course, that the second semiconductor wafer may be cut into second dies to be packaged, and then a second protective layer may be formed on the front surface of each second die to be packaged, as the process allows, and this is specifically selected according to the actual situation.
As shown in fig. 2 (g), the front surface of the second semiconductor wafer 100', i.e., the front surface corresponding to the second die 201' to be packaged, has a second insulating layer 2011' and a second pad 2012', and the second pad 2012' is for electrical connection with the outside. The front side of the second die 201 'to be packaged, i.e., the active side of the second die 201' to be packaged.
As shown in fig. 2 (h), a second protection layer 202' is formed on the front surface of the second semiconductor wafer 100', i.e., the front surface corresponding to the second die 201' to be packaged. The material of the second protection layer 202 'is the same as that of the first protection layer 202, and the description of the material of the first protection layer 202 is equally applicable to the material of the second protection layer 202', which will not be described again.
Next, as shown in fig. 2 (i), the back surface of the second semiconductor wafer 100', i.e., the back surface corresponding to the second die 201' to be packaged, is polished to thin the thickness of the second die 201' to be packaged, thereby thinning the thickness of the final overall package structure, and further realizing the beneficial effect of reducing the overall occupied space.
As shown in fig. 2 (j), the second semiconductor wafer 100 'is cut along the scribe lines to obtain a plurality of second dies 201' to be packaged. The cutting process may be mechanical cutting or laser cutting.
The structure of the formed second die 201 'to be packaged is shown in fig. 2 (k), in which the front surface of the second die 201' to be packaged still has the second insulating layer and the second bonding pad, but they are not labeled in the figure for convenience of subsequent process flow.
As shown in fig. 2 (l), second protection layer openings 2021' are formed on the second protection layer 202' at positions corresponding to the bonding pads of the second die 201' to be packaged, and each second protection layer opening 2021' is located at least corresponding to the bonding pads of the second die 201' to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the second die 201' to be packaged or the wires led out from the bonding pads are exposed from the second protection layer opening 2021 '.
As shown in fig. 2 (m), the second protective layer opening 2021 'is filled with a second conductive medium 203' so that the second conductive medium 203 'is electrically connected to the bonding pad of the second die 201' to be packaged, and the second conductive medium 203 'forms a vertical connection structure in the second protective layer opening 2021' so that the bonding pad on the surface of the second die 201 'to be packaged is electrically connected to the second rewiring layer formed in a subsequent step through the connection structure in the second conductive medium 203'.
In some embodiments, the second conductive medium may not be filled in the second protection layer openings, and the plurality of second protection layer openings may still be hollow after the second die to be packaged with the second protection layer is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer.
In step 1012, the following steps are included:
step 10121: as shown in fig. 2 (n), a first die 201 to be packaged with a first protective layer 202 formed on a front surface is attached to a carrier 300 through an adhesive layer (not labeled in the figure), and a back surface of the first die 201 to be packaged faces upward, and a front surface faces the carrier 300.
Step 10122: forming a first metal connection layer (not shown) on the back surface of the first die 201 to be packaged; a first heat conductive paste 600 is coated on the first metal connection layer. The first metal connection layer comprises a titanium metal layer and a copper metal layer which are stacked. Specifically, a titanium metal layer is formed on the back surface of the first die 201 to be packaged by a metal sputtering method; and forming a copper metal layer on the titanium metal layer by using a sputtering method. The first metal connection layer can increase interlayer bonding of the package structure.
Next, a first thermal conductive paste 600 is applied to the back side of the first die 201 to be packaged. The first heat-conductive glue 600 is gel-like or jelly-like to maintain good contact between the backside of the first die 201 to be packaged and the first portion 501 of the metal heat sink 500. The material of the first heat-conducting glue 600 may be silica gel or epoxy resin; the material may be conductive or nonconductive, and is not limited herein, as selected by the specific design requirements.
Step 10123: as shown in fig. 2 (o), the metal heat sink 500 is attached to the carrier 300 through an adhesive layer (not shown). The metal heat sink 500 includes a first portion 501, a second portion 502, and a connection 503 between the first portion 501 and the second portion 502. The first portion 501 of the metal heat sink 500 is located above the first metal connection layer and is connected to the first metal connection layer through the first heat conductive adhesive 600, and the second portion 502 of the metal heat sink 500 is attached to the carrier 300 through an adhesive layer.
In the above steps, in other embodiments, the first metal connection layer may be omitted, the first heat-conducting glue 600 may be directly coated on the back surface of the first die 201 to be packaged, and the first portion 501 of the metal heat spreader 500 is connected to the back surface of the first die 201 to be packaged through the first heat-conducting glue 600, so that the back surface of the first die 201 to be packaged and the first portion 501 of the metal heat spreader 500 maintain good contact.
The bonding layer is used for bonding the first die to be packaged and the metal heat sink, and the bonding layer can be made of a material which is easy to peel off, so that the carrier plate, the first die to be packaged and the metal heat sink are peeled off in the subsequent process, for example, a thermal separation material which can lose adhesiveness through heating can be adopted.
In other embodiments, the bonding layer may be a two-layer structure, where the thermally-separable material layer and the die attach layer are adhered to the carrier, and the thermally-separable material layer loses adhesion when heated, and is then peeled off from the carrier, and the die attach layer is an adhesive material layer, and may be used to adhere the first die to be packaged and the metal heat sink. And after the first die to be packaged and the metal heat sink are peeled off from the carrier plate, the die attachment layer thereon can be removed by a chemical cleaning mode. In one embodiment, the adhesive layer may be formed on the carrier plate by lamination, printing, or the like.
As shown in fig. 2 (o), the first die 201 to be packaged and the metal heat sink 500 are placed on the carrier 300 according to a predetermined arrangement position, and for convenience of illustration, only one stacked and combined first die 201 to be packaged and metal heat sink 500 are shown in the figure, and in fact, a plurality of stacked and combined first dies 201 to be packaged and metal heat sinks 500 are arranged on the carrier 300 according to a predetermined position.
It can be understood that in the one-time packaging process, the first die 201 to be packaged and the metal heat sink 500 may be plural, that is, the first die 201 to be packaged and the metal heat sink 500 are simultaneously mounted on the carrier 300 in a stacked manner, packaged, and then cut into plural packages after packaging is completed; one package may include one or more stacked and combined first dies 201 and metal heat sinks 500, and the positions of the one or more stacked and combined first dies 201 and metal heat sinks 500 may be freely set according to the needs of actual products.
In step 1013, as shown in fig. 2 (p), the first die 201 to be packaged with the first protective layer 202 formed on the front surface and the metal heat sink 500 are encapsulated by covering the entire carrier 300 with the encapsulation layer 204, so as to form the encapsulation structure 200. The encapsulation structure 200 is a flat structure on which rewiring and packaging can continue after the carrier 300 is peeled off.
In one embodiment, the encapsulation layer 204 may be formed by laminating an epoxy film or ABF (Ajinomoto buildup film), or may be formed by injection molding (Injection molding), compression molding (Compression molding), or Transfer molding (Transfer molding) an epoxy compound.
When encapsulating with the encapsulation layer 204, the encapsulation material easily penetrates between the carrier 300 and the first die 201 to be encapsulated during this process, since the encapsulation layer requires high pressure molding at the time of molding. By the embodiment of the application, a first protection layer 202 is formed outside the first die 201 to be packaged, the first protection layer 202 can prevent the encapsulation material from penetrating to the surface of the first die 201 to be packaged, and even if the encapsulation material penetrates, the surface of the first protection layer 202 can be directly treated by a chemical method or a grinding method after being peeled off from the carrier plate, so that the front surface of the first die 201 to be packaged cannot be directly contacted, and the circuit structure of the front surface of the first die 201 to be packaged cannot be damaged.
The encapsulation structure 200 includes a first surface 2001 and a second surface 2002 disposed opposite to each other, and the second surface 2002 is disposed opposite to the carrier 300, substantially flat, and parallel to the surface of the carrier 300. As shown in fig. 2 (q), the thickness of the encapsulating structure 200 may be reduced by grinding or polishing the second surface 2002, and further, by reducing the thickness of the encapsulating structure 200 to expose a surface of the first portion 501 of the metal heat spreader 500, which is far away from the first die 201 to be packaged, on the second surface 2002 of the encapsulating structure 200, a surface of the first portion 501 of the metal heat spreader 500, which is far away from the first die 201 to be packaged, is exposed by reducing the thickness of the encapsulating structure 200, which further helps to rapidly dissipate heat accumulated during use of the die, and ensures continuous and efficient operation of the die during use.
In step 1014, as shown in fig. 2 (r), the carrier plate 300 is peeled off, exposing the first surface 2001 of the encapsulation structure 200 with the front side of the first die 201 to be packaged and the second portion 502 of the metal heat sink 500.
Since the adhesive layer between the carrier 300 and the first die 201 to be packaged is a thermal separation film, the adhesive layer can be reduced in viscosity after being heated by heating, so as to peel off the carrier 300. By peeling the carrier 300 by heating the adhesive layer, damage to the first die 201 to be packaged during peeling can be minimized. In other embodiments, the carrier plate 300 may also be peeled off directly mechanically.
After the carrier 300 is peeled off, the first surface 2001 of the encapsulation structure 200 facing the carrier 300, the front surface of the first die 201 to be packaged, and the second portion 502 of the metal heat sink 500 are exposed. After the carrier 300 is peeled off, an encapsulation structure 200 is obtained that includes the first die 201 to be encapsulated, the metal heat sink 500, the first protective layer 202 covering the front surface of the first die 201 to be encapsulated, and the encapsulation layer 204 encapsulating the back surface of the first die 201 to be encapsulated and the metal heat sink 500, as shown in fig. 2(s). On the encapsulation structure 200 formed, rewiring or the like may be performed according to actual circumstances, so that the first die 201 to be packaged is electrically connected to the outside.
In the embodiment of the present application, after the carrier 300 is peeled off, the surfaces of the first protection layer 202 and the die attach layer in the adhesive layer are exposed, and when the die attach layer is chemically removed, the first protection layer 202 can also protect the surface of the first die 201 to be packaged from being damaged. After the bonding layer is completely removed, if the encapsulating material is permeated before, the surface can be leveled by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the first protective layer 202, the surface of the first die 201 to be packaged cannot be treated chemically or by polishing, so as not to damage the circuits on the front surface of the first die 201 to be packaged.
In step 102, as shown in fig. 2 (t), a first rewiring layer 206 is formed on the first surface 2001 of the encapsulation structure 200, the first rewiring layer 206 being electrically connected with the pads of the front side of the first die 201 to be packaged. Specifically, the method comprises the following steps:
step 1021: forming a first conductive trace 2061 on the first surface 2001 of the encapsulation structure 200 encapsulating the first die 201 to be packaged;
step 1022: a first conductive stud 2062 is formed on a side of the first conductive trace 2061 remote from the encapsulation structure 200.
In step 1021, the first conductive trace 2061 is electrically connected to the bonding pad of the front side of the first die 201 to be packaged, and the first conductive trace 2061 is electrically connected to the bonding pad of the first die 201 to be packaged through the first protection layer opening 2021.
In this case, since the first protective layer opening 2021 is already formed on the first protective layer 202, at least the protective layer opening 2021 can be directly seen when the first rewiring layer 206 is formed, and thus the first rewiring layer 206 can be more accurately aligned.
In forming the first conductive trace 2061, the first conductive medium 203 may be filled within the first protective layer opening 2021 of the first die 201 to be packaged at the same time, i.e., the first conductive trace and the first conductive medium are formed in the same conductive layer forming process. The first conductive medium 203 forms a vertical connection structure in the first protection layer opening 2021, such that the bonding pad on the surface of the first die 201 to be packaged is electrically connected to the first rewiring layer 206 through the connection structure in the first conductive medium 203.
In step 1022, the shape of the first conductive bump 2062 is preferably circular, but may be rectangular, square, or other shapes, and the first conductive bump 2062 is electrically connected to the first conductive trace 2061. Specifically, the first conductive stud 2062 may be formed on the first conductive trace 2061 by photolithography and electroplating.
In another embodiment, a first dielectric layer may be formed on the first surface 2001 of the encapsulation structure 200 and the exposed first protective layer 202 and the first conductive trace 2061 after forming the first conductive trace 2061, and the first dielectric layer has a first opening, and then forming a first conductive stud 2062 electrically connected with the first conductive trace 2061 in the first opening of the first dielectric layer. In this process, the first rewiring layer 206 includes the first conductive trace 2061 and the first conductive stud 2062.
In yet another embodiment, the first opening of the first conductive trace may also be left unfilled, i.e., the first conductive stud 2062 electrically connected to the first conductive trace 2061 is not formed, such that the bond pad or connection point of the first rewiring layer of the completed package is exposed from the first opening. In this process, the first rewiring layer 206 comprises only the first conductive trace 2061.
In step 103, as shown in fig. 2 (u), a first dielectric layer 207 is formed, the first dielectric layer 207 is formed on the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protective layer 202 of the first die 201 to be packaged and the second portion 502 of the metal heat sink 500, and the second die 201' to be packaged having the second protective layer 202' formed on the front side is fixed on the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207, and the back side of the second die 201' to be packaged is abutted against the second portion 502 of the metal heat sink 500. Specifically, the method comprises the following steps:
Step 1031: a first dielectric layer 207 is applied over the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protective layer 202 of the first die 201 to be packaged, and the second portion 502 of the metal heat sink 500. The first dielectric layer 207 is made of an insulating material such as one or more of polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. The first dielectric layer 207 may be formed by Lamination (Lamination), molding (Molding), or Printing (Printing), and preferably an epoxy compound is used.
Step 1031: after the first dielectric layer 207 is initially heated, a second die 201 'to be packaged having a second protective layer 202' formed on a front surface thereof is applied through the first dielectric layer 207 to a location in the first surface 2001 of the encapsulation structure 200 corresponding to the second portion 502 of the metal heat sink 500. Since the viscosity of the initially heated first dielectric layer 207 is first reduced and the first dielectric layer 207 at this time has a strong fluidity, the second die 201 'to be packaged is placed at a predetermined position corresponding to the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200, and the back surface of the second die 201' to be packaged faces the first surface 2001 of the encapsulation structure 200, and the initially heated first dielectric layer 207 between the second portion 502 of the metal heat sink 500 and the second die 201 'to be packaged can be squeezed away and around the second die 201' to be packaged by applying pressure.
Step 1033: continuing to heat the first dielectric layer 207, as the heating proceeds, the first dielectric layer 207 is thermally cured, and the second die 201' to be packaged is brought into close proximity with the second portion 502 of the metal heat sink 500 as the first dielectric layer 207 cures to a position in the first surface 2001 of the encapsulation structure 200 corresponding to the second portion 502 of the metal heat sink 500.
It should be noted that the time and temperature of the preliminary heating are determined according to the specific kind of the material of the first dielectric layer 207, and general rules are as follows: the temperature of the preliminary heating is below the curing temperature of the material of the first dielectric layer 207.
The viscosity of the material of the first dielectric layer 207 decreases due to an increase in temperature, which increases the viscosity by cross-linking between molecules of the material of the first dielectric layer 207 when the temperature is increased above the curing temperature, which is chosen to be below and controllable below the curing temperature, according to the rheological characteristics of the material of the first dielectric layer 207 during curing.
After the second die 201 'to be encapsulated having the second protective layer 202' formed on the front surface is applied to the first surface 2001 of the encapsulation structure 200 at a location corresponding to the second portion 502 of the metal heat spreader 500, the temperature may be raised to or above the curing temperature of the material of the first dielectric layer 207, the curing thermodynamics of the different materials being different, the specific heating time being determined from the data of the curing thermodynamics of the material, the heating temperature being a temperature above the curing temperature, the heating time being the time for complete curing corresponding to the heating of the first dielectric layer 207 to the heating temperature, generally the shorter the heating temperature, i.e. the shorter the curing time, the higher the heating temperature the required for complete cross-linking of the material.
In this embodiment, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees. The heating time is 1-4 hours, and the temperature is 190-200 ℃.
As shown in fig. 2 (u), a surface of the second protection layer 202 'away from the second die 201' to be packaged is flush with a surface of the first dielectric layer 207 away from the first die 201 to be packaged, so as to ensure that the connection is formed on a plane when the first rewiring layer 208 is formed.
As can be seen from the above, the step of fixing the second die 201' to be packaged to the first surface 2001 of the encapsulation structure 200 at a position corresponding to the second portion 502 of the metal heat sink 500 and the step of forming the first dielectric layer 207 on the first surface 2001 of the encapsulation structure 200 are performed simultaneously.
Before step 1031, i.e., before the second die 201 'to be packaged having the second protective layer 202' formed on the front surface is fixed on the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200 by the first dielectric layer 207, further comprises: forming a second metal connection layer (not labeled in the figure) on the back side of the second die 201' to be packaged; a second heat conductive paste 600' is coated on the second metal connection layer. The structure of the second metal connecting layer is the same as that of the first metal connecting layer, and the description is not repeated here; the second heat conductive paste 600' is the same as the first heat conductive paste 600, and will not be described again.
The second portion 502 of the metal heat sink 500 is connected to the second metal connection layer of the second die 201 'to be packaged by a second heat conductive glue 600'.
In the above steps, in other embodiments, the second metal connection layer may be omitted, and the second heat-conducting glue 600' may be directly coated on the back surface of the second die 201' to be packaged, and the second portion 502 of the metal heat spreader 500 is connected to the back surface of the second die 201' through the second heat-conducting glue 600', so that the back surface of the second die 201' to be packaged and the second portion 502 of the metal heat spreader 500 are kept in good contact.
In step 104, as shown in fig. 2 (v), a second rewiring layer 208 is formed on a side of the first dielectric layer 206 remote from the encapsulation structure 200, the second rewiring layer 208 being electrically connected to both the first rewiring layer 206 and the bonding pads of the front side of the second die 201' to be packaged. Specifically, the method comprises the following steps:
step 1041: forming a second conductive trace 2081 on a surface of the first dielectric layer 206 away from the encapsulation structure 200, wherein the second conductive trace 2081 is electrically connected to the first rewiring layer 206 and the bonding pad on the front surface of the second die 201' to be packaged;
step 1042: a second conductive stud 2082 is formed on a side of the second conductive trace 2081 away from the first dielectric layer 207.
In step 1041, the second conductive trace 2081 is electrically connected to the pad on the front side of the second die 201' to be packaged, and the second conductive trace 2081 is electrically connected to the pad of the second die 201' to be packaged through the second conductive medium 203' in the second passivation layer opening 2021.
In this embodiment, since the second conductive medium 203 'is already formed in the second passivation layer opening 2021, at least the second conductive medium 203' can be directly seen when the second conductive trace 2081 is formed, and thus the second conductive trace 2081 can be more accurately aligned when formed.
In some embodiments, where the second conductive medium is not filled in the second protective layer opening before the second die to be packaged with the second protective layer formed on the front side is fixed to the first surface of the encapsulation structure by the first dielectric layer, the second conductive medium may be filled in the second protective layer opening of the second die to be packaged at the same time when the second conductive trace is formed, i.e., the second conductive trace and the second conductive medium are formed in the same conductive layer forming process.
In step 1042, the shape of the second conductive stud 2082 is preferably circular, but it can be rectangular, square, etc., and the second conductive stud 2082 is electrically connected to the second conductive trace 2081. Specifically, the second conductive stud 2082 may be formed on the second conductive trace 2081 by photolithography and electroplating.
In another embodiment, a second dielectric layer may be formed on the second conductive trace 2081 and the exposed second passivation layer 202' and the first dielectric layer after the second conductive trace 2081, and the second dielectric layer has a second opening, and then a second conductive stud 2082 electrically connected to the second conductive trace 2081 is formed in the second opening of the second dielectric layer. In this process, the second rewiring layer 208 includes the second conductive trace 2081 and the second conductive stud 2082.
In yet another embodiment, the second openings of the second conductive traces may also be left unfilled, i.e., the second conductive studs 2082 electrically connected to the second conductive traces 2081 are not formed, so that the pads or connection points of the second rewiring layer of the completed package are exposed from the second openings. In this process, the second rewiring layer 208 comprises only the second conductive trace 2081.
In step 105, as shown in fig. 2 (w), a second dielectric layer 209 is formed on the second protective layer 202 'formed on the second rewiring layer 208 and the exposed first dielectric layer 207 and second die 201' to be packaged.
The material of the second dielectric layer 209 is the same as that of the first dielectric layer 207, and will not be described again.
In order to expose the second conductive stud 2082 on a surface of the second dielectric layer 209 away from the first rewiring layer 206, the thickness of the second dielectric layer 209 may be the thickness of the surface of the second conductive stud 2082 that is just exposed; the second dielectric layer 209 may also cover all exposed surfaces of the first dielectric layer 207 and the second rewiring layer 208, and then be thinned to the surface of the second conductive stud 2082. In this process, the second rewiring layer 208 includes the second conductive trace 2081 and the second conductive stud 2082.
The first rewiring layer 206, the first dielectric layer 207, the second rewiring layer 208 and the second dielectric layer 209 all belong to a rewiring structure.
Further, in an embodiment, repeated rewiring may be performed on the front sides of the first die and the second die, such as a third rewiring layer or layers may be formed outside the second dielectric layer in the same manner to achieve a multi-layer rewiring structure of the product.
Then, after the package of the rewiring structure is completed, the whole package structure is cut into a plurality of packages, that is, a plurality of semiconductor package structures, by laser or mechanical cutting, as shown in fig. 2 (x), and the structure diagram of the formed semiconductor package structure is shown in fig. 3.
As shown in fig. 4 (a) -4 (d), the method for manufacturing the metal heat sink in the above semiconductor packaging method is as follows:
step 1001: as shown in fig. 4 (a), a large sheet of metal foil 400, preferably copper foil, is provided.
Step 1002: the large sheet of metal foil 400 is cut or stamped to form a plurality of small sheets of metal foil 400' in an asymmetric H-shape as shown in fig. 4 (b). That is, a plurality of H-shaped small pieces of metal foil 400' are formed at one time by cutting or punching the large piece of metal foil 400.
Step 1003: as shown in fig. 4 (c), the metal foil of the die is bent to form a metal heat sink 500 with a semi-convex structure, and the bottom space of the metal heat sink 500 with the semi-convex structure is suitable for accommodating the first die to be packaged. Specifically, the metal heat sink 500 includes a first portion 501, a second portion 502, and a connection 503 between the first portion 501 and the second portion 502, wherein the first portion 501 and the second portion 502 are located in different planes. The first portion 501 and the connection portion 503 form a receiving cavity 504 for receiving a first die to be packaged.
The shape and size of the first portion 501 of the metal heat sink 500 and the shape and size of the back side of the first die 201 to be packaged are matched, and the shape and size of the second portion 502 of the metal heat sink 500 and the shape and size of the back side of the second die 201' to be packaged are matched for better heat dissipation. The width w3 of the connection portion 503 of the metal heat sink 500 is smaller than the width w1 of the first portion 501 and the width w2 of the second portion 502 of the metal heat sink 500 to more easily achieve bending. The width w3 of the connection portion 503 of the metal heat sink 500 is smaller than the width w1 of the first portion 501 and the width w2 of the second portion 502 of the metal heat sink 500, which is achieved in step 1002 by forming the metal foil 400' in an H shape (refer to fig. 4 (b)), i.e. the connection portion 503 removes a part of the material, so that the overall shape of the metal heat sink 500 is in an H shape. After the connection portion 503 removes the partial area, a deformation accommodating space can be provided for the thermal expansion and the cold contraction of the metal heat sink 500 in the packaging process.
Then, the metal heat sink with the semi-convex structure can be adhered to the supporting plate by the adhesive layer, or directly adhered into a whole by the thick adhesive layer.
As shown in fig. 4 (d), by bonding the metal heat sink 500 of a semi-convex structure to the support plate 700 using an adhesive layer, a plurality of metal heat sinks 500 arranged on the support plate 700 can be simultaneously transferred to predetermined positions on the carrier plate in batch, and the first portion 501 of the metal heat sink 500 is contacted with the back surface of the first die to be packaged through the first heat conductive adhesive.
Referring back to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by using the above semiconductor packaging method according to an exemplary embodiment of the present application. The semiconductor package structure includes: an encapsulation structure 200 encapsulating a first die 201 and a metal heat sink 500, a first rewiring layer 206, a first dielectric layer 207 with a second die 201' affixed thereto, a second rewiring layer 208, and a second dielectric layer 209. Wherein the first rewiring layer 206, the first dielectric layer 207, the second rewiring layer 208 and the second dielectric layer 209 all belong to a rewiring structure, that is, the second die 201 'is fixed on the first surface 2001 of the encapsulation structure 200 during the process of forming the rewiring structure on the first surface 2001 of the encapsulation structure 200, and the rewiring structure is electrically connected with both the first die 201 and the second die 201'.
The encapsulation structure 200 includes opposing first and second surfaces 2001, 2002, and the encapsulation structure 200 is provided with a plurality of first cavities recessed therein and a metal heat sink 500. The metal heat sink 500 includes a first portion 501, a second portion 502, and a connection 503 between the first portion 501 and the second portion 502. A first die 201 with a first protective layer 202 formed on the front surface is located within the first cavity. The front side of the first die 201 and the second portion 502 of the metal heat sink 500 are exposed at the first surface 2001 of the encapsulation structure 200, and the back side of the first die 201 faces the first portion 501 of the metal heat sink 500.
The first rewiring layer 206 is located on the first surface 2001 of the encapsulation structure 200 and the front side of the first die 201, the first rewiring layer 206 being electrically connected with the pads of the front side of the first die 201. Specifically, the first rewiring layer 206 includes a first conductive trace 2061 and a first conductive stud 2062. A first conductive trace 2061 is formed on the first surface 2001 of the encapsulation structure 200, the first conductive trace 2061 being electrically connected with a bond pad of the front side of the first die 201, in particular, the first conductive trace 2061 being electrically connected with a bond pad of the first die 201 through the second conductive medium 203 in the first protective layer opening 2021. A first conductive stud 2062 is formed on a side of the first conductive trace 2061 remote from the encapsulation structure 200.
The first dielectric layer 207 is formed on the first rewiring layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protection layer 202 of the first die 201, and the second portion 502 of the metal heat spreader 500, the first dielectric layer 207 is further provided with a plurality of concave second cavities, the second die 201' having the second protection layer 202' formed on the front surface is located in the second cavities, and the back surface of the second die 201' faces the second portion 502 of the metal heat spreader 500.
The second rewiring layer 208 is located on a side of the first dielectric layer 206 remote from the encapsulation structure 200, and the second rewiring layer 208 is electrically connected to both the first rewiring layer 206 and the bonding pads on the front side of the second die 201'. Specifically, the second rewiring layer 208 includes a second conductive trace 2081 and a second conductive stud 2082. Second conductive trace 2081 is formed on a side of first dielectric layer 206 remote from encapsulation structure 200, second conductive trace 2081 is electrically connected to a pad on the front side of second die 201', and second conductive trace 2081 is electrically connected to a pad of second die 201' through second conductive medium 203' in second cap opening 2021. The first conductive stud 2062 is formed on a side of the second conductive trace 2081 remote from the first dielectric layer 207.
A second dielectric layer 209 is formed over the second rewiring layer 208 and the exposed first dielectric layer 207 and second protective layer 202 'of the second die 201'.
In this way, in the semiconductor packaging structure of the embodiment, the first die with a certain function is firstly routed once in a manner of packaging and forming the conductive layer, and then the second die is fixed on the first surface of the packaging structural member through the first dielectric layer, so that on one hand, the space between the first die and the second die is reduced, the structure of the formed semiconductor packaging structure is more compact, the beneficial effect of reducing the whole occupied space is realized, on the other hand, the second die is directly fixed on the first surface of the packaging structural member through the first dielectric layer, the first die is prevented from being fixed through the adhesive layer, and therefore the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further realized; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, copper metal radiating fins are applied to the back surfaces of the first bare chip and the second bare chip, so that heat accumulated in the use process of the bare chip can be quickly radiated, and continuous and efficient operation of the bare chip in the use process is ensured.
In this embodiment, a side of the first portion 501 of the metal heat sink 500 remote from the first die 201 is exposed to the second surface 2002 of the encapsulation structure 200. By exposing the side of the first portion 501 of the metal heat sink 500 that is remote from the first die 201, the heat accumulated by the die during use is further facilitated to be dissipated quickly, ensuring continued efficient operation of the die during use.
In this embodiment, the semiconductor package further includes a first metal connection layer (not labeled in the drawing), a first thermal conductive adhesive, a second metal connection layer (not labeled in the drawing), and a second thermal conductive adhesive.
A first metal connection layer is formed on the back side of the first die 201. The first metal connection layer comprises a titanium metal layer and a copper metal layer which are stacked. Specifically, a titanium metal layer is formed on the back surface of the first die 201 by a metal sputtering method; and forming a copper metal layer on the titanium metal layer by using a sputtering method. The first metal connection layer can increase interlayer bonding of the package structure.
A first thermal conductive paste 600 is applied to the first metal connection layer between the first metal connection layer and the first portion 501 of the metal heat sink 500 for connecting the first portion 501 of the metal heat sink 500 to the first metal connection layer so that the back surface of the first die 201 and the first portion 501 of the metal heat sink 500 remain in good contact.
In other embodiments, the first metal connection layer may be omitted, the first heat-conducting glue 600 may be directly coated on the back surface of the first die 201, and the first portion 501 of the metal heat spreader 500 is connected to the back surface of the first die 201 through the first heat-conducting glue 600, so that the back surface of the first die 201 and the first portion 501 of the metal heat spreader 500 maintain good contact.
The second metal connection layer is formed on the back side of the second die. The second metal connection layer has the same structure as the first metal connection layer, and will not be described again here.
The second heat-conducting glue 600' is coated on the second metal connection layer, and is located between the second metal connection layer and the second portion 502 of the metal heat sink 500, for connecting the second portion 502 of the metal heat sink 500 with the second metal connection layer, so that the back surface of the first die 201 and the first portion 501 of the metal heat sink 500 maintain good contact.
In other embodiments, the second metal connection layer may be omitted, and the second heat-conducting glue 600' may be directly coated on the back surface of the second die 201', and the second portion 502 of the metal heat sink 500 may be connected to the back surface of the second die 201' through the second heat-conducting glue 600', so that the back surface of the second die 201' and the second portion 502 of the metal heat sink 500 maintain good contact.
In this embodiment, the thickness H1 of the second die 201' is less than the thickness H1 of the encapsulation structure 200. Since the second die 201' is secured to the encapsulation structure 200 by the first dielectric layer 207 during fabrication, the thickness H1 of the second die 201' is set to be less than the thickness H1 of the encapsulation structure 200 to enable the encapsulation structure 200 to provide better support when the second die 201' is secured to the encapsulation structure 200 by the first dielectric layer 207. In addition, the occupied space of the whole packaging structure is reduced.
The side of the second protective layer 202 'remote from the second die 201' is flush with the side of the first dielectric layer 207 remote from the encapsulation structure 200 to provide a flat base surface for the next step in the fabrication process to form the second rewiring layer 208 to improve the performance of the final semiconductor package.
The first portion 501 of the metal heat sink 500 and the back side of the first die 201 are shaped and sized to match the shape and size of the second portion 502 of the metal heat sink 500 and the back side of the second die 201' to achieve better heat dissipation.
The width of the connection portion 503 of the metal heat sink 500 is smaller than the width of the first portion 501 and the width of the second portion 502 of the metal heat sink 500, so as to provide a deformation accommodating space for thermal expansion and contraction of the metal heat sink 500 in the packaging process.
In another embodiment, the rewiring structure comprises a plurality of rewiring layers to achieve multi-layer rewiring of a product.
In the application, the device embodiment and the method embodiment can be mutually complemented under the condition of no conflict.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.

Claims (21)

1. A method of packaging a semiconductor, comprising:
providing an encapsulation structure encapsulated with a first die to be encapsulated and a metal heat sink, wherein a first protection layer is formed on the front surface of the first die to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first die to be encapsulated, and the second part of the metal heat sink and the first protection layer of the first die to be encapsulated are exposed on the first surface of the encapsulation structure;
forming a first rewiring layer on a first surface of the encapsulation structure, the first rewiring layer being electrically connected with a bond pad of a front side of the first die to be packaged;
Forming a first dielectric layer, wherein the first dielectric layer is formed on the first rewiring layer and the first surface of the encapsulation structure, the first protection layer of the first die to be packaged and the second part of the metal radiating fin, and fixing a second die to be packaged, the front surface of which is provided with a second protection layer, on the second part of the metal radiating fin in the first surface of the encapsulation structure through the first dielectric layer, and the back surface of the second die to be packaged is tightly attached to the second part of the metal radiating fin;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
and forming a second dielectric layer on a second protective layer formed on the second rewiring layer and the exposed first dielectric layer and the second die to be packaged.
2. The semiconductor packaging method according to claim 1, wherein, in forming a first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink, and fixing a second die to be packaged having a second protective layer formed on a front surface thereof on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, a back surface of the second die to be packaged is abutted in the second portion of the metal heat sink, the semiconductor packaging method comprising:
Applying the first dielectric layer over the first rewiring layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink;
after preliminary heating the first dielectric layer, applying the second die to be packaged with the second protective layer formed on the front surface to a position corresponding to the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer;
and continuing to heat the first dielectric layer, wherein the first dielectric layer is cured by heating, the second die to be packaged is cured to a position corresponding to the second part of the metal heat sink in the first surface of the encapsulation structure along with the first dielectric layer, and the back surface of the second die to be packaged is closely attached to the second part of the metal heat sink.
3. The semiconductor packaging method according to claim 2, wherein the preliminary heating time is 30 seconds to 60 seconds and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
4. The semiconductor packaging method of claim 1, wherein prior to forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
Forming a first protection layer on the front surface of a first die to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
mounting the first to-be-packaged bare chip with the first protection layer formed on the front surface and the metal radiating fin on a carrier plate, wherein the back surface of the first to-be-packaged bare chip faces upwards, the front surface faces towards the carrier plate, a first part of the metal radiating fin is clung to the back surface of the first to-be-packaged bare chip, a second part of the metal radiating fin is mounted on the carrier plate;
forming the encapsulation structural member by covering the first die to be encapsulated, the metal heat sink and the exposed carrier plate with an encapsulation layer;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first die to be packaged and the second portion of the metal heat sink.
5. The semiconductor packaging method according to claim 4, wherein after the encapsulation structure is formed, before peeling the carrier plate, the semiconductor packaging method comprises:
and thinning the second surface of the encapsulation structure far away from the carrier plate to expose one surface of the first part of the metal radiating fin far away from the first die to be packaged.
6. The semiconductor packaging method of claim 4, wherein in mounting the first die to be packaged and the metal heat sink with the first protective layer formed on the front surface on a carrier,
the semiconductor packaging method comprises the following steps:
attaching the first die to be packaged with the first protective layer formed on the front surface to a carrier plate;
forming a first metal connection layer on the back surface of the first die to be packaged;
coating a first heat-conducting adhesive on the first metal connecting layer; the method comprises the steps of,
the metal radiating fin is attached to the carrier plate, a first part of the metal radiating fin is located on the first metal connecting layer and is connected with the first metal connecting layer through the first heat conducting adhesive, and a second part of the metal radiating fin is attached to the carrier plate; or,
the semiconductor packaging method comprises the following steps:
attaching the first die to be packaged with the first protective layer formed on the front surface to a carrier plate;
coating a first heat-conducting adhesive on the back surface of the first bare chip to be packaged; the method comprises the steps of,
and the metal radiating fin is attached to the carrier plate, a first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat conducting adhesive, and a second part of the metal radiating fin is attached to the carrier plate.
7. The semiconductor packaging method according to claim 4, wherein before the first die to be packaged and the metal heat sink, on which the first protective layer is formed on the front surface, are mounted on a carrier, the semiconductor packaging method comprises:
and grinding the back surface of the first die to be packaged.
8. The semiconductor packaging method of claim 1, wherein, prior to securing a second die to be packaged having a second protective layer formed on a front side thereof on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer,
the semiconductor packaging method comprises the following steps:
forming a second metal connection layer on the back surface of the second die to be packaged; a kind of electronic device with high-pressure air-conditioning system
And coating a second heat-conducting adhesive on the second metal connecting layer.
9. The semiconductor packaging method of claim 8, wherein, prior to securing a second die to be packaged having a second protective layer formed on a front side thereof on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer,
in fixing a second die to be packaged, the front face of which is formed with a second protective layer, on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the second portion of the metal heat sink is connected with a second metal connection layer of the second die to be packaged through the second heat conductive glue.
10. The semiconductor packaging method of claim 1, wherein prior to securing a second die to be packaged having a second protective layer formed on a front side thereof on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method comprises:
the semiconductor packaging method comprises the following steps:
and coating a second heat-conducting adhesive on the back surface of the second bare chip to be packaged.
11. The semiconductor packaging method of claim 1, wherein prior to securing a second die to be packaged having a second protective layer formed on a front side thereof on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method comprises:
and grinding the back surface of the second die to be packaged.
12. The semiconductor packaging method of claim 1, wherein in forming the first rewiring layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming a first conductive trace on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive trace being electrically connected with a bond pad of a front side of the first die to be packaged;
A first conductive stud is formed on a side of the first conductive trace remote from the encapsulation structure.
13. The semiconductor packaging method of claim 1, wherein in forming the second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure, the semiconductor packaging method comprises:
forming a second conductive trace on a surface of the first dielectric layer away from the encapsulation structure, wherein the second conductive trace is electrically connected with the first rewiring layer and a bonding pad on the front surface of the second die to be packaged;
forming a second conductive convex column on one surface of the second conductive trace away from the first dielectric layer; and/or the number of the groups of groups,
in forming the second dielectric layer, the semiconductor packaging method includes:
the second conductive protruding columns are exposed on one surface of the second dielectric layer away from the first rewiring layer.
14. The semiconductor packaging method of claim 1, wherein prior to securing a second die to be packaged having a second protective layer formed on a front side thereof on a second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method comprises:
Forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front surface of the second die to be packaged.
15. A semiconductor package structure, comprising:
an encapsulation structure, which comprises a first surface and a second surface which are opposite, wherein the encapsulation structure is provided with a plurality of first cavities and metal radiating fins, each first cavity is concave, each metal radiating fin comprises a first part, a second part and a connecting part connected between the first part and the second part, a first bare chip with a first protection layer formed on the front surface is positioned in the first cavity, the front surface of the first bare chip and the second part of each metal radiating fin are exposed out of the first surface of the encapsulation structure, and the back surface of each first bare chip faces to the first part of each metal radiating fin;
a first rewiring layer located on the first surface of the encapsulation structure and the front side of the first die, the first rewiring layer being electrically connected with a bond pad of the front side of the first die;
A first dielectric layer formed on the first rewiring layer and the exposed first surface of the encapsulation structure, the first protection layer of the first die and the second part of the metal heat sink, wherein the first dielectric layer is also provided with a plurality of second cavities which are concave inwards, the second die with the second protection layer formed on the front surface is positioned in the second cavities, and the back surface of the second die faces to the second part of the metal heat sink;
a second rewiring layer located on a side of the first dielectric layer away from the encapsulation structure, the second rewiring layer being electrically connected to both the first rewiring layer and the bonding pads on the front side of the second die;
and a second dielectric layer formed on the second rewiring layer and the exposed second protective layer of the first dielectric layer and the second die.
16. The semiconductor package according to claim 15, wherein a side of the first portion of the metal heat spreader remote from the first die is exposed at the second surface of the encapsulation structure.
17. The semiconductor package according to claim 15, wherein the semiconductor package further comprises:
A first metal connection layer formed on the back surface of the first die;
the first heat-conducting glue is coated on the first metal connecting layer, is positioned between the first metal connecting layer and the first part of the metal radiating fin and is used for connecting the first part of the metal radiating fin with the first metal connecting layer;
a second metal connection layer formed on the back surface of the second die;
and the second heat-conducting glue is coated on the second metal connecting layer, is positioned between the second metal connecting layer and the second part of the metal radiating fin and is used for connecting the second part of the metal radiating fin with the second metal connecting layer.
18. The semiconductor package according to claim 15, wherein a thickness of the second die is less than a thickness of the encapsulation structure.
19. The semiconductor package according to claim 15, wherein a side of the second protective layer remote from the second die is flush with a side of the first dielectric layer remote from the encapsulation structure.
20. The semiconductor package according to claim 15, wherein the first portion of the metal heat spreader and the back surface of the first die are shaped and sized to match; and/or the second portion of the metal heat sink matches the shape and size of the back side of the second die.
21. The semiconductor package according to claim 15, wherein a width of the connection portion of the metal heat sink is smaller than a width of the first portion of the metal heat sink and a width of the second portion.
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US8134232B2 (en) * 2008-04-03 2012-03-13 Lsi Corporation Heat dissipation for integrated circuit
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