CN113725099A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

Info

Publication number
CN113725099A
CN113725099A CN202010231979.9A CN202010231979A CN113725099A CN 113725099 A CN113725099 A CN 113725099A CN 202010231979 A CN202010231979 A CN 202010231979A CN 113725099 A CN113725099 A CN 113725099A
Authority
CN
China
Prior art keywords
layer
packaged
die
metal
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010231979.9A
Other languages
Chinese (zh)
Other versions
CN113725099B (en
Inventor
周辉星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SIPLP Microelectronics Chongqing Ltd
Original Assignee
SIPLP Microelectronics Chongqing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SIPLP Microelectronics Chongqing Ltd filed Critical SIPLP Microelectronics Chongqing Ltd
Priority to CN202010231979.9A priority Critical patent/CN113725099B/en
Publication of CN113725099A publication Critical patent/CN113725099A/en
Application granted granted Critical
Publication of CN113725099B publication Critical patent/CN113725099B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing an encapsulating structural member encapsulating a first bare chip to be encapsulated and a metal heat sink; forming a first redistribution layer on the first surface of the encapsulation structure, wherein the first redistribution layer is electrically connected with a welding pad on the front surface of the first bare chip to be packaged; forming a first dielectric layer, and fixing a second die to be packaged with a second protective layer formed on the front surface on a second part of the metal heat sink in the first surface of the encapsulating structure through the first dielectric layer, wherein the back surface of the second die to be packaged is tightly attached to the second part of the metal heat sink; forming a second rewiring layer on one surface, far away from the encapsulation structure, of the first dielectric layer; forming a second dielectric layer. The semiconductor packaging structure manufactured by the semiconductor packaging method has the advantages of small size and compact structure, and can effectively dissipate heat.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
At present, dies with different functions are often packaged in a package structure during a packaging process to form a specific function, which is called MCM (multi-chip module, chinese name). The MCM has the advantages of small volume, high reliability, high performance, multiple functions and the like.
With the miniaturization and light weight of electronic devices, chip packages having compact structures and small volumes are gaining more and more market favor.
In addition, the chip generates heat during the working process, and if the generated heat is not dissipated in time, the working efficiency and the service life of the chip are adversely affected. The heat accumulated in the chip during working is effectively dissipated, and the basis for ensuring the continuous and efficient operation of the chip is provided.
However, how to further reduce the volume of the chip package and effectively dissipate heat is a problem to be solved in the art.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
providing an encapsulating structure member encapsulating a first bare chip to be encapsulated and a metal heat sink, wherein a first protective layer is formed on the front surface of the first bare chip to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first bare chip to be encapsulated, and the second part of the metal heat sink and the first protective layer of the first bare chip to be encapsulated are exposed out of the first surface of the encapsulating structure member;
forming a first redistribution layer on the first surface of the encapsulation structure, wherein the first redistribution layer is electrically connected with a welding pad on the front surface of the first bare chip to be packaged;
forming a first dielectric layer, wherein the first dielectric layer is formed on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protection layer of the first bare chip to be packaged and the second part of the metal heat sink, and fixing a second bare chip to be packaged with a second protection layer formed on the front surface on the second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, wherein the back surface of the second bare chip to be packaged is tightly attached to the second part of the metal heat sink;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
and forming a second dielectric layer on a second protective layer formed on a second re-wiring layer and the exposed first dielectric layer and the second to-be-packaged bare chip.
Optionally, after forming a first dielectric layer, the first dielectric layer is formed on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink, and fixing a second die to be packaged, a front surface of which is formed with a second protective layer, on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, and a back surface of the second die to be packaged is attached to the second portion of the metal heat sink, the semiconductor packaging method includes:
applying the first dielectric layer on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink;
after preliminary heating the first dielectric layer, applying the second to-be-packaged die with the second protective layer formed on the front surface to a position corresponding to a second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer;
and continuing to heat the first dielectric layer, wherein the first dielectric layer is heated and solidified, the second die to be packaged is solidified along with the first dielectric layer to a position, corresponding to the second part of the metal heat sink, in the first surface of the encapsulating structure, and the back surface of the second die to be packaged is tightly attached to the second part of the metal heat sink.
Optionally, the preliminary heating time is 30 to 60 seconds, and the temperature is 80 to 120 ℃; the continuous heating time is 1-4 hours, and the temperature is 190-200 ℃.
Optionally, before forming the first redistribution layer on the first surface of the encapsulation structure, the semiconductor packaging method includes:
forming the first protection layer on the front surface of the first bare chip to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first bare chip to be packaged;
the first bare chip to be packaged and the metal radiating fin, the front surface of which is provided with the first protective layer, are attached to a carrier plate, the back surface of the first bare chip to be packaged faces upwards, the front surface of the first bare chip to be packaged faces the carrier plate, the first part of the metal radiating fin is tightly attached to the back surface of the first bare chip to be packaged, and the second part of the metal radiating fin is attached to the carrier plate;
covering the first bare chip to be packaged, the metal heat sink and the exposed carrier plate by an encapsulating layer to form the encapsulating structural member;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first bare chip to be packaged and the second part of the metal heat sink.
Optionally, after the encapsulating structure is formed and before the carrier is peeled off, the semiconductor packaging method includes:
thinning a second surface of the encapsulation structure far away from the carrier plate, and exposing one surface of the first part of the metal heat sink far away from the first bare chip to be packaged.
Optionally, the first bare chip to be packaged and the metal heat sink, on the front surface of which the first protective layer is formed, are mounted on a carrier,
the semiconductor packaging method comprises the following steps:
mounting the first bare chip to be packaged with the first protective layer formed on the front surface on a carrier plate;
forming a first metal connecting layer on the back surface of the first bare chip to be packaged;
coating first heat-conducting glue on the first metal connecting layer; and a process for the preparation of a coating,
attaching the metal radiating fin to a carrier plate, wherein a first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat-conducting glue, and a second part of the metal radiating fin is attached to the carrier plate; alternatively, the first and second electrodes may be,
the semiconductor packaging method comprises the following steps:
mounting the first bare chip to be packaged with the first protective layer formed on the front surface on a carrier plate;
coating a first heat-conducting glue on the back surface of the first bare chip to be packaged; and a process for the preparation of a coating,
and attaching the metal radiating fin to the carrier plate, wherein the first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat-conducting glue, and the second part of the metal radiating fin is attached to the carrier plate.
Optionally, before the first bare chip to be packaged and the metal heat sink, on which the first protective layer is formed on the front surface, are attached to a carrier, the semiconductor packaging method includes:
and grinding the back surface of the first bare chip to be packaged.
Optionally, before the second die to be packaged with the second protection layer formed on the front surface is fixed on the second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer,
the semiconductor packaging method comprises the following steps:
forming a second metal connecting layer on the back surface of the second die to be packaged; and a process for the preparation of a coating,
coating a second heat-conducting glue on the second metal connecting layer; alternatively, the first and second electrodes may be,
the semiconductor packaging method comprises the following steps:
coating a second heat-conducting glue on the back surface of the second die to be packaged; and/or the presence of a gas in the gas,
in a second part of the metal heat sink which is fixed in the first surface of the encapsulating structure by the first dielectric layer, a second to-be-packaged die with a second protective layer formed on the front surface is connected with a second metal connecting layer of the second to-be-packaged die by the second heat-conducting glue.
Optionally, before the second die to be packaged with the second protection layer formed on the front surface is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
and grinding the back side of the second die to be packaged.
Optionally, in forming a first redistribution layer on the first surface of the encapsulation structure, the semiconductor packaging method includes:
forming first conductive traces on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive traces being electrically connected with pads on a front side of the first die to be packaged;
forming a first conductive convex column on one surface of the first conductive trace far away from the encapsulation structure; and/or the presence of a gas in the gas,
in forming a second rewiring layer on a side of the first dielectric layer away from the encapsulation structure, the semiconductor packaging method comprises the following steps:
forming a second conductive trace on a side of the first dielectric layer away from the encapsulation structure, the second conductive trace being electrically connected to both the first redistribution layer and a pad on a front side of the second die to be packaged;
and forming a second conductive convex column on one surface of the second conductive trace far away from the first dielectric layer.
Optionally, in forming the second dielectric layer, the semiconductor packaging method includes:
and exposing the second conductive convex column on one surface of the second dielectric layer far away from the first rewiring layer.
Optionally, before the second die to be packaged with the second protection layer formed on the front surface is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, the semiconductor packaging method includes:
forming a second protective layer opening on the second protective layer, wherein the second protective layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening, so that the second conductive medium is electrically connected with the welding pad on the front side of the second die to be packaged.
Another aspect of the present application provides a semiconductor package structure, including:
the encapsulating structure comprises a first surface and a second surface which are opposite, the encapsulating structure is provided with a plurality of first cavities and metal radiating fins which are concave inwards, each metal radiating fin comprises a first part, a second part and a connecting part connected between the first part and the second part, a first bare chip with a first protective layer formed on the front surface is positioned in the first cavity, the front surface of the first bare chip and the second part of the metal radiating fins are exposed out of the first surface of the encapsulating structure, and the back surface of the first bare chip faces to the first part of the metal radiating fins;
a first redistribution layer on the first surface of the encapsulation structure and the front side of the first die, the first redistribution layer electrically connected to pads on the front side of the first die;
the first dielectric layer is formed on the first rewiring layer, the exposed first surface of the packaging structure, the first protection layer of the first bare chip to be packaged and the second part of the metal heat sink, the first dielectric layer is further provided with a plurality of concave second cavities, the second bare chip with the second protection layer formed on the front surface is located in the second cavities, and the back surface of the second bare chip faces the second part of the metal heat sink;
a second redistribution layer on a surface of the first dielectric layer away from the encapsulation structure, the second redistribution layer electrically connected to the first redistribution layer and the bonding pads on the front side of the second die;
and the second dielectric layer is formed on the second re-wiring layer and the exposed first dielectric layer and the second protection layer of the second bare chip.
Optionally, a side of the first portion of the metal heat sink away from the first die is exposed at the second surface in the encapsulation structure.
Optionally, the semiconductor package structure further includes:
a first metal connection layer formed on a back side of the first die;
the first heat-conducting glue is coated on the first metal connecting layer, is positioned between the first metal connecting layer and the first part of the metal radiating fin and is used for connecting the first part of the metal radiating fin with the first metal connecting layer;
a second metal connection layer formed on a back side of the second die;
and the second heat-conducting glue is coated on the second metal connecting layer, is positioned between the second metal connecting layer and the second part of the metal radiating fin and is used for connecting the second part of the metal radiating fin with the second metal connecting layer.
Optionally, the thickness of the second die is less than the thickness of the encapsulation structure.
Optionally, a side of the second protective layer away from the second die is flush with a side of the first dielectric layer away from the encapsulation structure.
Optionally, the first portion of the metal heat spreader matches the shape and size of the back side of the first die; and/or the second portion of the metal heat sink matches the shape and size of the back side of the second die.
Optionally, the width of the connection portion of the metal heat sink is smaller than the width of the first portion and the width of the second portion of the metal heat sink.
According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the first bare chip to be packaged with a certain function is firstly subjected to primary wiring in a mode of packaging and forming the conductive layer, and then the second bare chip to be packaged is fixed on the first surface of the packaging structure through the first dielectric layer, so that on one hand, the distance between the first bare chip to be packaged and the second bare chip to be packaged is favorably reduced, the structure of the formed semiconductor packaging structure is more compact, and the beneficial effect of reducing the whole occupied space is achieved; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, the copper heat sink is applied to the back surfaces of the first die to be packaged and the second die to be packaged, so that heat accumulated by the dies during use is dissipated quickly, and the continuous and efficient operation of the dies during use is guaranteed.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 2(a) -2 (x) are process flow diagrams of a method of semiconductor packaging according to an exemplary embodiment of the present application.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 4(a) -4 (d) are process flow diagrams of a method for fabricating a metal heat spreader in a method for packaging a semiconductor according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
As shown in fig. 1, fig. 2(a) -fig. 2(x), fig. 3, and fig. 4(a) -fig. 4(d), the present application provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: providing an encapsulating structure member encapsulating a first bare chip to be encapsulated and a metal heat sink, wherein a first protective layer is formed on the front surface of the first bare chip to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first bare chip to be encapsulated, and the second part of the metal heat sink and the first protective layer of the first bare chip to be encapsulated are exposed out of the first surface of the encapsulating structure member;
step 102: forming a first redistribution layer on the first surface of the encapsulation structure, wherein the first redistribution layer is electrically connected with a welding pad on the front surface of the first bare chip to be packaged;
step 103: forming a first dielectric layer, wherein the first dielectric layer is formed on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protection layer of the first bare chip to be packaged and the second part of the metal heat sink, and fixing a second bare chip to be packaged with a second protection layer formed on the front surface on the second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, wherein the back surface of the second bare chip to be packaged is tightly attached to the second part of the metal heat sink;
step 104: forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
step 105: and forming a second dielectric layer on a second protective layer formed on a second re-wiring layer and the exposed first dielectric layer and the second to-be-packaged bare chip.
In the semiconductor packaging method and the semiconductor packaging structure in the embodiment, the first to-be-packaged bare chip with a certain function is firstly subjected to primary wiring in a mode of packaging and forming the conductive layer, and then the second to-be-packaged bare chip is fixed on the first surface of the packaging structural member through the first dielectric layer, so that on one hand, the distance between the first to-be-packaged bare chip and the second to-be-packaged bare chip is favorably reduced, the structure of the formed semiconductor packaging structure is more compact, and the beneficial effect of reducing the whole occupied space is achieved; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, the copper heat sink is applied to the back surfaces of the first die to be packaged and the second die to be packaged, so that heat accumulated by the dies during use is dissipated quickly, and the continuous and efficient operation of the dies during use is guaranteed.
In this embodiment, in step 101, the semiconductor packaging method includes:
step 1011: forming the first protection layer on the front surface of the first bare chip to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first bare chip to be packaged;
step 1012: the first bare chip to be packaged and the metal radiating fin, the front surface of which is provided with the first protective layer, are attached to a carrier plate, the back surface of the first bare chip to be packaged faces upwards, the front surface of the first bare chip to be packaged faces the carrier plate, the first part of the metal radiating fin is tightly attached to the back surface of the first bare chip to be packaged, and the second part of the metal radiating fin is attached to the carrier plate;
step 1013: covering the first bare chip to be packaged, the metal heat sink and the exposed carrier plate by an encapsulating layer to form the encapsulating structural member;
step 1014: and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first bare chip to be packaged and the second part of the metal heat sink.
In step 1011, a first protection layer is formed on the front surface of the first to-be-packaged die, and the first protection layer may be formed on the front surface of the first semiconductor wafer before the first semiconductor wafer is cut into a plurality of first to-be-packaged dies, and then the first semiconductor wafer is cut to obtain the first to-be-packaged die with the first protection layer formed on the front surface. It is understood that, when the process allows, the first protective layer may be formed on the front surface of each first die to be packaged after the first semiconductor wafer is cut into the first dies to be packaged, which is selected according to the actual situation.
As shown in fig. 2(a), the front surface of the first semiconductor wafer 100, i.e. the front surface corresponding to the first die to be packaged 201, has a first insulating layer 2011 and first pads 2012, and the first pads 2012 are used for making electrical connection with the outside. The front side of the first die to be packaged 201 is the active side of the first die to be packaged 201.
As shown in fig. 2(b), a first protection layer 202 is formed on the front surface of the first semiconductor wafer 100, i.e., the front surface corresponding to the first to-be-packaged die 201.
The first protection layer 202 is made of an insulating material, such as one or more of polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), and the like. Alternatively, the material of the protective layer is selected to be insulating and capable of accommodating chemical cleaning, polishing, and the like. The first protective layer 202 may be formed on the first semiconductor wafer by Lamination (Coating), Coating (Coating), Printing (Printing), or the like. The temperature, pressure and time ranges are different from material to material, and the curing conditions are different for different materials.
Subsequently, as shown in fig. 2(c), after the step of forming the first protection layer 202 is completed, the back surface of the first semiconductor wafer 100, that is, the back surface corresponding to the first die to be packaged 201, is ground to reduce the thickness of the first die to be packaged 201, so as to reduce the thickness of the final overall package structure, thereby further achieving the beneficial effect of reducing the overall occupied space.
Then, as shown in fig. 2(d), the first semiconductor wafer 100 with the first protection layer 202 formed thereon is cut along the dicing streets to obtain a plurality of first to-be-packaged dies 201 with the first protection layer 202 formed thereon. The cutting process can be mechanical cutting or laser cutting.
The structure of the first to-be-packaged die 201 with the first protection layer 202 formed thereon is shown in fig. 2(e), in which the front surface of the first to-be-packaged die 201 still has the first insulating layer and the first bonding pad, but for convenience of the subsequent process flow, the structure is not labeled in the figure. The first die to be packaged 201 formed through the above steps is a die to be packaged having a specific function.
Next, as shown in fig. 2(f), first protection layer openings 2021 are formed on the first protection layer 202 at positions corresponding to the pads of the first to-be-packaged die 201, where each first protection layer opening 2021 at least corresponds to a pad of the first to-be-packaged die 201 or a circuit led out from the pad, so that the pad on the front surface of the first to-be-packaged die 201 or the circuit led out from the pad is exposed from the first protection layer opening 2021.
If the first protection layer 202 material is a laser reactive material, the first protection layer opening 2021 can be formed by laser patterning; if the first protection layer 202 material is a photosensitive material, the first protection layer opening 2021 can be formed by photolithography patterning. The shape of the first passivation opening 2021 may be round, but may also be other shapes such as oval, square, line, etc.
In this embodiment, since the first protection layer opening 2021 is already formed on the first protection layer 202, at least the first protection layer opening 2021 can be directly seen when the first redistribution layer is formed subsequently, so that the first redistribution layer can be aligned more accurately when formed.
Similarly, the steps of forming the second protection layer on the front surface of the second bare chip to be packaged and forming the second protection layer opening on the second protection layer are substantially the same as the steps of forming the first protection layer on the front surface of the first bare chip to be packaged and forming the first protection layer opening on the first protection layer. The details are as follows:
the second protective layer may be formed on the front surface of the second semiconductor wafer before the second semiconductor wafer is cut into the plurality of second to-be-packaged dies, and then the second semiconductor wafer is cut to obtain the second to-be-packaged dies with the second protective layer formed on the front surface. It is understood that, where the process allows, after the second semiconductor wafer is cut into the second dies to be packaged, a second protection layer may be formed on the front surface of each second die to be packaged, which is selected according to the actual situation.
As shown in fig. 2(g), the front surface of the second semiconductor wafer 100 ', i.e. the front surface corresponding to the second die 201 ' to be packaged, has a second insulating layer 2011 ' and a second pad 2012 ', and the second pad 2012 ' is used for making an electrical connection with the outside. The front side of the second die 201 'to be packaged is the active side of the second die 201' to be packaged.
As shown in fig. 2(h), a second protection layer 202 ' is formed on the front surface of the second semiconductor wafer 100 ', i.e., the front surface corresponding to the second die 201 ' to be packaged. The material of the second protection layer 202 'is the same as that of the first protection layer 202, and the description of the material of the first protection layer 202 is also applicable to the material of the second protection layer 202', and will not be repeated herein.
Subsequently, as shown in fig. 2(i), the back surface of the second semiconductor wafer 100 ', that is, the back surface corresponding to the second die 201 ' to be packaged, is ground to reduce the thickness of the second die 201 ' to be packaged, so as to reduce the thickness of the final overall package structure, thereby further achieving the beneficial effect of reducing the overall occupied space.
As shown in fig. 2(j), the second semiconductor wafer 100 'is cut along the scribe lines to obtain a plurality of second dies 201' to be packaged. The cutting process can be mechanical cutting or laser cutting.
The structure of the second die 201 'to be packaged is shown in fig. 2(k), in which the front surface of the second die 201' to be packaged still has the second insulating layer and the second bonding pad, but for convenience of the subsequent process flow, the structure is not labeled in the figure.
As shown in fig. 2(l), second passivation layer openings 2021 ' are formed on the second passivation layer 202 ' at positions corresponding to the pads of the second die 201 ' to be packaged, and each second passivation layer opening 2021 ' is at least correspondingly located on a pad of the second die 201 ' to be packaged or a line led out from the pad, so that the pad on the front side of the second die 201 ' to be packaged or the line led out from the pad is exposed from the second passivation layer opening 2021 '.
As shown in fig. 2(m), the second protective layer opening 2021 'is filled with a second conductive medium 203', so that the second conductive medium 203 'is electrically connected to the pad of the second die 201' to be packaged, and the second conductive medium 203 'forms a vertical connection structure in the second protective layer opening 2021', so that the pad on the surface of the second die 201 'to be packaged is electrically connected to the second redistribution layer formed in the subsequent step through the connection structure in the second conductive medium 203'.
In some embodiments, the second protective layer opening may not be filled with the second conductive medium, and the plurality of second protective layer openings may still be in a hollow state after the second die to be packaged, on which the second protective layer is formed, is fixed on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer.
In step 1012, the method comprises the following steps:
step 10121: as shown in fig. 2(n), the first to-be-packaged die 201 with the first protection layer 202 formed on the front surface thereof is attached to the carrier 300 through an adhesive layer (not shown), the back surface of the first to-be-packaged die 201 faces upward, and the front surface faces the carrier 300.
Step 10122: forming a first metal connection layer (not labeled) on the back side of the first die 201 to be packaged; a first thermal conductive paste 600 is coated on the first metal connection layer. The first metal connecting layer comprises a titanium metal layer and a copper metal layer which are arranged in a stacked mode. Specifically, a titanium metal layer is formed on the back surface of the first bare chip 201 to be packaged by using a metal sputtering method; and forming a copper metal layer on the titanium metal layer by using a sputtering method. The first metal connecting layer can increase interlayer bonding of the packaging structure.
Next, a first thermal conductive paste 600 is applied to the back surface of the first die 201 to be packaged. The first thermal conductive paste 600 is in a gel or jelly shape to keep the back surface of the first die 201 to be packaged in good contact with the first portion 501 of the metal heat sink 500. The first thermal conductive adhesive 600 may be made of silica gel or epoxy resin; the material may be conductive or non-conductive, and is selected according to specific design requirements, and is not limited herein.
Step 10123: as shown in fig. 2(o), the metal heat sink 500 is attached to the carrier 300 through an adhesive layer (not shown). The metal heat sink 500 includes a first portion 501, a second portion 502, and a connection portion 503 connected between the first portion 501 and the second portion 502. The first portion 501 of the metal heat sink 500 is located above the first metal connection layer and connected to the first metal connection layer through the first thermal conductive adhesive 600, and the second portion 502 of the metal heat sink 500 is attached to the carrier 300 through the adhesive layer.
In the above step, in other embodiments, the first metal connection layer may not be provided, the first thermal conductive adhesive 600 is directly coated on the back surface of the first die to be packaged 201, and the first portion 501 of the metal heat sink 500 is connected to the back surface of the first die to be packaged 201 through the first thermal conductive adhesive 600, so that the back surface of the first die to be packaged 201 and the first portion 501 of the metal heat sink 500 keep good contact.
The adhesive layer is used to bond the first bare chip to be packaged and the metal heat sink, and the adhesive layer may be made of a material that is easily peeled off so as to peel the carrier plate, the first bare chip to be packaged and the metal heat sink away in a subsequent process, for example, a thermal separation material that can be heated to lose its adhesiveness.
In other embodiments, the adhesive layer may have a two-layer structure, including a thermal separation material layer and a die attach layer, the thermal separation material layer is attached to the carrier plate and loses its viscosity when heated, and can be peeled off from the carrier plate, and the die attach layer has a viscous material layer and can be used to attach the first die to be packaged and the metal heat sink. After the first bare chip to be packaged and the metal heat sink are stripped from the carrier plate, the bare chip attachment layer on the first bare chip to be packaged and the metal heat sink can be removed in a chemical cleaning mode. In one embodiment, the adhesive layer may be formed on the carrier by lamination, printing, or the like.
As shown in fig. 2(o), the first to-be-packaged die 201 and the metal heat sink 500 are placed on the carrier 300 at predetermined arrangement positions, for convenience of expression, only one stacked and combined first to-be-packaged die 201 and metal heat sink 500 are shown in the figure, and in fact, a plurality of stacked and combined first to-be-packaged dies 201 and metal heat sinks 500 are arranged on the carrier 300 at predetermined positions.
It can be understood that, in one packaging process, there may be a plurality of first to-be-packaged dies 201 and metal heat sinks 500, that is, a plurality of stacked and combined first to-be-packaged dies 201 and metal heat sinks 500 are simultaneously mounted on the carrier 300 for packaging, and after the packaging is completed, the first to-be-packaged dies are cut into a plurality of packages; one package may include one or more stacked and combined first to-be-packaged dies 201 and metal heat sinks 500, and the positions of the one or more stacked and combined first to-be-packaged dies 201 and metal heat sinks 500 may be freely set according to the needs of an actual product.
In step 1013, as shown in fig. 2(p), the encapsulating layer 204 covers the entire carrier 300, and encapsulates the first to-be-packaged die 201 and the metal heat sink 500 on which the first protection layer 202 is formed, so as to form the encapsulating structure 200. The encapsulation structure 200 is a flat plate structure on which the re-wiring and packaging can be continuously performed after the carrier 300 is peeled off.
In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or an abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material easily penetrates between the carrier 300 and the first die 201 to be encapsulated in this process. Through the embodiment of the application, the first protection layer 202 is formed outside the first to-be-packaged bare chip 201, the first protection layer 202 can prevent the encapsulating material from penetrating to the surface of the first to-be-packaged bare chip 201, and even if the encapsulating material penetrates, after the encapsulating material is peeled off from the carrier plate, the surface of the first protection layer 202 can be directly processed through a chemical mode or a grinding mode, and the surface of the first to-be-packaged bare chip 201 cannot be directly contacted with the front surface of the first to-be-packaged bare chip 201, so that the circuit structure of the front surface of the first to-be-packaged bare chip 201 cannot be damaged.
The encapsulation structure 200 comprises a first surface 2001 and a second surface 2002 which are oppositely arranged, wherein the second surface 2002 is arranged opposite to the carrier plate 300, is substantially flat, and is parallel to the surface of the carrier plate 300. As shown in fig. 2(q), the thickness of the encapsulation structure 200 may be reduced by grinding or polishing the second surface 2002, and further, by reducing the thickness of the encapsulation structure 200 to expose the side of the first portion 501 of the metal heat sink 500 away from the first die 201 to be packaged on the second surface 2002 of the encapsulation structure 200, the side of the first portion 501 of the metal heat sink 500 away from the first die 201 to be packaged is exposed by reducing the encapsulation structure 200, which further helps to quickly dissipate heat accumulated during the use of the die, and ensures continuous and efficient operation of the die during the use.
In step 1014, as shown in fig. 2(r), the carrier board 300 is peeled off, exposing the first surface 2001 of the encapsulating structure 200 with the front side of the first die to be packaged 201 and the second portion 502 of the metal heat sink 500.
Since the adhesive layer between the carrier 300 and the first die 201 to be packaged is a thermal separation film, the adhesive layer can be reduced in viscosity after being heated by a heating method, so as to peel off the carrier 300. By peeling the carrier 300 through the heated adhesive layer, damage to the first die 201 to be packaged during the peeling process can be minimized. In other embodiments, the carrier plate 300 may be mechanically peeled off directly.
After the carrier 300 is peeled off, the first surface 2001 of the encapsulating structure 200 facing the carrier 300, the front surface of the first die 201 to be packaged, and the second portion 502 of the metal heat sink 500 are exposed. After the carrier 300 is peeled off, the encapsulation structure 200 including the first die to be packaged 201, the metal heat sink 500, the first protection layer 202 covering the front surface of the first die to be packaged 201, and the encapsulation layer 204 encapsulating the back surface of the first die to be packaged 201 and the metal heat sink 500 is obtained, as shown in fig. 2(s). On the formed encapsulation structure 200, re-wiring or the like may be performed according to actual conditions, so that the first die 201 to be packaged is electrically connected to the outside.
In the embodiment of the present application, after the carrier 300 is peeled off, the surfaces of the first protection layer 202 and the first protection layer 202 are exposed, and the die attach layer in the adhesive layer is still present on the surface of the first protection layer 202, and when the adhesive layer is removed by a chemical method, the first protection layer 202 can also protect the surface of the first die 201 to be packaged from being damaged. After the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the first protection layer 202, the surface of the first die 201 to be packaged cannot be processed by a chemical method or a grinding method so as to avoid damaging the circuit on the front surface of the first die 201 to be packaged.
In step 102, as shown in fig. 2(t), a first redistribution layer 206 is formed on the first surface 2001 of the encapsulation structure 200, and the first redistribution layer 206 is electrically connected to a pad on the front side of the first to-be-packaged die 201. Specifically, the method comprises the following steps:
step 1021: forming a first conductive trace 2061 on the first surface 2001 of the encapsulation structure 200 encapsulating the first die 201 to be packaged;
step 1022: a first conductive post 2062 is formed on a side of the first conductive trace 2061 away from the encapsulation structure 200.
In step 1021, the first conductive traces 2061 are electrically connected to the pads on the front side of the first die to be packaged 201, and the first conductive traces 2061 are electrically connected to the pads of the first die to be packaged 201 through the first passivation opening 2021.
Since the first passivation layer opening 2021 is already formed on the first passivation layer 202, at least the passivation layer opening 2021 can be directly seen when the first redistribution layer 206 is formed, so that the first redistribution layer 206 can be aligned more accurately when formed.
When forming the first conductive traces 2061, the first conductive medium 203 may be filled in the first protective layer opening 2021 of the first die 201 to be packaged at the same time, i.e., the first conductive traces and the first conductive medium are formed in the same conductive layer forming process. The first conductive medium 203 forms a vertical connection structure in the first protection layer opening 2021, so that the pad on the surface of the first die 201 to be packaged is electrically connected to the first redistribution layer 206 through the connection structure in the first conductive medium 203.
In step 1022, the shape of the first conductive post 2062 is preferably circular, but may be other shapes such as rectangle, square, etc., and the first conductive post 2062 is electrically connected to the first conductive trace 2061. Specifically, the first conductive post 2062 may be formed on the first conductive trace 2061 by photolithography and electroplating.
In another embodiment, a first dielectric layer may be formed on the first conductive trace 2061 and the exposed first protective layer 202 and the first surface 2001 of the encapsulation structure 200 after the first conductive trace 2061 is formed, and the first dielectric layer has a first opening, and then the first conductive post 2062 electrically connected to the first conductive trace 2061 is formed in the first opening of the first dielectric layer. In this process, the first rewiring layer 206 includes first conductive traces 2061 and first conductive posts 2062.
In yet another embodiment, the first opening of the first conductive trace may not be filled, i.e., the first conductive post 2062 electrically connected to the first conductive trace 2061 is not formed, so that the bonding pad or the connection point of the first redistribution layer of the completed package is exposed from the first opening. In this process, the first redistribution layer 206 includes only the first conductive traces 2061.
In step 103, as shown in fig. 2(u), a first dielectric layer 207 is formed, the first dielectric layer 207 is formed on the first redistribution layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protective layer 202 of the first die to be packaged 201, and the second portion 502 of the metal heat sink 500, and the second die to be packaged 201 ' with the second protective layer 202 ' formed on the front surface is fixed on the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207, and the back surface of the second die to be packaged 201 ' is tightly attached to the second portion 502 of the metal heat sink 500. Specifically, the method comprises the following steps:
step 1031: a first dielectric layer 207 is applied on the first redistribution layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protective layer 202 of the first die to be packaged 201, and the second portion 502 of the metal heat sink 500. The first dielectric layer 207 is made of an insulating material, such as one or more of polyimide, epoxy, abf (ajinomoto build file), pbo (polybenzoxazole), and the like. The first dielectric layer 207 may be formed by Lamination (plating), Molding (Molding), or Printing (Printing), and preferably, an epoxy compound is used.
Step 1031: after the first dielectric layer 207 is preliminarily heated, the second die to be packaged 201 'with the second protective layer 202' formed on the front side is applied to the position corresponding to the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207. Since the viscosity of the first dielectric layer 207 after the preliminary heating is first reduced and the first dielectric layer 207 has strong fluidity at this time, the second die to be packaged 201 'is placed in the first surface 2001 of the encapsulation structure 200 at a predetermined position corresponding to the second portion 502 of the metal heat spreader 500, the back surface of the second die to be packaged 201' faces the first surface 2001 of the encapsulation structure 200, and the preliminary heated first dielectric layer 207 between the second portion 502 of the metal heat spreader 500 and the second die to be packaged 201 'can be pushed away and surrounded around the second die to be packaged 201' by pressing.
Step 1033: the first dielectric layer 207 is continuously heated, the first dielectric layer 207 is heated and cured as the heating is performed, and the second die to be packaged 201' is pressed against the second portion 502 of the metal heat sink 500 as the first dielectric layer 207 is cured to the position, corresponding to the second portion 502 of the metal heat sink 500, of the first surface 2001 of the encapsulation structure 200.
It should be noted that the time and temperature of the preliminary heating are determined according to the specific kind of the material of the first dielectric layer 207, and the general rule is: the temperature of the preliminary heating is lower than the curing temperature of the material of the first dielectric layer 207.
Depending on the rheological characteristics of the material of the first dielectric layer 207 during curing, the viscosity of the material of the first dielectric layer 207 decreases due to the increase in temperature, and when the temperature is increased above the curing temperature, the material of the first dielectric layer 207 undergoes intermolecular cross-linking, thereby increasing the viscosity, and the preliminary heating temperature is selected to be below and controllable below the curing temperature.
After applying the second to-be-packaged die 201 'with the second protection layer 202' formed on the front side to the position corresponding to the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200, the temperature may be raised to or above the curing temperature of the material of the first dielectric layer 207, and the curing thermodynamic characteristics of different materials are different, and the specific heating time is determined according to the data of the curing thermodynamics of the materials, the heating temperature is a certain temperature higher than the curing temperature, and the heating time is a time for heating the first dielectric layer 207 to a complete curing corresponding to the heating temperature, generally, the higher the heating temperature is, the shorter the time for completely crosslinking the material is, and the shorter the curing time is.
In this embodiment, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees. The continuous heating time is 1-4 hours, and the temperature is 190-200 ℃.
As shown in fig. 2(u), a side of the second passivation layer 202 'away from the second die 201' is flush with a side of the first dielectric layer 207 away from the first die 201 to ensure that the first redistribution layer 208 is formed on a plane.
As can be seen from the above, the step of fixing the second die to be packaged 201' to the first surface 2001 of the encapsulation structure 200 in a position corresponding to the second portion 502 of the metal heat sink 500 and the step of forming the first dielectric layer 207 on the first surface 2001 of the encapsulation structure 200 are performed simultaneously.
Before step 1031, that is, before fixing the second die to be packaged 201 'with the second protective layer 202' formed on the front surface thereof on the second portion 502 of the metal heat sink 500 in the first surface 2001 of the encapsulation structure 200 through the first dielectric layer 207, the method further includes: forming a second metal connection layer (not labeled) on the back side of the second die 201' to be packaged; and coating a second heat-conducting glue 600' on the second metal connecting layer. The structure of the second metal connecting layer is the same as that of the first metal connecting layer, and the description is not repeated here; the second thermal conductive paste 600' is made of the same material as the first thermal conductive paste 600, and will not be described in detail herein.
The second portion 502 of the metal heat spreader 500 is connected to the second metal connection layer of the second die 201 'to be packaged by a second thermally conductive glue 600'.
In the above step, in other embodiments, the second metal connection layer may not be provided, and the second thermal conductive adhesive 600 ' is directly coated on the back surface of the second die to be packaged 201 ', and the second portion 502 of the metal heat sink 500 is connected to the back surface of the second die 201 ' through the second thermal conductive adhesive 600 ', so that the back surface of the second die to be packaged 201 ' and the second portion 502 of the metal heat sink 500 are kept in good contact.
In step 104, as shown in fig. 2(v), a second redistribution layer 208 is formed on a surface of the first dielectric layer 206 away from the encapsulation structure 200, and the second redistribution layer 208 is electrically connected to the first redistribution layer 206 and the bonding pads on the front surface of the second die to be packaged 201'. Specifically, the method comprises the following steps:
step 1041: forming a second conductive trace 2081 on a side of the first dielectric layer 206 away from the encapsulation structure 200, the second conductive trace 2081 being electrically connected to the first redistribution layer 206 and a pad on the front side of the second die 201' to be packaged;
step 1042: a second conductive post 2082 is formed on a side of the second conductive trace 2081 distal to the first dielectric layer 207.
In step 1041, the second conductive traces 2081 are electrically connected to the pads on the front side of the second die 201 ' to be packaged, and the second conductive traces 2081 are electrically connected to the pads of the second die 201 ' to be packaged through the second conductive medium 203 ' in the second passivation opening 2021.
Since the second conductive medium 203 'is already formed in the second passivation opening 2021, at least the second conductive medium 203' can be directly seen when the second conductive trace 2081 is formed, so that the second conductive trace 2081 can be aligned more accurately when formed.
In some embodiments, in the case that the second conductive medium is not filled in the second protection layer opening before the second die to be packaged with the second protection layer formed on the front surface thereof is fixed on the first surface of the encapsulation structure through the first dielectric layer, the second conductive medium may be filled in the second protection layer opening of the second die to be packaged simultaneously when the second conductive trace is formed, that is, the second conductive trace and the second conductive medium are formed in the same conductive layer forming process.
In step 1042, the shape of the second conductive post 2082 is preferably circular, but may also be other shapes such as rectangle, square, etc., and the second conductive post 2082 is electrically connected to the second conductive trace 2081. Specifically, the second conductive post 2082 can be formed on the second conductive trace 2081 by photolithography and electroplating.
In another embodiment, a second dielectric layer can be formed after the second conductive trace 2081, and subsequently on the second conductive trace 2081 and the exposed second protective layer 202' and first dielectric layer, and the second dielectric layer has a second opening, and then a second conductive post 2082 electrically connected to the second conductive trace 2081 can be formed in the second opening of the second dielectric layer. In this process, the second re-routing layer 208 includes a second conductive trace 2081 and a second conductive post 2082.
In yet another embodiment, the second opening of the second conductive trace may not be filled, that is, the second conductive pillar 2082 electrically connected to the second conductive trace 2081 is not formed, so that the solder pad or the connection point of the second redistribution layer of the completed package is exposed from the second opening. In this process, second re-routing layer 208 includes only second conductive traces 2081.
In step 105, as shown in fig. 2(w), a second dielectric layer 209 is formed, wherein the second dielectric layer 209 is formed on the second redistribution layer 208 and the exposed first dielectric layer 207 and the second protection layer 202 'of the second die to be packaged 201'.
The material of the second dielectric layer 209 is the same as the material of the first dielectric layer 207, and will not be described again.
In order to expose the second conductive pillar 2082 on a surface of the second dielectric layer 209 away from the first redistribution layer 206, the second dielectric layer 209 may be formed to have a thickness equal to a thickness of a surface where the second conductive pillar 2082 is just exposed; the second dielectric layer 209 may cover all exposed surfaces of the first dielectric layer 207 and the second redistribution layer 208, and then be thinned to the surface of the second conductive pillar 2082. In this process, the second re-routing layer 208 includes a second conductive trace 2081 and a second conductive post 2082.
The first redistribution layer 206, the first dielectric layer 207, the second redistribution layer 208, and the second dielectric layer 209 all belong to a redistribution structure.
Further, in an embodiment, repeated rewiring may be performed on the front sides of the first and second dies, such as a third rewiring layer or more rewiring layers may be formed outside the second dielectric layer in the same manner to achieve a multi-layer rewiring structure of the product.
Subsequently, after the package of the rewiring structure is completed, the entire package structure is cut into a plurality of packages, i.e., a plurality of semiconductor package structures, by laser or mechanical cutting, as shown in fig. 2(x), and the structure of the formed semiconductor package structure is shown in fig. 3.
As shown in fig. 4(a) to 4(d), the method for manufacturing the metal heat sink in the semiconductor packaging method is as follows:
step 1001: as shown in fig. 4(a), a large sheet of metal foil 400, preferably copper foil, is provided.
Step 1002: the large-sized metal foil 400 is cut or punched to form a plurality of small-sized metal foils 400' of an asymmetrical H shape as shown in fig. 4 (b). That is, a large metal foil 400 is cut or punched to form a plurality of H-shaped small metal foils 400' at a time.
Step 1003: as shown in fig. 4(c), a small piece of metal foil is bent to form a metal heat sink 500 having a semi-convex structure, and a bottom space of the metal heat sink 500 having the semi-convex structure is suitable for accommodating a first die to be packaged. Specifically, the metal heat sink 500 includes a first portion 501, a second portion 502, and a connection portion 503 connected between the first portion 501 and the second portion 502, wherein the first portion 501 and the second portion 502 are located in different planes. The first portion 501 and the connecting portion 503 form a receiving cavity 504 to receive a first die to be packaged.
The shape and size of the first portion 501 of the metal heat sink 500 and the shape and size of the back side of the first die to be packaged 201 match, and the shape and size of the second portion 502 of the metal heat sink 500 and the shape and size of the back side of the second die to be packaged 201' match, so as to achieve better heat dissipation effect. The width w3 of the connection part 503 of the metal heat sink 500 is smaller than the width w1 of the first portion 501 and the width w2 of the second portion 502 of the metal heat sink 500 to more easily achieve bending. The width w3 of the connection portion 503 of the metal heat sink 500 is smaller than the width w1 of the first portion 501 and the width w2 of the second portion 502 of the metal heat sink 500, which are achieved by forming the H-shaped metal foil 400' in step 1002 (refer to fig. 4(b) again), that is, the connection portion 503 removes a part of the material, so that the overall shape of the metal heat sink 500 is H-shaped. After the connection portion 503 is removed, a deformation accommodating space can be provided for the metal heat sink 500 to expand with heat and contract with cold in the above-mentioned packaging process.
Then, the metal heat sink of the semi-convex structure may be bonded to the support plate by an adhesive layer, or directly bonded to the metal heat sink of the semi-convex structure by a thick adhesive layer.
As shown in fig. 4(d), by bonding the metal heat sink 500 of the semi-convex structure on the support plate 700 by using an adhesive layer, the plurality of metal heat sinks 500 arranged on the support plate 700 can be simultaneously transferred to a predetermined position on the carrier plate in batch, and the first portion 501 of the metal heat sink 500 is contacted with the back surface of the first die to be packaged by the first thermal conductive adhesive.
Referring to fig. 3 again, fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application. The semiconductor package structure includes: an encapsulation structure 200 encapsulating a first die 201 and a metal heat sink 500, a first redistribution layer 206, a first dielectric layer 207 to which a second die 201' is secured, a second redistribution layer 208, and a second dielectric layer 209. The first redistribution layer 206, the first dielectric layer 207, the second redistribution layer 208, and the second dielectric layer 209 all belong to a redistribution structure, that is, in the process of forming the redistribution structure on the first surface 2001 of the encapsulation structure 200, the second die 201 'is fixed to the first surface 2001 of the encapsulation structure 200, and the redistribution structure is electrically connected to the first die 201 and the second die 201'.
The enclosing structure 200 comprises a first 2001 and a second 2002 opposite surface, and the enclosing structure 200 is provided with a plurality of first cavities and metal fins 500 which are recessed. The metal heat sink 500 includes a first portion 501, a second portion 502, and a connection portion 503 connected between the first portion 501 and the second portion 502. A first die 201 having a first protective layer 202 formed on its front surface is located within the first cavity. The front side of the first die 201 and the second portion 502 of the metal heat sink 500 are exposed at the first surface 2001 of the encapsulation structure 200, and the back side of the first die 201 faces the first portion 501 of the metal heat sink 500.
A first redistribution layer 206 is located on the first surface 2001 of the encapsulation structure 200 and the front side of the first die 201, the first redistribution layer 206 being electrically connected to pads on the front side of the first die 201. Specifically, the first rewiring layer 206 includes first conductive traces 2061 and first conductive posts 2062. First conductive traces 2061 are formed on the first surface 2001 of the encapsulation structure 200, the first conductive traces 2061 being electrically connected to the pads of the front side of the first die 201, in particular, the first conductive traces 2061 being electrically connected to the pads of the first die 201 through the second conductive medium 203 in the first protective layer opening 2021. A first conductive post 2062 is formed on a side of the first conductive trace 2061 away from the encapsulation structure 200.
The first dielectric layer 207 is formed on the first redistribution layer 206 and the exposed first surface 2001 of the encapsulation structure 200, the first protection layer 202 of the first die 201, and the second portion 502 of the metal heat sink 500, the first dielectric layer 207 is further provided with a plurality of recessed second cavities, the second die 201 ' with the second protection layer 202 ' formed on the front surface is located in the second cavities, and the back surface of the second die 201 ' faces the second portion 502 of the metal heat sink 500.
The second redistribution layer 208 is disposed on a side of the first dielectric layer 206 away from the encapsulation structure 200, and the second redistribution layer 208 is electrically connected to the first redistribution layer 206 and the bonding pads on the front side of the second die 201'. Specifically, second redistribution layer 208 includes second conductive traces 2081 and second conductive posts 2082. A second conductive trace 2081 is formed on a side of the first dielectric layer 206 away from the encapsulation structure 200, the second conductive trace 2081 electrically connects to a pad on the front side of the second die 201 ', and the second conductive trace 2081 electrically connects to a pad of the second die 201 ' through the second conductive medium 203 ' in the second passivation opening 2021. The first conductive post 2062 is formed on a side of the second conductive trace 2081 that is distal from the first dielectric layer 207.
A second dielectric layer 209 is formed on the second re-routing layer 208 and the exposed first dielectric layer 207 and the second protective layer 202 'of the second die 201'.
In this way, in the semiconductor package structure of the embodiment, the first bare chip with a certain function is firstly wired in a manner of encapsulating and forming the conductive layer, and then the second bare chip is fixed on the first surface of the encapsulating structure through the first dielectric layer, so that on one hand, the distance between the first bare chip and the second bare chip is favorably reduced, the structure of the formed semiconductor package structure is more compact, and the beneficial effect of reducing the overall occupied space is achieved; the semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
Furthermore, by applying a copper heat sink to the back side of the first and second dies, the heat build-up of the dies during use is rapidly dissipated, ensuring continued efficient operation of the dies during use.
In the present embodiment, a surface of the first portion 501 of the metal heat sink 500 away from the first die 201 is exposed to the second surface 2002 in the encapsulation structure 200. By exposing the side of the first portion 501 of the metal heat spreader 500 remote from the first die 201, it further helps to dissipate quickly the heat that builds up during use of the die, ensuring continued efficient operation of the die during use.
In this embodiment, the semiconductor package structure further includes a first metal connection layer (not shown), a first thermal conductive adhesive, a second metal connection layer (not shown), and a second thermal conductive adhesive.
A first metal connection layer is formed on the back side of the first die 201. The first metal connecting layer comprises a titanium metal layer and a copper metal layer which are arranged in a stacked mode. Specifically, a titanium metal layer is formed on the back surface of the first die 201 by a metal sputtering method; and forming a copper metal layer on the titanium metal layer by using a sputtering method. The first metal connecting layer can increase interlayer bonding of the packaging structure.
The first thermal conductive adhesive 600 is coated on the first metal connection layer, located between the first metal connection layer and the first portion 501 of the metal heat sink 500, and is used for connecting the first portion 501 of the metal heat sink 500 with the first metal connection layer, so that the back surface of the first die 201 and the first portion 501 of the metal heat sink 500 keep good contact.
In other embodiments, the first metal connection layer may not be provided, and the first thermal conductive adhesive 600 is directly coated on the back surface of the first die 201, and the first portion 501 of the metal heat sink 500 is connected to the back surface of the first die 201 through the first thermal conductive adhesive 600, so that the back surface of the first die 201 and the first portion 501 of the metal heat sink 500 are in good contact.
The second metal connection layer is formed on a back side of the second die. The second metal connecting layer has the same structure as the first metal connecting layer, and the description thereof is omitted.
The second thermal conductive paste 600' is coated on the second metal connection layer, between the second metal connection layer and the second portion 502 of the metal heat spreader 500, for connecting the second portion 502 of the metal heat spreader 500 with the second metal connection layer, so that the back surface of the first die 201 and the first portion 501 of the metal heat spreader 500 keep good contact.
In other embodiments, the second metal connection layer may not be provided, and the second thermal conductive adhesive 600 ' is directly coated on the back surface of the second die 201 ', and the second portion 502 of the metal heat spreader 500 is connected to the back surface of the second die 201 ' through the second thermal conductive adhesive 600 ' so that the back surface of the second die 201 ' and the second portion 502 of the metal heat spreader 500 are in good contact.
In the present embodiment, the thickness H1 of the second die 201' is less than the thickness H1 of the encapsulation structure 200. Since the second die 201 ' is fixed on the encapsulation structure 200 through the first dielectric layer 207 during the manufacturing process, the thickness H1 of the second die 201 ' is smaller than the thickness H1 of the encapsulation structure 200, so that the encapsulation structure 200 can provide better support when the second die 201 ' is fixed on the encapsulation structure 200 through the first dielectric layer 207. In addition, the space occupied by the final integral packaging structure is reduced.
The side of the second passivation layer 202 'away from the second die 201' is flush with the side of the first dielectric layer 207 away from the encapsulating structure 200, so as to provide a flat base surface for the next step of forming the second redistribution layer 208 during the manufacturing process, thereby improving the performance of the finally manufactured semiconductor package structure.
The first portion 501 of the metal heat spreader 500 and the back side of the first die 201 are shaped and sized to match, and the second portion 502 of the metal heat spreader 500 and the back side of the second die 201' are shaped and sized to match, to achieve better heat dissipation.
The width of the connection portion 503 of the metal heat spreader 500 is smaller than the width of the first portion 501 and the width of the second portion 502 of the metal heat spreader 500, so as to provide a deformation accommodating space for the metal heat spreader 500 to expand with heat and contract with cold in the above-mentioned packaging process.
In another embodiment, the re-routing structure includes more re-routing layers to achieve multi-level re-routing of the product.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (19)

1. A semiconductor packaging method, comprising:
providing an encapsulating structure member encapsulating a first bare chip to be encapsulated and a metal heat sink, wherein a first protective layer is formed on the front surface of the first bare chip to be encapsulated, the metal heat sink comprises a first part, a second part and a connecting part connected between the first part and the second part, the first part of the metal heat sink is tightly attached to the back surface of the first bare chip to be encapsulated, and the second part of the metal heat sink and the first protective layer of the first bare chip to be encapsulated are exposed out of the first surface of the encapsulating structure member;
forming a first redistribution layer on the first surface of the encapsulation structure, wherein the first redistribution layer is electrically connected with a welding pad on the front surface of the first bare chip to be packaged;
forming a first dielectric layer, wherein the first dielectric layer is formed on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protection layer of the first bare chip to be packaged and the second part of the metal heat sink, and fixing a second bare chip to be packaged with a second protection layer formed on the front surface on the second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, wherein the back surface of the second bare chip to be packaged is tightly attached to the second part of the metal heat sink;
forming a second rewiring layer on one surface of the first dielectric layer, which is far away from the encapsulation structure, wherein the second rewiring layer is electrically connected with the first rewiring layer and a welding pad on the front surface of the second die to be packaged;
and forming a second dielectric layer on a second protective layer formed on a second re-wiring layer and the exposed first dielectric layer and the second to-be-packaged bare chip.
2. The semiconductor packaging method according to claim 1, wherein after forming a first dielectric layer formed on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protection layer of the first die to be packaged, and the second portion of the metal heat sink, and fixing a second die to be packaged having a second protection layer formed on a front surface thereof on the second portion of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer, a back surface of the second die to be packaged being in close contact with the second portion of the metal heat sink, the semiconductor packaging method comprises:
applying the first dielectric layer on the first redistribution layer and the exposed first surface of the encapsulation structure, the first protective layer of the first die to be packaged, and the second portion of the metal heat sink;
after preliminary heating the first dielectric layer, applying the second to-be-packaged die with the second protective layer formed on the front surface to a position corresponding to a second part of the metal heat sink in the first surface of the encapsulation structure through the first dielectric layer;
and continuing to heat the first dielectric layer, wherein the first dielectric layer is heated and solidified, the second die to be packaged is solidified along with the first dielectric layer to a position, corresponding to the second part of the metal heat sink, in the first surface of the encapsulating structure, and the back surface of the second die to be packaged is tightly attached to the second part of the metal heat sink.
3. The semiconductor packaging method according to claim 2, wherein the preliminary heating is performed for 30 to 60 seconds at a temperature of 80 to 120 degrees; the continuous heating time is 1-4 hours, and the temperature is 190-200 ℃.
4. The semiconductor packaging method of claim 1, wherein prior to forming the first redistribution layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming the first protection layer on the front surface of the first bare chip to be packaged, and forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first bare chip to be packaged;
the first bare chip to be packaged and the metal radiating fin, the front surface of which is provided with the first protective layer, are attached to a carrier plate, the back surface of the first bare chip to be packaged faces upwards, the front surface of the first bare chip to be packaged faces the carrier plate, the first part of the metal radiating fin is tightly attached to the back surface of the first bare chip to be packaged, and the second part of the metal radiating fin is attached to the carrier plate;
covering the first bare chip to be packaged, the metal heat sink and the exposed carrier plate by an encapsulating layer to form the encapsulating structural member;
and stripping the carrier plate to expose the first surface of the encapsulation structure with the front surface of the first bare chip to be packaged and the second part of the metal heat sink.
5. The semiconductor packaging method according to claim 4, wherein after the forming of the encapsulation structure and before the peeling of the carrier plate, the semiconductor packaging method comprises:
thinning a second surface of the encapsulation structure far away from the carrier plate, and exposing one surface of the first part of the metal heat sink far away from the first bare chip to be packaged.
6. The semiconductor packaging method according to claim 4, wherein the first bare chip to be packaged and the metal heat sink, on which the first protective layer is formed on the front surface, are mounted on a carrier,
the semiconductor packaging method comprises the following steps:
mounting the first bare chip to be packaged with the first protective layer formed on the front surface on a carrier plate;
forming a first metal connecting layer on the back surface of the first bare chip to be packaged;
coating first heat-conducting glue on the first metal connecting layer; and a process for the preparation of a coating,
attaching the metal radiating fin to a carrier plate, wherein a first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat-conducting glue, and a second part of the metal radiating fin is attached to the carrier plate; alternatively, the first and second electrodes may be,
the semiconductor packaging method comprises the following steps:
mounting the first bare chip to be packaged with the first protective layer formed on the front surface on a carrier plate;
coating a first heat-conducting glue on the back surface of the first bare chip to be packaged; and a process for the preparation of a coating,
and attaching the metal radiating fin to the carrier plate, wherein the first part of the metal radiating fin is positioned on the first metal connecting layer and is connected with the first metal connecting layer through the first heat-conducting glue, and the second part of the metal radiating fin is attached to the carrier plate.
7. The semiconductor packaging method according to claim 4, wherein before the first die to be packaged and the metal heat sink, on which the first protective layer is formed on the front surface, are mounted on a carrier board, the semiconductor packaging method comprises:
and grinding the back surface of the first bare chip to be packaged.
8. The semiconductor packaging method according to claim 1, wherein before the second die to be packaged having the second protective layer formed on the front surface thereof is fixed on the second portion of the metal heat sink in the first surface of the encapsulating structure through the first dielectric layer,
the semiconductor packaging method comprises the following steps:
forming a second metal connecting layer on the back surface of the second die to be packaged; and
coating a second heat-conducting glue on the second metal connecting layer; alternatively, the first and second electrodes may be,
the semiconductor packaging method comprises the following steps:
coating a second heat-conducting glue on the back surface of the second die to be packaged; and/or the presence of a gas in the gas,
in a second part of the metal heat sink which is fixed in the first surface of the encapsulating structure by the first dielectric layer, a second to-be-packaged die with a second protective layer formed on the front surface is connected with a second metal connecting layer of the second to-be-packaged die by the second heat-conducting glue.
9. The semiconductor packaging method according to claim 1, wherein before the second die to be packaged having the second protective layer formed on the front surface thereof is fixed on the second portion of the metal heat sink in the first surface of the encapsulating structure through the first dielectric layer, the semiconductor packaging method comprises:
and grinding the back side of the second die to be packaged.
10. The semiconductor packaging method of claim 1, wherein in forming the first redistribution layer on the first surface of the encapsulation structure, the semiconductor packaging method comprises:
forming first conductive traces on a first surface of an encapsulation structure encapsulating a first die to be packaged, the first conductive traces being electrically connected with pads on a front side of the first die to be packaged;
and forming a first conductive convex column on one surface of the first conductive trace far away from the encapsulation structure.
11. The semiconductor packaging method according to claim 1, wherein in forming a second rewiring layer on a side of the first dielectric layer remote from the encapsulation structure, the semiconductor packaging method comprises:
forming a second conductive trace on a side of the first dielectric layer away from the encapsulation structure, the second conductive trace being electrically connected to both the first redistribution layer and a pad on a front side of the second die to be packaged;
forming a second conductive convex column on one surface of the second conductive trace far away from the first dielectric layer; and/or the presence of a gas in the gas,
in forming the second dielectric layer, the semiconductor packaging method includes:
and exposing the second conductive convex column on one surface of the second dielectric layer far away from the first rewiring layer.
12. The semiconductor packaging method according to claim 1, wherein before the second die to be packaged having the second protective layer formed on the front surface thereof is fixed on the second portion of the metal heat sink in the first surface of the encapsulating structure through the first dielectric layer, the semiconductor packaging method comprises:
forming a second protective layer opening on the second protective layer, wherein the second protective layer opening is positioned at a welding pad of the second die to be packaged;
and filling a second conductive medium in the second protective layer opening, so that the second conductive medium is electrically connected with the welding pad on the front side of the second die to be packaged.
13. A semiconductor package, comprising:
the encapsulating structure comprises a first surface and a second surface which are opposite, the encapsulating structure is provided with a plurality of first cavities and metal radiating fins which are concave inwards, each metal radiating fin comprises a first part, a second part and a connecting part connected between the first part and the second part, a first bare chip with a first protective layer formed on the front surface is positioned in the first cavity, the front surface of the first bare chip and the second part of the metal radiating fins are exposed out of the first surface of the encapsulating structure, and the back surface of the first bare chip faces to the first part of the metal radiating fins;
a first redistribution layer on the first surface of the encapsulation structure and the front side of the first die, the first redistribution layer electrically connected to pads on the front side of the first die;
the first dielectric layer is formed on the first rewiring layer, the exposed first surface of the encapsulation structure, the first protection layer of the first bare chip and the second part of the metal heat sink, the first dielectric layer is further provided with a plurality of concave second cavities, the second bare chip with the second protection layer formed on the front surface is positioned in the second cavities, and the back surface of the second bare chip faces the second part of the metal heat sink;
a second redistribution layer on a surface of the first dielectric layer away from the encapsulation structure, the second redistribution layer electrically connected to the first redistribution layer and the bonding pads on the front side of the second die;
and the second dielectric layer is formed on the second re-wiring layer and the exposed first dielectric layer and the second protection layer of the second bare chip.
14. The semiconductor package structure of claim 13, wherein a side of the first portion of the metal heat spreader distal from the first die is exposed at the second surface in the encapsulation structure.
15. The semiconductor package structure of claim 13, wherein the semiconductor package structure further comprises:
a first metal connection layer formed on a back side of the first die;
the first heat-conducting glue is coated on the first metal connecting layer, is positioned between the first metal connecting layer and the first part of the metal radiating fin and is used for connecting the first part of the metal radiating fin with the first metal connecting layer;
a second metal connection layer formed on a back side of the second die;
and the second heat-conducting glue is coated on the second metal connecting layer, is positioned between the second metal connecting layer and the second part of the metal radiating fin and is used for connecting the second part of the metal radiating fin with the second metal connecting layer.
16. The semiconductor package structure of claim 13, wherein a thickness of the second die is less than a thickness of the encapsulation structure.
17. The semiconductor package structure of claim 13, wherein a side of the second protective layer distal from the second die is flush with a side of the first dielectric layer distal from the encapsulation structure.
18. The semiconductor package structure of claim 13, wherein the first portion of the metal heat spreader matches a shape and size of the back side of the first die; and/or the second portion of the metal heat sink matches the shape and size of the back side of the second die.
19. The semiconductor package structure of claim 13, wherein a width of the connection portion of the metal heat spreader is less than a width of the first portion of the metal heat spreader and a width of the second portion.
CN202010231979.9A 2020-03-27 2020-03-27 Semiconductor packaging method and semiconductor packaging structure Active CN113725099B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010231979.9A CN113725099B (en) 2020-03-27 2020-03-27 Semiconductor packaging method and semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010231979.9A CN113725099B (en) 2020-03-27 2020-03-27 Semiconductor packaging method and semiconductor packaging structure

Publications (2)

Publication Number Publication Date
CN113725099A true CN113725099A (en) 2021-11-30
CN113725099B CN113725099B (en) 2023-11-21

Family

ID=78671112

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010231979.9A Active CN113725099B (en) 2020-03-27 2020-03-27 Semiconductor packaging method and semiconductor packaging structure

Country Status (1)

Country Link
CN (1) CN113725099B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090250805A1 (en) * 2008-04-03 2009-10-08 Lsi Corporation Heat Dissipation For Integrated Circuit
CN104576409A (en) * 2013-10-25 2015-04-29 钰桥半导体股份有限公司 Semiconductor device with face-to-face chips on interposer and method of manufacturing the same
US20190295952A1 (en) * 2018-03-20 2019-09-26 International Business Machines Corporation Direct bonded heterogeneous integration packaging structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090250805A1 (en) * 2008-04-03 2009-10-08 Lsi Corporation Heat Dissipation For Integrated Circuit
CN104576409A (en) * 2013-10-25 2015-04-29 钰桥半导体股份有限公司 Semiconductor device with face-to-face chips on interposer and method of manufacturing the same
US20190295952A1 (en) * 2018-03-20 2019-09-26 International Business Machines Corporation Direct bonded heterogeneous integration packaging structures

Also Published As

Publication number Publication date
CN113725099B (en) 2023-11-21

Similar Documents

Publication Publication Date Title
CN108172551B (en) Chip packaging method and packaging structure
CN210182362U (en) Chip structure
US20130069218A1 (en) High density package interconnect with copper heat spreader and method of making the same
US10276545B1 (en) Semiconductor package and manufacturing method thereof
US9831219B2 (en) Manufacturing method of package structure
US11830866B2 (en) Semiconductor package with thermal relaxation block and manufacturing method thereof
WO2022042682A1 (en) Semiconductor packaging method and semiconductor packaging structure
CN111883431B (en) Packaging substrate with efficient heat dissipation structure and manufacturing method thereof
CN113725099B (en) Semiconductor packaging method and semiconductor packaging structure
CN113725102B (en) Semiconductor packaging method and semiconductor packaging structure
CN111599769A (en) Semiconductor module packaging method and semiconductor module
CN109768032B (en) Antenna packaging structure and packaging method
CN112582283B (en) Semiconductor packaging method and semiconductor packaging structure
CN113725098B (en) Semiconductor packaging method and semiconductor packaging structure
CN113471086A (en) Semiconductor packaging method and semiconductor packaging structure
CN113725095B (en) Semiconductor packaging method and semiconductor packaging structure
KR100487135B1 (en) Ball Grid Array Package
CN113937015A (en) Semiconductor packaging method and semiconductor packaging structure
CN113725090A (en) Semiconductor packaging method
CN111933534B (en) Semiconductor packaging method and semiconductor packaging structure
CN113451161B (en) Semiconductor packaging method and semiconductor packaging structure
CN112582282B (en) Semiconductor packaging method and semiconductor packaging structure
CN111883438B (en) Semiconductor packaging method and semiconductor packaging structure
CN114975398B (en) Packaging structure and chip packaging method thereof
CN113725101B (en) Semiconductor packaging method and semiconductor packaging structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant