WO2022042682A1

WO2022042682A1 - Semiconductor packaging method and semiconductor packaging structure

Info

Publication number: WO2022042682A1
Application number: PCT/CN2021/114983
Authority: WO
Inventors: 霍炎; 涂旭峰
Original assignee: 矽磐微电子(重庆)有限公司
Priority date: 2020-08-31
Filing date: 2021-08-27
Publication date: 2022-03-03
Also published as: CN111883442A

Abstract

The present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises: mounting a lead frame and a plurality of chips on a support plate, the plurality of chips being located in a hollow-out area of the lead frame; forming an encapsulated structural member; forming on a first surface of the encapsulated structural member a rewiring structure electrically connected to the front sides of the plurality of chips and a first side of the lead frame; and mounting a passive member to a second surface of the encapsulated structural member, the passive member being electrically connected to the lead frame. The semiconductor packaging structure is prepared by means of the semiconductor packaging method. According to the present application, a stacked structure of the chips and the passive member in the vertical direction is formed, and lead bonding package is replaced with an approach of electroplating interconnect leads, such that the chips and the passive member are integrally packaged in the vertical direction, improving the production efficiency of product and realizing miniaturization of system-in-package.

Description

Semiconductor packaging method and semiconductor packaging structure

technical field

The present application relates to the technical field of semiconductors, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.

Background technique

System-in-package (English abbreviation: SIP, English full name: System In a Package), refers to the integration of multiple chips and passive devices in a package to achieve a basically complete function. Compared with the traditional package of individual chips, the system-in-package can achieve smaller package volume and lower package cost.

The form of system-in-package is that different chips or passive devices are placed side by side or stacked in the same lead frame, as shown in FIG. 1A and FIG. 1B , wherein FIG. 1A is a schematic cross-sectional structure diagram of the package along the first direction X 1B is a schematic cross-sectional structure diagram of the package along the second direction Y perpendicular to the first direction X. As shown in FIG. The chip 11' and the passive device 12' are respectively drawn out by means of metal leads 20' and a lead frame 30' by direct welding, and the devices are interconnected by metal leads 20' or copper sheets 40'.

However, this system-in-package has the following two problems:

1. Wire bonding requires a large internal space, which makes the development of ultra-thin products impossible, and the wires need to be individually bonded, resulting in low production efficiency;

2. The use of lead frames makes it impossible to miniaturize products.

SUMMARY OF THE INVENTION

One aspect of the present application provides a semiconductor packaging method comprising:

The lead frame and a plurality of chips are mounted on the carrier board, the front surfaces of the plurality of chips face the carrier board, the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction, so the plurality of chips are located in the hollow area;

By covering the encapsulation layer on the plurality of chips, the lead frame and the exposed carrier board, and filling the encapsulation layer in the hollow area of the lead frame, an encapsulation structure is formed, the encapsulation structure includes a first surface and a second surface opposite to the first surface, and the front surfaces of the plurality of chips and the first surface of the lead frame are exposed from the first surface;

A redistribution structure is formed on the first surface of the encapsulation structure, and the redistribution structure is electrically connected to the front surfaces of the plurality of chips and the first surface of the lead frame;

A passive component is mounted on the second surface of the encapsulation structure, and the passive component is electrically connected to a second surface of the lead frame opposite to the first surface.

A second aspect of the present application provides a semiconductor package structure, comprising:

An encapsulation structure includes opposing first and second surfaces, the encapsulation structure includes a lead frame and a plurality of chips and an encapsulation layer for encapsulating the lead frame and the plurality of chips, wherein The lead frame is provided with a hollow area, the hollow area penetrates the lead frame along the thickness direction, the plurality of chips are located in the hollow area, and the encapsulation layer is filled in the hollow area of the lead frame, so The encapsulation structure includes a first surface and a second surface opposite to the first surface, and the front surfaces of the plurality of chips and the first surface of the lead frame are exposed from the first surface;

a redistribution structure, the redistribution structure is formed on the first surface of the encapsulation structure, and the redistribution structure is electrically connected to the front surfaces of the plurality of chips and the first surface of the lead frame;

A passive component, the passive component is disposed on the second surface of the encapsulation structural component, and the passive component is electrically connected to a second surface of the lead frame opposite to the first surface.

The above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the present application, by attaching the passive component to the second surface (the backside of the chip) of the encapsulation structural component, and at the same time, the electrical leads of the passive component to the encapsulation through the lead frame The first surface of the structural member, thereby forming a stack structure of the chip and the passive member along the thickness direction, that is, a stack structure in the vertical direction, and replacing the wire-bonding package by electroplating the interconnection wire, the chip and the passive member. The package is integrated in the vertical direction (ie, the thickness direction). Compared with the system-in-package process shown in FIG. 1A and FIG. 1B , the semiconductor package structure of the present application does not require a wire bonding process and large-area wiring, reduces the size of the product, increases the degree of freedom of product design, and achieves miniaturization. , The demand for thinning and improving production efficiency.

Compared with the traditional wire bonding method, the semiconductor package structure of the present application can complete laser drilling and electroplating copper wiring at one time, and the production efficiency is significantly improved.

In addition, since the chip and the passive components are integrated in the vertical direction, the interconnection area of the chip and the passive components in the horizontal direction is saved compared with the traditional method, and the product size is miniaturized. The area can be laid with heat-dissipating copper, and the heat-dissipating performance of the product is improved.

The structure of the lead frame provided by the present application, by setting the hollow area, compared with the lead frame without the hollow area, because the part of the lead frame structure under the chip is no longer required, it can not only be applied to a chip with a larger area, but also can be discharged More chips have excellent applicability and can greatly reduce the thickness of the final product.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.

Description of drawings

FIG. 1A is a schematic cross-sectional structure diagram of a package according to an exemplary embodiment of the present application along a first direction.

1B is a schematic cross-sectional structural diagram of a package according to an exemplary embodiment of the present application along a second direction.

FIG. 2 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.

3A to 3O are process flow diagrams of a method for packaging a medium-sized semiconductor according to an exemplary embodiment of the present application.

FIG. 4 is a schematic structural diagram of a semiconductor package structure proposed according to an exemplary embodiment of the present application.

FIG. 5 is a schematic structural diagram of another implementation manner of a semiconductor package structure according to an exemplary embodiment of the present application.

FIG. 6 is a schematic structural diagram of still another implementation manner of a semiconductor package structure according to an exemplary embodiment of the present application.

detailed description

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Words like "a" or "an" used in the specification and claims of this application also do not denote a quantitative limitation, but rather denote the presence of at least one. "Plurality" means two or more. Words like "include" or "include" mean that the elements or items appearing before "including" or "including" cover the elements or items listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words like "upper" and/or "lower" are for convenience of description and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

As shown in FIG. 2 , FIG. 3A- FIG. 3O and FIG. 4 , the present embodiment provides a semiconductor packaging method and a semiconductor packaging structure 1 .

FIG. 2 is a flowchart of the semiconductor packaging method proposed in this embodiment. As shown in FIG. 2, the semiconductor packaging method includes the following steps:

Step 100: Mount the lead frame and a plurality of chips to be packaged on the carrier board, the front surfaces of the chips to be packaged face the carrier board, the lead frame is provided with a hollow area, and the hollow area penetrates all the holes in the thickness direction. the lead frame, wherein a plurality of the chips to be packaged are located in the hollow area;

Step 200 : forming an encapsulation by covering the encapsulation layer on the chip to be packaged, the lead frame and the exposed carrier board, and filling the encapsulation layer in the hollow area of the lead frame A structure, the encapsulation structure includes a first surface and a second surface opposite to the first surface, and the front surface of the chip to be packaged and the first surface of the lead frame are exposed from the first surface ;

Step 300 : forming a redistribution structure on the first surface of the encapsulation structure, and the redistribution structure is electrically connected to the front surface of the chip to be packaged and the first surface of the lead frame;

Step 400 : Mount a passive component on the second surface of the encapsulation structure, and the passive component is electrically connected to a second surface of the lead frame opposite to the first surface.

In the above-mentioned semiconductor packaging method provided by this embodiment, the passive component is mounted on the second surface (the backside of the chip) of the encapsulating structural component, and at the same time, the electricity of the passive component is led out to the encapsulating structural component through the lead frame. The first surface, thereby forming a stack structure of chips and passive components along the thickness direction, that is, a stack structure along the vertical direction, and replacing the wire-bonded packaging by electroplating interconnect leads, the chips and passive components are arranged in the vertical direction. (that is, the thickness direction) is packaged as a whole. Compared with the system-in-package process shown in FIG. 1A and FIG. 1B , the semiconductor package structure of the present application does not require a wire bonding process and large-area wiring, reduces the size of the product, increases the degree of freedom of product design, and achieves miniaturization. , The demand for thinning and improving production efficiency.

The structure of the lead frame provided in this embodiment, by setting the hollow area, compared with the lead frame without the hollow area, because the part of the lead frame structure under the chip is no longer required, it is not only applicable to the chip with a larger area, but also can Discharging more chips, has excellent applicability, and can greatly reduce the thickness of the final product.

Specifically, as shown in FIGS. 3A-3O, the semiconductor packaging method of this embodiment includes:

In step 100 , as shown in FIG. 3A , the chip 11 to be packaged and the lead frame 20 are mounted on the carrier board 3 through the adhesive layer, the back side of the chip to be packaged 11 faces upwards, and the front side faces the carrier board 3 . The chip 11 to be packaged includes a front surface 11a (active surface) provided with bonding pads, and a back surface 11b disposed opposite to the front surface 11a, so that the front surface 11a of the chip 11 to be packaged with bonding pads has electrical leads.

The lead frame 20 is provided with a hollow area 21 , the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .

Each lead frame 20 includes a first surface 20a and a second surface 20b arranged opposite to each other along the thickness direction T. The first surface 20a is provided with a number of first electrical connection points, and the second surface 20b is provided with a number of second electrical connection points. .

The thickness of the lead frame 20 may be equal to or slightly larger than the thickness of the chip 11 to be packaged. When the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be packaged, the thickness of the lead frame 20 will also be reduced at the same time during the process of thinning the second surface 10 b of the encapsulation structure 10 to exposing the back surface 11 b of the chip 11 to be packaged The part of the chip 11 to be packaged is removed. When the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, when the second surface 10b of the encapsulation structure 10 is thinned to expose the back surface 11b of the chip to be packaged 11, the second surface 20b of the lead frame 20 is also exposed at the same time . In some embodiments, the thickness of the lead frame 20 is equal to the thickness of the chip 11 to be packaged, so that the grinding process can be effectively reduced.

The adhesive layer is used to bond the chip 11 to be packaged and the lead frame 20, and the adhesive layer can be made of an easily peelable material, so that the carrier 3, the chip to be packaged 11 and the lead frame 20 can be peeled off in the subsequent process, for example A thermally separable material that can be debonded by heating can be used.

In other embodiments, the adhesive layer may adopt a two-layer structure, a thermal separation material layer and a chip attach layer. The thermal separation material layer is pasted on the carrier board 3 and loses its viscosity when heated, so that it can be removed from the carrier board 3 . The chip is peeled off, and the chip attach layer adopts an adhesive material layer, which can be used to stick the chip 11 to be packaged. After the chip 11 to be packaged is peeled off from the carrier board 3 , the chip attach layer thereon may be removed by chemical cleaning. In one embodiment, an adhesive layer may be formed on the carrier board 3 by means of lamination, printing, or the like.

The number of chips 11 to be packaged is multiple. The number of chips 11 to be packaged can be adjusted according to design requirements, which is not limited herein.

In step 200, as shown in FIG. 3B, by covering the encapsulation layer 14 on the entire carrier 3, that is, covering the chip 11 to be packaged, the lead frame 20 and the exposed carrier 3, and the encapsulation layer 14 is filled in the hollow area 21 of the lead frame 20 , and the to-be-packaged chip 11 and the lead frame 20 are plastic-encapsulated to form the encapsulation structure 10 . The encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.

The encapsulation structure 10 includes a first surface 10a and a second surface 10b arranged opposite to each other. The second surface 10b of the encapsulation structure 10 is arranged opposite to the carrier plate 3 and is substantially flat and parallel to the surface of the carrier plate 3 . . The protective layer 30 formed on the front surface of the chip 11 to be packaged and the first surface 20 a of the lead frame 20 are exposed on the first surface 10 a of the encapsulation structure 10 .

In one embodiment, the encapsulation layer 14 may be formed by laminating epoxy resin film or Molding film, or may be formed by injection molding or compression molding of epoxy resin compound. molding) or transfer molding (Transfer molding).

Optionally, before entering step 300 , the packaging method further includes mounting the first support plate 41 on the second surface 10 b of the packaging structural member 10 .

The first support plate 41 is mounted on at least a partial area of the second surface 10 b of the encapsulation structure 10 . As shown in FIG. 3C , in one embodiment, the first support plate 41 is mounted on the second surface 10 b of the encapsulation structure 10 , and the first support plate 41 covers the second surface of the encapsulation structure 10 All areas of 10b.

The material strength of the first support plate 41 is greater than the material strength of the encapsulation layer, so that the support plate can effectively improve and ensure the mechanical strength of the encapsulation structure during the encapsulation process, effectively suppress the adverse effects caused by the deformation of each structure, thereby improving the product quality. The effect of encapsulation. In other embodiments, the first support plate 41 may also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, or the like.

Next, before entering step 300 , as shown in FIG. 3D , the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 . The first surface 10 a of the encapsulation structure 10 exposes the front surface of the chip 11 to be packaged and the first surface 20 a of the lead frame 20 .

In some embodiments, the adhesive layer between the carrier board 3 and the chip to be packaged 11 and the lead frame 20 is a thermal separation film, which can be heated to reduce the viscosity of the adhesive layer after being heated, thereby peeling off the carrier. plate 3. By heating the adhesive layer to peel off the carrier plate 3 , the damage to the chip 11 to be packaged during the peeling process can be minimized. In other embodiments, the carrier plate 3 can also be directly mechanically peeled off.

After the carrier board 3 is peeled off, the first surface 10 a of the encapsulation structure 10 facing the carrier board 3 , the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 are exposed. After peeling off the carrier board 3 , the first encapsulation structure 10 is obtained, which includes the chip to be packaged 11 , the lead frame 20 , and the encapsulation layer 14 that encapsulates the chip to be packaged 11 and the lead frame 20 . On the formed encapsulation structure 10 , rewiring and the like may be performed according to the actual situation, so that the chip 11 to be encapsulated is electrically connected to the outside world.

It should be noted that, the step of attaching the first support plate 41 may also be performed after peeling off the carrier plate 3 .

Next, before entering step 300 , as shown in FIG. 3E , a protective layer 30 is formed on the first surface 10 a of the encapsulation structure 10 . Then, as shown in FIG. 3F , the positions on the protective layer 30 corresponding to the pads on the front side of the chip 11 to be packaged and the positions corresponding to the first electrical connection points on the first side 20 a of the lead frame 20 A protective layer opening 31 is formed there.

In this embodiment, since the lead frame 20 and the chip 11 to be packaged are arranged on the same level, when the protective layer 30 is punched to form the protective layer opening 31 , the protective layer 30 is a transparent film layer, except for the use of the protective layer 30 . Transparency can be used for positioning, and the lead frame 20 can be used to assist positioning to improve the positional accuracy of laser drilling. However, it is not limited to this. In other embodiments, before the chip 11 to be packaged is mounted on the carrier 3 , the protective layer 30 may be formed on the front side of the chip to be packaged 11 , and the protective layer 30 may be connected to the surface of the chip to be packaged 11 . A protective layer opening 31 is formed at a position corresponding to the pad on the front side. Each protective layer opening 31 is at least correspondingly located on the bonding pad of the chip 11 to be packaged or the wire drawn from the bonding pad, so that the bonding pad on the front side of the chip 11 to be packaged or the wire drawn from the bonding pad is exposed from the protective layer opening 31 . Next, the redistribution structure 50 is directly formed on the first surface 10 a of the encapsulation structure 10 .

In step 300, as shown in FIG. 3G and FIG. 3H, a redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged, and It is electrically connected to the first electrical connection point of the first side 20a of the lead frame 20 . That is, the redistribution structure 50 is formed on the protective layer 30 on the first surface 10 a of the encapsulation structure 10 .

The redistribution structure 50 includes at least one redistribution layer 51 and a pin layer 52 . In this embodiment, the redistribution structure 50 includes one layer of redistribution layers 51, but it is not limited to this, and may also include multiple layers of redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip to be packaged, such as More rewiring structures can be formed in the same way, which can be adjusted according to design requirements.

Among them, since the protective layer opening 31 has been formed on the protective layer 30 , when the redistribution layer 51 is formed, at least the protective layer opening 31 can be directly seen, so the redistribution structure 50 can be more accurately aligned.

When the redistribution structure 50 is formed, a conductive medium may be simultaneously filled in the protective layer openings 31 of the protective layer 30 to form the conductive pillars 53 , that is, the redistribution layer 51 and the conductive pillars 53 are formed in the same conductive layer formation process. The conductive pillars 53 form a vertical connection structure in the protective layer opening 31 , and the bonding pads on the front surface 11 a of the chip 11 to be packaged are electrically led out through the conductive pillars 53 and the redistribution layer 51 .

The semiconductor package structure 1 is electrically connected to the outside through the pin layer 52 , and is installed in the next step through the pin layer 52 .

The material of the pin layer 52 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.

It should be noted that the thickness of the redistribution structure 50 is much smaller than the thickness of the lead frame 30' in FIGS. 1A and 1B . Generally, the thickness of the rewiring structure is 15um to 45um, and the thickness of the lead frame 30' is generally 150um to 450um. Therefore, the rewiring structure not only realizes the function of wiring, but also realizes the thinning of the product.

Next, as shown in FIG. 3I , a dielectric layer 60 is formed, and the dielectric layer 60 is formed on the redistribution structure 50 and the surface of the exposed protective layer 30 . The dielectric layer 60 may be formed by molding film, or the dielectric layer 60 may be formed by lamination or printing. The dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy, and PBO (Polybenzoxazole). In some embodiments, the dielectric layer 60 employs an epoxy compound.

As shown in FIG. 3J , after the dielectric layer 60 is formed, the method further includes thinning the side of the dielectric layer 60 away from the encapsulation structure 10 in the T direction shown in FIG. 3A until the redistribution structure is exposed. 50 is away from a surface of the encapsulation structure 10 , that is, thinned to expose a surface of the lead layer 52 away from the encapsulation structure 10 .

As shown in FIG. 3K , after forming the dielectric layer 60 , the packaging method further includes peeling off the first support plate 41 . The first support plate 41 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.

Optionally, after peeling off the first support plate 41 , the packaging method further includes attaching a second support plate 42 on the side of the dielectric layer 60 away from the encapsulation structure 10 .

The second support plate 42 is mounted on at least a partial area of the side of the dielectric layer 60 away from the encapsulation structure 10 . In one embodiment, the second support plate 42 is mounted on the dielectric layer 60 , and the second support plate 42 is mounted on the entire area of the side of the dielectric layer 60 away from the encapsulation structure 10 .

The material strength of the second support plate 42 is greater than that of the dielectric layer 60 , so that the support plate can effectively improve and ensure the mechanical strength of the packaging structure during the packaging process, effectively suppress the adverse effects caused by the deformation of each structure, and improve product packaging. Effect. In other embodiments, the second support plate 42 may also be formed on the dielectric layer 60 by spraying, printing, coating, or the like.

It should be noted that, the step of attaching the second support plate 42 may also be performed before peeling off the first support plate 41 .

Optionally, before entering step 400 , as shown in FIG. 3L , before the passive components are mounted on the second surface 10 b of the encapsulating structural member 10 , the encapsulation method further includes the second surface of the encapsulating structural member 10 being mounted on the second surface 10 b of the encapsulating structural member 10 . 10b is ground to reduce the thickness of the encapsulation structure 10 . In some embodiments, the encapsulation structure 10 is thinned in the T direction to expose the second side 20 b of the lead frame 20 .

The thickness of the lead frame 20 may be equal to or slightly larger than the thickness of the chip 11 to be packaged. When the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be packaged, in the process of thinning the second surface 10 b of the encapsulation structure 10 to expose the back surface 11 b of the chip 11 to be packaged, the lead frame 20 will also be thinned and thickened at the same time. The portion of the chip 11 to be packaged. When the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, when the second surface 10b of the encapsulation structure 10 is thinned to expose the back surface 11b of the chip to be packaged 11, the second surface 20b of the lead frame 20 is also exposed at the same time . In some embodiments, the thickness of the lead frame 20 is equal to the thickness of the chip 11 to be packaged, so that the grinding process can be effectively reduced.

Before entering step 400 , as shown in FIG. 3M , the limiting member 70 is provided on the second surface 10 b of the encapsulating structural member 10 . The orthographic projection of the limiting member 70 along the thickness direction T is located within the orthographic projection of the lead frame 20, so as to facilitate the position definition and reference when the passive member 80 is mounted on the second surface 10b of the encapsulating structural member 10 in subsequent steps; more Further, by disposing the limiting member 70 on the second surface 10b of the encapsulating structural member 10 , the impact resistance of the passive member 80 in the horizontal direction can also be enhanced, and the passive member 80 can be protected.

In this embodiment, the limiting member 70 is cylindrical, that is, a limiting column, and is formed on the second surface 10b of the encapsulating structural member 10 by means of electroplating. But not limited to this, the shape of the limiting member 70 can also be annular (ie, limiting ring), or spherical (ie, limiting ball), or other formed limiting members, the limiting member should try not to affect the original structure.

In step 400 , as shown in FIG. 3N , the passive device 80 is mounted on the second surface 10 b of the encapsulation structure 10 , and the passive device 80 is electrically connected to the second electrical connection point on the second surface 20 b of the lead frame 20 . connect. Passive element 80 includes one or more of capacitance, resistance and inductance.

The passive element 80 includes a main body 81 and solder pins 82 . The solder pins 82 are disposed on both sides of the main body 81 in the horizontal direction.

Preferably, the orthographic projection of the solder fillet 82 along the thickness direction is within the orthographic projection of the lead frame 20 . In this way, a more compact stacking structure along the vertical direction is formed, thereby achieving the purpose of reducing the size of the product.

During mounting, the passive element 80 is mounted on the second surface 10b of the encapsulating structural member 10 with reference to the position of the limiting element 70 , the impact resistance of the passive element 80 in the horizontal direction can be improved by the limiting element 70 , and at the same time, the impact resistance of the passive element 80 can be improved. The mounting position of the passive component 80 can be positioned more accurately.

The number of the limiting members 70 may be multiple, and the mounting position of the passive member 80 is pre-defined by the multiple limiting members 70 , and further, the mounting position of the solder pins 82 of the passive member 80 may be defined.

The limiting member 70 includes a first limiting member 71 and a second limiting member 72 arranged in the horizontal direction; the first limiting member 71 is located in the orthographic projection of the lead frame 20 along the thickness direction T, and is located on the positive side of the passive member 80 . Outside the projection; along the thickness direction T, the second limiting member 72 is located in the orthographic projection of the lead frame 20 and is located in the orthographic projection of the passive member 80 .

The welding leg 82 of the passive member 80 is located between the first limiting member 71 and the second limiting member 72 . Therefore, the welding legs 82 are limited by the first limiting member 71 and the second limiting member 72, so that the impact resistance of the passive member 80 in the horizontal direction can be improved, and at the same time, the positioning of the passive member 80 during mounting can be improved. more accurate.

Next, the second support plate 42 is peeled off, as shown in FIG. 3O. The second support plate 42 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.

In this embodiment, since the lead frame 20 is electrically connected to the redistribution structure 50 and the passive component 80 , the lead frame 20 realizes the interconnection between the passive component 80 located on the backside of the chip 11 to be packaged and the front surface of the chip to be packaged 11 .

The rewiring structure 50 and the lead frame 20 are used to realize the electrical lead-out of the passive component 80 and the electrical connection of the electronic components (the passive component 80 and the plurality of chips 11 to be packaged) inside the package of the semiconductor packaging structure 1, compared to the electrical connection completed by the leads solution, the semiconductor package structure of this embodiment requires less space, not only the space in the thickness direction, but also the space in the horizontal direction; and, because the electrical connection does not need to be drawn out from the pins of the lead frame, and then wiring The layout of the structure is more free and flexible.

Specifically, the electrical lead-out of the front side 11a of the chip 11 to be packaged is achieved by the direct electrical connection between the pads (not shown in the figure) of the front side 11a of the chip 11 to be packaged and the redistribution structure 50; The extraction is realized by electrical connection with the lead frame 20 and the redistribution structure 50 .

It should also be noted that, if multiple semiconductor package structures are packaged together, after the package is completed, the entire package structure is cut into multiple semiconductor package structures by laser or mechanical cutting. A structural diagram of the formed semiconductor package structure 1 is shown in FIG. 4 .

As shown in FIG. 4 , it is a schematic structural diagram of a semiconductor packaging structure 1 obtained by using the above-mentioned semiconductor packaging method according to the present embodiment. The semiconductor package structure 1 includes: an encapsulation structure 10 , a redistribution structure 50 and a passive component 80 .

The encapsulation structure 10 includes opposite first surfaces 10 a and second surfaces 10 b , the encapsulation structure 10 includes a lead frame 20 and a plurality of chips 11 and an encapsulation layer 14 for encapsulating the lead frame 20 and the plurality of chips 11 The lead frame 20 is provided with a hollow area, the hollow area penetrates the lead frame 20 along the thickness direction T, a plurality of the chips are located in the hollow area, and the encapsulation layer 14 is filled in the hollow area of the lead frame 20 .

The chip 11 includes a front surface provided with bonding pads, and a back surface disposed opposite to the front surface. The number of chips 11 is plural. The number of chips 11 can be adjusted according to design requirements, which is not limited here. In this embodiment, the number of chips 11 is two.

The lead frame 20 includes a first surface 20a and a second surface 20b disposed opposite to each other along the thickness direction T. The first surface 20a is provided with a number of first electrical connection points, and the second surface 20b is provided with a number of second electrical connection points. The number of hollow regions 21 of the lead frame 20 may be one or more. In this embodiment, each lead frame 20 is provided with one hollow area 21 , but it is not limited thereto, and the number of hollow areas 21 may be other numbers according to design requirements.

Both the front surface of the chip 11 and the first surface 20a of the lead frame 20 face the same direction. The front surface of the chip 11 and the first surface 20a of the lead frame 20 are exposed on the first surface 10a.

The redistribution structure 50 is formed on the first surface 10 a of the encapsulation structure 10 corresponding to the front surface of the chip 11 , and the redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and is connected to the first surface 20 a of the lead frame 20 . An electrical connection point is electrically connected. The redistribution structure 50 includes at least one redistribution layer 51 and a pin layer 52 . That is, the lead layer 52 is located on the side of the redistribution layer 51 away from the encapsulation structure 10 , and the redistribution layer 51 is located between the encapsulation structure 10 and the lead layer 52 . In this embodiment, the redistribution structure 50 includes one layer of redistribution layers 51, but it is not limited to this, and can also include multiple layers of redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip, for example, the same More re-wiring structures can be formed in different ways, which can be adjusted according to design requirements.

In some embodiments, the orthographic projection of the pin layer 52 lies within the orthographic projection of the redistribution layer 51 in the thickness direction. That is, the spacing between adjacent pin layers 52 is greater than the spacing between adjacent redistribution layers 51 corresponding to the adjacent pin layers 52, so that the final semiconductor package product is formed using tin or other materials. When welding, it is not easy to short circuit, which improves the electrical performance of the product.

The first surface of the encapsulation structure 10 is provided with a protective layer 30 , and the protective layer 30 is located between the redistribution structure 50 and the encapsulation structure 10 . A protective layer opening 31 is formed on the protective layer 30 , and a conductive column 53 formed by filling a conductive medium is arranged in the protective layer opening 31 . The first redistribution layer 51 and the conductive pillar 53 may be formed in the same conductive layer forming process.

The passive element 80 is disposed on the second surface of the encapsulation structure 10 , and the passive element 80 is electrically connected to the second electrical connection point of the second surface 20 b of the lead frame 20 . Passive element 80 includes one or more of capacitance, resistance and inductance. The passive component 80 includes a main body 81 and solder pins 82 . The solder pins 82 are disposed on both sides of the main body 81 in the horizontal direction.

In some embodiments, the orthographic projection of the passive element 80 in the thickness direction T lies within the orthographic projection of the leadframe 20 . In this way, a more compact stacking structure along the vertical direction is formed, thereby achieving the purpose of reducing the size of the product.

The thickness of the lead frame 20 is equal to the thickness of the chip 11 , so that the grinding process can be effectively reduced.

The second surface 20b of the lead frame 20 is exposed to the second surface 10b of the encapsulation structure 10 , that is, the thickness of the encapsulation structure 10 is equal to the thickness of the lead frame 20 , thereby achieving the thinnest semiconductor package structure 1 .

The encapsulation structure 10 further includes a dielectric layer 60 formed on the redistribution structure 50 and the exposed first surface of the protective layer 30 . The dielectric layer 60 may be formed by molding film, or the dielectric layer 60 may be formed by lamination or printing. The dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy, and PBO (Polybenzoxazole). In some embodiments, the dielectric layer 60 employs an epoxy compound. When the front side of the chip is repeatedly rewired, more dielectric layers can also be formed in the same way, which can be adjusted according to design requirements. In the thickness direction, the dielectric layer 60 is exposed on a surface away from the encapsulation structure 10 , and the redistribution structure 50 is exposed on a surface away from the encapsulation structure 10 , that is, the exposed pin layer 52 is away from the encapsulation structure. a surface of the member 10 .

In this embodiment, a limiting member 70 is disposed on the second surface 10 b of the encapsulating structural member 10 , and the passive member 80 is mounted on the second surface 10 b of the encapsulating structural member 10 corresponding to the limiting member 70 . By arranging the limiting member 70 , the passive member 80 can be limited to achieve precise welding; further, by arranging the limiting member 70 on the second surface 10 b of the encapsulating structural member 10 , the passive member 80 can also be strengthened. The impact resistance in the horizontal direction can protect the passive member 80 .

The orthographic projection of the limiting member 70 along the thickness direction T is located within the orthographic projection of the lead frame 20 , and the passive member 80 is mounted on the second surface 10 b of the encapsulating structural member 10 with reference to the position of the limiting member 70 , passing the limiting member 70 . The impact resistance of the passive element 80 in the horizontal direction can be improved, and the mounting position of the passive element 80 can be positioned more accurately.

The welding leg 82 of the passive member 80 is located between the first limiting member 71 and the second limiting member 72 . Therefore, the welding legs are limited by the first limiting member 71 and the second limiting member 72, so that the impact resistance of the passive member 80 in the horizontal direction can be improved, and the positioning of the passive member 80 during mounting can be improved. precise.

In this embodiment, the limiting member 70 is cylindrical, that is, a limiting column, and is formed on the second surface 10b of the encapsulating structural member 10 by means of electroplating. But not limited to this, the shape of the limiting member 70 can also be annular (ie, limiting ring), or spherical (ie, limiting ball), or a limiting member of other shapes, and the limiting member should try not to affect the original structure.

In another embodiment, the limiting member 70 only includes the first limiting member 71 . For example, the shape of the first limiting member 71 is annular, that is, the limiting ring, and the cross-section of the limiting ring (the first limiting member 71 ) The structure is shown in FIG. 5 , the solder pins 82 of the passive element 80 are directly mounted in the annular structure of the limiting ring (the first limiting element 71 ) to limit the passive element 80 and strengthen the passive element 80 The impact resistance in the horizontal direction can protect the passive component 80 and achieve precise welding.

In yet another embodiment, as shown in FIG. 6 , the limiting member 70 includes only the first limiting member 71 , and the first limiting member 71 is located in the orthographic projection of the lead frame 20 along the thickness direction T, and is located in the to-be-mounted outside the orthographic projection of the passive member 80; the position to be mounted of the passive member 80 can also be marked only by fixing the first limiting member 71 to the outer position of the outer periphery of the passive member 80, that is, by mounting the passive member 80 on The inner side of the first limiting member 71 enhances the impact resistance of the passive member 80 in the horizontal direction, and can also locate the mounting position of the passive member 80 .

In the above-mentioned semiconductor package structure provided by this embodiment, the passive component is disposed on the second surface (the backside of the chip) of the encapsulating structural component, and at the same time, the electric power of the passive component is led out to the second surface of the encapsulating structural component through the lead frame. A surface is formed to form a stack structure of chips and passive components along the thickness direction, that is, a stack structure along the vertical direction, and the chip and passive components are placed in a vertical direction ( That is, the thickness direction) is packaged upward as a whole. Compared with the system-in-package process shown in FIG. 1A and FIG. 1B , the semiconductor package structure of the present application does not require a wire bonding process and large-area wiring, reduces the size of the product, increases the degree of freedom of product design, and achieves miniaturization. , The demand for thinning and improving production efficiency.

In this application, the structural embodiments and the method embodiments may complement each other without conflict.

The above are only some embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims

A semiconductor packaging method, comprising:

The lead frame and a plurality of chips are mounted on the carrier board, the front surfaces of the plurality of chips face the carrier board, the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction, so the plurality of chips are located in the hollow area;

By covering the encapsulation layer on the plurality of chips, the lead frame and the exposed carrier board, and filling the encapsulation layer in the hollow area of the lead frame, an encapsulation structure is formed, the encapsulation structure includes a first surface and a second surface opposite to the first surface, and the front surfaces of the plurality of chips and the first surface of the lead frame are exposed from the first surface;

A redistribution structure is formed on the first surface of the encapsulation structure, and the redistribution structure is electrically connected to the front surfaces of the plurality of chips and the first surface of the lead frame;

A passive component is mounted on the second surface of the encapsulation structure, and the passive component is electrically connected to a second surface of the lead frame opposite to the first surface.
The semiconductor packaging method of claim 1, wherein the orthographic projection of the passive component along the thickness direction is within the orthographic projection of the lead frame.
The semiconductor packaging method of claim 1, wherein:

The thickness of the lead frame is equal to the thickness of one chip among the plurality of chips. When the passive component is mounted on the second surface of the encapsulation structure, the passive component and the lead frame are opposite to the first surface. Before the second surface provided on one side is electrically connected, the method further includes: thinning the encapsulation structure in the thickness direction to expose the back surfaces of the plurality of chips and the first surface of the lead frame. two sides.
The semiconductor packaging method of claim 1, wherein a passive component is mounted on the second surface of the encapsulation structure, and the passive component and the lead frame are disposed opposite to the first surface Before the second surface of the encapsulation is electrically connected, the method further includes: disposing a limiting member on the second surface of the encapsulating structural member;

Mounting the passive component on the second surface of the encapsulating structural component includes: mounting the passive component on the second surface of the encapsulating structural component corresponding to the limiting component.
5. The semiconductor packaging method according to claim 4, wherein the orthographic projection of the limiting member along the thickness direction is located within the orthographic projection of the lead frame.
A semiconductor packaging structure, comprising:

An encapsulation structure includes opposing first and second surfaces, the encapsulation structure includes a lead frame and a plurality of chips and an encapsulation layer for encapsulating the lead frame and the plurality of chips, wherein The lead frame is provided with a hollow area, the hollow area penetrates the lead frame along the thickness direction, the plurality of chips are located in the hollow area, and the encapsulation layer is filled in the hollow area of the lead frame, so the front surfaces of the plurality of chips and the first surface of the lead frame are exposed from the first surface;

a redistribution structure, the redistribution structure is formed on the first surface of the encapsulation structure, and the redistribution structure is electrically connected to the front surfaces of the plurality of chips and the first surface of the lead frame;

A passive component, the passive component is disposed on the second surface of the encapsulation structural component, and the passive component is electrically connected to a second surface of the lead frame opposite to the first surface.
6. The semiconductor package structure of claim 6, wherein the orthographic projection of the passive component along the thickness direction is within the orthographic projection of the lead frame.
6. The semiconductor package structure of claim 6, wherein a thickness of the lead frame is equal to a thickness of one of the plurality of chips.
6. The semiconductor package structure of claim 6, wherein a limiting member is disposed on the second surface of the encapsulating structural member, and the passive member is mounted on the encapsulating structural member corresponding to the limiting member the second surface.
The semiconductor package structure according to claim 9, wherein the orthographic projection of the limiting member along the thickness direction is located within the orthographic projection of the lead frame;

The shape of the limiting member is cylindrical, spherical, or annular.
The semiconductor package structure according to claim 9, wherein,

The limiting member includes a first limiting member, and the orthographic projection of the first limiting member along the thickness direction is located within the orthographic projection of the lead frame, and is located outside the orthographic projection of the passive member.
The semiconductor package structure according to claim 9, wherein,

The limiting member includes a first limiting member, and the orthographic projection of the first limiting member along the thickness direction is located in the orthographic projection of the lead frame, and the passive member includes a main body and at least one welding leg, so The welding leg is located in the first limiting member.
The semiconductor package structure according to claim 9, wherein,

The limiting member includes a first limiting member and a second limiting member; the first limiting member is located in the orthographic projection of the lead frame along the thickness direction, and is located outside the orthographic projection of the passive member; The second limiting member in the thickness direction is located in the orthographic projection of the lead frame, and is located in the orthographic projection of the passive member;

The passive member includes a main body and at least one welding leg, and the welding leg is located between the first limiting member and the second limiting member.
6. The semiconductor package structure of claim 6, wherein a first surface of the encapsulation structure is provided with a protective layer, and the protective layer is located on the first surface of the redistribution structure and the encapsulation structure between the surfaces.
15. The semiconductor package structure according to claim 14, wherein the protective layer is provided with a protective layer opening, and the protective layer opening is provided in the protective layer corresponding to the pads on the front surfaces of the plurality of chips locations and corresponding locations of electrical connection points on the first side of the leadframe.