WO2022021799A1 - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
WO2022021799A1
WO2022021799A1 PCT/CN2020/141965 CN2020141965W WO2022021799A1 WO 2022021799 A1 WO2022021799 A1 WO 2022021799A1 CN 2020141965 W CN2020141965 W CN 2020141965W WO 2022021799 A1 WO2022021799 A1 WO 2022021799A1
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WIPO (PCT)
Prior art keywords
lead frame
chip
packaged
encapsulation
chips
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PCT/CN2020/141965
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French (fr)
Chinese (zh)
Inventor
霍炎
涂旭峰
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矽磐微电子(重庆)有限公司
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Publication of WO2022021799A1 publication Critical patent/WO2022021799A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • a lead frame 30' and a wiring layer 40' are often used to implement a double-sided interconnect package of two chips 10'.
  • the backsides of the two chips 10' are mounted on the upper surface of the lead frame 30' through the conductive adhesive 20' to realize the backside electrical connection, and the wiring layer 40' is connected to the front side of the chip 10' through the copper pillars 50'.
  • the copper pillar 50' needs to be implanted by means of ultrasonic bonding, and the cost of this process is extremely high, but the efficiency is extremely low.
  • arranging the lead frame 30' on the backside of the chip 10' results in a thicker product, which will be limited when applied to wearable equipment or other scenarios that have higher requirements on product thickness.
  • the present application provides a semiconductor packaging method and a semiconductor packaging structure.
  • One aspect of the present application provides a semiconductor packaging method, which includes: mounting a lead frame and a plurality of chips to be packaged on a carrier board, the front surfaces of the chips to be packaged face the carrier board, and the lead frame is provided with a hollow area , the hollow area runs through the lead frame along the thickness direction, and a plurality of the chips to be packaged are located in the hollow area; by covering the chips to be packaged, the lead frame and the carrier board with an encapsulation layer The exposed part is filled in the hollow area of the lead frame to form an encapsulation structure, the encapsulation structure includes a first surface and a second surface arranged oppositely, the front side of the chip to be packaged and all the The first surface of the lead frame is exposed on the first surface of the encapsulation structure; a first redistribution structure is formed on the first surface of the encapsulation structure, and the first redistribution structure is connected to the to-be-packaged structure The front surface of the chip and the first surface of the lead frame are electrically connected; and
  • a second aspect of the present application provides a semiconductor package structure including an encapsulation structure having opposing first and second surfaces, the encapsulation structure including a lead frame assembly, a plurality of chips, and a an encapsulation layer that encapsulates the lead frame assembly and the plurality of chips, the lead frame assembly is disposed on the periphery of each of the chips to define the respective accommodating spaces of the plurality of chips, and the accommodating space is The space runs through the lead frame assembly in the thickness direction, the encapsulation layer is filled in the accommodating space defined by the lead frame assembly, and the front surface of the chip and the first surface of the lead frame assembly are exposed to the package the first surface of the encapsulation structure; the first redistribution structure, the first redistribution structure is formed on the first surface of the encapsulation structure, the first redistribution structure and the front surface of the chip and the The first surface of the lead frame assembly is electrically connected; the second redistribution structure is formed on the second surface of the encapsulation structure, and the
  • the above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application realize the double-sided interconnection packaging of the chip through the lead frame and the double-sided re-wiring interconnection process, improve the thinning of the product, and enhance the electrical reliability of the product. sex.
  • the thickness is greatly reduced.
  • the thickness of the product is reduced, and the thinning of the product is effectively realized.
  • the technical solution in this application directly leads the electricity from the front side of the chip to the back side of the chip through the lead frame, and no longer needs copper pillar components, improves the wiring area, can realize multi-layer wiring process, and increases product design.
  • the degree of freedom increases the electrical reliability of the product; at the same time, the production cost is saved and the overall production efficiency is improved.
  • the double-sided interconnection of the chip can be realized directly through the lead frame, without the need for copper pillar components. , so as to increase the interconnection area, realize multi-layer wiring process, increase the degree of freedom of product design, and enhance the electrical reliability of the product.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor
  • the lead frame assembly in the semiconductor package structure of the present application no longer needs the lead portion located under the chip, it can be applied to chips with larger area and can discharge more chips, and has excellent applicability.
  • FIG. 1 is a cross-sectional view of a semiconductor package structure in the prior art.
  • FIG. 2 is a flowchart of a semiconductor packaging method according to Embodiment 1 of the present application.
  • 3A-3B are process flow diagrams of forming a protective layer and a protective layer opening on the front side of a chip to be packaged according to Embodiment 1 of the present application.
  • FIG. 4 is a schematic view of the front structure of the lead frame according to the first embodiment of the present application.
  • FIG. 5 is a schematic diagram of the front structure of the lead frame according to Embodiment 1 of the present application.
  • 6A-6M are process flow diagrams of the semiconductor packaging method proposed according to Embodiment 1 of the present application.
  • FIG. 7 is a schematic structural diagram of a semiconductor packaging structure obtained by using the above-mentioned semiconductor packaging method according to Embodiment 1 of the present application.
  • FIG. 8A is a schematic diagram of front connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 8B is a schematic diagram of the backside connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 9 is a schematic structural diagram of another embodiment of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • 10A-10E are process flow diagrams of a semiconductor packaging method in Embodiment 2 according to the present application.
  • Words like "connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words like “upper” and/or “lower” are for convenience of description and are not limited to one position or one spatial orientation.
  • Words like “upper” and/or “lower” are for convenience of description and are not limited to one position or one spatial orientation.
  • the singular forms “a,” “the,” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term “and/or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
  • This embodiment provides a semiconductor packaging method and a semiconductor packaging structure.
  • FIG. 2 is a flowchart of the semiconductor packaging method proposed in this embodiment. As shown in FIG. 2, the semiconductor packaging method includes the following steps:
  • Step 100 Mount the lead frame and a plurality of chips to be packaged on the carrier board.
  • the front side of the chip to be packaged faces the carrier board;
  • the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction; a plurality of the chips to be packaged are located in the hollow area .
  • Step 200 Cover the chip to be packaged, the lead frame and the exposed part of the carrier with an encapsulation layer, and fill the hollow area of the lead frame to form an encapsulation structure.
  • the encapsulation structure includes a first surface and a second surface disposed opposite to each other; the front surface of the chip to be packaged and the first surface of the lead frame are exposed on the first surface.
  • Step 300 forming a first redistribution structure on the first surface of the encapsulation structure, and the first redistribution structure is electrically connected to the front surface of the to-be-packaged chip and the first surface of the lead frame; and forming a second redistribution structure on the second surface of the encapsulation structure, the second redistribution structure and the back surface of the chip to be packaged and the second surface of the lead frame disposed opposite to the first surface All electrical connections.
  • the semiconductor packaging method of this embodiment improves the thinning of the product and can enhance the electrical reliability of the product.
  • the thickness is greatly reduced. the thickness of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. electrical reliability.
  • a plurality of copper pillars are provided, since a plurality of independent copper pillars are to be provided, not only the positioning process is complicated, but also the positioning errors will be accumulated; but in this application, since the lead frame is integrally formed, the lead Each part of the frame is fixed on the carrier plate at one time and is encapsulated in the encapsulating structural member correspondingly, which greatly saves the production cost and improves the overall production efficiency.
  • the lead frame assembly in the semiconductor package structure of the present embodiment no longer needs the lead portion under the chip, so it can be applied to a chip with a larger area, and can discharge more chips , with excellent applicability.
  • a protective layer 12 is formed on the front surface of the chip 11 to be packaged.
  • the chip 11 to be packaged includes a front surface 11a provided with solder pads, and a back surface 11b disposed opposite to the front surface 11a.
  • the back surface 11b is provided with a metal layer (not marked in the figure), so that the front surface 11a and the back surface 11b of the chip to be packaged 11 are electrically connected. lead out.
  • protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the bonding pads on the front side 11 a of the chip 11 to be packaged, and each protective layer opening 121 is at least opposite to the bonding pads or the bonding pads of the chip 11 to be packaged.
  • the lines drawn from the bonding pads enable the bonding pads on the front side of the chip 11 to be packaged or the lines drawn from the bonding pads to be exposed from the protective layer opening 121 .
  • the specific structure of the lead frame 20 in this embodiment can be shown in FIG. 4 and FIG. 5 .
  • Each final semiconductor package structure after packaging and dicing corresponds to one lead frame 20 .
  • the lead frame 20 constitutes the lead frame 2 , and the lead frame 2 may also be constituted by only one lead frame 20 .
  • Each lead frame 20 includes a frame body 22, and the frame body 22 is provided with a hollow area 21 extending through the frame body 22 along the thickness direction T in the frame body 22. As shown in FIG.
  • the number of hollow regions 21 of the lead frame 20 may be one or more.
  • the lead frame 20 also includes a connection portion 24 .
  • Two ends of the connecting portion 24 are respectively connected to two opposite sides of the frame body 22 , and the connecting portion 24 separates the hollow regions 21 into a plurality of hollow regions 21 , that is, adjacent hollow regions 21 are separated by the connecting portions 24 .
  • connecting portions 24 For example, adjacent hollow regions 21 in the same lead frame 20 are separated by connecting portions 24 .
  • the inner space of each lead frame 20 is separated into two hollow regions 21 by the connecting portion 24 , that is, the number of hollow regions 21 provided in each lead frame 20 is Two, two hollow regions 21 are separated by connecting parts 24 .
  • the connecting portion 24 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇ .
  • the first part 241 and the second part 243 are respectively connected to opposite sides of the frame body 22 .
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are substantially parallel to each other, so that the structure of the connecting portion 24 is more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 is more compact.
  • the lead frame 20 also includes a number of mutually isolated edge portions 23 .
  • One end of the edge portion 23 is connected to the frame body 22 , and the other end extends toward the hollow area 21 .
  • Each hollow area 21 is provided with a plurality of mutually isolated edge portions 23 .
  • the edge portion 23 includes a main body 231 and a support portion 232 , and the support portion 232 is connected between the frame body 22 and the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the chips to be packaged respectively located in the different hollow regions can be electrically connected through the connecting portion.
  • the front side of one of the chips to be packaged and the back side of the other chip to be packaged can be electrically connected; or, the front side of one of the chips to be packaged and the front side of the other chip to be packaged can be electrically connected;
  • the backside of the chip to be packaged is in electrical communication with the backside of another chip to be packaged.
  • each lead frame 20 includes a first surface 20 a and a second surface 20 b disposed opposite to each other along the thickness direction T. As shown in FIG. The first surface 20a is provided with a number of first electrical connection points, and the second surface 20b is provided with a number of second electrical connection points.
  • step 100 as shown in FIG. 6A , the chip to be packaged 11 and the lead frame 20 with the protective layer 12 formed on the front side are mounted on the carrier board 3 through the adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the lead frame 20 is provided with a hollow area 21 , the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
  • the thickness of the lead frame 20 is approximately equal to the thickness of the chip to be packaged.
  • the thickness of the chip to be packaged refers to the distance from the backside of the chip to be packaged 11 to the surface of the carrier board 3 when the chip to be packaged 11 is mounted on the carrier board 3 .
  • the thinning of the final semiconductor package structure 1 can be achieved in the above manner.
  • the thickness of the lead frame 20 may be greater than that of the chip to be packaged, so as to protect the chip 11 to be packaged.
  • the adhesive layer is used to bond the chip to be packaged 11 and the lead frame 20 to the carrier board 3 .
  • the adhesive layer can be made of an easily peelable material, so that the carrier board 3 is peeled off from the chip 11 to be packaged and the lead frame 20 in a subsequent process.
  • a thermally separable material that can be debonded by heating can be used.
  • the adhesive layer may adopt a two-layer structure, a thermal separation material layer and a die attach layer.
  • the thermal separation material layer is pasted on the carrier board 3, and will lose its viscosity when heated, and then can be peeled off from the carrier board 3; and the chip attachment layer adopts a sticky material layer, which can be used to paste the to-be-packaged chip 11. .
  • the chip attach layer thereon may be removed by chemical cleaning.
  • an adhesive layer may be formed on the carrier board 3 by means of lamination, printing, or the like.
  • the number of chips 11 to be packaged may be multiple.
  • the number of chips 11 to be packaged can be adjusted according to design requirements.
  • the lead frame 20 is integrally formed, that is, the frame body 22 , the connection portion 24 , and the edge portion 23 of the lead frame are integrally formed, the frame body 22 , the connection portion 24 , the edge portion 23 , etc. of the lead frame are integrally formed.
  • Each part of the machine is fixed on the carrier board at one time, which greatly saves the production cost and improves the overall production efficiency.
  • step 200 as shown in FIG. 6B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) above), and fill in the hollow area 21 of the lead frame 20 to form the encapsulation structure 10 for encapsulating the chip to be packaged 11 and the lead frame 20 .
  • the encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.
  • the encapsulation structure 10 includes a first surface 10a and a second surface 10b which are disposed opposite to each other. Wherein, the second surface 10 b of the encapsulation structure 10 is disposed opposite to the carrier plate 3 , is substantially flat, and is parallel to the surface of the carrier plate 3 .
  • the first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be encapsulated, and the first surface 20 a of the lead frame 20 .
  • the encapsulation layer 14 may be formed by laminating epoxy resin film or Molding film, or may be formed by injection molding or compression molding of epoxy resin compound. molding) or transfer molding (Transfer molding).
  • the packaging method further includes mounting a first support plate 41 on the second surface 10 b of the packaging structure 10 .
  • the first support plate 41 is mounted on at least a partial area of the second surface 10 b of the encapsulation structure 10 . As shown in FIG. 6C , in one embodiment, the first support plate 41 is mounted on the second surface 10 b of the encapsulation structure 10 , and the first support plate 41 covers the second surface of the encapsulation structure 10 All areas of 10b.
  • the material strength of the first support plate 41 is greater than the material strength of the encapsulation layer 14, so that the mechanical strength of the encapsulation structure during the encapsulation process can be effectively improved and guaranteed, and the adverse effects caused by the deformation of each structure can be effectively suppressed, thereby improving the product encapsulation quality. Effect.
  • the first support plate 41 may also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, or the like.
  • the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
  • the first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 .
  • the adhesive layer between the carrier board 3 and the chip to be packaged 11 and the lead frame 20 is a thermal separation film
  • the adhesive layer can be heated to reduce the viscosity after being heated, and then the carrier board can be peeled off. 3.
  • the carrier plate 3 can also be directly mechanically peeled off.
  • the first surface 10 a of the encapsulation structure 10 facing the carrier 3 , the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 are exposed.
  • the first encapsulation structure 10 is obtained, which includes the chip to be packaged 11 , the lead frame 20 , and the encapsulation layer 14 that encapsulates the chip to be packaged 11 and the lead frame 20 .
  • rewiring and the like may be performed according to the actual situation, so that the chip 11 to be encapsulated is electrically connected to the outside world.
  • the surface of the protective layer 12 is exposed. At this time, it is possible that the chip attach layer in the adhesive layer still exists on the surface of the protective layer 12 .
  • the protective layer 12 can also protect the surface of the chip 11 to be packaged from damage when the chip attach layer is chemically removed. After the adhesive layer is completely removed, if the encapsulation material has penetrated before, chemical cleaning or grinding can be used to make the surface smooth to facilitate subsequent wiring. If there is no protective layer 12 , the surface of the chip to be packaged 11 cannot be processed by chemical means or grinding, so as to avoid damaging the circuit on the front side of the chip to be packaged 11 .
  • the step of attaching the first support plate 41 may also be performed after peeling off the carrier plate 3 .
  • a first redistribution structure 50 is formed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged, and is electrically connected to the first electrical connection point of the first surface 20 a of the lead frame 20 .
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front surface of the chip 11 to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the protective layer opening 121 since the protective layer opening 121 has been formed on the protective layer 12 , the protective layer opening 121 can be directly seen at least when the first redistribution layer 51 is formed, so the alignment can be more accurate when the first redistribution structure 50 is formed. .
  • a conductive medium may be filled in the protective layer openings 121 of the chip 11 to be packaged at the same time to form the conductive pillars 52 , that is, the first redistribution layer 51 and the conductive layers are formed in the same conductive layer forming process.
  • the conductive pillars 52 form a vertical connection structure in the protective layer opening 121, and the bonding pads on the front side 11a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51.
  • a dielectric layer 60 is formed.
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • the packaging method further includes peeling off the first support plate 41 .
  • the first support plate 41 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
  • the packaging method further includes mounting the second support plate 42 on a surface of the dielectric layer 60 away from the encapsulation structure 10 .
  • the second support plate 42 is mounted on at least a partial area of the side of the dielectric layer 60 away from the encapsulation structure 10 . As shown in FIG. 6I , in one embodiment, the second support plate 42 is mounted on the entire area of the side of the dielectric layer 60 away from the encapsulation structure 10 .
  • the material strength of the second support plate 42 is greater than that of the dielectric layer 60 , so that the mechanical strength of the packaging structure during the packaging process can be effectively improved and guaranteed, and the adverse effects of structural deformation can be effectively suppressed, thereby improving the effect of product packaging.
  • the second support plate 42 may also be formed on the dielectric layer 60 by spraying, printing, coating, or the like.
  • the step of attaching the second support plate 42 may also be performed before peeling off the first support plate 41 .
  • the packaging method further includes grinding the second surface 10b of the encapsulation structure 10 , so as to reduce the thickness of the encapsulating structural member 10 . Preferably, it is thinned to expose the metal layer of the backside 11b of the chip 11 to be packaged.
  • the thickness of the lead frame 20 may be equal to or slightly larger than the thickness of the chip to be packaged.
  • the thickness of the lead frame 20 is also reduced to expose the thickness of the chip to be packaged 11 . part.
  • the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, when the encapsulation structure 10 is thinned to expose the back surface 11 b of the chip to be packaged 11 , the second surface 20 b of the lead frame 20 is also exposed at the same time.
  • the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, so that the process of grinding the second surface 10b of the encapsulation structure 10 can be effectively reduced.
  • a second redistribution structure 70 is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 to be packaged and the second electrical connection point of the second surface 20 b of the lead frame 20 .
  • the second redistribution structure 70 includes at least one second redistribution layer 71 .
  • the second redistribution structure 70 includes a second redistribution layer 71 .
  • the second redistribution structure 70 can also include multiple layers of second redistribution layers 71 according to design requirements, that is, repeated redistribution is performed on the backside of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the thickness of the redistribution structure (including the second redistribution structure 70) is much smaller than the thickness of the lead frame 30' in the prior art (as in FIG. 1).
  • the general rewiring structure is 15um-45um
  • the lead frame 30' is generally 150um-450um. Therefore, the rewiring structure not only realizes the function of wiring, but also improves the thinning of the product.
  • the lead frame 20 since the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 to be packaged is realized, that is, the lead frame 20 communicates with each other.
  • the first redistribution structure 50 located on the first surface 10a of the encapsulation structure 10 and the second redistribution structure 70 located on the second surface 10b of the encapsulation structure 10 are shown.
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction.
  • the layout of the rewiring structure is more free and flexible.
  • the electrical lead-out of the front side 11a of the chip 11 to be packaged is realized by the electrical connection of the pads 111 on the front side 11a of the chip 11 to be packaged, the first rewiring structure 50 , the lead frame 20 and the second rewiring structure 70 in sequence.
  • the electrical lead-out of the back surface 11b of the chip 11 to be packaged is realized by directly electrically connecting with the second redistribution structure 70; the interconnection of different chips 11 to be packaged includes the interconnection on the same surface or the interconnection on different surfaces (For example, the interconnection between the front side of one of the chips 11 to be packaged and the back side of the other chip 11 to be packaged) can be achieved through the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
  • the backside 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 are exposed on the second surface 10b of the encapsulation structure 10, so that the encapsulation structure
  • the second redistribution structure 70 formed on the second surface 10b of the component 10 is directly overlaid on the back surface 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 .
  • the orthographic projection of the chip 11 to be packaged is located within the orthographic projection of the second redistribution structure 70 , so that the backside 11 b of the chip to be packaged 11 is protected by the second redistribution structure 70 so as not to be exposed.
  • the method further includes forming a lead layer 80 on the second redistribution structure 70 , that is, forming a lead layer 80 on the side of the second redistribution structure 70 away from the encapsulation structure 10 . .
  • the orthographic projection of the pin layer 80 is located within the orthographic projection of the second redistribution structure 70 .
  • the spacing W1 between adjacent pin layers 80 is greater than the spacing W2 between adjacent second redistribution structures 70 located in the adjacent pin layers 80 , so that the final formation
  • the semiconductor package products of our company are not easy to be short-circuited, which improves the electrical performance of the products.
  • the semiconductor package structure 1 can be electrically connected to the outside through the pin layer 80 , and the next step can be installed through the pin layer 80 .
  • the material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
  • the lead layer 80 may not be included, but the lead layer is formed on the surface of other structures (such as PBC boards) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 is mounted by alignment .
  • the second support plate 42 is peeled off, as shown in FIG. 6M .
  • the second support plate 42 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
  • a step of cutting off the frame body of the lead frame 20 by means of laser or mechanical cutting is also included, and the illustration of this step is omitted.
  • a structural diagram of the formed semiconductor package structure 1 may be shown in FIG. 7 .
  • FIG. 7 it is a schematic structural diagram of a semiconductor packaging structure 1 obtained by using the above-mentioned semiconductor packaging method according to the present embodiment.
  • the semiconductor package structure 1 includes an encapsulation structure 10 , a first redistribution structure 50 and a second redistribution structure 70 .
  • the encapsulation structure 10 includes opposing first surfaces 10a and second surfaces 10b, and the encapsulation structure 10 includes a lead frame assembly (mainly corresponding to the connection portion 24 and the edge portion 23 in the lead frame 20 in the aforementioned semiconductor packaging method) , a plurality of chips 11 , and an encapsulation layer 14 for encapsulating the lead frame assembly and the plurality of chips 11 .
  • the lead frame assembly is arranged on the outer circumference of each chip 11 to define the respective accommodating spaces of the chips, the accommodating space penetrates the lead frame assembly along the thickness direction T, and a plurality of the chips 11 are located in the accommodating space, so
  • the encapsulation layer 14 is filled in the accommodating space defined by the lead frame assembly. It can be seen that the respective accommodating spaces of the plurality of chips 11 defined by the lead frame assembly may correspond to the hollow regions 21 in the lead frame 20 in the aforementioned semiconductor packaging method.
  • the number of chips 11 is plural.
  • the number of chips 11 can be adjusted according to design requirements, which is not limited here.
  • the number of chips 11 is two.
  • the number of hollow regions of the lead frame 20 may be one or more.
  • each lead frame 20 is provided with two hollow regions in number. But not limited to this, the number of hollow regions 21 can be other numbers according to design requirements.
  • the lead frame 20 also includes a connection portion 24 .
  • the connection portion 24 divides the space in the lead frame 20 into a plurality of the hollow regions.
  • the chips 11 respectively located in the different hollow regions are electrically connected through the connecting portions 24 .
  • each lead frame 20 is separated by two through the connecting portions 24 , that is, the number of hollow regions 21 provided on each lead frame 20 is two, and the two hollow regions 21 It is cut off by the connecting portion 24 .
  • the two chips 11 are respectively located in two different hollow areas.
  • the chip 11 includes a front side provided with bonding pads, and a back side 11b opposite to the front side.
  • the back side 11b is provided with a metal layer (not shown in the figure), so that both the front side 11a and the back side 11b of the chip 11 are electrically led out.
  • the front surface of the chip 11 and the first surface 20 a of the lead frame 20 are exposed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 corresponds to the front surface of the chip 11 and is formed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and is connected to the first surface of the lead frame 20 .
  • the first electrical connection point of one side 20a is electrically connected.
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip. For example, more redistribution structures and more dielectric layers can be formed in the same way, which can be adjusted according to design requirements.
  • a protective layer 12 is provided on the front surface of the chip 11 .
  • a protective layer opening 121 is formed on the protective layer 12 .
  • Conductive pillars 52 formed by filling the conductive medium are provided in the protective layer opening 121 .
  • the first redistribution layer 51 and the conductive pillar 52 may be formed in the same conductive layer forming process.
  • the second redistribution structure 70 corresponds to the back surface of the chip 11 and is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 and the second electrical connection point of the second surface 20 b of the lead frame 20 .
  • the second redistribution structure 70 includes at least one second redistribution layer 71 .
  • the second redistribution structure 70 includes a second redistribution layer 71 .
  • the second redistribution structure 70 includes multiple layers of second redistribution layers 71 , that is, repeated redistribution is performed on the backside of the chip. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 is realized, that is, the lead frame 20 is connected to the The first redistribution structure 50 on the first surface 10 a of the encapsulation structure 10 and the second redistribution structure 70 on the second surface 10 b of the encapsulation structure 10 .
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction.
  • the layout of the rewiring structure is more free and flexible.
  • the electrical lead-out of the front side 11a of the chip 11 is realized through the electrical connection of the bonding pads on the front side 11a of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70;
  • the electrical lead-out of the backside 11b is realized by being directly electrically connected to the second redistribution structure 70;
  • the interconnection of different chips 11 includes the interconnection on the same plane or the interconnection on different planes (such as the front side and the front side of one of the chips 11).
  • the interconnection of the backside of the other chip 11 can be realized by the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
  • the thickness of the lead frame 20 is approximately equal to the thickness of the chip 11 .
  • the back surface 11 b of the chip 11 and the second surface 20 b of the lead frame 20 are both exposed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 formed on the second surface 10b of the encapsulation structure 10 is directly overlaid on the back surface 11b of the chip 11 and the second surface 20b of the lead frame 20 to further reduce the overall thickness.
  • the orthographic projection of the chip 11 is located within the orthographic projection of the second redistribution structure 70 , so as to protect the back surface 11 b of the chip 11 from being exposed by the second redistribution structure 70 .
  • the encapsulation structure 10 further includes a dielectric layer 60 .
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • PBO Polybenzoxazole
  • the encapsulation structure 10 further includes a lead layer 80 , and the lead layer is located on a side of the second redistribution structure 70 away from the encapsulation structure 10 .
  • the orthographic projection of the pin layers 80 is located within the orthographic projection of the second redistribution structure 70 , that is, the spacing W1 between adjacent pin layers 80 is greater than that of the adjacent pin layers 80 .
  • the distance W2 between the adjacent second redistribution structures 70 makes it difficult to short-circuit when the finally formed semiconductor package product is soldered with tin or other materials, thereby improving the electrical performance of the product.
  • the semiconductor package structure 1 is electrically connected to the outside through the pin layer 80 , and is installed in the next step through the pin layer 80 .
  • the material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
  • the pin layer 80 may not be included, and the pin layer may be formed on the surface of other structures (such as a PCB board) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 may be mounted thereon by alignment .
  • the connecting portion 24 of the lead frame 20 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇ .
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are approximately parallel to each other, so that the structure of the connecting portion 24 can be more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 can be more compact.
  • the lead frame 20 further includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is exposed on the surface of the encapsulation structure 10, and the other end extends toward the hollow area 21; each hollow area 21 can be provided with a number of mutually isolated edge portion 23 .
  • the edge portion 23 includes a main body 231 and a supporting portion 232 . One end of the supporting portion 232 away from the main body 231 is exposed on the surface of the encapsulating structural member 10 , and the other end is connected to the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the lead frame 20 is integrally formed, positioned and encapsulated in the encapsulation structure 10, the production cost is greatly saved, and the overall production efficiency is improved.
  • FIG. 8A a schematic diagram of the front side connection of the semiconductor package structure (as shown in FIG. 8A ) and the back side are given.
  • FIG. 8B A schematic diagram of the connection (shown in Figure 8B). In the figure, only a schematic connection is made for the rewiring structure to illustrate the connection relationship.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 to realize the interconnection of the front side and the back side of the chip 11, and can also realize the double-sided interconnection of different chips 11 ( For example, the interconnection of the front side of one chip 11 and the back side of the other chip 11 ) is achieved by the electrical connection of the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , and the second redistribution structure 70 .
  • the lead frame 20 shown in FIG. 8A and FIG. 8B includes two upper and lower hollow regions 21 along the vertical direction of the paper surface, and each hollow region 21 is respectively placed with a chip 11 .
  • the front side of the chip 11 in the upper hollow area 21 is electrically connected to the connecting portion 24 and one of the edge portions 23 of the upper hollow area 21 through the first redistribution structure 50 respectively;
  • the front surface of the chip 11 in the hollow area 21 is electrically connected to the two edge portions 23 of the hollow area 21 located below through the first redistribution structure 50 respectively.
  • the backside of the chip 11 in the upper hollow region 21 is electrically connected to the other two edge portions 23 of the upper hollow region 21 through the second redistribution structure 70 ;
  • the back surface is electrically connected to the connection portion 24 through the second redistribution structure 70 . That is, the front surface of the chip 11 in the upper hollow region 21 is electrically connected to the back surface of the chip 11 in the lower hollow region 21 through the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , the second redistribution structure 70 and the lower hollow region 21 in sequence. connect.
  • the lead frame 20 extends from the first surface 10a of the encapsulation structure 10 to the second surface 10b of the encapsulation structure 10 along the thickness direction T, and includes the first portion 27 and Second part 28.
  • the width w21 of the first portion 27 is greater than the width w22 of the second portion 28 , that is, the lead frame 20 having a stepped structure in cross section is formed.
  • the relatively wide contact surface of the first portion 27 can facilitate the formation of the first redistribution structure 50 over the lead frame 20, and can provide a relatively large area of support for the first redistribution structure 50;
  • the bonding force between the lead frame 20 and the encapsulation layer 14 is enhanced and the strength of the lead layer 80 of the semiconductor package structure on the PCB is enhanced, thereby enhancing the board-level reliability performance of the product.
  • the backside of the chip 11 is not provided with a metal layer, so that the backside of the chip 11 is not electrically drawn out, and only the front side of the chip 11 needs to be electrically drawn out, that is, the second rewiring structure 70 and the backside of the chip 11 Not electrically connected.
  • the electrical connection of the front surface of the chip 11 is realized through the electrical connection of the bonding pads on the front surface 11 a of the chip 11 , the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 in sequence.
  • the electricity from the front side of the chip can be directly led to the back side of the chip through the lead frame, and the copper pillar components are no longer needed, the wiring area is increased, the multi-layer wiring process can be realized, and the freedom of product design can be increased. It increases the electrical reliability of the product; at the same time, it saves the production cost and improves the overall production efficiency.
  • the semiconductor package structure of the present embodiment improves the thinning of the product by setting the overall structure, and can enhance the electrical reliability of the product.
  • the hollow area penetrates the lead frame along the thickness direction, and a plurality of chips are located in the hollow area, which greatly reduces the thickness of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. At the same time, it saves the production cost and improves the overall production efficiency.
  • the content of the semiconductor packaging method of this embodiment is basically the same as that of the semiconductor packaging method in Embodiment 1, the difference is that in the semiconductor packaging method of this embodiment, the step of forming the protective layer 12 on the front surface of the chip 11 to be packaged It is placed after the encapsulation of the chip 11 to be packaged and the lead frame 20 is completed, that is, after the encapsulation structure 10 is formed.
  • the semiconductor packaging method of this embodiment includes:
  • step 100 as shown in FIG. 10A , the chip 11 to be packaged and the lead frame 20 are mounted on the carrier board 3 through an adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the lead frame 20 is provided with a hollow area 21 extending through the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
  • step 200 as shown in FIG. 10B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) ), and fill in the hollow area 21 of the lead frame 20 to encapsulate the chip to be packaged 11 and the lead frame 20 to form the encapsulation structure 10 .
  • the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
  • a protective layer 12 is formed on the first surface 10 a of the encapsulation structure 10 .
  • the protective layer 12 can be a transparent film layer to utilize the protective layer 12 transparency for positioning. In addition, positioning can be assisted by the lead frame 20 to improve the positional accuracy of the laser drilling.

Abstract

The present application provides a semiconductor packaging method and a semiconductor packaging structure. According to an example, the semiconductor packaging method comprises: mounting a lead frame and multiple chips to be packaged on a carrier plate, said multiple chips being located in a hollowed-out region of the lead frame; enabling a packaging layer to cover said chips, the lead frame, and an exposed portion of the carrier plate, and filling the packaging layer in the hollowed-out region, so as to form a packaging structure member; and forming a first rewiring structure on a first surface of the packaging structure member, the first rewiring structure being electrically connected to the front surfaces of said chips and a first side of the lead frame, and forming a second rewiring structure on a second surface of the packaging structure member, the second rewiring structure being electrically connected to a second side, provided opposite to the first side, of the lead frame. The semiconductor packaging structure is manufactured by the semiconductor packaging method.

Description

半导体封装方法及半导体封装结构Semiconductor packaging method and semiconductor packaging structure 技术领域technical field
本申请涉及半导体技术领域，尤其涉及一种半导体封装方法及半导体封装结构。The present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
背景技术Background technique
如图1所示，现有技术中常采用引线框30’与布线层40’配合实现两个芯片10’的双面互连封装。其中，两个芯片10’的背面通过导电胶20’贴装于引线框30’上表面实现背面电连接，布线层40’通过铜柱50’与芯片10’的正面连接。铜柱50’需要通过超声键和的方式植出，该工艺的成本极高，效率却极低。另外，将引线框30’布置在芯片10’的背面，导致所形成产品的厚度较厚，在应用于可穿戴装备或其他对产品厚度有较高要求的场景时，将受到限制。As shown in FIG. 1 , in the prior art, a lead frame 30' and a wiring layer 40' are often used to implement a double-sided interconnect package of two chips 10'. Wherein, the backsides of the two chips 10' are mounted on the upper surface of the lead frame 30' through the conductive adhesive 20' to realize the backside electrical connection, and the wiring layer 40' is connected to the front side of the chip 10' through the copper pillars 50'. The copper pillar 50' needs to be implanted by means of ultrasonic bonding, and the cost of this process is extremely high, but the efficiency is extremely low. In addition, arranging the lead frame 30' on the backside of the chip 10' results in a thicker product, which will be limited when applied to wearable equipment or other scenarios that have higher requirements on product thickness.
发明内容SUMMARY OF THE INVENTION
有鉴于此，本申请提供了一种半导体封装方法和一种半导体封装结构。In view of this, the present application provides a semiconductor packaging method and a semiconductor packaging structure.
本申请的一个方面提供半导体封装方法，其包括：将引线框与多个待封装芯片贴装于载板上，所述待封装芯片的正面朝向所述载板，所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框，多个所述待封装芯片位于所述镂空区域中；通过将包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述引线框的镂空区域内，形成包封结构件，所述包封结构件包括相对设置的第一表面和第二表面，所述待封装芯片的正面和所述引线框的第一面露出于所述包封结构件的第一表面；在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述引线框相对所述第一面设置的第二面电连接。One aspect of the present application provides a semiconductor packaging method, which includes: mounting a lead frame and a plurality of chips to be packaged on a carrier board, the front surfaces of the chips to be packaged face the carrier board, and the lead frame is provided with a hollow area , the hollow area runs through the lead frame along the thickness direction, and a plurality of the chips to be packaged are located in the hollow area; by covering the chips to be packaged, the lead frame and the carrier board with an encapsulation layer The exposed part is filled in the hollow area of the lead frame to form an encapsulation structure, the encapsulation structure includes a first surface and a second surface arranged oppositely, the front side of the chip to be packaged and all the The first surface of the lead frame is exposed on the first surface of the encapsulation structure; a first redistribution structure is formed on the first surface of the encapsulation structure, and the first redistribution structure is connected to the to-be-packaged structure The front surface of the chip and the first surface of the lead frame are electrically connected; and a second redistribution structure is formed on the second surface of the encapsulation structure, and the second redistribution structure is opposite to the lead frame. The second surface provided on the first surface is electrically connected.
本申请的第二个方面提供一种半导体封装结构，其包括：包封结构件，具有相对的第一表面和第二表面，所述包封结构件包括引线架组件、多个芯片以及用于包封所述引线架组件和所述多个所述芯片的包封层，所述引线架组件设置在各所述芯片的外周以限定所述多个芯片各自的容置空间，所述容置空间沿厚度方向贯穿所述引线架组件，所述包封层填充于所述引线架组件限定的容置空间内，所述芯片的正面和所述引线架组件的 第一面露出于所述包封结构件的第一表面；第一再布线结构，所述第一再布线结构形成于所述包封结构件的第一表面，所述第一再布线结构与所述芯片的正面以及所述引线架组件的第一面电连接；第二再布线结构，所述第二再布线结构形成于所述包封结构件的第二表面，所述第二再布线结构与所述引线架组件相对所述第一面设置的第二面电连接。A second aspect of the present application provides a semiconductor package structure including an encapsulation structure having opposing first and second surfaces, the encapsulation structure including a lead frame assembly, a plurality of chips, and a an encapsulation layer that encapsulates the lead frame assembly and the plurality of chips, the lead frame assembly is disposed on the periphery of each of the chips to define the respective accommodating spaces of the plurality of chips, and the accommodating space is The space runs through the lead frame assembly in the thickness direction, the encapsulation layer is filled in the accommodating space defined by the lead frame assembly, and the front surface of the chip and the first surface of the lead frame assembly are exposed to the package the first surface of the encapsulation structure; the first redistribution structure, the first redistribution structure is formed on the first surface of the encapsulation structure, the first redistribution structure and the front surface of the chip and the The first surface of the lead frame assembly is electrically connected; the second redistribution structure is formed on the second surface of the encapsulation structure, and the second redistribution structure is opposite to the lead frame assembly The second surface provided on the first surface is electrically connected.
本申请实施例提供的上述半导体封装方法及半导体封装结构，通过引线框和双面重布线互连工艺，实现了芯片的双面互连封装，提升了产品的薄型化，可增强产品的电学信赖性。The above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application realize the double-sided interconnection packaging of the chip through the lead frame and the double-sided re-wiring interconnection process, improve the thinning of the product, and enhance the electrical reliability of the product. sex.
具体的，通过在引线框设置沿厚度方向贯穿所述引线框的镂空区域，并将多个待封装芯片位于所述镂空区域中，即，将待封装芯片嵌入在引线框中，大大地减薄了产品的厚度，有效实现了产品轻薄化。Specifically, by arranging a hollow area in the lead frame that runs through the lead frame in the thickness direction, and placing a plurality of chips to be packaged in the hollow area, that is, embedding the chips to be packaged in the lead frame, the thickness is greatly reduced. The thickness of the product is reduced, and the thinning of the product is effectively realized.
本申请中的技术方案直接通过引线框实将芯片的正面的电气引至芯片的背面后再引出，而不再需要铜柱部件，提升了布线面积，可实现多层布线工艺，增加了产品设计的自由度，增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，且定位误差会产生累加；而在本申请中，由于引线框是一体成型，引线框上的各部分是一次定位就固定在载板上并包封在包封结构件中，大大地节省了生产成本，提高了整体生产效率。The technical solution in this application directly leads the electricity from the front side of the chip to the back side of the chip through the lead frame, and no longer needs copper pillar components, improves the wiring area, can realize multi-layer wiring process, and increases product design. The degree of freedom increases the electrical reliability of the product; at the same time, the production cost is saved and the overall production efficiency is improved. In the prior art, if a plurality of copper pillars are provided, since multiple independent copper pillars are to be provided, not only the positioning process is complicated, but also the positioning errors will accumulate; in the present application, since the lead frame is integrally formed, the lead frame Each part of the upper part is fixed on the carrier board and encapsulated in the encapsulation structural member at one time, which greatly saves the production cost and improves the overall production efficiency.
其中，当芯片为MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)型芯片时，可以直接通过引线框实现芯片的双面互连，而不再需要铜柱部件，从而提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，增强产品的电学信赖性。Among them, when the chip is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor) type chip, the double-sided interconnection of the chip can be realized directly through the lead frame, without the need for copper pillar components. , so as to increase the interconnection area, realize multi-layer wiring process, increase the degree of freedom of product design, and enhance the electrical reliability of the product.
通过将多个待封装芯片设置于引线框的镂空区域中，并将待封装芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。By arranging a plurality of chips to be packaged in the hollow area of the lead frame, and encapsulating the chips to be packaged together with the lead frame, the use of conductive glue to fix the chips is avoided, thereby improving the introduction efficiency.
本申请的半导体封装结构中的引线架组件，由于不再需要位于芯片下方的引线部分，从而能够适用于面积更大的芯片，并可以排放更多的芯片，具有优异的适用性。Since the lead frame assembly in the semiconductor package structure of the present application no longer needs the lead portion located under the chip, it can be applied to chips with larger area and can discharge more chips, and has excellent applicability.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.
附图说明Description of drawings
图1为现有技术中的半导体封装结构的剖面图。FIG. 1 is a cross-sectional view of a semiconductor package structure in the prior art.
图2是根据本申请的实施例1提出的半导体封装方法的流程图。FIG. 2 is a flowchart of a semiconductor packaging method according to Embodiment 1 of the present application.
图3A-图3B是根据本申请的实施例1提出的在待封装芯片正面形成保护层及保护层开口的工艺流程图。3A-3B are process flow diagrams of forming a protective layer and a protective layer opening on the front side of a chip to be packaged according to Embodiment 1 of the present application.
图4是根据本申请的实施例1提出的引线框架的正面结构示意图。FIG. 4 is a schematic view of the front structure of the lead frame according to the first embodiment of the present application.
图5是根据本申请的实施例1提出的引线框的正面结构示意图。FIG. 5 is a schematic diagram of the front structure of the lead frame according to Embodiment 1 of the present application.
图6A-图6M是根据本申请的实施例1提出的中半导体封装方法的工艺流程图。6A-6M are process flow diagrams of the semiconductor packaging method proposed according to Embodiment 1 of the present application.
图7是根据本申请的实施例1提出的利用上述半导体封装方法得到的半导体封装结构的结构示意图。FIG. 7 is a schematic structural diagram of a semiconductor packaging structure obtained by using the above-mentioned semiconductor packaging method according to Embodiment 1 of the present application.
图8A是根据本申请的实施例1提出的半导体封装结构的正面连接的示意图。FIG. 8A is a schematic diagram of front connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
图8B是根据本申请的实施例1提出的半导体封装结构的背面连接的示意图。8B is a schematic diagram of the backside connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
图9是根据本申请的实施例1提出的半导体封装结构的另一实施方式的结构示意图。FIG. 9 is a schematic structural diagram of another embodiment of the semiconductor package structure proposed according to Embodiment 1 of the present application.
图10A-图10E是根据本申请的实施例2中半导体封装方法的工艺流程图。10A-10E are process flow diagrams of a semiconductor packaging method in Embodiment 2 according to the present application.
具体实施方式detailed description
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。事实上，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Indeed, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性 的连接，不管是直接的还是间接的。“上”和/或“下”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Words like "a" or "an" used in the specification and claims of this application also do not denote a quantitative limitation, but rather denote the presence of at least one. "Plurality" means two or more. Words like "include" or "include" mean that the elements or items appearing before "including" or "including" cover the elements or items listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words like "upper" and/or "lower" are for convenience of description and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
实施例1Example 1
本实施例提供一种半导体封装方法及半导体封装结构。This embodiment provides a semiconductor packaging method and a semiconductor packaging structure.
图2是本实施例提出的半导体封装方法的流程图。如图2所示，所述半导体封装方法包括下述步骤：FIG. 2 is a flowchart of the semiconductor packaging method proposed in this embodiment. As shown in FIG. 2, the semiconductor packaging method includes the following steps:
步骤100：将引线框与多个待封装芯片贴装于载板上。其中，所述待封装芯片的正面朝向所述载板；所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框；多个所述待封装芯片位于所述镂空区域中。Step 100: Mount the lead frame and a plurality of chips to be packaged on the carrier board. The front side of the chip to be packaged faces the carrier board; the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction; a plurality of the chips to be packaged are located in the hollow area .
步骤200：通过包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述引线框的镂空区域内，形成包封结构件。其中，所述包封结构件包括相对设置的第一表面和第二表面；所述待封装芯片的正面和所述引线框的第一面露出于所述第一表面。Step 200: Cover the chip to be packaged, the lead frame and the exposed part of the carrier with an encapsulation layer, and fill the hollow area of the lead frame to form an encapsulation structure. Wherein, the encapsulation structure includes a first surface and a second surface disposed opposite to each other; the front surface of the chip to be packaged and the first surface of the lead frame are exposed on the first surface.
步骤300：在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述待封装芯片的背面以及所述引线框相对所述第一面设置的第二面均电连接。Step 300 : forming a first redistribution structure on the first surface of the encapsulation structure, and the first redistribution structure is electrically connected to the front surface of the to-be-packaged chip and the first surface of the lead frame; and forming a second redistribution structure on the second surface of the encapsulation structure, the second redistribution structure and the back surface of the chip to be packaged and the second surface of the lead frame disposed opposite to the first surface All electrical connections.
本实施例的半导体封装方法提升了产品的薄型化，可增强产品的电学信赖性。The semiconductor packaging method of this embodiment improves the thinning of the product and can enhance the electrical reliability of the product.
具体的，通过在引线框设置沿厚度方向贯穿所述引线框的镂空区域，并将多个待封装芯片位于所述镂空区域中，即，将待封装芯片嵌入在引线框中，大大地减薄了产品的厚度。Specifically, by arranging a hollow area in the lead frame that runs through the lead frame in the thickness direction, and placing a plurality of chips to be packaged in the hollow area, that is, embedding the chips to be packaged in the lead frame, the thickness is greatly reduced. the thickness of the product.
本实施例中的技术方案直接通过引线框实现芯片的双面互连，而不再需要铜柱部件，提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，增强产品的电学信赖性。现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，而且定位误差会产生累加；而在本申请中，由于引线框是一体成型，因此引线框上的各部分是一次定位就固定在载板上并相应包封在包封结构件中，大大地节省了生 产成本，提高了整体生产效率。The technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. electrical reliability. In the prior art, if a plurality of copper pillars are provided, since a plurality of independent copper pillars are to be provided, not only the positioning process is complicated, but also the positioning errors will be accumulated; but in this application, since the lead frame is integrally formed, the lead Each part of the frame is fixed on the carrier plate at one time and is encapsulated in the encapsulating structural member correspondingly, which greatly saves the production cost and improves the overall production efficiency.
通过将多个待封装芯片设置于引线框的镂空区域中，并将待封装芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。By arranging a plurality of chips to be packaged in the hollow area of the lead frame, and encapsulating the chips to be packaged together with the lead frame, the use of conductive glue to fix the chips is avoided, thereby improving the introduction efficiency.
本实施例的半导体封装结构中的引线架组件，相对于现有技术中的引线框，由于不再需要位于芯片下方的引线部分，能够适用于面积更大的芯片，并可以排放更多的芯片，具有优异的适用性。Compared with the lead frame in the prior art, the lead frame assembly in the semiconductor package structure of the present embodiment no longer needs the lead portion under the chip, so it can be applied to a chip with a larger area, and can discharge more chips , with excellent applicability.
可选的，在步骤100前，如图3A所示，在待封装芯片11的正面形成保护层12。待封装芯片11包括设有焊垫的正面11a、以及相对于正面11a设置的背面11b，背面11b设有金属层(图中未标示)，从而待封装芯片11的正面11a及背面11b均有电气引出。Optionally, before step 100, as shown in FIG. 3A, a protective layer 12 is formed on the front surface of the chip 11 to be packaged. The chip 11 to be packaged includes a front surface 11a provided with solder pads, and a back surface 11b disposed opposite to the front surface 11a. The back surface 11b is provided with a metal layer (not marked in the figure), so that the front surface 11a and the back surface 11b of the chip to be packaged 11 are electrically connected. lead out.
如图3B所示，在保护层12上与待封装芯片11的正面11a的焊垫相对应的位置处形成保护层开口121，每个保护层开口121至少对位于待封装芯片11的焊垫或者从焊垫引出的线路，使得待封装芯片11正面的焊垫或者从焊垫引出的线路能够从保护层开口121暴露出来。As shown in FIG. 3B , protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the bonding pads on the front side 11 a of the chip 11 to be packaged, and each protective layer opening 121 is at least opposite to the bonding pads or the bonding pads of the chip 11 to be packaged. The lines drawn from the bonding pads enable the bonding pads on the front side of the chip 11 to be packaged or the lines drawn from the bonding pads to be exposed from the protective layer opening 121 .
本实施例中的引线框20的具体结构可如图4和图5所示，每一个完成封装后且进行切割后的最终半导体封装结构对应一个引线框20，多个呈阵列排列的相互连接的引线框20组成引线框架2，引线框架2也可以仅由一个引线框20组成。The specific structure of the lead frame 20 in this embodiment can be shown in FIG. 4 and FIG. 5 . Each final semiconductor package structure after packaging and dicing corresponds to one lead frame 20 . The lead frame 20 constitutes the lead frame 2 , and the lead frame 2 may also be constituted by only one lead frame 20 .
每一引线框20均包括框体22，框体22内设有沿厚度方向T贯穿框体22的镂空区域21。引线框20的镂空区域21的数量可以为一个或者多个。Each lead frame 20 includes a frame body 22, and the frame body 22 is provided with a hollow area 21 extending through the frame body 22 along the thickness direction T in the frame body 22. As shown in FIG. The number of hollow regions 21 of the lead frame 20 may be one or more.
引线框20还包括连接部24。连接部24的两端分别与框体22相对的两侧连接，且连接部24将镂空区域21间隔为多个，即，相邻的镂空区域21通过连接部24隔断。The lead frame 20 also includes a connection portion 24 . Two ends of the connecting portion 24 are respectively connected to two opposite sides of the frame body 22 , and the connecting portion 24 separates the hollow regions 21 into a plurality of hollow regions 21 , that is, adjacent hollow regions 21 are separated by the connecting portions 24 .
例如，在同一引线框20内的相邻的镂空区域21之间通过连接部24隔断。具体的，在本实施例中，如图5所示，每一引线框20内空间通过连接部24间隔为两个镂空区域21，即，每一引线框20设有的镂空区域21的数量为两个，两个镂空区域21通过连接部24隔断。For example, adjacent hollow regions 21 in the same lead frame 20 are separated by connecting portions 24 . Specifically, in this embodiment, as shown in FIG. 5 , the inner space of each lead frame 20 is separated into two hollow regions 21 by the connecting portion 24 , that is, the number of hollow regions 21 provided in each lead frame 20 is Two, two hollow regions 21 are separated by connecting parts 24 .
连接部24包括依次连接的第一部分241、中间部分242和第二部分243。其中，第一部分241与中间部分242形成有第一夹角α，第二部分243与中间部分242形成有第二夹角β。第一部分241与第二部分243分别与框体22相对的两侧连接。这样，通过设置连接部24的具体结构，能够通过第一部分241和第二部分243实现更大的连接面积。较佳的，第一夹角α与第二夹角β均约等于90度，以使得第一部分241与第二部 分243大致相互平行，这样，连接部24的结构更为稳定。较佳的，第一部分241远离连接部24的一端与第二部分243远离连接部24的一端，均位于连接部24的同一侧，这样，连接部24的结构更为紧凑。The connecting portion 24 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence. The first portion 241 and the middle portion 242 form a first angle α, and the second portion 243 and the middle portion 242 form a second angle β. The first part 241 and the second part 243 are respectively connected to opposite sides of the frame body 22 . In this way, by setting the specific structure of the connection portion 24 , a larger connection area can be achieved through the first portion 241 and the second portion 243 . Preferably, the first included angle α and the second included angle β are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are substantially parallel to each other, so that the structure of the connecting portion 24 is more stable. Preferably, one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 is more compact.
引线框20还包括若干相互隔离的边缘部23。其中，边缘部23的一端与框体22连接，另一端向镂空区域21延伸。每一镂空区域21内均设有若干相互隔离的边缘部23。具体的，边缘部23包括主体231和支撑部232，支撑部232连接于框体22和主体231之间。支撑部232的数量可以是一个，也可以是多个。当支撑部232的数量是多个时，多个支撑部232间隔设置。主体231可以是方形、条形或者L字形。较佳的，主体231为L字形的边缘部23设置于镂空区域21中远离连接部24的一角部。The lead frame 20 also includes a number of mutually isolated edge portions 23 . One end of the edge portion 23 is connected to the frame body 22 , and the other end extends toward the hollow area 21 . Each hollow area 21 is provided with a plurality of mutually isolated edge portions 23 . Specifically, the edge portion 23 includes a main body 231 and a support portion 232 , and the support portion 232 is connected between the frame body 22 and the main body 231 . The number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals. The main body 231 may be square, bar-shaped or L-shaped. Preferably, the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
进一步，分别位于不同的所述镂空区域中的所述待封装芯片可通过所述连接部进行电连接。例如，可以将其中一待封装芯片的正面与另一待封装芯片的背面进行电气连通；或者，将其中一待封装芯片的正面与另一待封装芯片的正面进行电气连通；或者，将其中一待封装芯片的背面与另一待封装芯片的背面进行电气连通。Further, the chips to be packaged respectively located in the different hollow regions can be electrically connected through the connecting portion. For example, the front side of one of the chips to be packaged and the back side of the other chip to be packaged can be electrically connected; or, the front side of one of the chips to be packaged and the front side of the other chip to be packaged can be electrically connected; The backside of the chip to be packaged is in electrical communication with the backside of another chip to be packaged.
如图6A所示，每一引线框20沿厚度方向T包括相对设置的第一面20a和第二面20b。其中，第一面20a上设有若干第一电连接点，第二面20b上设有若干第二电连接点。As shown in FIG. 6A , each lead frame 20 includes a first surface 20 a and a second surface 20 b disposed opposite to each other along the thickness direction T. As shown in FIG. The first surface 20a is provided with a number of first electrical connection points, and the second surface 20b is provided with a number of second electrical connection points.
在步骤100中，如图6A所示，将正面形成保护层12的待封装芯片11和引线框20通过粘接层贴装在载板3上。其中，待封装芯片11的背面朝上，正面朝向载板3。引线框20设有镂空区域21，镂空区域21沿厚度方向T贯穿引线框20，多个待封装芯片11位于镂空区域21中。In step 100 , as shown in FIG. 6A , the chip to be packaged 11 and the lead frame 20 with the protective layer 12 formed on the front side are mounted on the carrier board 3 through the adhesive layer. The backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 . The lead frame 20 is provided with a hollow area 21 , the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
在本实施例中，引线框20的厚度大致等于待封装芯片的厚度。其中，待封装芯片的厚度是指将待封装芯片11贴装在载板3上时，待封装芯片11的背面到载板3的表面的距离。通过以上方式可实现最终的半导体封装结构1的薄型化。可选的，引线框20的厚度可以大于待封装芯片的厚度，以还能够对待封装芯片11起到保护作用。In this embodiment, the thickness of the lead frame 20 is approximately equal to the thickness of the chip to be packaged. The thickness of the chip to be packaged refers to the distance from the backside of the chip to be packaged 11 to the surface of the carrier board 3 when the chip to be packaged 11 is mounted on the carrier board 3 . The thinning of the final semiconductor package structure 1 can be achieved in the above manner. Optionally, the thickness of the lead frame 20 may be greater than that of the chip to be packaged, so as to protect the chip 11 to be packaged.
粘接层用以将待封装芯片11和引线框20粘结于载板3。粘接层可采用易剥离的材料，以便在后续工序中，将载板3和待封装芯片11和引线框20剥离开来。例如可采用通过加热能够使其失去粘性的热分离材料。The adhesive layer is used to bond the chip to be packaged 11 and the lead frame 20 to the carrier board 3 . The adhesive layer can be made of an easily peelable material, so that the carrier board 3 is peeled off from the chip 11 to be packaged and the lead frame 20 in a subsequent process. For example, a thermally separable material that can be debonded by heating can be used.
在其他实施例中，粘接层可采用两层结构，热分离材料层和芯片附着层。其中，热分离材料层粘贴在载板3上，在加热时会失去黏性，进而能够从载板3上剥离下来；而芯片附着层采用具有粘性的材料层，可以用于粘贴待封装芯片11。待封装芯片11从载 板3剥离开来后，可以通过化学清洗方式去除其上的芯片附着层。在一实施例中，可通过层压、印刷等方式，在载板3上形成粘接层。In other embodiments, the adhesive layer may adopt a two-layer structure, a thermal separation material layer and a die attach layer. Among them, the thermal separation material layer is pasted on the carrier board 3, and will lose its viscosity when heated, and then can be peeled off from the carrier board 3; and the chip attachment layer adopts a sticky material layer, which can be used to paste the to-be-packaged chip 11. . After the packaged chip 11 is peeled off from the carrier board 3, the chip attach layer thereon may be removed by chemical cleaning. In one embodiment, an adhesive layer may be formed on the carrier board 3 by means of lamination, printing, or the like.
待封装芯片11的数量可为多个。待封装芯片11的数量根据设计要求可以调整。The number of chips 11 to be packaged may be multiple. The number of chips 11 to be packaged can be adjusted according to design requirements.
如前所述，由于引线框20是一体成型，即引线框的框体22、连接部24、和边缘部23为一体成型，因此引线框的框体22、连接部24、和边缘部23等的各部分是一次定位就固定在载板上，从而大大地节省了生产成本，提高了整体生产效率。As described above, since the lead frame 20 is integrally formed, that is, the frame body 22 , the connection portion 24 , and the edge portion 23 of the lead frame are integrally formed, the frame body 22 , the connection portion 24 , the edge portion 23 , etc. of the lead frame are integrally formed. Each part of the machine is fixed on the carrier board at one time, which greatly saves the production cost and improves the overall production efficiency.
在步骤200中，如图6B所示，通过将包封层14覆盖在整个载板3上(即，将包封层14覆盖在待封装芯片11片、引线框20以及载板3露出的部分上)，且填充于引线框20的镂空区域21内，可形成对待封装芯片11和引线框20进行包封的包封结构件10。包封结构件10为一平板结构，在将载板3剥离后，能够继续在该平板结构上进行再布线和封装。In step 200 , as shown in FIG. 6B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) above), and fill in the hollow area 21 of the lead frame 20 to form the encapsulation structure 10 for encapsulating the chip to be packaged 11 and the lead frame 20 . The encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.
包封结构件10包括相对设置的第一表面10a和第二表面10b。其中，包封结构件10的第二表面10b与载板3相对设置，基本上呈平板状，且与载板3的表面平行。包封结构件10的第一表面10a露出有待封装芯片11的正面的保护层12、以及引线框20的第一表面20a。The encapsulation structure 10 includes a first surface 10a and a second surface 10b which are disposed opposite to each other. Wherein, the second surface 10 b of the encapsulation structure 10 is disposed opposite to the carrier plate 3 , is substantially flat, and is parallel to the surface of the carrier plate 3 . The first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be encapsulated, and the first surface 20 a of the lead frame 20 .
在一实施例中，包封层14可采用层压环氧树脂膜或Molding film(塑封膜)的方式形成，也可以通过对环氧树脂化合物进行注塑成型(Injection molding)、压模成型(Compression molding)或转移成型(Transfer molding)的方式形成。In one embodiment, the encapsulation layer 14 may be formed by laminating epoxy resin film or Molding film, or may be formed by injection molding or compression molding of epoxy resin compound. molding) or transfer molding (Transfer molding).
可选的，在进入步骤300前，如图6C所示，所述封装方法还包括在包封结构件10的第二表面10b贴装第一支撑板41。Optionally, before entering step 300 , as shown in FIG. 6C , the packaging method further includes mounting a first support plate 41 on the second surface 10 b of the packaging structure 10 .
第一支撑板41至少贴装在包封结构件10的第二表面10b的至少部分区域。如图6C所示，在一实施例中，在包封结构件10的第二表面10b之上贴装第一支撑板41，且第一支撑板41覆盖在包封结构件10的第二表面10b的全部区域。The first support plate 41 is mounted on at least a partial area of the second surface 10 b of the encapsulation structure 10 . As shown in FIG. 6C , in one embodiment, the first support plate 41 is mounted on the second surface 10 b of the encapsulation structure 10 , and the first support plate 41 covers the second surface of the encapsulation structure 10 All areas of 10b.
第一支撑板41的材料强度大于所述包封层14的材料强度，使得能够有效提高并保证封装过程中封装结构的机械强度，有效抑制各结构变形带来的不利影响，从而提高产品封装的效果。在另一些实施例中，第一支撑板41也可通过喷涂(Spraying)、印刷(Printing)、涂覆(Coating)等方式形成于包封结构件10的第二表面10b上。The material strength of the first support plate 41 is greater than the material strength of the encapsulation layer 14, so that the mechanical strength of the encapsulation structure during the encapsulation process can be effectively improved and guaranteed, and the adverse effects caused by the deformation of each structure can be effectively suppressed, thereby improving the product encapsulation quality. Effect. In other embodiments, the first support plate 41 may also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, or the like.
接续，在进入步骤300前，如图6D所示，所述封装方法还包括剥离所述载板3，露出包封结构件10的第一表面10a。包封结构件10的第一表面10a露出有待封装芯片11 的正面的保护层12、以及引线框20的第一面20a。Next, before entering step 300 , as shown in FIG. 6D , the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 . The first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 .
在载板3与待封装芯片11以及引线框20之间具有的粘接层为热分离膜的情况下，可以通过加热的方式，使得粘接层在遇热后降低黏性，进而剥离载板3。通过加热粘接层剥离载板3的方式，能够将在剥离过程中对待封装芯片11的损害降至最低。在其他实施例中，也可直接机械地剥离载板3。In the case where the adhesive layer between the carrier board 3 and the chip to be packaged 11 and the lead frame 20 is a thermal separation film, the adhesive layer can be heated to reduce the viscosity after being heated, and then the carrier board can be peeled off. 3. By heating the adhesive layer to peel off the carrier plate 3 , the damage to the chip 11 to be packaged during the peeling process can be minimized. In other embodiments, the carrier plate 3 can also be directly mechanically peeled off.
如图6E所示，载板3剥离后，暴露出了朝向载板3的包封结构件10的第一表面10a、待封装芯片11的正面、以及引线框20的第一面20a。剥离载板3后，得到了包括待封装芯片11、引线框20以及包封待封装芯片11和引线框20的包封层14的第一包封结构件10。在包封结构件10上，可以根据实际情况进行再布线等，使待封装芯片11与外界形成电连接。As shown in FIG. 6E , after the carrier 3 is peeled off, the first surface 10 a of the encapsulation structure 10 facing the carrier 3 , the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 are exposed. After peeling off the carrier board 3 , the first encapsulation structure 10 is obtained, which includes the chip to be packaged 11 , the lead frame 20 , and the encapsulation layer 14 that encapsulates the chip to be packaged 11 and the lead frame 20 . On the encapsulation structure 10 , rewiring and the like may be performed according to the actual situation, so that the chip 11 to be encapsulated is electrically connected to the outside world.
本实施例中，在剥离了载板3之后，暴露出保护层12的表面，此时可能粘接层中芯片附着层还存在于保护层12的表面。在通过化学方式去除该芯片附着层时，保护层12还能够保护待封装芯片11的表面不受破坏。在完全去除粘接层后，如果之前渗入了包封材料，还可以采用化学清洗或研磨的方式使得表面平整，以有利于后面布线。如果没有保护层12，则无法通过化学方式或者研磨的方式处理待封装芯片11的表面，以免破坏待封装芯片11的正面的电路。In this embodiment, after the carrier board 3 is peeled off, the surface of the protective layer 12 is exposed. At this time, it is possible that the chip attach layer in the adhesive layer still exists on the surface of the protective layer 12 . The protective layer 12 can also protect the surface of the chip 11 to be packaged from damage when the chip attach layer is chemically removed. After the adhesive layer is completely removed, if the encapsulation material has penetrated before, chemical cleaning or grinding can be used to make the surface smooth to facilitate subsequent wiring. If there is no protective layer 12 , the surface of the chip to be packaged 11 cannot be processed by chemical means or grinding, so as to avoid damaging the circuit on the front side of the chip to be packaged 11 .
需要说明的是，贴装第一支撑板41的步骤也可以放在剥离载板3之后。It should be noted that, the step of attaching the first support plate 41 may also be performed after peeling off the carrier plate 3 .
在步骤300中，如图6F所示，在包封结构件10的第一表面10a上形成第一再布线结构50。其中，第一再布线结构50与待封装芯片11的正面的焊垫电连接、且与引线框20的第一面20a的所述第一电连接点电连接。第一再布线结构50包括至少一层第一再布线层51。在本实施例中，第一再布线结构50包括一层第一再布线层51。但不限于此，第一再布线结构50也可以根据设计需要，包括多层第一再布线层51，即在待封装芯片11的正面进行重复再布线。比如可以同样地方式形成更多的再布线结构，可以根据设计要求进行调整。In step 300 , as shown in FIG. 6F , a first redistribution structure 50 is formed on the first surface 10 a of the encapsulation structure 10 . The first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged, and is electrically connected to the first electrical connection point of the first surface 20 a of the lead frame 20 . The first redistribution structure 50 includes at least one first redistribution layer 51 . In this embodiment, the first redistribution structure 50 includes a first redistribution layer 51 . But not limited to this, the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front surface of the chip 11 to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
其中，由于在保护层12上已经形成有保护层开口121，至少在形成第一再布线层51时可以直接看到保护层开口121，因此形成第一再布线结构50时能够更加准确的对位。Among them, since the protective layer opening 121 has been formed on the protective layer 12 , the protective layer opening 121 can be directly seen at least when the first redistribution layer 51 is formed, so the alignment can be more accurate when the first redistribution structure 50 is formed. .
在形成第一再布线结构50时，可以同时在待封装芯片11的保护层开口121内填充导电介质以形成导电柱52，即，在同一导电层形成工艺中形成第一再布线层51和导电柱52。导电柱52在保护层开口121中形成竖直的连接结构，通过导电柱52、以及第一 再布线层51将待封装芯片11的正面11a的焊垫电气引出。When the first redistribution structure 50 is formed, a conductive medium may be filled in the protective layer openings 121 of the chip 11 to be packaged at the same time to form the conductive pillars 52 , that is, the first redistribution layer 51 and the conductive layers are formed in the same conductive layer forming process. Post 52. The conductive pillars 52 form a vertical connection structure in the protective layer opening 121, and the bonding pads on the front side 11a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51.
接续，如图6G所示，形成介电层60，介电层60形成于第一再布线结构50、以及包封结构件10露出的第一表面10a上。介电层60可采用塑封膜(Molding film)的方式形成，或者介电层60可通过层压(Lamination)或印刷(Printing)的方式形成。介电层60可采用绝缘材料，如聚酰亚胺、环氧树脂、以及PBO(Polybenzoxazole)等中的一种或多种，优选采用环氧化合物。Next, as shown in FIG. 6G , a dielectric layer 60 is formed. The dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 . The dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing. The dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
如图6H所示，在形成介电层60后，所述封装方法还包括剥离第一支撑板41。可直接机械的剥离第一支撑板41，也可通过其他方法进行剥离，本申请对此不做限定，可根据具体应用环境进行设置。As shown in FIG. 6H , after forming the dielectric layer 60 , the packaging method further includes peeling off the first support plate 41 . The first support plate 41 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
可选的，在剥离第一支撑板41之后，如图6I所示，所述封装方法还包括在介电层60远离包封结构件10的一表面上贴装第二支撑板42。Optionally, after peeling off the first support plate 41 , as shown in FIG. 6I , the packaging method further includes mounting the second support plate 42 on a surface of the dielectric layer 60 away from the encapsulation structure 10 .
第二支撑板42至少贴装在介电层60远离包封结构件10的一面的至少部分区域。如图6I所示，在一实施例中，第二支撑板42贴装在介电层60远离包封结构件10的一面的全部区域。The second support plate 42 is mounted on at least a partial area of the side of the dielectric layer 60 away from the encapsulation structure 10 . As shown in FIG. 6I , in one embodiment, the second support plate 42 is mounted on the entire area of the side of the dielectric layer 60 away from the encapsulation structure 10 .
第二支撑板42的材料强度大于介电层60的材料强度，使得能够有效提高并保证封装过程中封装结构的机械强度，有效抑制各结构变形带来的不利影响，从而提高产品封装的效果。在另一些实施例中，第二支撑板42也可通过喷涂(Spraying)、印刷(Printing)、涂覆(Coating)等方式形成于介电层60上。The material strength of the second support plate 42 is greater than that of the dielectric layer 60 , so that the mechanical strength of the packaging structure during the packaging process can be effectively improved and guaranteed, and the adverse effects of structural deformation can be effectively suppressed, thereby improving the effect of product packaging. In other embodiments, the second support plate 42 may also be formed on the dielectric layer 60 by spraying, printing, coating, or the like.
需要说明的是，贴装第二支撑板42的步骤也可以放在剥离第一支撑板41之前。It should be noted that, the step of attaching the second support plate 42 may also be performed before peeling off the first support plate 41 .
可选的，如图6J所示，在包封结构件10的第二表面10b形成第二再布线结构70之前，所述封装方法还还包括对包封结构件10的第二表面10b进行研磨，以减薄包封结构件10的厚度。较佳的，减薄至露出待封装芯片11的背面11b的金属层。Optionally, as shown in FIG. 6J, before the second redistribution structure 70 is formed on the second surface 10b of the encapsulation structure 10, the packaging method further includes grinding the second surface 10b of the encapsulation structure 10 , so as to reduce the thickness of the encapsulating structural member 10 . Preferably, it is thinned to expose the metal layer of the backside 11b of the chip 11 to be packaged.
其中，引线框20的厚度可等于或稍大于待封装芯片的厚度。当引线框20的厚度大于待封装芯片的厚度时，在减薄包封结构件10至露出待封装芯片11的背面11b过程中，也会同时减薄引线框20的厚度露出待封装芯片11的部分。当引线框20的厚度等于待封装芯片的厚度时，在减薄包封结构件10至露出待封装芯片11的背面11b时，也会同时露出引线框20的第二面20b。优选的，引线框20的厚度等于待封装芯片的厚度，从而能够有效缩减研磨包封结构件10的第二表面10b的过程。The thickness of the lead frame 20 may be equal to or slightly larger than the thickness of the chip to be packaged. When the thickness of the lead frame 20 is greater than the thickness of the chip to be packaged, in the process of thinning the encapsulation structure 10 to expose the back surface 11b of the chip to be packaged 11 , the thickness of the lead frame 20 is also reduced to expose the thickness of the chip to be packaged 11 . part. When the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, when the encapsulation structure 10 is thinned to expose the back surface 11 b of the chip to be packaged 11 , the second surface 20 b of the lead frame 20 is also exposed at the same time. Preferably, the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, so that the process of grinding the second surface 10b of the encapsulation structure 10 can be effectively reduced.
接续，如图6K所示，在包封结构件10的第二表面10b形成第二再布线结构70。第 二再布线结构70与待封装芯片11的背面11b的金属层、以及引线框20的第二面20b的所述第二电连接点均电连接。第二再布线结构70包括至少一层第二再布线层71。在本实施例中，第二再布线结构70包括一层第二再布线层71。但不限于此，也可以根据设计需要，第二再布线结构70包括多层第二再布线层71，即在待封装芯片的背面进行重复再布线。比如可以同样地方式形成更多的再布线结构，可以根据设计要求进行调整。Next, as shown in FIG. 6K , a second redistribution structure 70 is formed on the second surface 10 b of the encapsulation structure 10 . The second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 to be packaged and the second electrical connection point of the second surface 20 b of the lead frame 20 . The second redistribution structure 70 includes at least one second redistribution layer 71 . In this embodiment, the second redistribution structure 70 includes a second redistribution layer 71 . But it is not limited to this, and the second redistribution structure 70 can also include multiple layers of second redistribution layers 71 according to design requirements, that is, repeated redistribution is performed on the backside of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
再布线结构(包括第二再布线结构70)的厚度远小于现有技术中(如图1中)的引线框30’的厚度。例如，一般再布线结构为15um-45um，引线框30’一般为150um-450um，因此，通过再布线结构不仅实现了布线的功能，还提升了产品的薄型化。The thickness of the redistribution structure (including the second redistribution structure 70) is much smaller than the thickness of the lead frame 30' in the prior art (as in FIG. 1). For example, the general rewiring structure is 15um-45um, and the lead frame 30' is generally 150um-450um. Therefore, the rewiring structure not only realizes the function of wiring, but also improves the thinning of the product.
在本实施例中，由于引线框20与第一再布线结构50以及第二再布线结构70均电连接，实现待封装芯片11的正面与背面的双面互连，即，通过引线框20连通了位于包封结构件10的第一表面10a上的第一再布线结构50和位于包封结构件10的第二表面10b上的第二再布线结构70。In this embodiment, since the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 to be packaged is realized, that is, the lead frame 20 communicates with each other. The first redistribution structure 50 located on the first surface 10a of the encapsulation structure 10 and the second redistribution structure 70 located on the second surface 10b of the encapsulation structure 10 are shown.
这样，通过第一再布线结构50、引线框20、第二再布线结构70来实现待封装芯片11的正面11a和背面11b的电气引出以及半导体封装结构1内部各电子元件(不同的多个待封装芯片11)之间的电气连接，相对于通过引线完成电气连接，本实施例的半导体封装结构需要的空间更小，特别是厚度方向的空间。并且，由于不用再将电气连接最后集中于引线框架的引脚引出，再布线结构的布局更自由灵活。In this way, through the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 , the electrical lead-out of the front side 11 a and the back side 11 b of the chip 11 to be packaged and the electronic components (a plurality of different ones to be packaged) inside the semiconductor packaging structure 1 are realized. For the electrical connection between the packaged chips 11 ), compared with the electrical connection completed by the leads, the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction. In addition, since the electrical connection does not need to be finally concentrated on the pins of the lead frame, the layout of the rewiring structure is more free and flexible.
具体地，待封装芯片11的正面11a的电气引出，是依次通过待封装芯片11的正面11a的焊垫111、第一再布线结构50、引线框20、第二再布线结构70的电连接实现的；待封装芯片11的背面11b的电气引出，是通过直接与第二再布线结构70电连接实现的；不同的待封装芯片11的互连，包括同面的互连或者不同面的互连(如其中一个待封装芯片11的正面和另一个待封装芯片11的背面的互连)，可以通过第一再布线结构50、引线框20、第二再布线结构70的电连接实现的。Specifically, the electrical lead-out of the front side 11a of the chip 11 to be packaged is realized by the electrical connection of the pads 111 on the front side 11a of the chip 11 to be packaged, the first rewiring structure 50 , the lead frame 20 and the second rewiring structure 70 in sequence. The electrical lead-out of the back surface 11b of the chip 11 to be packaged is realized by directly electrically connecting with the second redistribution structure 70; the interconnection of different chips 11 to be packaged includes the interconnection on the same surface or the interconnection on different surfaces (For example, the interconnection between the front side of one of the chips 11 to be packaged and the back side of the other chip 11 to be packaged) can be achieved through the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
如上所述，由于减薄包封结构件10后，待封装芯片11的背面11b、以及引线框20的第二面20b均露出于包封结构件10的第二表面10b，从而在包封结构件10的第二表面10b形成的第二再布线结构70直接覆设于待封装芯片11的背面11b、以及引线框20的第二面20b上。As described above, after the encapsulation structure 10 is thinned, the backside 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 are exposed on the second surface 10b of the encapsulation structure 10, so that the encapsulation structure The second redistribution structure 70 formed on the second surface 10b of the component 10 is directly overlaid on the back surface 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 .
较佳的，待封装芯片11的正投影位于第二再布线结构70的正投影之内，以通过第二再布线结构70保护待封装芯片11的背面11b，使其不裸露出来。Preferably, the orthographic projection of the chip 11 to be packaged is located within the orthographic projection of the second redistribution structure 70 , so that the backside 11 b of the chip to be packaged 11 is protected by the second redistribution structure 70 so as not to be exposed.
在步骤S300之后，如图6L所示，还包括在第二再布线结构70上形成引脚层80，即，在第二再布线结构70远离包封结构件10的一侧形成引脚层80。After step S300 , as shown in FIG. 6L , the method further includes forming a lead layer 80 on the second redistribution structure 70 , that is, forming a lead layer 80 on the side of the second redistribution structure 70 away from the encapsulation structure 10 . .
较佳的，引脚层80的正投影位于第二再布线结构70的正投影之内。例如，如图7所示，相邻的引脚层80之间的间距W1大于对位于该相邻的引脚层80的相邻第二再布线结构70之间的间距W2，以使最终形成的半导体封装产品在使用锡或其他材料进行焊接时，不易短路，提升了产品的电学性能。Preferably, the orthographic projection of the pin layer 80 is located within the orthographic projection of the second redistribution structure 70 . For example, as shown in FIG. 7 , the spacing W1 between adjacent pin layers 80 is greater than the spacing W2 between adjacent second redistribution structures 70 located in the adjacent pin layers 80 , so that the final formation When using tin or other materials for soldering, the semiconductor package products of our company are not easy to be short-circuited, which improves the electrical performance of the products.
半导体封装结构1可通过引脚层80实现和外部的电气连接，并通过引脚层80进行下一步安装。The semiconductor package structure 1 can be electrically connected to the outside through the pin layer 80 , and the next step can be installed through the pin layer 80 .
引脚层80的材料可为锡，但不限于锡，也可以是镍金合金，或者其他金属。The material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
在其他实施例中，也可以不包括引脚层80，而通过在待安装半导体封装结构1的其他结构(如PBC板)的表面形成引脚层，并通过对位将半导体封装结构1安装上去。In other embodiments, the lead layer 80 may not be included, but the lead layer is formed on the surface of other structures (such as PBC boards) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 is mounted by alignment .
接续，剥离第二支撑板42，如图6M所示。可直接机械的剥离第二支撑板42，也可通过其他方法进行剥离，本申请对此不做限定，可根据具体应用环境进行设置。Next, the second support plate 42 is peeled off, as shown in FIG. 6M . The second support plate 42 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
可选的，在剥离第二支撑板42之前或之后，还包括通过激光或机械切割的方式将引线框20的框体切除的步骤，该步骤的图示省略。Optionally, before or after peeling off the second support plate 42, a step of cutting off the frame body of the lead frame 20 by means of laser or mechanical cutting is also included, and the illustration of this step is omitted.
如果是多个半导体封装结构一起封装，在完成封装后，可通过激光或机械切割方式将整个封装结构切割成多个半导体封装结构。形成的半导体封装结构1的结构图可如图7所示。If multiple semiconductor package structures are packaged together, after the package is completed, the entire package structure may be cut into multiple semiconductor package structures by laser or mechanical cutting. A structural diagram of the formed semiconductor package structure 1 may be shown in FIG. 7 .
如图7所示，是根据本实施例提供的利用上述半导体封装方法得到的半导体封装结构1的结构示意图。半导体封装结构1包括包封结构件10、第一再布线结构50和第二再布线结构70。As shown in FIG. 7 , it is a schematic structural diagram of a semiconductor packaging structure 1 obtained by using the above-mentioned semiconductor packaging method according to the present embodiment. The semiconductor package structure 1 includes an encapsulation structure 10 , a first redistribution structure 50 and a second redistribution structure 70 .
包封结构件10包括相对的第一表面10a和第二表面10b，包封结构件10包括引线架组件(主要对应于前述半导体封装方法中的引线框20中的连接部24和边缘部23)、多个芯片11以及用于包封引线架组件和多个芯片11的包封层14。其中，引线架组件设置在各芯片11的外周以限定芯片各自的容置空间，所述容置空间沿厚度方向T贯穿引线架组件，多个所述芯片11位于所述容置空间中，所述包封层14填充于引线架组件限定的容置空间内。可见，引线架组件限定的多个芯片11各自的容置空间，可对应于前述半导体封装方法中的引线框20内的镂空区域21。The encapsulation structure 10 includes opposing first surfaces 10a and second surfaces 10b, and the encapsulation structure 10 includes a lead frame assembly (mainly corresponding to the connection portion 24 and the edge portion 23 in the lead frame 20 in the aforementioned semiconductor packaging method) , a plurality of chips 11 , and an encapsulation layer 14 for encapsulating the lead frame assembly and the plurality of chips 11 . Wherein, the lead frame assembly is arranged on the outer circumference of each chip 11 to define the respective accommodating spaces of the chips, the accommodating space penetrates the lead frame assembly along the thickness direction T, and a plurality of the chips 11 are located in the accommodating space, so The encapsulation layer 14 is filled in the accommodating space defined by the lead frame assembly. It can be seen that the respective accommodating spaces of the plurality of chips 11 defined by the lead frame assembly may correspond to the hollow regions 21 in the lead frame 20 in the aforementioned semiconductor packaging method.
芯片11的数量为多个。芯片11的数量根据设计要求可以调整，在此不做限定。在本实施例中，芯片11的数量为两个。引线框20的镂空区域的数量可以为一个或者多个。在本实施例中，每一引线框20设有的镂空区域的数量为两个。但不限于此，镂空区域21的数量可以根据设计需要为其他数量。The number of chips 11 is plural. The number of chips 11 can be adjusted according to design requirements, which is not limited here. In this embodiment, the number of chips 11 is two. The number of hollow regions of the lead frame 20 may be one or more. In this embodiment, each lead frame 20 is provided with two hollow regions in number. But not limited to this, the number of hollow regions 21 can be other numbers according to design requirements.
引线框20还包括连接部24。连接部24将所述引线框20内的空间间隔为多个所述镂空区域。分别位于不同的所述镂空区域中的芯片11通过连接部24进行电连接。The lead frame 20 also includes a connection portion 24 . The connection portion 24 divides the space in the lead frame 20 into a plurality of the hollow regions. The chips 11 respectively located in the different hollow regions are electrically connected through the connecting portions 24 .
具体的，在本实施例中，每一引线框20的内部空间通过连接部24间隔为两个，即，每一引线框20设有的镂空区域21的数量为两个，两个镂空区域21通过连接部24隔断。两个芯片11分别位于两个不同的镂空区域中。Specifically, in this embodiment, the inner space of each lead frame 20 is separated by two through the connecting portions 24 , that is, the number of hollow regions 21 provided on each lead frame 20 is two, and the two hollow regions 21 It is cut off by the connecting portion 24 . The two chips 11 are respectively located in two different hollow areas.
芯片11包括设有焊垫的正面、以及相对于正面设置的背面11b，背面11b设有金属层(图中未标示)，从而芯片11的正面11a及背面11b均有电气引出。芯片11的正面和引线框20的第一面20a露出于包封结构件10的第一表面10a。The chip 11 includes a front side provided with bonding pads, and a back side 11b opposite to the front side. The back side 11b is provided with a metal layer (not shown in the figure), so that both the front side 11a and the back side 11b of the chip 11 are electrically led out. The front surface of the chip 11 and the first surface 20 a of the lead frame 20 are exposed on the first surface 10 a of the encapsulation structure 10 .
第一再布线结构50对应于芯片11的正面并形成于包封结构件10的第一表面10a，第一再布线结构50与芯片11的正面的焊垫电连接、且与引线框20的第一面20a的第一电连接点电连接。The first redistribution structure 50 corresponds to the front surface of the chip 11 and is formed on the first surface 10 a of the encapsulation structure 10 . The first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and is connected to the first surface of the lead frame 20 . The first electrical connection point of one side 20a is electrically connected.
第一再布线结构50包括至少一层第一再布线层51。在本实施例中，第一再布线结构50包括一层第一再布线层51。但不限于此，也可以根据设计需要，第一再布线结构50包括多层第一再布线层51，即在芯片的正面进行重复再布线。比如可以同样地方式形成更多的再布线结构、以及更多的介电层，可以根据设计要求进行调整。The first redistribution structure 50 includes at least one first redistribution layer 51 . In this embodiment, the first redistribution structure 50 includes a first redistribution layer 51 . However, it is not limited to this, and the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip. For example, more redistribution structures and more dielectric layers can be formed in the same way, which can be adjusted according to design requirements.
芯片11的正面设有保护层12。保护层12上开设有保护层开口121。保护层开口121内设有通过填充导电介质而形成的导电柱52。可以在同一导电层形成工艺中形成第一再布线层51和导电柱52。A protective layer 12 is provided on the front surface of the chip 11 . A protective layer opening 121 is formed on the protective layer 12 . Conductive pillars 52 formed by filling the conductive medium are provided in the protective layer opening 121 . The first redistribution layer 51 and the conductive pillar 52 may be formed in the same conductive layer forming process.
第二再布线结构70对应于芯片11的背面并形成于包封结构件10的第二表面10b。第二再布线结构70与芯片11的背面11b的金属层、以及引线框20的第二面20b的第二电连接点均电连接。第二再布线结构70包括至少一层第二再布线层71。在本实施例中，第二再布线结构70包括一层第二再布线层71。但不限于此，也可以根据设计需要，第二再布线结构70包括多层第二再布线层71，即在芯片的背面进行重复再布线。比如可以同样地方式形成更多的再布线结构，可以根据设计要求进行调整。The second redistribution structure 70 corresponds to the back surface of the chip 11 and is formed on the second surface 10 b of the encapsulation structure 10 . The second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 and the second electrical connection point of the second surface 20 b of the lead frame 20 . The second redistribution structure 70 includes at least one second redistribution layer 71 . In this embodiment, the second redistribution structure 70 includes a second redistribution layer 71 . However, it is not limited to this, and according to design requirements, the second redistribution structure 70 includes multiple layers of second redistribution layers 71 , that is, repeated redistribution is performed on the backside of the chip. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
在本实施例中，由于引线框20与第一再布线结构50以及第二再布线结构70均电连 接，实现芯片11的正面与背面的双面互连，即，通过引线框20连通了位于包封结构件10的第一表面10a上的第一再布线结构50和位于包封结构件10的第二表面10b上的第二再布线结构70。In this embodiment, since the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 is realized, that is, the lead frame 20 is connected to the The first redistribution structure 50 on the first surface 10 a of the encapsulation structure 10 and the second redistribution structure 70 on the second surface 10 b of the encapsulation structure 10 .
这样，通过第一再布线结构50、引线框20、第二再布线结构70来实现芯片11的正面11a和背面11b的电气引出以及半导体封装结构1内部各电子元件(不同的多个芯片11)的电气连接，相对于通过引线完成电气连接，本实施例的半导体封装结构需要的空间更小，特别是厚度方向的空间。并且，由于不用再将电气连接最后集中于引线框架的引脚引出，再布线结构的布局更自由灵活。In this way, through the first redistribution structure 50 , the lead frame 20 and the second redistribution structure 70 , the electrical extraction of the front surface 11 a and the back surface 11 b of the chip 11 and the electronic components (different multiple chips 11 ) inside the semiconductor package structure 1 are realized. Compared with the electrical connection completed by the lead wire, the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction. In addition, since the electrical connection does not need to be finally concentrated on the pins of the lead frame, the layout of the rewiring structure is more free and flexible.
具体地，芯片11的正面11a的电气引出，是依次通过芯片11的正面11a的焊垫、第一再布线结构50、引线框20、第二再布线结构70的电连接实现的；芯片11的背面11b的电气引出，是通过直接与第二再布线结构70电连接实现的；不同的芯片11的互连，包括同面的互连或者不同面的互连(如其中一个芯片11的正面和另一个芯片11的背面的互连)，可以通过第一再布线结构50、引线框20、第二再布线结构70的电连接实现的。Specifically, the electrical lead-out of the front side 11a of the chip 11 is realized through the electrical connection of the bonding pads on the front side 11a of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70; The electrical lead-out of the backside 11b is realized by being directly electrically connected to the second redistribution structure 70; the interconnection of different chips 11 includes the interconnection on the same plane or the interconnection on different planes (such as the front side and the front side of one of the chips 11). The interconnection of the backside of the other chip 11 ) can be realized by the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
引线框20的厚度大致等于芯片11的厚度，芯片11的背面11b、以及引线框20的第二面20b均露出于包封结构件10的第二表面10b。在包封结构件10的第二表面10b形成的第二再布线结构70直接覆设于芯片11的背面11b、以及引线框20的第二面20b上，以进一步减薄整体厚度。The thickness of the lead frame 20 is approximately equal to the thickness of the chip 11 . The back surface 11 b of the chip 11 and the second surface 20 b of the lead frame 20 are both exposed on the second surface 10 b of the encapsulation structure 10 . The second redistribution structure 70 formed on the second surface 10b of the encapsulation structure 10 is directly overlaid on the back surface 11b of the chip 11 and the second surface 20b of the lead frame 20 to further reduce the overall thickness.
较佳的，芯片11的正投影位于第二再布线结构70的正投影之内，以通过第二再布线结构70保护芯片11的背面11b，使其不裸露出来。Preferably, the orthographic projection of the chip 11 is located within the orthographic projection of the second redistribution structure 70 , so as to protect the back surface 11 b of the chip 11 from being exposed by the second redistribution structure 70 .
包封结构件10还包括介电层60，介电层60形成于第一再布线结构50、以及包封结构件10露出的第一表面10a上。介电层60可采用塑封膜(Molding film)的方式形成，或者介电层60可通过层压(Lamination)或印刷(Printing)的方式形成。介电层60可采用绝缘材料，如聚酰亚胺、环氧树脂、以及PBO(Polybenzoxazole)等中的一种或多种，优选采用环氧化合物。当芯片的正面进行重复再布线时，也可以同样地方式形成更多的介电层，可以根据设计要求进行调整。The encapsulation structure 10 further includes a dielectric layer 60 . The dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 . The dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing. The dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound. When the front side of the chip is repeatedly rewired, more dielectric layers can also be formed in the same way, which can be adjusted according to design requirements.
包封结构件10还包括引脚层80，所述引脚层位于所述第二再布线结构70远离所述包封结构件10的一侧。The encapsulation structure 10 further includes a lead layer 80 , and the lead layer is located on a side of the second redistribution structure 70 away from the encapsulation structure 10 .
较佳的，引脚层80的正投影位于第二再布线结构70的正投影之内，即，相邻 的引脚层80之间的间距W1大于对位于该相邻的引脚层80的相邻第二再布线结构70之间的间距W2，以使最终形成的半导体封装产品在使用锡或其他材料进行焊接时，不易短路，提升了产品的电学性能。Preferably, the orthographic projection of the pin layers 80 is located within the orthographic projection of the second redistribution structure 70 , that is, the spacing W1 between adjacent pin layers 80 is greater than that of the adjacent pin layers 80 . The distance W2 between the adjacent second redistribution structures 70 makes it difficult to short-circuit when the finally formed semiconductor package product is soldered with tin or other materials, thereby improving the electrical performance of the product.
半导体封装结构1通过引脚层80实现和外部的电气连接，并通过引脚层80进行下一步安装。The semiconductor package structure 1 is electrically connected to the outside through the pin layer 80 , and is installed in the next step through the pin layer 80 .
引脚层80的材料可为锡，但不限于锡，也可以是镍金合金，或者其他金属。The material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
在其他实施例中，也可以不包括引脚层80，而通过在待安装半导体封装结构1的其他结构(如PCB板)的表面形成引脚层、并通过对位将半导体封装结构1安装上去。In other embodiments, the pin layer 80 may not be included, and the pin layer may be formed on the surface of other structures (such as a PCB board) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 may be mounted thereon by alignment .
如图8A和图8B所示，引线框20的连接部24包括依次连接的第一部分241、中间部分242和第二部分243。其中，第一部分241与中间部分242形成有第一夹角α，第二部分243与中间部分242形成有第二夹角β。这样，通过设置连接部24的具体结构，能够通过第一部分241和第二部分243实现更大的连接面积。较佳的，第一夹角α与第二夹角β均约等于90度，以使得第一部分241与第二部分243大致相互平行，这样，连接部24的结构可更为稳定。较佳的，第一部分241远离连接部24的一端与第二部分243远离连接部24的一端，均位于连接部24的同一侧，这样，连接部24的结构可更为紧凑。As shown in FIGS. 8A and 8B , the connecting portion 24 of the lead frame 20 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence. The first portion 241 and the middle portion 242 form a first angle α, and the second portion 243 and the middle portion 242 form a second angle β. In this way, by setting the specific structure of the connection portion 24 , a larger connection area can be achieved through the first portion 241 and the second portion 243 . Preferably, the first included angle α and the second included angle β are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are approximately parallel to each other, so that the structure of the connecting portion 24 can be more stable. Preferably, one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 can be more compact.
引线框20还包括若干相互隔离的边缘部23，边缘部23的一端露出于包封结构件10的表面，另一端向镂空区域21延伸；每一镂空区域21内均可设有若干相互隔离的边缘部23。具体的，边缘部23包括主体231和支撑部232，支撑部232远离主体231的一端露出于包封结构件10的表面，另一端与主体231连接。支撑部232的数量可以是一个，也可以是多个。当支撑部232的数量是多个时，多个支撑部232间隔设置。主体231可以是方形、条形或者L字形。较佳的，主体231为L字形的边缘部23设置于镂空区域21中远离连接部24的一角部。The lead frame 20 further includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is exposed on the surface of the encapsulation structure 10, and the other end extends toward the hollow area 21; each hollow area 21 can be provided with a number of mutually isolated edge portion 23 . Specifically, the edge portion 23 includes a main body 231 and a supporting portion 232 . One end of the supporting portion 232 away from the main body 231 is exposed on the surface of the encapsulating structural member 10 , and the other end is connected to the main body 231 . The number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals. The main body 231 may be square, bar-shaped or L-shaped. Preferably, the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
如前所述，由于引线框20是一体成型、并一体定位以及包封在包封结构件10中，大大地节省了生产成本，提高了整体生产效率。As mentioned above, since the lead frame 20 is integrally formed, positioned and encapsulated in the encapsulation structure 10, the production cost is greatly saved, and the overall production efficiency is improved.
进一步的，为了示意芯片11的正面与引线框20的连接关系、以及芯片11的背面与引线框20的连接关系，给出了半导体封装结构的正面连接的示意图(如图8A所示)和背面连接的示意图(如图8B所示)。在图中，仅是对于再布线结构做了一个示意性 连接，以说明连接关系。可以看出，引线框20与第一再布线结构50以及第二再布线结构70均电连接，实现芯片11的正面以及背面的互连，而且还可以实现不同的芯片11的双面互连(例如一个芯片11的正面和另一个芯片11的背面的互连)通过第一再布线结构50、引线框20的连接部24、第二再布线结构70的电连接实现的。Further, in order to illustrate the connection relationship between the front side of the chip 11 and the lead frame 20 and the connection relationship between the back side of the chip 11 and the lead frame 20, a schematic diagram of the front side connection of the semiconductor package structure (as shown in FIG. 8A ) and the back side are given. A schematic diagram of the connection (shown in Figure 8B). In the figure, only a schematic connection is made for the rewiring structure to illustrate the connection relationship. It can be seen that the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 to realize the interconnection of the front side and the back side of the chip 11, and can also realize the double-sided interconnection of different chips 11 ( For example, the interconnection of the front side of one chip 11 and the back side of the other chip 11 ) is achieved by the electrical connection of the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , and the second redistribution structure 70 .
具体地，图8A和图8B中所示的引线框20沿纸面垂直方向包括上下两个镂空区域21，每个镂空区域21分别放置了一个芯片11。其中，在图8A中，位于上面的镂空区域21的芯片11的正面通过第一再布线结构50分别与连接部24、以及位于上面的镂空区域21的其中一个边缘部23实现电连接；位于下面的镂空区域21的芯片11的正面通过第一再布线结构50分别与位于下面的镂空区域21的两个边缘部23实现电连接。在图8B中，位于上面的镂空区域21的芯片11的背面通过第二再布线结构70与位于上面的镂空区域21的另外两个边缘部23电连接；位于下面的镂空区域21的芯片11的背面通过第二再布线结构70与连接部24电连接。即，位于上面的镂空区域21的芯片11的正面依次通过第一再布线结构50、引线框20的连接部24、第二再布线结构70与位于下面的镂空区域21的芯片11的背面实现电连接。Specifically, the lead frame 20 shown in FIG. 8A and FIG. 8B includes two upper and lower hollow regions 21 along the vertical direction of the paper surface, and each hollow region 21 is respectively placed with a chip 11 . 8A , the front side of the chip 11 in the upper hollow area 21 is electrically connected to the connecting portion 24 and one of the edge portions 23 of the upper hollow area 21 through the first redistribution structure 50 respectively; The front surface of the chip 11 in the hollow area 21 is electrically connected to the two edge portions 23 of the hollow area 21 located below through the first redistribution structure 50 respectively. In FIG. 8B , the backside of the chip 11 in the upper hollow region 21 is electrically connected to the other two edge portions 23 of the upper hollow region 21 through the second redistribution structure 70 ; The back surface is electrically connected to the connection portion 24 through the second redistribution structure 70 . That is, the front surface of the chip 11 in the upper hollow region 21 is electrically connected to the back surface of the chip 11 in the lower hollow region 21 through the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , the second redistribution structure 70 and the lower hollow region 21 in sequence. connect.
在另一实施方式中，如图9所示，引线框20沿厚度方向T由包封结构件10的第一表面10a延伸至包封结构件10的第二表面10b，依次包括第一部分27和第二部分28。其中，第一部分27的宽度w21大于第二部分28的宽度w22，即形成剖面为阶梯形状的结构的引线框20。这样，第一部分27的相对较宽的接触面可以利于在引线框20上方形成第一再布线结构50时，能为第一再布线结构50提供较为大面积的支持；而且，阶梯形状的结构可以提升引线框20与包封层14之间的结合力并提升半导体封装结构的引脚层80在PCB板上的强度，从而提升产品的板级可靠性能。In another embodiment, as shown in FIG. 9 , the lead frame 20 extends from the first surface 10a of the encapsulation structure 10 to the second surface 10b of the encapsulation structure 10 along the thickness direction T, and includes the first portion 27 and Second part 28. Wherein, the width w21 of the first portion 27 is greater than the width w22 of the second portion 28 , that is, the lead frame 20 having a stepped structure in cross section is formed. In this way, the relatively wide contact surface of the first portion 27 can facilitate the formation of the first redistribution structure 50 over the lead frame 20, and can provide a relatively large area of support for the first redistribution structure 50; The bonding force between the lead frame 20 and the encapsulation layer 14 is enhanced and the strength of the lead layer 80 of the semiconductor package structure on the PCB is enhanced, thereby enhancing the board-level reliability performance of the product.
在又一实施方式中，芯片11的背面没有设置金属层，从而，芯片11的背面没有电气引出，仅需对芯片11的正面进行电气引出，即，第二再布线结构70与芯片11的背面不电连接。具体的，依次通过芯片11的正面11a的焊垫、第一再布线结构50、引线框20、第二再布线结构70的电连接实现芯片11的正面的电气引出。这样，能够直接通过引线框实现了将芯片的正面的电气引至芯片的背面后再引出，而不再需要铜柱部件，提升了布线面积，可实现多层布线工艺，增加了产品设计的自由度，增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。In yet another embodiment, the backside of the chip 11 is not provided with a metal layer, so that the backside of the chip 11 is not electrically drawn out, and only the front side of the chip 11 needs to be electrically drawn out, that is, the second rewiring structure 70 and the backside of the chip 11 Not electrically connected. Specifically, the electrical connection of the front surface of the chip 11 is realized through the electrical connection of the bonding pads on the front surface 11 a of the chip 11 , the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 in sequence. In this way, the electricity from the front side of the chip can be directly led to the back side of the chip through the lead frame, and the copper pillar components are no longer needed, the wiring area is increased, the multi-layer wiring process can be realized, and the freedom of product design can be increased. It increases the electrical reliability of the product; at the same time, it saves the production cost and improves the overall production efficiency.
本实施例的半导体封装结构通过设置整体结构，提升了产品的薄型化，可增强产品的电学信赖性。The semiconductor package structure of the present embodiment improves the thinning of the product by setting the overall structure, and can enhance the electrical reliability of the product.
具体的，通过在引线框设置镂空区域，所述镂空区域沿厚度方向贯穿所述引线框，并将多个芯片位于所述镂空区域中，大大地减薄了产品的厚度。Specifically, by arranging a hollow area in the lead frame, the hollow area penetrates the lead frame along the thickness direction, and a plurality of chips are located in the hollow area, which greatly reduces the thickness of the product.
本实施例中的技术方案直接通过引线框实现芯片的双面互连，而不再需要铜柱部件，提升了互连面积，可实现多层布线工艺，增加了产品设计的自由度，增强产品的电学信赖性；同时，节省了生产成本，提高了整体生产效率。需要说明的是，现有技术中，如果设置多个铜柱，由于要设置多个各自独立的铜柱，不仅定位工艺复杂，而且定位误差会产生累加；而在本申请中，由于引线框是一体成型，引线框上的各部分是一次定位就固定在载板上并包封在包封结构件中，大大地节省了生产成本，提高了整体生产效率。The technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. At the same time, it saves the production cost and improves the overall production efficiency. It should be noted that, in the prior art, if a plurality of copper pillars are provided, since a plurality of independent copper pillars are to be provided, not only the positioning process is complicated, but also the positioning errors will accumulate; in this application, since the lead frame is It is integrally formed, and each part of the lead frame is fixed on the carrier board and encapsulated in the encapsulation structure at one time, which greatly saves the production cost and improves the overall production efficiency.
通过将多个芯片设置于引线框的镂空区域中，并将芯片和引线框一起进行包封，避免了使用导电胶进行芯片的固定，从而提高了导入效率。By arranging a plurality of chips in the hollow area of the lead frame, and encapsulating the chips and the lead frame together, the use of conductive glue to fix the chips is avoided, thereby improving the introduction efficiency.
实施例2Example 2
本实施例的半导体封装方法的内容和实施例1中的半导体封装方法基本相同，不同的之处在于，在本实施例的半导体封装方法中，在待封装芯片11的正面形成保护层12的步骤放在了完成待封装芯片11和引线框20的封装之后，即在形成包封结构件10之后。The content of the semiconductor packaging method of this embodiment is basically the same as that of the semiconductor packaging method in Embodiment 1, the difference is that in the semiconductor packaging method of this embodiment, the step of forming the protective layer 12 on the front surface of the chip 11 to be packaged It is placed after the encapsulation of the chip 11 to be packaged and the lead frame 20 is completed, that is, after the encapsulation structure 10 is formed.
具体地，如图10A-图10E所示，本实施例的半导体封装方法包括：Specifically, as shown in FIGS. 10A-10E , the semiconductor packaging method of this embodiment includes:
步骤100中，如图10A所示，将待封装芯片11和引线框20通过粘接层贴装在载板3上。其中，待封装芯片11的背面朝上，正面朝向载板3。引线框20设有沿厚度方向T贯穿引线框20的镂空区域21，多个待封装芯片11位于镂空区域21中。In step 100 , as shown in FIG. 10A , the chip 11 to be packaged and the lead frame 20 are mounted on the carrier board 3 through an adhesive layer. The backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 . The lead frame 20 is provided with a hollow area 21 extending through the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
在步骤200中，如图10B所示，通过将包封层14覆盖在整个载板3上(即，将包封层14覆盖在待封装芯片11、引线框20以及载板3露出的部分上)，且填充于引线框20的镂空区域21内，对待封装芯片11和引线框20进行包封形成包封结构件10。In step 200 , as shown in FIG. 10B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) ), and fill in the hollow area 21 of the lead frame 20 to encapsulate the chip to be packaged 11 and the lead frame 20 to form the encapsulation structure 10 .
接续，如图10C所示，所述封装方法还包括剥离所述载板3，露出包封结构件10的第一表面10a。Then, as shown in FIG. 10C , the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
接续，在进入步骤300前，如图10D所示，在包封结构件10的第一表面10a形成保护层12。Next, before entering step 300 , as shown in FIG. 10D , a protective layer 12 is formed on the first surface 10 a of the encapsulation structure 10 .
之后，如图10E所示，在保护层12上与待封装芯片11的正面的焊垫相对应的 位置处、以及与引线框20的第一面20a的第二电连接点的相对应的位置处形成保护层开口121。在本实施例中，由于引线框20与待封装芯片11大致布置在同一水平面上，在对保护层12进行打孔形成保护层开口121时，保护层12可为透明膜层，以利用保护层12的透明度进行定位。此外，还可通过引线框20辅助定位，以提高镭射钻孔的位置精确度。After that, as shown in FIG. 10E , on the protective layer 12 at positions corresponding to the pads on the front side of the chip 11 to be packaged, and at positions corresponding to the second electrical connection points of the first side 20 a of the lead frame 20 A protective layer opening 121 is formed there. In the present embodiment, since the lead frame 20 and the chip 11 to be packaged are arranged approximately on the same level, when the protective layer 12 is punched to form the protective layer opening 121 , the protective layer 12 can be a transparent film layer to utilize the protective layer 12 transparency for positioning. In addition, positioning can be assisted by the lead frame 20 to improve the positional accuracy of the laser drilling.
在本申请中，所述结构实施例与方法实施例在不冲突的情况下，可以互为补充。In this application, the structural embodiments and the method embodiments may complement each other without conflict.
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the present application. within the scope of protection.

Claims (15)

  1. 一种半导体封装方法，包括：A semiconductor packaging method, comprising:
    将引线框与多个待封装芯片贴装于载板上，其中The lead frame and a plurality of chips to be packaged are mounted on the carrier board, wherein
    所述待封装芯片的正面朝向所述载板，The front side of the chip to be packaged faces the carrier board,
    所述引线框设有镂空区域，所述镂空区域沿厚度方向贯穿所述引线框，The lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction,
    多个所述待封装芯片位于所述镂空区域中；A plurality of the chips to be packaged are located in the hollow area;
    通过将包封层覆盖在所述待封装芯片、所述引线框以及所述载板露出的部分上，且填充于所述镂空区域内，形成包封结构件，其中An encapsulation structure is formed by covering an encapsulation layer on the chip to be encapsulated, the lead frame and the exposed part of the carrier board, and filling the hollow area, wherein the encapsulation structure is formed.
    所述包封结构件包括相对设置的第一表面和第二表面，The encapsulating structural member includes a first surface and a second surface disposed opposite to each other,
    所述待封装芯片的正面和所述引线框的第一面露出于所述包封结构件的第一表面；The front surface of the chip to be packaged and the first surface of the lead frame are exposed on the first surface of the packaging structure;
    在所述包封结构件的第一表面形成第一再布线结构，所述第一再布线结构与所述待封装芯片的正面以及所述引线框的第一面均电连接；以及，A first redistribution structure is formed on the first surface of the encapsulation structure, and the first redistribution structure is electrically connected to both the front surface of the to-be-packaged chip and the first surface of the lead frame; and,
    在所述包封结构件的第二表面形成第二再布线结构，所述第二再布线结构与所述引线框相对所述第一面设置的第二面电连接。A second redistribution structure is formed on the second surface of the encapsulation structure, and the second redistribution structure is electrically connected to a second surface of the lead frame opposite to the first surface.
  2. 如权利要求1所述的半导体封装方法，其特征在于，The semiconductor packaging method of claim 1, wherein:
    所述引线框包括连接部，The lead frame includes a connecting portion,
    所述连接部将所述引线框内的空间间隔为多个所述镂空区域，The connecting portion divides the space in the lead frame into a plurality of the hollow areas,
    分别位于不同的所述镂空区域中的所述待封装芯片通过所述连接部进行电连接。The chips to be packaged respectively located in the different hollow regions are electrically connected through the connection portion.
  3. 如权利要求2所述的半导体封装方法，其特征在于，The semiconductor packaging method according to claim 2, wherein,
    所述引线框还包括框体，所述镂空区域沿所述厚度方向贯穿所述框体；The lead frame further includes a frame body, and the hollow area penetrates the frame body along the thickness direction;
    所述连接部的两端分别与所述框体相对的两侧连接。Both ends of the connecting portion are respectively connected to opposite sides of the frame body.
  4. 如权利要求3所述的半导体封装方法，其特征在于，The semiconductor packaging method according to claim 3, wherein,
    所述连接部包括依次连接的第一部分、中间部分和第二部分，所述第一部分与所述第二部分分别与所述框体相对的两侧连接；The connecting part comprises a first part, a middle part and a second part which are connected in sequence, and the first part and the second part are respectively connected with opposite sides of the frame body;
    所述第一部分远离所述连接部的一端与所述第二部分远离所述连接部的一端，均位于所述连接部的同一侧。One end of the first portion away from the connection portion and an end of the second portion away from the connection portion are located on the same side of the connection portion.
  5. 如权利要求3所述的半导体封装方法，其特征在于，The semiconductor packaging method according to claim 3, wherein,
    所述引线框还包括若干相互隔离的边缘部，所述边缘部的一端与所述框体连接，另一端向镂空区域延伸；The lead frame further includes a plurality of mutually isolated edge portions, one end of the edge portion is connected with the frame body, and the other end extends toward the hollow area;
    每一所述镂空区域内均设有若干相互隔离的边缘部。Each of the hollowed-out regions is provided with a plurality of mutually isolated edge portions.
  6. 如权利要求1所述的半导体封装方法，其特征在于，所述待封装芯片的背面与所述第二再布线结构电连接。The semiconductor packaging method of claim 1, wherein the backside of the chip to be packaged is electrically connected to the second redistribution structure.
  7. 如权利要求1所述的半导体封装方法，其特征在于，The semiconductor packaging method of claim 1, wherein:
    所述引线框的厚度等于所述待封装芯片的厚度，The thickness of the lead frame is equal to the thickness of the chip to be packaged,
    在形成所述第二再布线结构之前，所述半导体封装方法还包括：Before forming the second redistribution structure, the semiconductor packaging method further includes:
    对所述包封结构件进行减薄至从所述包封结构件的第二表面露出所述待封装芯片的背面、以及所述引线框的第二面；thinning the encapsulation structure to expose the backside of the to-be-packaged chip and the second surface of the lead frame from the second surface of the encapsulation structure;
    在形成所述第二再布线结构中，所述第二再布线结构直接覆设于所述待封装芯片的背面、以及所述引线框的第二面。In forming the second redistribution structure, the second redistribution structure is directly covered on the back surface of the chip to be packaged and the second surface of the lead frame.
  8. 如权利要求1所述的半导体封装方法，其特征在于，所述待封装芯片的正投影位于所述第二再布线结构的正投影之内。The semiconductor packaging method of claim 1, wherein the orthographic projection of the chip to be packaged is located within the orthographic projection of the second redistribution structure.
  9. 如权利要求1所述的半导体封装方法，其特征在于，在将所述引线框与所述多个待封装芯片贴装于所述载板上之前，所述半导体封装方法还包括：The semiconductor packaging method according to claim 1, wherein before the lead frame and the plurality of chips to be packaged are mounted on the carrier board, the semiconductor packaging method further comprises:
    在所述待封装芯片的正面形成保护层，并A protective layer is formed on the front side of the chip to be packaged, and
    在所述保护层上形成保护层开口。A protective layer opening is formed on the protective layer.
  10. 如权利要求1所述的半导体封装方法，其特征在于，在形成所述包封结构件之后，所述半导体封装方法还包括：The semiconductor packaging method according to claim 1, wherein after forming the encapsulation structure, the semiconductor packaging method further comprises:
    在所述包封结构件的第一表面形成保护层，并A protective layer is formed on the first surface of the encapsulation structure, and
    在所述保护层上形成保护层开口。A protective layer opening is formed on the protective layer.
  11. 一种半导体封装结构，包括：A semiconductor packaging structure, comprising:
    包封结构件，具有相对的第一表面和第二表面，并包括：An encapsulation structure having opposing first and second surfaces and comprising:
    多个芯片；multiple chips;
    引线架组件，设置在各所述芯片的外周，用于限定所述多个芯片各自的容置空间；以及，a lead frame assembly, disposed on the periphery of each of the chips, and used to define the respective accommodating spaces of the plurality of chips; and,
    用于包封所述引线架组件以及所述多个所述芯片的包封层，所述包封层填充于所述引线架组件限定的所述容置空间内，an encapsulation layer for encapsulating the lead frame assembly and the plurality of chips, the encapsulation layer is filled in the accommodating space defined by the lead frame assembly,
    其中，所述芯片的正面和所述引线架组件的第一面露出于所述包封结构件的第一表面；Wherein, the front surface of the chip and the first surface of the lead frame assembly are exposed on the first surface of the encapsulation structure;
    第一再布线结构，形成于所述包封结构件的第一表面，并与所述芯片的正面以及所述引线架组件的第一面电连接；a first redistribution structure, formed on the first surface of the encapsulation structure, and electrically connected to the front surface of the chip and the first surface of the lead frame assembly;
    第二再布线结构，形成于所述包封结构件的第二表面，并与所述引线架组件相对所 述第一面设置的第二面电连接。The second redistribution structure is formed on the second surface of the encapsulation structure and is electrically connected to the second surface of the lead frame assembly opposite to the first surface.
  12. 如权利要求11所述的半导体封装结构，其特征在于，The semiconductor package structure of claim 11, wherein:
    所述引线架组件包括连接部，The lead frame assembly includes a connecting portion,
    所述连接部用于指示将所述多个芯片相互间隔开，the connecting portion is used to instruct the plurality of chips to be spaced apart from each other,
    分别位于不同的所述容置空间中的所述芯片通过所述连接部进行电连接。The chips respectively located in the different accommodating spaces are electrically connected through the connecting portion.
  13. 如权利要求12所述的半导体封装结构，其特征在于，The semiconductor package structure according to claim 12, wherein,
    所述连接部包括依次连接的第一部分、中间部分和第二部分，The connecting part includes a first part, a middle part and a second part connected in sequence,
    所述第一部分远离所述连接部的一端与所述第二部分远离所述连接部的一端，均位于所述连接部的同一侧。One end of the first portion away from the connection portion and an end of the second portion away from the connection portion are located on the same side of the connection portion.
  14. 如权利要求11所述的半导体封装结构，其特征在于，The semiconductor package structure of claim 11, wherein:
    所述引线架组件还包括若干相互隔离的边缘部，所述边缘部沿所述包封结构件的内周缘设置，The lead frame assembly further includes a plurality of mutually isolated edge portions, the edge portions are arranged along the inner periphery of the encapsulation structural member,
    所述边缘部的一端露出于所述包封结构件的表面，另一端向所述镂空区域延伸；One end of the edge portion is exposed on the surface of the encapsulation structure, and the other end extends toward the hollow area;
    每一所述镂空区域内均设有若干相互隔离的所述边缘部。Each of the hollowed-out regions is provided with a plurality of the edge portions isolated from each other.
  15. 如权利要求10所述的半导体封装结构，其特征在于，所述芯片的背面与所述第二再布线结构电连接。11. The semiconductor package structure of claim 10, wherein the backside of the chip is electrically connected to the second redistribution structure.
PCT/CN2020/141965 2020-07-31 2020-12-31 Semiconductor packaging method and semiconductor packaging structure WO2022021799A1 (en)

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