WO2022021799A1 - Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur - Google Patents

Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur Download PDF

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Publication number
WO2022021799A1
WO2022021799A1 PCT/CN2020/141965 CN2020141965W WO2022021799A1 WO 2022021799 A1 WO2022021799 A1 WO 2022021799A1 CN 2020141965 W CN2020141965 W CN 2020141965W WO 2022021799 A1 WO2022021799 A1 WO 2022021799A1
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Prior art keywords
lead frame
chip
packaged
encapsulation
chips
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PCT/CN2020/141965
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English (en)
Chinese (zh)
Inventor
霍炎
涂旭峰
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矽磐微电子(重庆)有限公司
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Publication of WO2022021799A1 publication Critical patent/WO2022021799A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • a lead frame 30' and a wiring layer 40' are often used to implement a double-sided interconnect package of two chips 10'.
  • the backsides of the two chips 10' are mounted on the upper surface of the lead frame 30' through the conductive adhesive 20' to realize the backside electrical connection, and the wiring layer 40' is connected to the front side of the chip 10' through the copper pillars 50'.
  • the copper pillar 50' needs to be implanted by means of ultrasonic bonding, and the cost of this process is extremely high, but the efficiency is extremely low.
  • arranging the lead frame 30' on the backside of the chip 10' results in a thicker product, which will be limited when applied to wearable equipment or other scenarios that have higher requirements on product thickness.
  • the present application provides a semiconductor packaging method and a semiconductor packaging structure.
  • One aspect of the present application provides a semiconductor packaging method, which includes: mounting a lead frame and a plurality of chips to be packaged on a carrier board, the front surfaces of the chips to be packaged face the carrier board, and the lead frame is provided with a hollow area , the hollow area runs through the lead frame along the thickness direction, and a plurality of the chips to be packaged are located in the hollow area; by covering the chips to be packaged, the lead frame and the carrier board with an encapsulation layer The exposed part is filled in the hollow area of the lead frame to form an encapsulation structure, the encapsulation structure includes a first surface and a second surface arranged oppositely, the front side of the chip to be packaged and all the The first surface of the lead frame is exposed on the first surface of the encapsulation structure; a first redistribution structure is formed on the first surface of the encapsulation structure, and the first redistribution structure is connected to the to-be-packaged structure The front surface of the chip and the first surface of the lead frame are electrically connected; and
  • a second aspect of the present application provides a semiconductor package structure including an encapsulation structure having opposing first and second surfaces, the encapsulation structure including a lead frame assembly, a plurality of chips, and a an encapsulation layer that encapsulates the lead frame assembly and the plurality of chips, the lead frame assembly is disposed on the periphery of each of the chips to define the respective accommodating spaces of the plurality of chips, and the accommodating space is The space runs through the lead frame assembly in the thickness direction, the encapsulation layer is filled in the accommodating space defined by the lead frame assembly, and the front surface of the chip and the first surface of the lead frame assembly are exposed to the package the first surface of the encapsulation structure; the first redistribution structure, the first redistribution structure is formed on the first surface of the encapsulation structure, the first redistribution structure and the front surface of the chip and the The first surface of the lead frame assembly is electrically connected; the second redistribution structure is formed on the second surface of the encapsulation structure, and the
  • the above-mentioned semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application realize the double-sided interconnection packaging of the chip through the lead frame and the double-sided re-wiring interconnection process, improve the thinning of the product, and enhance the electrical reliability of the product. sex.
  • the thickness is greatly reduced.
  • the thickness of the product is reduced, and the thinning of the product is effectively realized.
  • the technical solution in this application directly leads the electricity from the front side of the chip to the back side of the chip through the lead frame, and no longer needs copper pillar components, improves the wiring area, can realize multi-layer wiring process, and increases product design.
  • the degree of freedom increases the electrical reliability of the product; at the same time, the production cost is saved and the overall production efficiency is improved.
  • the double-sided interconnection of the chip can be realized directly through the lead frame, without the need for copper pillar components. , so as to increase the interconnection area, realize multi-layer wiring process, increase the degree of freedom of product design, and enhance the electrical reliability of the product.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor
  • the lead frame assembly in the semiconductor package structure of the present application no longer needs the lead portion located under the chip, it can be applied to chips with larger area and can discharge more chips, and has excellent applicability.
  • FIG. 1 is a cross-sectional view of a semiconductor package structure in the prior art.
  • FIG. 2 is a flowchart of a semiconductor packaging method according to Embodiment 1 of the present application.
  • 3A-3B are process flow diagrams of forming a protective layer and a protective layer opening on the front side of a chip to be packaged according to Embodiment 1 of the present application.
  • FIG. 4 is a schematic view of the front structure of the lead frame according to the first embodiment of the present application.
  • FIG. 5 is a schematic diagram of the front structure of the lead frame according to Embodiment 1 of the present application.
  • 6A-6M are process flow diagrams of the semiconductor packaging method proposed according to Embodiment 1 of the present application.
  • FIG. 7 is a schematic structural diagram of a semiconductor packaging structure obtained by using the above-mentioned semiconductor packaging method according to Embodiment 1 of the present application.
  • FIG. 8A is a schematic diagram of front connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 8B is a schematic diagram of the backside connection of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • FIG. 9 is a schematic structural diagram of another embodiment of the semiconductor package structure proposed according to Embodiment 1 of the present application.
  • 10A-10E are process flow diagrams of a semiconductor packaging method in Embodiment 2 according to the present application.
  • Words like "connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words like “upper” and/or “lower” are for convenience of description and are not limited to one position or one spatial orientation.
  • Words like “upper” and/or “lower” are for convenience of description and are not limited to one position or one spatial orientation.
  • the singular forms “a,” “the,” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term “and/or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
  • This embodiment provides a semiconductor packaging method and a semiconductor packaging structure.
  • FIG. 2 is a flowchart of the semiconductor packaging method proposed in this embodiment. As shown in FIG. 2, the semiconductor packaging method includes the following steps:
  • Step 100 Mount the lead frame and a plurality of chips to be packaged on the carrier board.
  • the front side of the chip to be packaged faces the carrier board;
  • the lead frame is provided with a hollow area, and the hollow area penetrates the lead frame along the thickness direction; a plurality of the chips to be packaged are located in the hollow area .
  • Step 200 Cover the chip to be packaged, the lead frame and the exposed part of the carrier with an encapsulation layer, and fill the hollow area of the lead frame to form an encapsulation structure.
  • the encapsulation structure includes a first surface and a second surface disposed opposite to each other; the front surface of the chip to be packaged and the first surface of the lead frame are exposed on the first surface.
  • Step 300 forming a first redistribution structure on the first surface of the encapsulation structure, and the first redistribution structure is electrically connected to the front surface of the to-be-packaged chip and the first surface of the lead frame; and forming a second redistribution structure on the second surface of the encapsulation structure, the second redistribution structure and the back surface of the chip to be packaged and the second surface of the lead frame disposed opposite to the first surface All electrical connections.
  • the semiconductor packaging method of this embodiment improves the thinning of the product and can enhance the electrical reliability of the product.
  • the thickness is greatly reduced. the thickness of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. electrical reliability.
  • a plurality of copper pillars are provided, since a plurality of independent copper pillars are to be provided, not only the positioning process is complicated, but also the positioning errors will be accumulated; but in this application, since the lead frame is integrally formed, the lead Each part of the frame is fixed on the carrier plate at one time and is encapsulated in the encapsulating structural member correspondingly, which greatly saves the production cost and improves the overall production efficiency.
  • the lead frame assembly in the semiconductor package structure of the present embodiment no longer needs the lead portion under the chip, so it can be applied to a chip with a larger area, and can discharge more chips , with excellent applicability.
  • a protective layer 12 is formed on the front surface of the chip 11 to be packaged.
  • the chip 11 to be packaged includes a front surface 11a provided with solder pads, and a back surface 11b disposed opposite to the front surface 11a.
  • the back surface 11b is provided with a metal layer (not marked in the figure), so that the front surface 11a and the back surface 11b of the chip to be packaged 11 are electrically connected. lead out.
  • protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the bonding pads on the front side 11 a of the chip 11 to be packaged, and each protective layer opening 121 is at least opposite to the bonding pads or the bonding pads of the chip 11 to be packaged.
  • the lines drawn from the bonding pads enable the bonding pads on the front side of the chip 11 to be packaged or the lines drawn from the bonding pads to be exposed from the protective layer opening 121 .
  • the specific structure of the lead frame 20 in this embodiment can be shown in FIG. 4 and FIG. 5 .
  • Each final semiconductor package structure after packaging and dicing corresponds to one lead frame 20 .
  • the lead frame 20 constitutes the lead frame 2 , and the lead frame 2 may also be constituted by only one lead frame 20 .
  • Each lead frame 20 includes a frame body 22, and the frame body 22 is provided with a hollow area 21 extending through the frame body 22 along the thickness direction T in the frame body 22. As shown in FIG.
  • the number of hollow regions 21 of the lead frame 20 may be one or more.
  • the lead frame 20 also includes a connection portion 24 .
  • Two ends of the connecting portion 24 are respectively connected to two opposite sides of the frame body 22 , and the connecting portion 24 separates the hollow regions 21 into a plurality of hollow regions 21 , that is, adjacent hollow regions 21 are separated by the connecting portions 24 .
  • connecting portions 24 For example, adjacent hollow regions 21 in the same lead frame 20 are separated by connecting portions 24 .
  • the inner space of each lead frame 20 is separated into two hollow regions 21 by the connecting portion 24 , that is, the number of hollow regions 21 provided in each lead frame 20 is Two, two hollow regions 21 are separated by connecting parts 24 .
  • the connecting portion 24 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇ .
  • the first part 241 and the second part 243 are respectively connected to opposite sides of the frame body 22 .
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are substantially parallel to each other, so that the structure of the connecting portion 24 is more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 is more compact.
  • the lead frame 20 also includes a number of mutually isolated edge portions 23 .
  • One end of the edge portion 23 is connected to the frame body 22 , and the other end extends toward the hollow area 21 .
  • Each hollow area 21 is provided with a plurality of mutually isolated edge portions 23 .
  • the edge portion 23 includes a main body 231 and a support portion 232 , and the support portion 232 is connected between the frame body 22 and the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the chips to be packaged respectively located in the different hollow regions can be electrically connected through the connecting portion.
  • the front side of one of the chips to be packaged and the back side of the other chip to be packaged can be electrically connected; or, the front side of one of the chips to be packaged and the front side of the other chip to be packaged can be electrically connected;
  • the backside of the chip to be packaged is in electrical communication with the backside of another chip to be packaged.
  • each lead frame 20 includes a first surface 20 a and a second surface 20 b disposed opposite to each other along the thickness direction T. As shown in FIG. The first surface 20a is provided with a number of first electrical connection points, and the second surface 20b is provided with a number of second electrical connection points.
  • step 100 as shown in FIG. 6A , the chip to be packaged 11 and the lead frame 20 with the protective layer 12 formed on the front side are mounted on the carrier board 3 through the adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the lead frame 20 is provided with a hollow area 21 , the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
  • the thickness of the lead frame 20 is approximately equal to the thickness of the chip to be packaged.
  • the thickness of the chip to be packaged refers to the distance from the backside of the chip to be packaged 11 to the surface of the carrier board 3 when the chip to be packaged 11 is mounted on the carrier board 3 .
  • the thinning of the final semiconductor package structure 1 can be achieved in the above manner.
  • the thickness of the lead frame 20 may be greater than that of the chip to be packaged, so as to protect the chip 11 to be packaged.
  • the adhesive layer is used to bond the chip to be packaged 11 and the lead frame 20 to the carrier board 3 .
  • the adhesive layer can be made of an easily peelable material, so that the carrier board 3 is peeled off from the chip 11 to be packaged and the lead frame 20 in a subsequent process.
  • a thermally separable material that can be debonded by heating can be used.
  • the adhesive layer may adopt a two-layer structure, a thermal separation material layer and a die attach layer.
  • the thermal separation material layer is pasted on the carrier board 3, and will lose its viscosity when heated, and then can be peeled off from the carrier board 3; and the chip attachment layer adopts a sticky material layer, which can be used to paste the to-be-packaged chip 11. .
  • the chip attach layer thereon may be removed by chemical cleaning.
  • an adhesive layer may be formed on the carrier board 3 by means of lamination, printing, or the like.
  • the number of chips 11 to be packaged may be multiple.
  • the number of chips 11 to be packaged can be adjusted according to design requirements.
  • the lead frame 20 is integrally formed, that is, the frame body 22 , the connection portion 24 , and the edge portion 23 of the lead frame are integrally formed, the frame body 22 , the connection portion 24 , the edge portion 23 , etc. of the lead frame are integrally formed.
  • Each part of the machine is fixed on the carrier board at one time, which greatly saves the production cost and improves the overall production efficiency.
  • step 200 as shown in FIG. 6B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) above), and fill in the hollow area 21 of the lead frame 20 to form the encapsulation structure 10 for encapsulating the chip to be packaged 11 and the lead frame 20 .
  • the encapsulation structure 10 is a flat structure, and after the carrier board 3 is peeled off, rewiring and packaging can be continued on the flat structure.
  • the encapsulation structure 10 includes a first surface 10a and a second surface 10b which are disposed opposite to each other. Wherein, the second surface 10 b of the encapsulation structure 10 is disposed opposite to the carrier plate 3 , is substantially flat, and is parallel to the surface of the carrier plate 3 .
  • the first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be encapsulated, and the first surface 20 a of the lead frame 20 .
  • the encapsulation layer 14 may be formed by laminating epoxy resin film or Molding film, or may be formed by injection molding or compression molding of epoxy resin compound. molding) or transfer molding (Transfer molding).
  • the packaging method further includes mounting a first support plate 41 on the second surface 10 b of the packaging structure 10 .
  • the first support plate 41 is mounted on at least a partial area of the second surface 10 b of the encapsulation structure 10 . As shown in FIG. 6C , in one embodiment, the first support plate 41 is mounted on the second surface 10 b of the encapsulation structure 10 , and the first support plate 41 covers the second surface of the encapsulation structure 10 All areas of 10b.
  • the material strength of the first support plate 41 is greater than the material strength of the encapsulation layer 14, so that the mechanical strength of the encapsulation structure during the encapsulation process can be effectively improved and guaranteed, and the adverse effects caused by the deformation of each structure can be effectively suppressed, thereby improving the product encapsulation quality. Effect.
  • the first support plate 41 may also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, or the like.
  • the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
  • the first surface 10 a of the encapsulation structure 10 exposes the protective layer 12 on the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 .
  • the adhesive layer between the carrier board 3 and the chip to be packaged 11 and the lead frame 20 is a thermal separation film
  • the adhesive layer can be heated to reduce the viscosity after being heated, and then the carrier board can be peeled off. 3.
  • the carrier plate 3 can also be directly mechanically peeled off.
  • the first surface 10 a of the encapsulation structure 10 facing the carrier 3 , the front surface of the chip 11 to be packaged, and the first surface 20 a of the lead frame 20 are exposed.
  • the first encapsulation structure 10 is obtained, which includes the chip to be packaged 11 , the lead frame 20 , and the encapsulation layer 14 that encapsulates the chip to be packaged 11 and the lead frame 20 .
  • rewiring and the like may be performed according to the actual situation, so that the chip 11 to be encapsulated is electrically connected to the outside world.
  • the surface of the protective layer 12 is exposed. At this time, it is possible that the chip attach layer in the adhesive layer still exists on the surface of the protective layer 12 .
  • the protective layer 12 can also protect the surface of the chip 11 to be packaged from damage when the chip attach layer is chemically removed. After the adhesive layer is completely removed, if the encapsulation material has penetrated before, chemical cleaning or grinding can be used to make the surface smooth to facilitate subsequent wiring. If there is no protective layer 12 , the surface of the chip to be packaged 11 cannot be processed by chemical means or grinding, so as to avoid damaging the circuit on the front side of the chip to be packaged 11 .
  • the step of attaching the first support plate 41 may also be performed after peeling off the carrier plate 3 .
  • a first redistribution structure 50 is formed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged, and is electrically connected to the first electrical connection point of the first surface 20 a of the lead frame 20 .
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front surface of the chip 11 to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the protective layer opening 121 since the protective layer opening 121 has been formed on the protective layer 12 , the protective layer opening 121 can be directly seen at least when the first redistribution layer 51 is formed, so the alignment can be more accurate when the first redistribution structure 50 is formed. .
  • a conductive medium may be filled in the protective layer openings 121 of the chip 11 to be packaged at the same time to form the conductive pillars 52 , that is, the first redistribution layer 51 and the conductive layers are formed in the same conductive layer forming process.
  • the conductive pillars 52 form a vertical connection structure in the protective layer opening 121, and the bonding pads on the front side 11a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51.
  • a dielectric layer 60 is formed.
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • the packaging method further includes peeling off the first support plate 41 .
  • the first support plate 41 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
  • the packaging method further includes mounting the second support plate 42 on a surface of the dielectric layer 60 away from the encapsulation structure 10 .
  • the second support plate 42 is mounted on at least a partial area of the side of the dielectric layer 60 away from the encapsulation structure 10 . As shown in FIG. 6I , in one embodiment, the second support plate 42 is mounted on the entire area of the side of the dielectric layer 60 away from the encapsulation structure 10 .
  • the material strength of the second support plate 42 is greater than that of the dielectric layer 60 , so that the mechanical strength of the packaging structure during the packaging process can be effectively improved and guaranteed, and the adverse effects of structural deformation can be effectively suppressed, thereby improving the effect of product packaging.
  • the second support plate 42 may also be formed on the dielectric layer 60 by spraying, printing, coating, or the like.
  • the step of attaching the second support plate 42 may also be performed before peeling off the first support plate 41 .
  • the packaging method further includes grinding the second surface 10b of the encapsulation structure 10 , so as to reduce the thickness of the encapsulating structural member 10 . Preferably, it is thinned to expose the metal layer of the backside 11b of the chip 11 to be packaged.
  • the thickness of the lead frame 20 may be equal to or slightly larger than the thickness of the chip to be packaged.
  • the thickness of the lead frame 20 is also reduced to expose the thickness of the chip to be packaged 11 . part.
  • the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, when the encapsulation structure 10 is thinned to expose the back surface 11 b of the chip to be packaged 11 , the second surface 20 b of the lead frame 20 is also exposed at the same time.
  • the thickness of the lead frame 20 is equal to the thickness of the chip to be packaged, so that the process of grinding the second surface 10b of the encapsulation structure 10 can be effectively reduced.
  • a second redistribution structure 70 is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 to be packaged and the second electrical connection point of the second surface 20 b of the lead frame 20 .
  • the second redistribution structure 70 includes at least one second redistribution layer 71 .
  • the second redistribution structure 70 includes a second redistribution layer 71 .
  • the second redistribution structure 70 can also include multiple layers of second redistribution layers 71 according to design requirements, that is, repeated redistribution is performed on the backside of the chip to be packaged. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the thickness of the redistribution structure (including the second redistribution structure 70) is much smaller than the thickness of the lead frame 30' in the prior art (as in FIG. 1).
  • the general rewiring structure is 15um-45um
  • the lead frame 30' is generally 150um-450um. Therefore, the rewiring structure not only realizes the function of wiring, but also improves the thinning of the product.
  • the lead frame 20 since the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 to be packaged is realized, that is, the lead frame 20 communicates with each other.
  • the first redistribution structure 50 located on the first surface 10a of the encapsulation structure 10 and the second redistribution structure 70 located on the second surface 10b of the encapsulation structure 10 are shown.
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction.
  • the layout of the rewiring structure is more free and flexible.
  • the electrical lead-out of the front side 11a of the chip 11 to be packaged is realized by the electrical connection of the pads 111 on the front side 11a of the chip 11 to be packaged, the first rewiring structure 50 , the lead frame 20 and the second rewiring structure 70 in sequence.
  • the electrical lead-out of the back surface 11b of the chip 11 to be packaged is realized by directly electrically connecting with the second redistribution structure 70; the interconnection of different chips 11 to be packaged includes the interconnection on the same surface or the interconnection on different surfaces (For example, the interconnection between the front side of one of the chips 11 to be packaged and the back side of the other chip 11 to be packaged) can be achieved through the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
  • the backside 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 are exposed on the second surface 10b of the encapsulation structure 10, so that the encapsulation structure
  • the second redistribution structure 70 formed on the second surface 10b of the component 10 is directly overlaid on the back surface 11b of the chip 11 to be packaged and the second surface 20b of the lead frame 20 .
  • the orthographic projection of the chip 11 to be packaged is located within the orthographic projection of the second redistribution structure 70 , so that the backside 11 b of the chip to be packaged 11 is protected by the second redistribution structure 70 so as not to be exposed.
  • the method further includes forming a lead layer 80 on the second redistribution structure 70 , that is, forming a lead layer 80 on the side of the second redistribution structure 70 away from the encapsulation structure 10 . .
  • the orthographic projection of the pin layer 80 is located within the orthographic projection of the second redistribution structure 70 .
  • the spacing W1 between adjacent pin layers 80 is greater than the spacing W2 between adjacent second redistribution structures 70 located in the adjacent pin layers 80 , so that the final formation
  • the semiconductor package products of our company are not easy to be short-circuited, which improves the electrical performance of the products.
  • the semiconductor package structure 1 can be electrically connected to the outside through the pin layer 80 , and the next step can be installed through the pin layer 80 .
  • the material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
  • the lead layer 80 may not be included, but the lead layer is formed on the surface of other structures (such as PBC boards) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 is mounted by alignment .
  • the second support plate 42 is peeled off, as shown in FIG. 6M .
  • the second support plate 42 can be peeled off mechanically directly, or can be peeled off by other methods, which is not limited in this application, and can be set according to specific application environments.
  • a step of cutting off the frame body of the lead frame 20 by means of laser or mechanical cutting is also included, and the illustration of this step is omitted.
  • a structural diagram of the formed semiconductor package structure 1 may be shown in FIG. 7 .
  • FIG. 7 it is a schematic structural diagram of a semiconductor packaging structure 1 obtained by using the above-mentioned semiconductor packaging method according to the present embodiment.
  • the semiconductor package structure 1 includes an encapsulation structure 10 , a first redistribution structure 50 and a second redistribution structure 70 .
  • the encapsulation structure 10 includes opposing first surfaces 10a and second surfaces 10b, and the encapsulation structure 10 includes a lead frame assembly (mainly corresponding to the connection portion 24 and the edge portion 23 in the lead frame 20 in the aforementioned semiconductor packaging method) , a plurality of chips 11 , and an encapsulation layer 14 for encapsulating the lead frame assembly and the plurality of chips 11 .
  • the lead frame assembly is arranged on the outer circumference of each chip 11 to define the respective accommodating spaces of the chips, the accommodating space penetrates the lead frame assembly along the thickness direction T, and a plurality of the chips 11 are located in the accommodating space, so
  • the encapsulation layer 14 is filled in the accommodating space defined by the lead frame assembly. It can be seen that the respective accommodating spaces of the plurality of chips 11 defined by the lead frame assembly may correspond to the hollow regions 21 in the lead frame 20 in the aforementioned semiconductor packaging method.
  • the number of chips 11 is plural.
  • the number of chips 11 can be adjusted according to design requirements, which is not limited here.
  • the number of chips 11 is two.
  • the number of hollow regions of the lead frame 20 may be one or more.
  • each lead frame 20 is provided with two hollow regions in number. But not limited to this, the number of hollow regions 21 can be other numbers according to design requirements.
  • the lead frame 20 also includes a connection portion 24 .
  • the connection portion 24 divides the space in the lead frame 20 into a plurality of the hollow regions.
  • the chips 11 respectively located in the different hollow regions are electrically connected through the connecting portions 24 .
  • each lead frame 20 is separated by two through the connecting portions 24 , that is, the number of hollow regions 21 provided on each lead frame 20 is two, and the two hollow regions 21 It is cut off by the connecting portion 24 .
  • the two chips 11 are respectively located in two different hollow areas.
  • the chip 11 includes a front side provided with bonding pads, and a back side 11b opposite to the front side.
  • the back side 11b is provided with a metal layer (not shown in the figure), so that both the front side 11a and the back side 11b of the chip 11 are electrically led out.
  • the front surface of the chip 11 and the first surface 20 a of the lead frame 20 are exposed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 corresponds to the front surface of the chip 11 and is formed on the first surface 10 a of the encapsulation structure 10 .
  • the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and is connected to the first surface of the lead frame 20 .
  • the first electrical connection point of one side 20a is electrically connected.
  • the first redistribution structure 50 includes at least one first redistribution layer 51 .
  • the first redistribution structure 50 includes a first redistribution layer 51 .
  • the first redistribution structure 50 may also include multiple layers of first redistribution layers 51 according to design requirements, that is, repeated redistribution is performed on the front side of the chip. For example, more redistribution structures and more dielectric layers can be formed in the same way, which can be adjusted according to design requirements.
  • a protective layer 12 is provided on the front surface of the chip 11 .
  • a protective layer opening 121 is formed on the protective layer 12 .
  • Conductive pillars 52 formed by filling the conductive medium are provided in the protective layer opening 121 .
  • the first redistribution layer 51 and the conductive pillar 52 may be formed in the same conductive layer forming process.
  • the second redistribution structure 70 corresponds to the back surface of the chip 11 and is formed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 is electrically connected to the metal layer of the back surface 11 b of the chip 11 and the second electrical connection point of the second surface 20 b of the lead frame 20 .
  • the second redistribution structure 70 includes at least one second redistribution layer 71 .
  • the second redistribution structure 70 includes a second redistribution layer 71 .
  • the second redistribution structure 70 includes multiple layers of second redistribution layers 71 , that is, repeated redistribution is performed on the backside of the chip. For example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 , the double-sided interconnection between the front and the back of the chip 11 is realized, that is, the lead frame 20 is connected to the The first redistribution structure 50 on the first surface 10 a of the encapsulation structure 10 and the second redistribution structure 70 on the second surface 10 b of the encapsulation structure 10 .
  • the semiconductor package structure of this embodiment requires less space, especially the space in the thickness direction.
  • the layout of the rewiring structure is more free and flexible.
  • the electrical lead-out of the front side 11a of the chip 11 is realized through the electrical connection of the bonding pads on the front side 11a of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70;
  • the electrical lead-out of the backside 11b is realized by being directly electrically connected to the second redistribution structure 70;
  • the interconnection of different chips 11 includes the interconnection on the same plane or the interconnection on different planes (such as the front side and the front side of one of the chips 11).
  • the interconnection of the backside of the other chip 11 can be realized by the electrical connection of the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 .
  • the thickness of the lead frame 20 is approximately equal to the thickness of the chip 11 .
  • the back surface 11 b of the chip 11 and the second surface 20 b of the lead frame 20 are both exposed on the second surface 10 b of the encapsulation structure 10 .
  • the second redistribution structure 70 formed on the second surface 10b of the encapsulation structure 10 is directly overlaid on the back surface 11b of the chip 11 and the second surface 20b of the lead frame 20 to further reduce the overall thickness.
  • the orthographic projection of the chip 11 is located within the orthographic projection of the second redistribution structure 70 , so as to protect the back surface 11 b of the chip 11 from being exposed by the second redistribution structure 70 .
  • the encapsulation structure 10 further includes a dielectric layer 60 .
  • the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10 a of the encapsulation structure 10 .
  • the dielectric layer 60 can be formed by molding film, or the dielectric layer 60 can be formed by lamination or printing.
  • the dielectric layer 60 can be made of insulating materials, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), etc., preferably an epoxy compound.
  • PBO Polybenzoxazole
  • the encapsulation structure 10 further includes a lead layer 80 , and the lead layer is located on a side of the second redistribution structure 70 away from the encapsulation structure 10 .
  • the orthographic projection of the pin layers 80 is located within the orthographic projection of the second redistribution structure 70 , that is, the spacing W1 between adjacent pin layers 80 is greater than that of the adjacent pin layers 80 .
  • the distance W2 between the adjacent second redistribution structures 70 makes it difficult to short-circuit when the finally formed semiconductor package product is soldered with tin or other materials, thereby improving the electrical performance of the product.
  • the semiconductor package structure 1 is electrically connected to the outside through the pin layer 80 , and is installed in the next step through the pin layer 80 .
  • the material of the pin layer 80 may be tin, but not limited to tin, and may also be nickel-gold alloy, or other metals.
  • the pin layer 80 may not be included, and the pin layer may be formed on the surface of other structures (such as a PCB board) on which the semiconductor package structure 1 is to be mounted, and the semiconductor package structure 1 may be mounted thereon by alignment .
  • the connecting portion 24 of the lead frame 20 includes a first portion 241 , an intermediate portion 242 and a second portion 243 that are connected in sequence.
  • the first portion 241 and the middle portion 242 form a first angle ⁇
  • the second portion 243 and the middle portion 242 form a second angle ⁇ .
  • the first included angle ⁇ and the second included angle ⁇ are both approximately equal to 90 degrees, so that the first portion 241 and the second portion 243 are approximately parallel to each other, so that the structure of the connecting portion 24 can be more stable.
  • one end of the first part 241 away from the connecting part 24 and one end of the second part 243 away from the connecting part 24 are located on the same side of the connecting part 24 , so that the structure of the connecting part 24 can be more compact.
  • the lead frame 20 further includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is exposed on the surface of the encapsulation structure 10, and the other end extends toward the hollow area 21; each hollow area 21 can be provided with a number of mutually isolated edge portion 23 .
  • the edge portion 23 includes a main body 231 and a supporting portion 232 . One end of the supporting portion 232 away from the main body 231 is exposed on the surface of the encapsulating structural member 10 , and the other end is connected to the main body 231 .
  • the number of the support portion 232 may be one or a plurality of them. When the number of the support parts 232 is plural, the plural support parts 232 are provided at intervals.
  • the main body 231 may be square, bar-shaped or L-shaped.
  • the L-shaped edge portion 23 of the main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24 .
  • the lead frame 20 is integrally formed, positioned and encapsulated in the encapsulation structure 10, the production cost is greatly saved, and the overall production efficiency is improved.
  • FIG. 8A a schematic diagram of the front side connection of the semiconductor package structure (as shown in FIG. 8A ) and the back side are given.
  • FIG. 8B A schematic diagram of the connection (shown in Figure 8B). In the figure, only a schematic connection is made for the rewiring structure to illustrate the connection relationship.
  • the lead frame 20 is electrically connected to the first redistribution structure 50 and the second redistribution structure 70 to realize the interconnection of the front side and the back side of the chip 11, and can also realize the double-sided interconnection of different chips 11 ( For example, the interconnection of the front side of one chip 11 and the back side of the other chip 11 ) is achieved by the electrical connection of the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , and the second redistribution structure 70 .
  • the lead frame 20 shown in FIG. 8A and FIG. 8B includes two upper and lower hollow regions 21 along the vertical direction of the paper surface, and each hollow region 21 is respectively placed with a chip 11 .
  • the front side of the chip 11 in the upper hollow area 21 is electrically connected to the connecting portion 24 and one of the edge portions 23 of the upper hollow area 21 through the first redistribution structure 50 respectively;
  • the front surface of the chip 11 in the hollow area 21 is electrically connected to the two edge portions 23 of the hollow area 21 located below through the first redistribution structure 50 respectively.
  • the backside of the chip 11 in the upper hollow region 21 is electrically connected to the other two edge portions 23 of the upper hollow region 21 through the second redistribution structure 70 ;
  • the back surface is electrically connected to the connection portion 24 through the second redistribution structure 70 . That is, the front surface of the chip 11 in the upper hollow region 21 is electrically connected to the back surface of the chip 11 in the lower hollow region 21 through the first redistribution structure 50 , the connection portion 24 of the lead frame 20 , the second redistribution structure 70 and the lower hollow region 21 in sequence. connect.
  • the lead frame 20 extends from the first surface 10a of the encapsulation structure 10 to the second surface 10b of the encapsulation structure 10 along the thickness direction T, and includes the first portion 27 and Second part 28.
  • the width w21 of the first portion 27 is greater than the width w22 of the second portion 28 , that is, the lead frame 20 having a stepped structure in cross section is formed.
  • the relatively wide contact surface of the first portion 27 can facilitate the formation of the first redistribution structure 50 over the lead frame 20, and can provide a relatively large area of support for the first redistribution structure 50;
  • the bonding force between the lead frame 20 and the encapsulation layer 14 is enhanced and the strength of the lead layer 80 of the semiconductor package structure on the PCB is enhanced, thereby enhancing the board-level reliability performance of the product.
  • the backside of the chip 11 is not provided with a metal layer, so that the backside of the chip 11 is not electrically drawn out, and only the front side of the chip 11 needs to be electrically drawn out, that is, the second rewiring structure 70 and the backside of the chip 11 Not electrically connected.
  • the electrical connection of the front surface of the chip 11 is realized through the electrical connection of the bonding pads on the front surface 11 a of the chip 11 , the first redistribution structure 50 , the lead frame 20 , and the second redistribution structure 70 in sequence.
  • the electricity from the front side of the chip can be directly led to the back side of the chip through the lead frame, and the copper pillar components are no longer needed, the wiring area is increased, the multi-layer wiring process can be realized, and the freedom of product design can be increased. It increases the electrical reliability of the product; at the same time, it saves the production cost and improves the overall production efficiency.
  • the semiconductor package structure of the present embodiment improves the thinning of the product by setting the overall structure, and can enhance the electrical reliability of the product.
  • the hollow area penetrates the lead frame along the thickness direction, and a plurality of chips are located in the hollow area, which greatly reduces the thickness of the product.
  • the technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, without the need for copper pillar components, which increases the interconnection area, realizes the multi-layer wiring process, increases the freedom of product design, and enhances the product design. At the same time, it saves the production cost and improves the overall production efficiency.
  • the content of the semiconductor packaging method of this embodiment is basically the same as that of the semiconductor packaging method in Embodiment 1, the difference is that in the semiconductor packaging method of this embodiment, the step of forming the protective layer 12 on the front surface of the chip 11 to be packaged It is placed after the encapsulation of the chip 11 to be packaged and the lead frame 20 is completed, that is, after the encapsulation structure 10 is formed.
  • the semiconductor packaging method of this embodiment includes:
  • step 100 as shown in FIG. 10A , the chip 11 to be packaged and the lead frame 20 are mounted on the carrier board 3 through an adhesive layer.
  • the backside of the chip 11 to be packaged faces upward, and the front face faces the carrier board 3 .
  • the lead frame 20 is provided with a hollow area 21 extending through the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21 .
  • step 200 as shown in FIG. 10B , by covering the encapsulation layer 14 on the entire carrier 3 (that is, covering the encapsulation layer 14 on the chip 11 to be packaged, the lead frame 20 and the exposed part of the carrier 3 ) ), and fill in the hollow area 21 of the lead frame 20 to encapsulate the chip to be packaged 11 and the lead frame 20 to form the encapsulation structure 10 .
  • the packaging method further includes peeling off the carrier board 3 to expose the first surface 10 a of the packaging structure 10 .
  • a protective layer 12 is formed on the first surface 10 a of the encapsulation structure 10 .
  • the protective layer 12 can be a transparent film layer to utilize the protective layer 12 transparency for positioning. In addition, positioning can be assisted by the lead frame 20 to improve the positional accuracy of the laser drilling.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne un procédé d'encapsulation de semi-conducteur et une structure d'encapsulation de semi-conducteur. Selon un exemple, le procédé d'encapsulation de semi-conducteur comprend les étapes consistant à : monter une grille de connexion et de multiples puces à encapsuler sur une plaque porteuse, lesdites multiples puces étant situées dans une région évidée de la grille de connexion ; permettre à une couche d'encapsulation de recouvrir lesdites puces, la grille de connexion et une portion exposée de la plaque support, et remplir la couche d'encapsulation dans la région évidée, de façon à former un élément de structure d'encapsulation ; et former une première structure de recâblage sur une première surface de l'élément de structure d'encapsulation, la première structure de recâblage étant reliée électriquement aux surfaces avant desdites puces et un premier côté de la grille de connexion, et former une deuxième structure de recâblage sur une deuxième surface de l'élément de structure d'encapsulation, la deuxième structure de recâblage étant reliée électriquement à un deuxième côté, disposé à l'opposé du premier côté, de la grille de connexion. La structure d'encapsulation de semi-conducteur est fabriquée par le procédé d'encapsulation de semi-conducteur.
PCT/CN2020/141965 2020-07-31 2020-12-31 Procédé d'encapsulation de semi-conducteur et structure d'encapsulation de semi-conducteur WO2022021799A1 (fr)

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