TWI665740B - 堆疊封裝結構的製造方法 - Google Patents

堆疊封裝結構的製造方法 Download PDF

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TWI665740B
TWI665740B TW106135989A TW106135989A TWI665740B TW I665740 B TWI665740 B TW I665740B TW 106135989 A TW106135989 A TW 106135989A TW 106135989 A TW106135989 A TW 106135989A TW I665740 B TWI665740 B TW I665740B
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Taiwan
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conductive
circuit carrier
interposer
package structure
die
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TW106135989A
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TW201828372A (zh
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王啓安
徐宏欣
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力成科技股份有限公司
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Abstract

本發明提供一種堆疊封裝結構的製造方法，其包含至少以下步驟。形成第一封裝結構且在第一封裝結構上形成第二封裝結構。第一封裝結構包含電路載體以及設置於電路載體上的晶粒。形成第一封裝結構包含：在電路載體上提供導電中介板，經由密封體密封導電中介板，以及移除密封體和導電中介板的板的一部分。導電中介板包含板體、從板體分別延伸到電路載體和晶粒的多個導電柱以及導電突起。導電突起設置於晶粒上，且導電柱電性連接到電路載體。第二封裝結構經由導電中介板電性連接到第一封裝結構。

Description

堆疊封裝結構的製造方法
本發明是有關於一種封裝結構的製造方法，且特別是有關於一種堆疊封裝(package-on-package，POP)結構的製造方法。
為了使電子產品設計實現輕、薄、短且小，半導體封裝技術正持續進步，以嘗試開發出體積較小、重量較輕、整合度較高且更具市場競爭力的產品。舉例來說，已開發例如POP等3D堆疊技術以滿足較高封裝密度的要求。因此，如何以較低製造成本實現更薄的POP結構已經變為本領域中的研究人員的挑戰。
本發明提供一種堆疊封裝(POP)結構的製造方法，其減少所述結構的總體厚度和製造成本。
本發明的POP結構的製造方法。所述方法至少包含以下步驟。形成第一封裝結構且在第一封裝結構上形成第二封裝結構。第一封裝結構包含電路載體以及設置於電路載體上的晶粒。 形成第一封裝結構包含：在電路載體上提供導電中介板，經由密封體密封導電中介板，以及移除密封體的一部分和導電中介板的板體。導電中介板包含板體、多個導電柱以及從板體分別延伸到電路載體和晶粒的導電突起。導電突起設置於晶粒上，且導電柱電性連接到電路載體。第二封裝結構經由導電中介板電性連接到第一封裝結構。
在本發明的一實施例中，在電路載體上提供導電中介板之後，導電突起在電路載體上的正投影面積等於晶粒在電路載體上的正投影面積。
在本發明的一實施例中，導電中介板的板體包括中心區以及連接到中心區的外圍區，導電突起形成於中心區中且導電柱形成於外圍區中。
在本發明的一實施例中，晶粒透過覆晶接合電性連接到電路載體。
在本發明的一實施例中，導電中介板的導電柱透過多個導電膏連接到第一封裝結構的電路載體。
本發明提供一種POP結構的製造方法。所述方法至少包含以下步驟。形成第一封裝結構且在第一封裝結構上形成第二封裝結構。第一封裝結構包含電路載體以及設置於電路載體上的晶粒。形成第一封裝結構包含：在電路載體上提供導電中介板，經由密封體密封導電中介板，以及移除密封體的一部分以及導電中介板的一部分。導電中介板包含晶粒定位區。晶粒定位區在電路 載體上的正投影面積等於晶粒在電路載體上的正投影面積。密封體暴露出導電中介板的表面。第二封裝結構經由導電中介板電性連接到第一封裝結構。
在本發明的一實施例中，在移除密封體的部分和導電中介板的板體的部分之後，導電柱中的每一者的頂部表面與導電突起的頂部表面共面。
在本發明的一實施例中，在移除密封體的部分和導電中介板的板體的部分之後，在導電突起的頂部表面上形成導熱介面材料。
在本發明的一實施例中，第二封裝結構包括設置於導電柱上的多個導電端子，在第一封裝結構上形成第二封裝之後，導電端子中的每一者的高度等於導熱介面材料的厚度。
在本發明的一實施例中，在移除密封體的部分以及導電中介板的部分之後，密封體的厚度大於導電線中的每一者的線弧高度。
基於上述，由於密封體的厚度減少且導電中介板的板體也被移除以形成第一封裝結構，因此從密封體暴露出的導電中介板的導電柱可以作為第一封裝結構與第二封裝結構之間的電性連接路徑，且被密封體暴露出的導電突起可以作為散熱片，以使散熱效率更好。換句話說，不必在第一封裝結構與第二封裝結構之間設置用於電性連接其間的額外的中介板(interposer)。在移除密封體的一部分和導電中介板的板體之後，可減少封裝結構的總厚 度，進而實現封裝小型化。形成於導電突起的頂部表面上的導熱介面材料(thermal interface material)有利於將第二封裝結構接合到第一封裝結構，且改善第一封裝結構的散熱。當提供導電中介板在電路載體上時，對位視窗可以與晶粒對位。也就是，不需要形成額外的對位標記以使導電中介板與晶粒對位。因此，可以減少POP結構的總體厚度並可實現較低的製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10、30‧‧‧堆疊封裝結構
50、130、330‧‧‧導電中介板
52、132、332‧‧‧板體
52a、54a、56a、132b、134a、332b、334a、S1‧‧‧頂部表面
52b、132c、332c、S2‧‧‧底部表面
54、134、334‧‧‧導電柱
54h‧‧‧高度
56‧‧‧導電突起
56t、T1、T1'、T2‧‧‧厚度
60‧‧‧導熱介面材料
100-1、100-2、100-3‧‧‧第一封裝結構
110‧‧‧第一電路載體
112‧‧‧核心層
114‧‧‧頂部電路層
114a‧‧‧導電接墊
116‧‧‧底部電路層
116a‧‧‧導電接墊
118‧‧‧導電結構
120、320‧‧‧第一晶粒
120a‧‧‧主動表面
120b‧‧‧非主動表面
122‧‧‧導電凸塊
132a、332a‧‧‧對位視窗
140‧‧‧導電膏
150‧‧‧密封體
200‧‧‧第二封裝結構
202‧‧‧第二晶粒
204‧‧‧導電端子
210‧‧‧第二電路載體
360‧‧‧導電線
370‧‧‧黏著層
C‧‧‧中心區
H1、H2‧‧‧高度
P‧‧‧外圍區
圖1A到圖1E是繪示根據本發明的實施例的POP結構的製造方法的剖面示意圖。
圖2A到圖2D是繪示根據本發明的另一實施例的POP結構的製造方法的剖面示意圖。
圖3是繪示根據本發明的實施例的導電中介板的立體示意圖。
圖4A到圖4E是繪示根據本發明的又一實施例的POP結構的製造方法的剖面示意圖。
圖1A到圖1E是繪示根據本發明的實施例的POP結構的 製造方法的剖面示意圖。參考圖1A，提供第一電路載體(circuit carrier)110且第一晶粒(die)120接合於第一電路載體110上。第一電路載體110可以具有頂部表面S1以及與頂部表面S1相對的底部表面S2。舉例來說，第一電路載體110可包含核心層(core layer)112、設置於頂部表面S1上的頂部電路層114以及設置於第一電路載體110的底部表面S2上的底部電路層116。核心層112設置於頂部電路層114與底部電路層116之間且電性連接頂部電路層114和底部電路層116。在一些實施例中，頂部電路層114和底部電路層116可以分別包含多個導電接墊(conductive pad)114a和116a，用於進一步電性連接。此外，導電接墊114a和導電接墊116a可以透過相同材料和相同製程形成，例如透過微影(photolithography)和蝕刻(etching)製程使用銅、焊料、金、鎳或類似物來形成。在一些其它實施例中，導電接墊114a和導電接墊116a可以根據設計要求透過不同材料和/或不同製程形成。
核心層112可進一步包含多個嵌入電路層，其作為電性連接到頂部電路層114和底部電路層116的中間電路層。核心層112可以包含基底層(base layer)以及穿透所述基底層的多個導電通孔(conductive vias)。核心層112的導電通孔的兩個相對端可以電性連接到頂部電路層114的導電接墊114a和底部電路層116的導電接墊116a。在一些實施例中，多個導電結構118可形成於第一電路載體110的底部表面S2上。舉例來說，導電結構118的材料可包含銅、錫、金、鎳或其它合適的導電材料。導電結構 118可以例如為導電凸塊(conductive bump)、導電柱(conductive pillar)或透過植球製程(ball placement process)以及回焊製程(reflow process)形成的焊球(solder ball)。可以利用其它可能形式和形狀的導電結構118以進行進一步電性連接。在一些實施例中，導電結構118可以形成陣列，所述陣列被佈置成在第一電路載體110的底部表面S2上具有微間距(fine pitch)以用於後續製程中的需求。
第一晶粒120可設置於第一電路載體110的頂部表面S1上。第一晶粒120可透過覆晶接合(flip-chip bonding)電性連接到第一電路載體110。第一晶粒120可以透過其它方法接合到第一電路載體110。將在後續其它實施例中描述細節。在本實施例中，舉例來說，第一晶粒120可包含面朝第一電路載體110的主動表面(active surface)120a以及與主動表面120a相對的非主動表面(inactive surface)120b。另外，第一晶粒120的主動表面120a可以透過多個導電凸塊122耦合到第一電路載體110的頂部電路層114的導電接墊114a。導電凸塊122可以是銅凸塊(copper bumps)。在一些實施例中，焊料(未示出)可以施加到導電凸塊122的表面上以與導電接墊114a耦合。第一晶粒120可以是例如特殊應用積體電路(Application-Specific Integrated Circuit，ASIC)。在一些實施例中，第一晶粒120可以用來執行邏輯應用(logic applications)，但本發明並不以此為限。其它合適的主動裝置也可以用作第一晶粒120。
參考圖1B，導電中介板(conductive interposer)50提供於第一電路載體110上。在一些實施例中，導電中介板50包含板體(plate)52、多個導電柱54以及導電突起(conductive protrusion)56。舉例來說，板體52具有頂部表面52a以及與頂部表面52a相對的底部表面52b。導電柱54和導電突起56形成於板體52的底部表面52b上。在一些實施例中，導電柱54和導電突起56分別延伸到第一電路載體110和第一晶粒120。在提供導電中介板50於第一電路載體110上之後，板體52設置於第一電路載體110上方，導電柱54電性連接到第一電路載體110且導電突起56設置於第一晶粒120上。
在一些實施例中，導電突起56的大小和形狀可以相似或等於第一晶粒120。舉例來說，在第一電路載體110上提供導電中介板50之後，導電突起56可以覆蓋第一晶粒120。導電突起56在第一電路載體110上的正投影面積(orthographic projection area)可以與第一晶粒120在第一電路載體110上的正投影面積重疊。在一些實施例中，導電突起56在第一電路載體110上的正投影面積等於第一晶粒120在第一電路載體110上的正投影面積。在一些實施例中，導電突起56可以與第一晶粒120的非主動表面120b直接接觸。在一些其它實施例中，導電突起56可以使用導熱介面材料(thermal interface material)(未示出)貼附在第一晶粒120的非主動表面120b上。
舉例來說，導電中介板50可包含晶粒定位區(die positioning region)。在第一電路載體110上提供導電中介板50之後，導電中介板50的晶粒定位區可以對應於第一晶粒120。舉例來說，導電中介板50可以透過晶粒定位區與第一晶粒120對位。在一些實施例中，導電中介板50的板體52可包含中心區C以及連接到中心區C的外圍區P。中心區C可稱為晶粒定位區。導電突起56可以形成於中心區C中，且圍繞導電突起56的導電柱54可以形成於外圍區P中。
在一些實施例中，導電突起56的厚度56t小於導電柱54中的每一者的高度54h。舉例來說，在第一電路載體110上提供導電中介板50之後，板體52的頂部表面52a可以平行於第一電路載體110的頂部表面S1。導電柱54的材料可包含例如鋁、銅、鎳、金或其合金等導電材料。另外，導電柱54可以根據導電柱54的高度要求，透過電鍍(electroplating)、微影和蝕刻或其組合形成。舉例來說，對於較厚的第一晶粒120，導電柱54可以透過電鍍和蝕刻的組合而形成，以獲得具有較長高度的導電柱54。然而，可利用其它合適的形成方法且其在本發明中並不解釋為限制。導電突起56的材料和形成過程可類似於導電柱54。板體52的材料可包含與導電柱54相同的導電材料。板體52和導電柱54的大小和形狀在本發明中並不解釋為限制。
在一些實施例中，板體52、導電柱54以及導電突起56可以一體地形成。在一些其它實施例中，板體52可以與導電柱54和導電突起56分開製造。舉例來說，板體52的材料可包含導電 材料或非導電材料，例如玻璃、剛性塑膠(rigid plastic)或類似物等。其它合適的材料可以適於作為板體52，只要所述材料能夠承受於其上形成的導電柱54和導電突起56的處理製程即可。
在一些實施例中，導電中介板50的導電柱54透過多個導電膏(conductive paste)140耦合到第一電路載體110。舉例來說，在第一電路載體110上設置導電中介板50之前，導電膏140可以對應於第一電路載體110的頂部表面S1上的導電接墊114a而形成。在一些實施例中，在第一電路載體110上提供導電中介板50之前，導電膏140可以形成於導電中介板50的導電柱54上。舉例來說，導電膏140的材料可包含焊膏(solder paste)、銀膏(silver paste)或具有良好導電率的其它合適的材料。在一些其它實施例中，在透過導電膏140在第一電路載體110的頂部表面S1上設置導電中介板50的導電柱54之後，可以在第一電路載體110的頂部表面S1上執行回焊製程，以增強導電中介板50與第一電路載體110之間的接合能力和導電率。
參考圖1C，密封體(encapsulant)150形成於第一電路載體110的頂部表面S1上，以密封導電中介板50和第一晶粒120。舉例來說，密封體150可包含由模製製程(molding process)形成的模製化合物(molding compound)。在一些實施例中，密封體150可以透過絕緣材料形成，例如環氧樹脂(epoxy resin)或其它合適的樹脂，其不限於此。此外，密封體150的厚度T1可以大於板體52的頂部表面52a與第一電路載體110的頂部表面S1之 間的距離，以完全密封導電中介板50。在一些實施例中，密封體150的厚度T1可等於板體52的頂部表面52a與第一電路載體110的頂部表面S1之間的距離。也就是，在形成密封體150之後，密封體150可從暴露出板體52的頂部表面52a。在一些其它實施例中，密封體150可以密封第一晶粒120且部分地覆蓋導電中介板50的導電柱54。換句話說，在第一晶粒120由密封體150密封時，密封體150的厚度T1可小於導電中介板50的底部表面52b與第一電路載體110的頂部表面S1之間的距離。
參考圖1D，移除密封體150的一部分和導電中介板50的板體52，以形成第一封裝結構100-1。在一些實施例中，可透過研磨製程(grinding process)移除密封體150和板體52。此外，研磨製程可以是機械研磨、化學機械拋光(chemical mechanical polishing，CMP)、蝕刻或不限於此的其它合適的方法。另外，在移除密封體150的部分和導電中介板50的板體52之後，密封體150暴露出導電柱54中的每一者的至少頂部表面54a以及導電突起56的至少頂部表面56a。在移除過程之後，導電柱54可以用於進一步電性連接，且導電突起56可以用於散熱，以實現較好的散熱效率。在一些實施例中，在移除過程之後，導電柱54中的每一者的頂部表面54a可以與導電突起56的頂部表面56a以及密封體150的頂部表面共面。如圖1D所示的移除過程能夠說明封裝結構整體的總厚度減少，進而實現封裝小型化。在一些其它實施例中，不僅密封體150的部分和導電中介板50的板體52，還有導電柱 54的一部分和導電突起56的一部分也被移除，以實現更薄的第一封裝結構100-1。
參考圖1E，第二封裝結構200形成於第一封裝結構100-1上，以形成堆疊封裝(POP)結構10。舉例來說，第二封裝結構200電性連接到導電中介板50的導電柱54。在一些實施例中，第二封裝結構200可包含第二晶粒202，例如動態隨機存取記憶體(DRAM)或NAND快閃記憶體。在一些實施例中，第二封裝結構200中也可以利用其它合適的主動裝置。在一些實施例中，第二封裝結構200包含連接到導電柱54的頂部表面54a的多個導電端子(conductive terminals)204。因此，導電端子204可以作為第二封裝結構200與第一封裝結構100-1之間的電性連接路徑。在一些實施例中，第二晶粒202和導電端子204可以透過第二電路載體210電性連接。舉例來說，第二電路載體210可包含與第一電路載體110相似的形成構造。
在一些實施例中，在移除密封體150的部分和導電中介板50的板體52之後，導熱介面材料(thermal interface material，TIM)60可形成於導電突起56的頂部表面56a上。TIM 60可用以有利地將第二封裝結構200接合到第一封裝結構100-1。在一些實施例中，TIM 60可用以改善第一封裝結構100-1的散熱。舉例來說，在第一封裝結構100-1上形成第二封裝結構200之後，TIM 60可以與第二封裝結構200和第一封裝結構100-1熱接觸(thermal contact)或者熱電耦(thermal couple)於這兩者之間，以用於增 強散熱效率。在一些實施例中，TIM 60具有足夠厚度，以接合在導電突起56與第二封裝結構200之間。舉例來說，在接合第一封裝結構100-1和第二封裝結構200之後，TIM 60的厚度可實質上等於導電端子204中的每一者的高度。TIM 60可有利於平衡總體POP結構10，且在後續進行可靠性測試(reliability test)期間，TIM 60可分擔施加到POP結構10上的應力，進而增加POP結構10的可靠性。
圖2A到圖2D是繪示根據本發明的另一實施例的POP結構的製造方法的剖面示意圖，且圖3是繪示根據本發明的實施例的導電中介板的立體示意圖。參考圖2A和圖3，如圖1A中所繪示提供第一電路載體110以及設置於第一電路載體110上的第一晶粒120。為簡潔起見於此省略了詳細描述。
在提供第一電路載體110和第一晶粒120之後，在第一電路載體110上提供導電中介板130。在一些實施例中，導電中介板130可包含板體132以及多個導電柱134。另外，板體132可以具有對位視窗(alignment window)132a，且導電柱134可以從板體132延伸到第一電路載體110。舉例來說，導電中介板130的板體132可包含中心區C(也稱為晶粒定位區)以及連接到中心區C的外圍區P。此外，板體132的對位視窗132a可形成於對應於第一晶粒120的中心區C處且導電柱134可形成於外圍區P處。舉例來說，導電柱134可以沿著板體132的邊緣佈置且垂直於板體132形成。
板體132的對位視窗132a可以暴露出第一晶粒120。舉例來說，對位視窗132a的大小和形狀可以相似或等於第一晶粒120，使得導電中介板130的對位視窗132a可以透過對位視窗132a與第一晶粒120對位。在一些實施例中，對位視窗132a在第一電路載體110上的正投影面積與第一晶粒120在第一電路載體110上的正投影面積重疊且相等。在一些其它實施例中，第一晶粒120的至少邊緣可以從導電中介板130的板體132的對位視窗132a暴露，以用於對位。舉例來說，當在第一電路載體110上設置導電中介板130時，第一晶粒120的至少一個邊緣可透過導電中介板130的板體132的對位視窗132a定位，使得導電中介板130的導電柱134可以對應於第一電路載體110的導電接墊114a而接合。換句話說，對位視窗132a有利於定位第一晶粒120，且進一步增強導電中介板130的導電柱134與第一電路載體110之間的電性連接的準確性。對位視窗132a的數目、形狀和大小並不解釋為限制，只要當在第一電路載體110上設置導電中介板130時第一晶粒120可透過對位視窗132a定位即可，進而實現其間的精確對位。
舉例來說，導電中介板130的板體132和導電柱134可以一體地形成。導電柱134的材料和形成製程可以類似於圖1B中繪示的導電柱56，且在此不重複詳細描述。板體132的對位視窗132a可以透過機械鑽孔(mechanical drilling)、微影和蝕刻或不限於此的其它合適的方法來形成。舉例來說，板體132的對位視窗132a可以在同一過程中連同導電柱134一起形成。另外，板體132 的對位視窗132a可以在形成導電柱134之前或之後形成。形成對位視窗132a和導電柱134的順序在本發明中並不解釋為限制。
在一些實施例中，導電中介板130的導電柱134透過導電膏140連接到第一電路載體110。導電膏140的形成過程可以與圖1B中描述相似。此處不重複詳細描述。舉例來說，在第一電路載體110上接合導電中介板130之後，導電中介板130的板體132的底部表面132c可相對於第一電路載體110的頂部表面S1高於第一晶粒120的非主動表面120b。在一些其它實施例中，在第一電路載體110上接合導電中介板130之後，導電中介板130的板體132的底部表面132c和第一晶粒120的非主動表面120b可以共面。
參考圖2B，密封體150形成於第一電路載體110的頂部表面S1上，以密封導電中介板130和第一晶粒120。此外，密封體150的厚度T1'可大於導電中介板130的板體132與第一電路載體110的頂部表面S1之間的距離，以完全密封導電中介板130。在一些實施例中，密封體150的厚度T1'可等於導電中介板130的板體132與第一電路載體110的頂部表面S1之間的距離。即，在形成密封體150之後，密封體150可暴露出板體132的與底部表面132c相對的頂部表面132b。在一些其它實施例中，密封體150可以密封第一晶粒120且部分地覆蓋導電中介板130的導電柱134。換句話說，在第一晶粒120由密封體150密封時，密封體150的厚度T1'可小於導電中介板130的底部表面132c與第一電路載 體110的頂部表面S1之間的距離。
參考圖2C，移除密封體150的一部分和導電中介板130的板體132，以形成第一封裝結構100-2。所述移除過程可類似於在圖1D中繪示的實施例。此處不重複詳細描述。在移除密封體150的部分和導電中介板130的板體132之後，密封體150暴露出導電柱134中的每一者的至少頂部表面134a。因此，導電中介板130的導電柱134可以用於進一步電性連接。在一些實施例中，不僅密封體150的部分和導電中介板130的板體132，還有導電中介板130的導電柱134的一部分也被移除，以實現更薄的第一封裝結構100-2。
參考圖2D，第二封裝結構200形成於第一封裝結構100-2上，以形成POP結構20。舉例來說，第二封裝結構200電性連接到導電中介板130的導電柱134。在一些實施例中，導電端子204可以對應於導電柱134的頂部表面134a而形成。因此，導電端子204可以作為第二封裝結構200與第一封裝結構100-2之間的電性連接路徑。
圖4A到圖4E是繪示根據本發明的又一實施例的POP結構的製造方法的剖面示意圖。參考圖4A，提供第一電路載體110且第一晶粒320接合於第一電路載體110上。舉例來說，第一晶粒320可為特殊應用積體電路(ASIC)。在一些實施例中，第一晶粒320可以用來執行邏輯應用程式。然而，其在本發明中並不解釋為限制。圖4A中的實施例與圖1A中的實施例之間的主要差異 在於，第一晶粒320透過多根導電線360電性連接到第一電路載體110。
舉例來說，導電線360可以透過打線機(wire bonder)(未示出)而形成。打線機的類型可包含楔型接合(wedge bond)或球型接合(ball bond)或者不限於此的根據設計要求的其它合適的打線機。導電線360的材料可以是金、銅或不限於此的其它合適材料。在一個實施例中，導電線360可以從第一電路載體110到第一晶粒320形成。在一些其它實施例中，導電線360可以從第一晶粒320到第一電路載體110形成。導電線360的形成順序可以取決於設計要求，並不限於此。導電線360中的每一者的頂端(peak)定義為在連接第一電路載體110和第一晶粒320之後，相對於導電線360中的每一者的兩個末端的最高點。此外，導電線360中的每一者的線弧(loop)高度H1定義為導電線360中的每一者的頂端與第一電路載體110之間的距離。導電線360中的每一者的線弧高度H1取決於打線機的類型和/或設計要求。
此外，黏著層(adhesive layer)370可設置於第一晶粒320與第一電路載體110之間，以用於增強第一晶粒320到第一電路載體110的接合。舉例來說，黏著層370可以是晶粒貼附膜(die attach film)、銀膏或類似物。在一些實施例中，黏著層370的其它合適的材料可用於增強第一晶粒320與第一電路載體110之間的黏合。
參考圖4B和圖3，導電中介板330透過導電膏140接合 於第一電路載體110上。本實施例的導電膏140的接合過程類似於在圖2A中繪示的實施例。在此省略詳細描述。另外，類似於在圖2A中繪示的導電中介板130的導電中介板330包含板體332，板體332具有對位視窗332a以及多個導電柱334。此外，本實施例的導電中介板330的形成類似於在圖2A中繪示的導電中介板130。因此，在此不重複導電中介板330的形成過程的詳細描述。本實施例的導電中介板330與在圖2A實施例中繪示的導電中介板130之間的差異在於，導電中介板330的高度H2大於導電線360中的每一者的線弧高度H1。舉例來說，導電中介板330的高度H2定義為導電中介板330的板體332的頂部表面332b與第一電路載體110的頂部表面S1之間的距離。因此，在第一電路載體110上接合導電中介板330之後，導電中介板330不接觸導電線360，因此接合導電中介板330的過程不影響第一晶粒320的可靠性。
參考圖4C，密封體150形成於第一電路載體110的頂部表面S1上，以密封導電中介板330、第一晶粒320、黏著層370以及導電線360。在圖4C中繪示的實施例的密封體150的形成過程類似於圖2B中所示的實施例的密封體150的形成過程。在此省略詳細描述。此外，密封體150的厚度T2可大於導電中介板330的板體332與第一電路載體110的頂部表面S1之間的距離，以完全密封導電中介板330。在一些實施例中，密封體150的厚度T2可等於導電中介板330的板體332與第一電路載體110的頂部表面S1之間的距離。即，在形成密封體150之後，密封體150可暴 露出板體332的頂部表面332b。在一些其它實施例中，密封體150可以完全密封導電線360且部分地暴露出導電中介板330。換句話說，在密封體150密封第一晶粒320時，密封體150的厚度T2可小於導電中介板330的板體332的與頂部表面332b相對的底部表面332c與第一電路載體110的頂部表面S1之間的距離。
參考圖4D，移除密封體150的一部分和導電中介板330的板體332，以形成第一封裝結構100-3。本發明的實施例的密封體150和板體332的移除過程類似於圖2C中所繪示的實施例。在此省略詳細描述。另外，在移除密封體150的部分和導電中介板330的板體332之後，密封體150暴露出導電中介板330的導電柱334中的每一者的至少頂部表面334a。因此，導電中介板330的導電柱334可以作為導電路徑，以用於進一步電性連接。另外，如圖4D所示的移除過程能夠使封裝結構整體的總厚度減少，進而實現封裝小型化。在一些實施例中，在密封體150密封導電線360時，不僅密封體150的部分和導電中介板330的板體332，還有導電中介板330的導電柱334的一部分也被移除，進而實現更薄的第一封裝結構100-3。
參考圖4E，第二封裝結構200形成於第一封裝結構100-3上，以形成POP結構30。舉例來說，第二封裝結構200電性連接到導電中介板330的導電柱334。在一些實施例中，導電端子204可對應於導電中介板330的導電柱334的頂部表面334a而形成。因此，導電端子204可以作為第二封裝結構200與第一封裝結構 100-3之間的電性連接路徑。換句話說，第二封裝結構200的第二晶粒202透過導電端子204和導電中介板330的導電柱334電性連接到第一封裝結構100-3的第一電路載體110。
綜上所述，由於至少移除導電中介板的導電板，因此被密封體暴露出的導電柱可以作為第一封裝結構與第二封裝結構之間的電性連接路徑，且被密封體暴露出的導電突起可以作為散熱片以用於更好的散熱效率。不必在第一封裝結構與第二封裝結構之間設置用於電性連接其間的額外的中介板。在移除密封體的一部分和導電中介板的板體之後，可減少封裝結構的總厚度，進而實現封裝小型化。形成於導電突起的頂部表面上的導熱介面材料有利於將第二封裝結構接合到第一封裝結構，且改善第一封裝結構的散熱。當具有對位視窗的導電中介板設置於電路載體上時，對位視窗有利於使導電中介板與晶粒對位。因此，不需要形成額外的對位標記以對位導電中介板和晶粒，故製造成本可以減少。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (10)

  1. 一種堆疊封裝結構的製造方法，包括：形成第一封裝結構，其中所述第一封裝結構包括電路載體以及設置於所述電路載體上的晶粒，形成所述第一封裝結構包括：在所述電路載體上提供導電中介板，其中所述導電中介板包括板體、從所述板體分別延伸到所述電路載體和所述晶粒的多個導電柱以及導電突起，所述導電突起設置於所述晶粒上，所述導電柱電性連接到所述電路載體，所述導電突起在所述電路載體上的正投影面積等於所述晶粒在所述電路載體上的正投影面積，且所述導電突起直接接觸所述晶粒；經由密封體密封所述導電中介板；以及移除所述密封體的一部分和所述導電中介板的所述板體；以及在所述第一封裝結構上形成第二封裝結構，其中所述第二封裝結構經由所述導電中介板電性連接到所述第一封裝結構。
  2. 如申請專利範圍第1項所述的堆疊封裝結構的製造方法，其中在所述電路載體上提供所述導電中介板之後，所述導電突起在所述電路載體上的正投影面積與所述晶粒在所述電路載體上的正投影面積重疊。
  3. 如申請專利範圍第1項所述的堆疊封裝結構的製造方法，其中在移除所述密封體的所述部分和所述導電中介板的所述板體之後，所述密封體至少暴露出所述導電柱中的每一者的頂部表面以及所述導電突起的頂部表面。
  4. 如申請專利範圍第3項所述的堆疊封裝結構的製造方法，其中所述導電突起的厚度小於所述導電柱中的每一者的高度，在移除所述密封體的所述部分和所述導電中介板的所述板體之後，所述導電柱中的每一者的所述頂部表面與所述導電突起的所述頂部表面共面。
  5. 如申請專利範圍第3項所述的堆疊封裝結構的製造方法，其中在移除所述密封體的所述部分和所述導電中介板的所述板體之後，在所述導電突起的所述頂部表面上形成導熱介面材料，所述第二封裝結構包括設置於所述導電柱上的多個導電端子，在所述第一封裝結構上形成所述第二封裝結構之後，所述導電端子中的每一者的高度等於所述導熱介面材料的厚度。
  6. 一種堆疊封裝結構的製造方法，包括：形成第一封裝結構，其中所述第一封裝結構包括電路載體以及設置於所述電路載體上的晶粒，形成所述第一封裝結構包括：在所述電路載體上設置晶粒的步驟之後，在所述電路載體上提供導電中介板，其中所述導電中介板包括晶粒定位區，所述晶粒定位區在所述電路載體上的正投影面積等於所述晶粒在所述電路載體上的正投影面積；經由密封體密封所述導電中介板；以及移除所述密封體的一部分以及所述導電中介板的一部分，其中所述密封體暴露出所述導電中介板的表面；以及在所述第一封裝結構上形成第二封裝結構，其中所述第二封裝結構經由所述導電中介板電性連接到所述第一封裝結構。
  7. 如申請專利範圍第6項所述的堆疊封裝結構的製造方法，其中所述導電中介板包括位於所述晶粒定位區中的導電突起以及圍繞所述導電突起的多個導電柱，在所述電路載體上提供所述導電中介板之後，所述導電柱電性連接到所述電路載體且所述導電突起設置於所述晶粒上。
  8. 如申請專利範圍第7項所述的堆疊封裝結構的製造方法，其中所述導電突起的厚度小於所述導電柱中的每一者的高度，在移除所述密封體的所述部分和所述導電中介板的所述部分之後，所述密封體至少暴露出所述導電柱中的每一者的頂部表面以及所述導電突起的頂部表面。
  9. 如申請專利範圍第6項所述的堆疊封裝結構的製造方法，其中所述導電中介板包括板體以及多個導電柱，所述晶粒定位區包括形成於所述板體處的對位視窗，且所述導電柱形成於所述板體上並圍繞所述晶粒定位區，在所述電路載體上提供所述導電中介板之後，所述對位視窗與所述晶粒對位且至少暴露出所述晶粒的邊緣。
  10. 如申請專利範圍第9項所述的堆疊封裝結構的製造方法，其中所述晶粒經由多根導電線電性連接到所述電路載體，在移除所述密封體的所述部分以及所述導電中介板的所述部分之前，所述導電中介板的高度大於所述導電線中的每一者的線弧高度。
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