CN107978566A - 堆叠封装结构的制造方法 - Google Patents

堆叠封装结构的制造方法 Download PDF

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Publication number
CN107978566A
CN107978566A CN201710984049.9A CN201710984049A CN107978566A CN 107978566 A CN107978566 A CN 107978566A CN 201710984049 A CN201710984049 A CN 201710984049A CN 107978566 A CN107978566 A CN 107978566A
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China
Prior art keywords
conductive
intermediate plate
circuit carrier
crystal grain
encapsulating structure
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CN201710984049.9A
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王启安
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN107978566A publication Critical patent/CN107978566A/zh
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Abstract

本发明提供一种堆叠封装结构的制造方法，其包含至少以下步骤。形成第一封装结构且在第一封装结构上形成第二封装结构。第一封装结构包含电路载体以及设置于电路载体上的晶粒。形成第一封装结构包含：在电路载体上提供导电中介板，通过密封体密封导电中介板，以及移除密封体和导电中介板的板的一部分。导电中介板包含板体、从板体分别延伸到电路载体和晶粒的多个导电柱以及导电突起。导电突起设置于晶粒上，且导电柱电性连接到电路载体。第二封装结构通过导电中介板电性连接到第一封装结构。

Description

堆叠封装结构的制造方法
技术领域
本发明大体上涉及封装结构的制造方法，且更具体地说涉及堆叠封装(package-on-package，POP)结构的制造方法。
背景技术
为了使电子产品设计实现轻、薄、短且小，半导体封装技术正持续进步，以尝试开发出体积较小、重量较轻、集成度较高且更具市场竞争力的产品。举例来说，已开发例如POP等3D堆叠技术以满足较高封装密度的要求。因此，如何以较低制造成本实现更薄的POP结构已经变为本领域中的研究人员的挑战。
发明内容
本发明提供一种堆叠封装(POP)结构的制造方法，其减少所述结构的总体厚度和制造成本。
本发明提供一种POP结构的制造方法。所述方法至少包含以下步骤。形成第一封装结构且在第一封装结构上形成第二封装结构。第一封装结构包含电路载体以及设置于电路载体上的晶粒。形成第一封装结构包含：在电路载体上提供导电中介板，通过密封体密封导电中介板，以及移除密封体的一部分和导电中介板的板体。导电中介板包含板体、多个导电柱以及从板体分别延伸到电路载体和晶粒的导电突起。导电突起设置于晶粒上，且导电柱电性连接到电路载体。第二封装结构通过导电中介板电性连接到第一封装结构。
在本发明的一实施例中，在电路载体上提供导电中介板之后，导电突起在电路载体上的正投影面积等于晶粒在电路载体上的正投影面积。
在本发明的一实施例中，导电中介板的板体包括中心区以及连接到中心区的外围区，导电突起形成于中心区中且导电柱形成于外围区中。
在本发明的一实施例中，晶粒通过倒装芯片接合电性连接到电路载体。
在本发明的一实施例中，导电中介板的导电柱通过多个导电膏连接到第一封装结构的电路载体。
本发明提供一种POP结构的制造方法。所述方法至少包含以下步骤。形成第一封装结构且在第一封装结构上形成第二封装结构。第一封装结构包含电路载体以及设置于电路载体上的晶粒。形成第一封装结构包含：在电路载体上提供导电中介板，通过密封体密封导电中介板，以及移除密封体的一部分以及导电中介板的一部分。导电中介板包含晶粒定位区。晶粒定位区在电路载体上的正投影面积等于晶粒在电路载体上的正投影面积。密封体暴露出导电中介板的表面。第二封装结构通过导电中介板电性连接到第一封装结构。
在本发明的一实施例中，在移除密封体的部分和导电中介板的板体的部分之后，导电柱中的每一者的顶部表面与导电突起的顶部表面共面。
在本发明的一实施例中，在移除密封体的部分和导电中介板的板体的部分之后，在导电突起的顶部表面上形成导热界面材料。
在本发明的一实施例中，第二封装结构包括设置于导电柱上的多个导电端子，在第一封装结构上形成第二封装之后，导电端子中的每一者的高度等于导热界面材料的厚度。
在本发明的一实施例中，在移除密封体的部分以及导电中介板的部分之后，密封体的厚度大于导电线中的每一者的线弧高度。
基于上述，由于密封体的厚度减少且导电中介板的板体也被移除以形成第一封装结构，因此从密封体暴露出的导电中介板的导电柱可以作为第一封装结构与第二封装结构之间的电性连接路径，且被密封体暴露出的导电突起可以作为散热片，以使散热效率更好。换句话说，不必在第一封装结构与第二封装结构之间设置用于电性连接其间的额外的中介板(interposer)。在移除密封体的一部分和导电中介板的板体之后，可减少封装结构的总厚度，进而实现封装小型化。形成于导电突起的顶部表面上的导热界面材料(thermalinterface material)有利于将第二封装结构接合到第一封装结构，且改善第一封装结构的散热。当提供导电中介板在电路载体上时，对准窗口可以与晶粒对准。也就是，不需要形成额外的对准标记以使导电中介板与晶粒对准。因此，可以减少POP结构的总体厚度并可实现较低的制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A到图1E是说明根据本发明的实施例的POP结构的制造方法的剖面示意图。
图2A到图2D是说明根据本发明的另一实施例的POP结构的制造方法的剖面示意图。
图3是说明根据本发明的实施例的导电中介板的立体示意图。
图4A到图4E是说明根据本发明的又一实施例的POP结构的制造方法的剖面示意图。
附图标号说明
10、30：堆叠封装结构；
50、130、330：导电中介板；
52、132、332：板体；
52a、54a、56a、132b、134a、332b、334a、S1：顶部表面；
52b、132c、332c、S2：底部表面；
54、134、334：导电柱；
54h：高度；
56：导电突起；
56t、T1、T1'、T2：厚度；
60：导热界面材料；
100-1、100-2、100-3：第一封装结构；
110：第一电路载体；
112：核心层；
114：顶部电路层；
114a：导电衬垫；
116：底部电路层；
116a：导电衬垫；
118：导电结构；
120、320：第一晶粒；
120a：有源表面；
120b：非有源表面；
122：导电凸块；
132a、332a：对准窗口；
140：导电膏；
150：密封体；
200：第二封装结构；
202：第二晶粒；
204：导电端子；
210：第二电路载体；
360：导电线；
370：粘着层；
C：中心区；
H1、H2：高度；
P：外围区。
具体实施方式
图1A到图1E是说明根据本发明的实施例的POP结构的制造方法的剖面示意图。参考图1A，提供第一电路载体(circuit carrier)110且第一晶粒(die)120接合于第一电路载体110上。第一电路载体110可以具有顶部表面S1以及与顶部表面S1相对的底部表面S2。举例来说，第一电路载体110可包含核心层(core layer)112、设置于顶部表面S1上的顶部电路层114以及设置于第一电路载体110的底部表面S2上的底部电路层116。核心层112设置于顶部电路层114与底部电路层116之间且电性连接所述顶部电路层114和底部电路层116。在一些实施例中，顶部电路层114和底部电路层116可以分别包含多个导电衬垫(conductivepad)114a和116a，用于进一步电性连接。此外，导电衬垫114a和导电衬垫116a可以通过相同材料和相同工艺形成，例如通过光刻(photolithography)和蚀刻(etching)工艺使用铜、焊料、金、镍或类似物来形成。在一些其它实施例中，导电衬垫114a和导电衬垫116a可以根据设计要求通过不同材料和/或不同工艺形成。
核心层112可进一步包含多个嵌入电路层，其作为电性连接到顶部电路层114和底部电路层116的中间电路层。核心层112可以包含基底层(baselayer)以及穿透所述基底层的多个导电通孔(conductive vias)。核心层112的导电通孔的两个相对端可以电性连接到顶部电路层114的导电衬垫114a和底部电路层116的导电衬垫116a。在一些实施例中，多个导电结构118可形成于第一电路载体110的底部表面S2上。举例来说，导电结构118的材料可包含铜、锡、金、镍或其它合适的导电材料。导电结构118可以例如为导电凸块(conductivebump)、导电柱(conductivepillar)或通过植球工艺(ball placementprocess)以及回焊工艺(reflow process)形成的焊球(solderball)。可以利用其它可能形式和形状的导电结构118以进行进一步电性连接。在一些实施例中，导电结构118可以形成阵列，所述阵列被布置成在第一电路载体110的底部表面S2上具有微间距(fine pitch)以用于后续工艺中的需求。
第一晶粒120可设置于第一电路载体110的顶部表面S1上。第一晶粒120可通过倒装芯片接合(flip-chip bonding)电性连接到第一电路载体110。第一晶粒120可以通过其它方法接合到第一电路载体110。将在后续其它实施例中描述细节。在本实施例中，举例来说，第一晶粒120可包含面朝第一电路载体110的有源表面(active surface)120a以及与有源表面120a相对的非有源表面(inactive surface)120b。另外，第一晶粒120的有源表面120a可以通过多个导电凸块122耦合到第一电路载体110的顶部电路层114的导电衬垫114a。导电凸块122可以是铜凸块(copper bumps)。在一些实施例中，焊料(未示出)可以施加到导电凸块122的表面上以与导电衬垫114a耦合。第一晶粒120可以是例如专用集成电路(Application-Specific Integrated Circuit，ASIC)。在一些实施例中，第一晶粒120可以用来执行逻辑应用(logic applications)，但本发明并不以此为限。其它合适的有源装置也可以用作第一晶粒120。
参考图1B，导电中介板(conductive interposer)50提供于第一电路载体110上。在一些实施例中，导电中介板50包含板体(plate)52、多个导电柱54以及导电突起(conductive protrusion)56。举例来说，板体52具有顶部表面52a以及与顶部表面52a相对的底部表面52b。导电柱54和导电突起56形成于板体52的底部表面52b上。在一些实施例中，导电柱54和导电突起56分别延伸到第一电路载体110和第一晶粒120。在提供导电中介板50于第一电路载体110上之后，板体52设置于第一电路载体110上方，导电柱54电性连接到第一电路载体110且导电突起56设置于第一晶粒120上。
在一些实施例中，导电突起56的大小和形状可以相似或等于第一晶粒120。举例来说，在第一电路载体110上提供导电中介板50之后，导电突起56可以覆盖第一晶粒120。导电突起56在第一电路载体110上的正投影面积(orthographic projection area)可以与第一晶粒120在第一电路载体110上的正投影面积重叠。在一些实施例中，导电突起56在第一电路载体110上的正投影面积等于第一晶粒120在第一电路载体110上的正投影面积。在一些实施例中，导电突起56可以与第一晶粒120的非有源表面120b直接接触。在一些其它实施例中，导电突起56可以使用导热界面材料(thermal interface material)(未示出)贴附在第一晶粒120的非有源表面120b上。
举例来说，导电中介板50可包含晶粒定位区(die positioning region)。在第一电路载体110上提供导电中介板50之后，导电中介板50的晶粒定位区可以对应于第一晶粒120。举例来说，导电中介板50可以通过晶粒定位区与第一晶粒120对准。在一些实施例中，导电中介板50的板体52可包含中心区C以及连接到中心区C的外围区P。中心区C可称为晶粒定位区。导电突起56可以形成于中心区C中，且围绕导电突起56的导电柱54可以形成于外围区P中。
在一些实施例中，导电突起56的厚度56t小于导电柱54中的每一者的高度54h。举例来说，在第一电路载体110上提供导电中介板50之后，板体52的顶部表面52a可以平行于第一电路载体110的顶部表面S1。导电柱54的材料可包含例如铝、铜、镍、金或其合金等导电材料。另外，导电柱54可以根据导电柱54的高度要求，通过电镀(electroplating)、光刻和蚀刻或其组合形成。举例来说，对于较厚的第一晶粒120，导电柱54可以通过电镀和蚀刻的组合而形成，以获得具有较长高度的导电柱54。然而，可利用其它合适的形成方法且其在本发明中并不解释为限制。导电突起56的材料和形成过程可类似于导电柱54。板体52的材料可包含与导电柱54相同的导电材料。板体52和导电柱54的大小和形状在本发明中并不解释为限制。
在一些实施例中，板体52、导电柱54以及导电突起56可以一体地形成。在一些其它实施例中，板体52可以与导电柱54和导电突起56分开制造。举例来说，板体52的材料可包含导电材料或非导电材料，例如玻璃、刚性塑料(rigid plastic)或类似物等。其它合适的材料可以适于作为板体52，只要所述材料能够承受于其上形成的导电柱54和导电突起56的处理工艺即可。
在一些实施例中，导电中介板50的导电柱54通过多个导电膏(conductive paste)140耦合到第一电路载体110。举例来说，在第一电路载体110上设置导电中介板50之前，导电膏140可以对应于第一电路载体110的顶部表面S1上的导电衬垫114a而形成。在一些实施例中，在第一电路载体110上提供导电中介板50之前，导电膏140可以形成于导电中介板50的导电柱54上。举例来说，导电膏140的材料可包含焊膏(solder paste)、银膏(silverpaste)或具有良好导电率的其它合适的材料。在一些其它实施例中，在通过导电膏140在第一电路载体110的顶部表面S1上设置导电中介板50的导电柱54之后，可以在第一电路载体110的顶部表面S1上执行回焊工艺，以增强导电中介板50与第一电路载体110之间的接合能力和导电率。
参考图1C，密封体(encapsulant)150形成于第一电路载体110的顶部表面S1上，以密封导电中介板50和第一晶粒120。举例来说，密封体150可包含由模制工艺(moldingprocess)形成的模制化合物(molding compound)。在一些实施例中，密封体150可以通过绝缘材料形成，例如环氧树脂(epoxy resin)或其它合适的树脂，其不限于此。此外，密封体150的厚度T1可以大于板体52的顶部表面52a与第一电路载体110的顶部表面S1之间的距离，以完全密封导电中介板50。在一些实施例中，密封体150的厚度T1可等于板体52的顶部表面52a与第一电路载体110的顶部表面S1之间的距离。也就是，在形成密封体150之后，密封体150可从暴露出板体52的顶部表面52a。在一些其它实施例中，密封体150可以密封第一晶粒120且部分地覆盖导电中介板50的导电柱54。换句话说，在第一晶粒120由密封体150密封时，密封体150的厚度T1可小于导电中介板50的底部表面52b与第一电路载体110的顶部表面S1之间的距离。
参考图1D，移除密封体150的一部分和导电中介板50的板体52，以形成第一封装结构100-1。在一些实施例中，可通过研磨工艺(grinding process)移除密封体150和板体52。此外，研磨工艺可以是机械研磨、化学机械抛光(chemical mechanical polishing，CMP)、蚀刻或不限于此的其它合适的方法。另外，在移除密封体150的部分和导电中介板50的板体52之后，密封体150暴露出导电柱54中的每一者的至少顶部表面54a以及导电突起56的至少顶部表面56a。在移除过程之后，导电柱54可以用于进一步电性连接，且导电突起56可以用于散热，以实现较好的散热效率。在一些实施例中，在移除过程之后，导电柱54中的每一者的顶部表面54a可以与导电突起56的顶部表面56a以及密封体150的顶部表面共面。如图1D所示的移除过程能够帮助封装结构整体的总厚度减少，进而实现封装小型化。在一些其它实施例中，不仅密封体150的部分和导电中介板50的板体52，还有导电柱54的一部分和导电突起56的一部分也被移除，以实现更薄的第一封装结构100-1。
参考图1E，第二封装结构200形成于第一封装结构100-1上，以形成堆叠封装(POP)结构10。举例来说，第二封装结构200电性连接到导电中介板50的导电柱54。在一些实施例中，第二封装结构200可包含第二晶粒202，例如动态随机存取存储器(DRAM)或NAND快闪存储器。在一些实施例中，第二封装结构200中也可以利用其它合适的有源装置。在一些实施例中，第二封装结构200包含连接到导电柱54的顶部表面54a的多个导电端子(conductiveterminals)204。因此，导电端子204可以作为第二封装结构200与第一封装结构100-1之间的电性连接路径。在一些实施例中，第二晶粒202和导电端子204可以通过第二电路载体210电性连接。举例来说，第二电路载体210可包含与第一电路载体110相似的构形。
在一些实施例中，在移除密封体150的部分和导电中介板50的板体52之后，导热界面材料(thermal interface material，TIM)60可形成于导电突起56的顶部表面56a上。TIM60可用以有利地将第二封装结构200接合到第一封装结构100-1。在一些实施例中，TIM 60可用以改善第一封装结构100-1的散热。举例来说，在第一封装结构100-1上形成第二封装结构200之后，TIM 60可以与第二封装结构200和第一封装结构100-1热接触(thermalcontact)或者热电耦(thermal couple)于这两者之间，以用于增强散热效率。在一些实施例中，TIM 60具有足够厚度，以接合在导电突起56与第二封装结构200之间。举例来说，在接合第一封装结构100-1和第二封装结构200之后，TIM 60的厚度可实质上等于导电端子204中的每一者的高度。TIM 60可有利于平衡总体POP结构10，且在后续进行可靠性测试(reliability test)期间，TIM60可分担施加到POP结构10上的应力，进而增加POP结构10的可靠性。
图2A到图2D是说明根据本发明的另一实施例的POP结构的制造方法的剖面示意图，且图3是说明根据本发明的实施例的导电中介板的立体示意图。参考图2A和图3，如图1A中所说明提供第一电路载体110以及设置于第一电路载体110上的第一晶粒120。为简洁起见省略了详细描述。
在提供第一电路载体110和第一晶粒120之后，在第一电路载体110上提供导电中介板130。在一些实施例中，导电中介板130可包含板体132以及多个导电柱134。另外，板体132可以具有对准窗口(alignment window)132a，且导电柱134可以从板体132延伸到第一电路载体110。举例来说，导电中介板130的板体132可包含中心区C(也称为晶粒定位区)以及连接到中心区C的外围区P。此外，板体132的对准窗口132a可形成于对应于第一晶粒120的中心区C处且导电柱134可形成于外围区P处。举例来说，导电柱134可以沿着板体132的边缘布置且垂直于板体132形成。
板体132的对准窗口132a可以暴露出第一晶粒120。举例来说，对准窗口132a的大小和形状可以相似或等于第一晶粒120，使得导电中介板130的对准窗口132a可以通过对准窗口132a与第一晶粒120对准。在一些实施例中，对准窗口132a在第一电路载体110上的正投影面积与第一晶粒120在第一电路载体110上的正投影面积重叠且相等。在一些其它实施例中，第一晶粒120的至少边缘可以从导电中介板130的板体132的对准窗口132a暴露，以用于对准。举例来说，当在第一电路载体110上设置导电中介板130时，第一晶粒120的至少一个边缘可通过导电中介板130的板体132的对准窗口132a定位，使得导电中介板130的导电柱134可以对应于第一电路载体110的导电衬垫114a而接合。换句话说，对准窗口132a有利于定位第一晶粒120，且进一步增强导电中介板130的导电柱134与第一电路载体110之间的电性连接的准确性。对准窗口132a的数目、形状和大小并不解释为限制，只要当在第一电路载体110上设置导电中介板130时第一晶粒120可通过对准窗口132a定位即可，进而实现其间的精确对准。
举例来说，导电中介板130的板体132和导电柱134可以一体地形成。导电柱134的材料和形成工艺可以类似于图1B中说明的导电柱56，且在此不重复详细描述。板体132的对准窗口132a可以通过机械钻孔(mechanical drilling)、光刻和蚀刻或不限于此的其它合适的方法来形成。举例来说，板体132的对准窗口132a可以在同一过程中连同导电柱134一起形成。另外，板体132的对准窗口132a可以在形成导电柱134之前或之后形成。形成对准窗口132a和导电柱134的顺序在本发明中并不解释为限制。
在一些实施例中，导电中介板130的导电柱134通过导电膏140连接到第一电路载体110。导电膏140的形成过程可以与图1B中描述相似。此处不重复详细描述。举例来说，在第一电路载体110上接合导电中介板130之后，导电中介板130的板体132的底部表面132c可相对于第一电路载体110的顶部表面S1高于第一晶粒120的非有源表面120b。在一些其它实施例中，在第一电路载体110上接合导电中介板130之后，导电中介板130的板体132的底部表面132c和第一晶粒120的非有源表面120b可以共面。
参考图2B，密封体150形成于第一电路载体110的顶部表面S1上，以密封导电中介板130和第一晶粒120。此外，密封体150的厚度T1'可大于导电中介板130的板体132与第一电路载体110的顶部表面S1之间的距离，以完全密封导电中介板130。在一些实施例中，密封体150的厚度T1'可等于导电中介板130的板体132与第一电路载体110的顶部表面S1之间的距离。即，在形成密封体150之后，密封体150可暴露出板体132的与底部表面132c相对的顶部表面132b。在一些其它实施例中，密封体150可以密封第一晶粒120且部分地覆盖导电中介板130的导电柱134。换句话说，在第一晶粒120由密封体150密封时，密封体150的厚度T1'可小于导电中介板130的底部表面132c与第一电路载体110的顶部表面S1之间的距离。
参考图2C，移除密封体150的一部分和导电中介板130的板体132，以形成第一封装结构100-2。所述移除过程可类似于在图1D中说明的实施例。此处不重复详细描述。在移除密封体150的部分和导电中介板130的板体132之后，密封体150暴露出导电柱134中的每一者的至少顶部表面134a。因此，导电中介板130的导电柱134可以用于进一步电性连接。在一些实施例中，不仅密封体150的部分和导电中介板130的板体132，还有导电中介板130的导电柱134的一部分也被移除，以实现更薄的第一封装结构100-2。
参考图2D，第二封装结构200形成于第一封装结构100-2上，以形成POP结构20。举例来说，第二封装结构200电性连接到导电中介板130的导电柱134。在一些实施例中，导电端子204可以对应于导电柱134的顶部表面134a而形成。因此，导电端子204可以作为第二封装结构200与第一封装结构100-2之间的电性连接路径。
图4A到图4E是说明根据本发明的又一实施例的POP结构的制造方法的剖面示意图。参考图4A，提供第一电路载体110且第一晶粒320接合于第一电路载体110上。举例来说，第一晶粒320可为专用集成电路(ASIC)。在一些实施例中，第一晶粒320可以用来执行逻辑应用程序。然而，其在本发明中并不解释为限制。图4A中的实施例与图1A中的实施例之间的主要差异在于，第一晶粒320通过多根导电线360电性连接到第一电路载体110。
举例来说，导电线360可以通过打线机(wire bonder)(未示出)而形成。打线机的类型可包含楔型接合(wedge bond)或球型接合(ball bond)或者不限于此的根据设计要求的其它合适的打线机。导电线360的材料可以是金、铜或不限于此的其它合适材料。在一个实施例中，导电线360可以从第一电路载体110到第一晶粒320形成。在一些其它实施例中，导电线360可以从第一晶粒320到第一电路载体110形成。导电线360的形成顺序可以取决于设计要求，并不限于此。导电线360中的每一者的顶端(peak)定义为在连接第一电路载体110和第一晶粒320之后，相对于导电线360中的每一者的两个末端的最高点。此外，导电线360中的每一者的线弧(loop)高度H1定义为导电线360中的每一者的顶端与第一电路载体110之间的距离。导电线360中的每一者的线弧高度H1取决于打线机的类型和/或设计要求。
此外，粘着层(adhesive layer)370可设置于第一晶粒320与第一电路载体110之间，以用于增强第一晶粒320到第一电路载体110的接合。举例来说，粘着层370可以是晶粒贴附膜(die attach film)、银膏或类似物。在一些实施例中，粘着层370的其它合适的材料可用于增强第一晶粒320与第一电路载体110之间的粘合。
参考图4B和图3，导电中介板330通过导电膏140接合于第一电路载体110上。本实施例的导电膏140的接合过程类似于在图2A中说明的实施例。在此省略详细描述。另外，类似于在图2A中说明的导电中介板130的导电中介板330包含板体332，板体332具有对准窗口332a以及多个导电柱334。此外，本实施例的导电中介板330的形成类似于在图2A中说明的导电中介板130。因此，在此不重复导电中介板330的形成过程的详细描述。本实施例的导电中介板330与在图2A实施例中说明的导电中介板130之间的差异在于，导电中介板330的高度H2大于导电线360中的每一者的线弧高度H1。举例来说，导电中介板330的高度H2定义为导电中介板330的板体332的顶部表面332b与第一电路载体110的顶部表面S1之间的距离。因此，在第一电路载体110上接合导电中介板330之后，导电中介板330不接触导电线360，因此接合导电中介板330的过程不影响第一晶粒320的可靠性。
参考图4C，密封体150形成于第一电路载体110的顶部表面S1上，以密封导电中介板330、第一晶粒320、粘着层370以及导电线360。在图4C中说明的实施例的密封体150的形成过程类似于图2B中所示的实施例的密封体150的形成过程。在此省略详细描述。此外，密封体150的厚度T2可大于导电中介板330的板体332与第一电路载体110的顶部表面S1之间的距离，以完全密封导电中介板330。在一些实施例中，密封体150的厚度T2可等于导电中介板330的板体332与第一电路载体110的顶部表面S1之间的距离。即，在形成密封体150之后，密封体150可暴露出板体332的顶部表面332b。在一些其它实施例中，密封体150可以完全密封导电线360且部分地暴露出导电中介板330。换句话说，在密封体150密封第一晶粒320时，密封体150的厚度T2可小于导电中介板330的板体332的与顶部表面332b相对的底部表面332c与第一电路载体110的顶部表面S1之间的距离。
参考图4D，移除密封体150的一部分和导电中介板330的板体332，以形成第一封装结构100-3。本发明的实施例的密封体150和板体332的移除过程类似于图2C中所说明的实施例。在此省略详细描述。另外，在移除密封体150的部分和导电中介板330的板体332之后，密封体150暴露出导电中介板330的导电柱334中的每一者的至少顶部表面334a。因此，导电中介板330的导电柱334可以作为导电路径，以用于进一步电性连接。另外，如图4D所示的移除过程能够帮助封装结构整体的总厚度减少，进而实现封装小型化。在一些实施例中，在密封体150密封导电线360时，不仅密封体150的部分和导电中介板330的板体332，还有导电中介板330的导电柱334的一部分也被移除，进而实现更薄的第一封装结构100-3。
参考图4E，第二封装结构200形成于第一封装结构100-3上，以形成POP结构30。举例来说，第二封装结构200电性连接到导电中介板330的导电柱334。在一些实施例中，导电端子204可对应于导电中介板330的导电柱334的顶部表面334a而形成。因此，导电端子204可以作为第二封装结构200与第一封装结构100-3之间的电性连接路径。换句话说，第二封装结构200的第二晶粒210通过导电端子204和导电中介板330的导电柱334电性连接到第一封装结构100-3的第一电路载体110。
基于上述，由于至少移除导电中介板的导电板，因此被密封体暴露出的导电柱可以作为第一封装结构与第二封装结构之间的电性连接路径，且被密封体暴露出的导电突起可以作为散热片以用于更好的散热效率。不必在第一封装结构与第二封装结构之间设置用于电性连接其间的额外的中介板。在移除密封体的一部分和导电中介板的板体之后，可减少封装结构的总厚度，进而实现封装小型化。形成于导电突起的顶部表面上的导热界面材料有利于将第二封装结构接合到第一封装结构，且改善第一封装结构的散热。当具有对准窗口的导电中介板设置于电路载体上时，对准窗口有利于使导电中介板与晶粒对准。因此，不需要形成额外的对准标记以对准导电中介板和晶粒。因此，制造成本可以减少。
对于所属领域的技术人员将显而易见的是，在不脱离本发明的范围或精神的情况下，可以对本发明的结构进行各种修改和变化。鉴于以上内容，希望本发明涵盖本发明的修改和变化，只要所述修改和变化落入所附权利要求和其等效物的范围内。

Claims (10)

1.一种堆叠封装结构的制造方法，其特征在于，包括：
形成第一封装结构，其中所述第一封装结构包括电路载体以及设置于所述电路载体上的晶粒，形成所述第一封装结构包括：
在所述电路载体上提供导电中介板，其中所述导电中介板包括板体、从所述板体分别延伸到所述电路载体和所述晶粒的多个导电柱以及导电突起，所述导电突起设置于所述晶粒上，且所述导电柱电性连接到所述电路载体；
通过密封体密封所述导电中介板；以及
移除所述密封体的一部分和所述导电中介板的所述板体；以及
在所述第一封装结构上形成第二封装结构，其中所述第二封装结构通过所述导电中介板电性连接到所述第一封装结构。
2.根据权利要求1所述的堆叠封装结构的制造方法，其特征在于，在所述电路载体上提供所述导电中介板之后，所述导电突起在所述电路载体上的正投影面积与所述晶粒在所述电路载体上的正投影面积重叠。
3.根据权利要求1所述的堆叠封装结构的制造方法，其特征在于，在移除所述密封体的所述部分和所述导电中介板的所述板体之后，所述密封体至少暴露出所述导电柱中的每一者的顶部表面以及所述导电突起的顶部表面。
4.根据权利要求3所述的堆叠封装结构的制造方法，其特征在于，所述导电突起的厚度小于所述导电柱中的每一者的高度，在移除所述密封体的所述部分和所述导电中介板的所述板体之后，所述导电柱中的每一者的所述顶部表面与所述导电突起的所述顶部表面共面。
5.根据权利要求3所述的堆叠封装结构的制造方法，其特征在于，在移除所述密封体的所述部分和所述导电中介板的所述板体之后，在所述导电突起的所述顶部表面上形成导热界面材料，所述第二封装结构包括设置于所述导电柱上的多个导电端子，在所述第一封装结构上形成所述第二封装之后，所述导电端子中的每一者的高度等于所述导热界面材料的厚度。
6.一种堆叠封装结构的制造方法，其特征在于，包括：
形成第一封装结构，其中所述第一封装结构包括电路载体以及设置于所述电路载体上的晶粒，形成所述第一封装结构包括：
在所述电路载体上提供导电中介板，其中所述导电中介板包括晶粒定位区，所述晶粒定位区在所述电路载体上的正投影面积等于所述晶粒在所述电路载体上的正投影面积；
通过密封体密封所述导电中介板；以及
移除所述密封体的一部分以及所述导电中介板的一部分，其中所述密封体暴露出所述导电中介板的表面；以及
在所述第一封装结构上形成第二封装结构，其中所述第二封装结构通过所述导电中介板电性连接到所述第一封装结构。
7.根据权利要求6所述的堆叠封装结构的制造方法，其特征在于，所述导电中介板包括位于所述晶粒定位区中的导电突起以及围绕所述导电突起的多个导电柱，在所述电路载体上提供所述导电中介板之后，所述导电柱电性连接到所述电路载体且所述导电突起设置于所述晶粒上。
8.根据权利要求7所述的堆叠封装结构的制造方法，其特征在于，所述导电突起的厚度小于所述导电柱中的每一者的高度，在移除所述密封体的所述部分和所述导电中介板的所述板体的所述部分之后，所述密封体至少暴露出所述导电柱中的每一者的顶部表面以及所述导电突起的顶部表面。
9.根据权利要求6所述的堆叠封装结构的制造方法，其特征在于，所述导电中介板包括板体以及多个导电柱，所述晶粒定位区包括形成于所述板体处的对准窗口，且所述导电柱形成于所述板体上并围绕所述晶粒定位区，在所述电路载体上提供所述导电中介板之后，所述对准窗口与所述晶粒对准且至少暴露出所述晶粒的边缘。
10.根据权利要求9所述的堆叠封装结构的制造方法，其特征在于，所述晶粒通过多根导电线电性连接到所述电路载体，在移除所述密封体的所述部分以及所述导电中介板的所述部分之前，所述导电中介板的高度大于所述导电线中的每一者的线弧高度。
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TWI674708B (zh) * 2018-08-31 2019-10-11 唐虞企業股份有限公司 晶片封裝結構半成品、晶片封裝結構模組與晶片封裝結構的製造方法
CN111987048A (zh) * 2019-05-23 2020-11-24 矽品精密工业股份有限公司 电子封装件及其制法

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