TWI749860B - 晶片封裝方法 - Google Patents

晶片封裝方法 Download PDF

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TWI749860B
TWI749860B TW109139220A TW109139220A TWI749860B TW I749860 B TWI749860 B TW I749860B TW 109139220 A TW109139220 A TW 109139220A TW 109139220 A TW109139220 A TW 109139220A TW I749860 B TWI749860 B TW I749860B
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chip
hole
packaging
carrier
conductive metal
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TW202220067A (zh
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杜明德
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菱生精密工業股份有限公司
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Abstract

本發明所提供之晶片封裝方法首先將一顆晶片固定於一塊載板之頂面，接著利用一個封裝膠體將晶片包覆起來，然後從封裝膠體之頂面對封裝膠體進行鑽孔，使封裝膠體具有一個鄰設於晶片之貫孔，最後在晶片與該貫孔之間及在貫孔的孔壁分別鍍設一導電金屬，使晶片經由導電金屬與載板電性導通。藉此，本發明所提供之晶片封裝方法可以解決傳統打線接合製程的產生的問題，進而以達到簡化封裝製程及提升傳輸效率的效果。

Description

晶片封裝方法
本發明與晶片封裝方法有關，特別是指一種可簡化製程及提升傳輸效率之晶片封裝方法。
傳統的封裝製程是利用黏膠將晶片固定於載板上，接著利用多條金屬線材連接晶片與載板，使兩者相互導通，最後再利用封裝膠體(如環氧樹脂)將晶片進行包覆，如此即完成整個封裝製程。
然而，金屬線材是利用打線接合方式(wire bonding)連接在晶片與載板之間，對封裝製程來說會較為繁瑣。此外，金屬線材因為本身長度的關係不但會造成傳輸路徑較長而影響性能，並且也會造成產品尺寸難以達到理想的要求，導致應用於產品時容易缺乏競爭力。
本發明之主要目的在於提供一種晶片封裝方法，其能簡化封裝製程及提升傳輸效率。
為了達成上述主要目的，本發明之晶片封裝方法包含有下列步驟:將一顆晶片固定於一個載板之頂面；將一個封裝膠體包覆該晶片；自該封裝膠體之頂面對該封裝膠體進行鑽孔，使該封裝膠體具有一個鄰設於該晶片之第一貫孔；在該晶片之頂面與該第一貫孔之頂端之間和該第一貫孔的孔壁分別鍍設一層導電金屬，使該晶片經由該導電金屬與該載板電性導通。
由上述可知，本發明所提供之晶片封裝方法透過該導電金屬將該晶片與該載板作電性導通，無需透過金屬線材，因此可以解決傳統打線接合製程所產生各種問題，進而達到簡化封裝製程及提升傳輸效率的效果。
較佳地，該載板可以雙面利用來提高利用率，也就是依照上述步驟在該載板的頂底二面分別設置一該晶片、一該封裝膠體、一該第一貫孔及一該導電金屬，然後將該載板從中間切開成上下二部分，最後根據該晶片的數量進行切割而製成多個晶片封裝結構，如此可以提升製程效率。
較佳地，該第一貫孔可以貫穿該封裝膠體與該載板，然後自該載板之底面對該載板進行鑽孔，使該載板具有一個鄰設於該晶片之第二貫孔，然後在該載板之底面與該第一貫孔之底端之間、該載板之底面與該第二貫孔之底端之間和該第二貫孔的孔壁分別鍍設一層導電金屬，如此在與印刷電路板作電性連接時不需要將整個晶片封裝結構上下顛倒180度，以增加使用上的便利性。
有關本發明所提供對於晶片封裝方法的詳細構造、特點、組裝或使用方式，將於後續的實施方式詳細說明中予以描述。然而，在本發明領域中具有通常知識者應能瞭解，該等詳細說明以及實施本發明所列舉的特定實施例，僅係用於說明本發明，並非用以限制本發明之專利申請範圍。
申請人首先在此說明，於整篇說明書中，包括以下介紹的實施例以及申請專利範圍的請求項中，有關方向性的名詞皆以圖式中的方向為基準。其次，在以下將要介紹之實施例以及圖式中，相同之元件標號，代表相同或近似之元件或其結構特徵。
請先參閱圖1A及圖1B，本發明第1實施例之晶片封裝方法包含有下列步驟:
a):如圖1A所示之步驟S1，利用黏膠32將一顆晶片30固定於一塊載板20之頂面。前述載板20是用來作為晶片30與印刷電路板(圖中未示)之間的橋樑，並同時提供保護電路及散熱的功能。
b):如圖1A所示之步驟S2，使用一層封裝膠體40(如環氧樹脂)將晶片30包覆住，用以對晶片30提供保護效果。
c):如圖1A所示之步驟S3，自封裝膠體40之頂面由上往下對封裝膠體40進行鑽孔，使封裝膠體40具有一個鄰設於晶片30之第一貫孔42，第一貫孔42貫穿封裝膠體40之頂底二面。
d):如圖1B所示之步驟S4，在晶片30之頂面與第一貫孔42之頂端之間和第一貫孔42的孔壁分別鍍設一層導電金屬50(例如銅)，使晶片30經由導電金屬50與載板20電性導通，其中在晶片30之頂面與第一貫孔42之頂端之間的導電金屬50會將封裝膠體40覆蓋住。
e):如圖1B所示之步驟S5，在封裝膠體40之頂面設置一層用來保護導電金屬50之阻焊層54(solder mask)，阻焊層54具有一個開口56讓導電金屬50的一部分暴露出來，使晶片30可以利用導電金屬50的外露部分與印刷電路板(圖中未示)作電性連接。
由上述可知，本發明所提供之晶片封裝方法透過第一貫孔42搭配導電金屬50的設計將晶片30與載板20作電性導通，整個製程無需透過金屬線材，因此可以解決傳統打線接合製程所產生的問題，進而達到簡化封裝製程及提升傳輸效率的效果。
請繼續參閱圖2A及圖2B，本發明第2實施例所提供之晶片封裝方法與上述第1實施例大致相同，主要差異在於由上述第1實施例所製成的晶片封裝結構10在與印刷電路板作電性連接時，因為導電金屬50位於晶片30上方，所以整個晶片封裝結構10需要上下顛倒180度，至於由第2實施例所製成的晶片封裝結構60將導電金屬50設置於晶片30下方，所以在與印刷電路板作電性連接時並不需要上下顛倒180度。詳而言之:
a):如圖2A所示之步驟S1，利用黏膠32將晶片30固定於載板20之頂面。
b):如圖2A所示之步驟S2，使用封裝膠體40(如環氧樹脂)將晶片30包覆住，用以對晶片30提供保護效果。
c):如圖2A所示之步驟S3，一方面自封裝膠體40之頂面由上往下對封裝膠體40進行鑽孔，使封裝膠體40具有一個鄰設於晶片30之第一貫孔42，第一貫孔42貫穿封裝膠體40之頂底二面及載板20之頂底二面，另一方面自載板20之底面由下往上對載板20進行鑽孔，使載板20具有一個鄰設於晶片30之第二貫孔22，第二貫孔22貫穿載板20之頂底二面。
d):如圖2B所示之步驟S4，在晶片30之頂面與第一貫孔42之頂端之間、第一貫孔42的孔壁、載板20之底面與第二貫孔22之底端之間及第二貫孔22的孔壁分別鍍設一層導電金屬50(例如銅)，一方面藉由鍍設有導電金屬50的第一貫孔42將晶片30頂面的線路接引至載板20的底面，另一方面藉由鍍設有導電金屬50的第二貫孔22對晶片30提供接地保護。
e):如圖2B所示之步驟S5，在載板20之底面設置一層用來保護導電金屬52之阻焊層54(solder mask)，阻焊層54具有一個開口56讓下方導電金屬50的一部分暴露出來，至於暴露的部分可以進一步作抗氧化處理(例如鍍金)。
由上述可知，由本發明第2實施例所製成的晶片封裝結構60利用下方導電金屬50的外露部分與印刷電路板(圖中未示)作電性連接，在使用時不需要上下顛倒180度，因而增加使用上的便利性。
另一方面，請參閱圖3A至圖3C，本發明第3實施例所提供之晶片封裝方法與上述第1實施例大致相同，主要差異在於上述第1實施例只針對載板24的單一面進行封裝製程，第3實施例則是對載板24的雙面同時依照上述第1實施例之晶片封裝方法進行封裝製程，以提高載板24的利用率，並提高製程效率。詳而言之:
a):如圖3A所示之步驟S1，利用黏膠32將多顆晶片30(為便於說明，在圖中以上下各3顆為例，並不以此為限)以上下相互對應的方式固定於同一塊載板24之頂底二面。
b):如圖3A所示之步驟S2，使用上下二層封裝膠體40(如環氧樹脂)將該等晶片30包覆住，用以對該等晶片30提供保護效果。
c):如圖3A所示之步驟S3，對上下二層封裝膠體40分別進行鑽孔，使每一層封裝膠體40具有多個第一貫孔42，每一個第一貫孔42鄰設於一顆晶片30。
d):如圖3B所示之步驟S4，在每一顆晶片30之頂面和與其相鄰的第一貫孔42之頂端之間及每一個第一貫孔42的孔壁分別鍍設一層導電金屬50(例如銅)，使每一顆晶片30經由一層導電金屬50與載板20電性導通。
e):如圖3B所示之步驟S5，在上層封裝膠體40之頂面及下層封裝膠體40之底面分別設置一層用來保護導電金屬50之阻焊層54(solder mask)，上下二層阻焊層54分別具有多個開口56，每一個開口56對應一層導電金屬50且讓與其相對應之導電金屬50的一部分暴露出來。
f):如圖3C所示之步驟S6，將載板24從中間切開成上下二部分，然後根據晶片30的數量進行切割而製成多個晶片封裝結構10。
由上述可知，本發明第3實施例之晶片封裝方法不但可以提高載板24的利用率，並且可以一次製成多個晶片封裝結構10，以達到提高製程效率的目的。
10:晶片封裝結構 20:載板 22:第二貫孔 24:載板 30:晶片 32:黏膠 40:封裝膠體 42:第一貫孔 50:導電金屬 54:阻焊層 56:開口 60:晶片封裝結構 S1:步驟 S2:步驟 S3:步驟 S4:步驟 S5:步驟 S6:步驟
圖1A與圖1B為本發明第1實施例之晶片封裝方法的流程圖。 圖2A與圖2B為本發明第2實施例之晶片封裝方法的流程圖。 圖3A至圖3C為本發明第3實施例之晶片封裝方法的流程圖。
10:晶片封裝結構
20:載板
30:晶片
40:封裝膠體
42:第一貫孔
50:導電金屬
54:阻焊層
56:開口
S4:步驟
S5:步驟

Claims (8)

  1. 一種晶片封裝方法，包含有下列步驟：a)將一晶片固定於一載板之頂面；b)將一封裝膠體包覆該晶片；c)自該封裝膠體之頂面對該封裝膠體進行鑽孔，使該封裝膠體具有一鄰設於該晶片之第一貫孔；d)在該晶片之頂面與該第一貫孔之頂端之間和該第一貫孔的孔壁分別鍍設一導電金屬，使該晶片經由該導電金屬與該載板電性導通；以及e)在該封裝膠體之頂面設置一阻焊層，該阻焊層具有一開口讓該導電金屬的一部分暴露出來。
  2. 如請求項1所述之晶片封裝方法，其中，該第一貫孔貫穿該封裝膠體之頂底二面。
  3. 如請求項1所述之晶片封裝方法，在步驟c)中，自該載板之底面對該載板進行鑽孔，使該載板具有一鄰設於該晶片之第二貫孔，該第二貫孔貫穿該載板之頂底二面；在步驟d)中，在該載板之底面與該第一貫孔之底端之間、該載板之底面與該第二貫孔之底端之間及該第二貫孔的孔壁分別鍍設另一該導電金屬。
  4. 如請求項3所述之晶片封裝方法，更包含有一步驟e)，在該載板之底面設置一阻焊層，該阻焊層具有一開口讓該導電金屬的一部分暴露出來。
  5. 如請求項3所述之晶片封裝方法，其中，該第一貫孔貫穿該封裝膠體與該載板。
  6. 一種晶片封裝方法，包含有下列步驟：a)將二晶片分別固定於一載板之頂底二面；b)將二封裝膠體分別包覆一該晶片；c)分別對一該封裝膠體進行鑽孔，使各該封裝膠體具有一鄰設於一該晶片之第一貫孔；d)在各該晶片和與其相鄰之一該第一貫孔之間及各該第一貫孔的孔壁分別鍍設一導電金屬，使該等晶片經由該等導電金屬與該載板電性導通；以及e)將該載板從中間切開成上下二部分。
  7. 如請求項6所述之晶片封裝方法，在步驟d)與步驟e)之間，在各該封裝膠體之表面設置一阻焊層，各該阻焊層具有多個開口讓該等導電金屬的一部分暴露出來。
  8. 如請求項6所述之晶片封裝方法，其中，該第一貫孔貫穿該封裝膠體之頂底二面。
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