TWI613771B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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TWI613771B
TWI613771B TW105141745A TW105141745A TWI613771B TW I613771 B TWI613771 B TW I613771B TW 105141745 A TW105141745 A TW 105141745A TW 105141745 A TW105141745 A TW 105141745A TW I613771 B TWI613771 B TW I613771B
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circuit board
semiconductor wafer
semiconductor package
holes
item
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TW105141745A
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TW201733048A (zh
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蔡憲聰
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體封裝，包括：一電路板，其包括：相對的第一和第二表面以及複數個通孔；一半導體晶片，形成於該電路板的該第一表面上，並且該半導體晶片的主動面朝向該電路板的該第一表面；以及複數個導電連接，穿過該等通孔並且將該半導體晶片與該電路板電性連接。

Description

半導體封裝
本發明涉及積體電路(Integrated Circuit，IC)裝置，特別係涉及一種半導體封裝，具有降低的電壓降(IR drop)效應及更加靈活的接合墊(bond-pad)設計。
一般的BGA(Ball Grid Array，球柵陣列)半導體封裝包括：一半導體晶片，安裝在絕緣PCB(Printed Circuit Board，印刷電路板)基底的上表面上。該基底可以由玻璃纖維填充的有機層壓板製成，諸如FR4板，FRS板或者BT(bismaleimide triazine，雙馬來醯亞胺三嗪)板，並且該基底在其上下表面上具有互連的導電電路圖案。變硬的包封(encapsulating)材料覆蓋該晶片、該基底的上表面以及電導體(諸如接合線)，該電導體於該晶片和該基底的上表面上的電路圖案之間延伸。導電球或者其他輸入/輸出(Input/output，I/O)端形成於該基底的下表面的電路圖案上。
然而，雖然現存的BGA半導體封裝已經足夠用於其預期目的，但是現存的BGA半導體封裝並非在各個方面完全令人滿意。
因此，本發明之主要目的即在於提供一種半導體 封裝，能夠降低電壓降效應。
根據本發明至少一個實施例提供了一種半導體封裝，包括：一電路板，包括：相對的第一和第二表面，以及複數個通孔；一半導體晶片，形成於該電路板的該第一表面的中央部分上，並且該半導體晶片的主動面朝向該電路板的該第一表面；以及複數個導電連接，穿過該等通孔並且將該半導體晶片與該電路板電性連接。
本發明實施例，由於導電連接穿過電路板上的通孔並且將半導體晶片與該電路板電性連接，因此能夠優化半導體晶片與電路板之間的電性連接路徑，從而降低半導體晶片的電壓降效應。
10、100‧‧‧半導體封裝
12、112‧‧‧電路板
20、120‧‧‧半導體晶片
28‧‧‧襯墊
30、130‧‧‧包封層
32、132‧‧‧散熱層
36、136‧‧‧導電元件
22、14、122、114‧‧‧第一表面
24、16、124、116‧‧‧第二表面
A、A'‧‧‧I/O墊
118‧‧‧附著層
18‧‧‧第一附著層
B、B'‧‧‧接合墊
34、134‧‧‧導電連接
26‧‧‧第二附著層
30、130‧‧‧包封層
32、132‧‧‧散熱層
1-1‧‧‧線
150‧‧‧通孔
112a‧‧‧梯狀部分
160‧‧‧次層
通過閱讀接下來的詳細描述和參考所附的圖式所做的示例，能夠更加全面地理解本發明，其中：第1圖為根據本發明實施例的半導體封裝的橫截面示意圖；第2圖為第1圖所示的半導體封裝的俯視圖；第3圖為根據本發明另一實施例的半導體封裝的橫截面示意圖；第4圖為第3圖所示的半導體晶片的平面示意圖；第5~7圖為第3圖所示的電路板的仰視圖。
在說明書及後續的申請專利範圍當中使用了某些 詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
以下描述為實現本發明的較佳預期模式。該描述是出於說明本發明一般原理的目的，而不具有限制意義。最好的確定本發明的範圍的方式係通過參考所附的申請專利範圍。
第1圖示出了示范性的一半導體封裝10的橫截面示意圖，其包括：一電路板12、一半導體晶片20、一襯墊(spacer)28、一包封層30、一散熱(heat spreading)層32以及複數個導電元件36。
如第1圖所示，該半導體晶片20例如為功能性晶片，諸如微處理器晶片、記憶體晶片、邏輯晶片或者其他的功能性晶片，並且該半導體晶片20具有一主動的(active)第一表面22和一鈍性的(inactive)第二表面24。該半導體晶片20的第一表面22包括：複數個I/O墊A(或者接合墊)，位於鄰近第一表面22的周邊邊緣的位置。通過磨光(polishing)第二表面24來使該半導體晶片20變薄。在一個實施例中，半 導體晶片20可以具有大約4~8mil(密耳)的厚度。
半導體晶片20通過第一附著層(adhesive layer)18安置在電路板12的中央部分上。電路板12具有相對的第一和第二表面14和16，並且第一附著層18和半導體晶片20係順序地形成於電路板12的第一表面14的中央部分上。電路板12主要由樹脂層(未示出)構成，該樹脂層形成於BT板、FR4板、FR5板或者一些其他類的用來製作半導體封裝的PCB基底的填充有玻璃纖維的有機(環氧樹脂)層壓板。另外，導電線路(conductive trace)及導電互連(均未示出)也形成於電路板12中，從而在半導體晶片20與導電元件36之間提供合適的電連接。第一附著層18可以包括：環氧樹脂或類似物。
如第1圖所示，複數個接合墊B及電性的導電電路圖案(未示出)形成於電路板12的第一表面14上，並且導電元件36形成於電路板12的第二表面16上。半導體晶片20的每個I/O墊A係通過導電連接34電性連接至接合墊B之一，其中該導電連接34跨越在半導體晶片20和接合墊B之間。如第1圖所示，導電連接34可以為由金或者鋁形成的接合線。
另外，襯墊28通過第二附著層26安置在半導體晶片20的第一表面22的中央部分上。襯墊28例如為矩形的由空白的半導體晶圓製成的非功能性(non-functional)晶片，並且襯墊28可以包括：半導體材料，與半導體晶片20的半導體層(未示出)的材料相同。形成的襯墊28的橫截面尺寸(例如寬度W1)小於半導體晶片20的橫截面尺寸(例如寬度W2)。在一個實施例中，襯墊28形成為大約4~10mil的厚度。
包封層30覆蓋半導體晶片20的第一表面22、電路板12的第一表面14的一部分、以及散熱層32的一部分，從而露出散熱層32的頂面中位於襯墊28和半導體晶片20上方的部分。包封層30也填充散熱層32與襯墊28之間的空間。通過使樹脂材料(如環氧樹脂)成型和固化或者通過澆注和固化液體樹脂材料(如環氧樹脂)來形成包封層30。散熱層32例如可以形成為第1圖所示的像Ω一樣的形狀，該散熱層32具有接觸電路板12的部分並且可以由銅、鋁或者另一金屬合金形成。
導電元件36例如可以由鉛錫焊料(lead tin solder)或者一些其他的金屬來形成，並且作為半導體封裝10的輸入/輸出(Input/output，I/O)端。每個導電元件36係通過導電連接34、接合墊B、導電線路與導電互連(均未示出)而分別電性連接至半導體晶片20的I/O墊A，其中接合墊B形成於電路板12上，導電線路與導電互連(均未示出)形成於電路板12中。導電元件36允許半導體封裝10安置在母板(未示出)上。其他組態的I/O端也是可能的。
第2圖示出了第1圖所示的半導體封裝10的俯視圖，並且第1圖示意了沿第2圖中的線1-1的橫截面示意圖。出於簡化目的，在第2圖中，沒有示出散熱層32和包封層30，而示意了電路板12、半導體晶片20、襯墊28和導電連接34。
如第1及第2圖所示，於半導體晶片20的第一表面22上提供導電連接34以電性連接I/O墊A和接合墊B，其中I/O墊A形成於半導體晶片20的周邊邊緣附近，接合墊B 形成於封裝基底12的第一表面12上。
在第1~2圖所示的示范性的半導體封裝10中，由於I/O墊係全部位於半導體晶片20的第一表面22的周邊邊緣的附近，使得以密集的組態在半導體晶片20的I/O墊A和封裝基底12上形成的接合墊B之間提供導電連接34。因此，隨著增加半導體晶片20中的主動或被動元件數量的趨勢，半導體晶片20將具有更大的尺寸來容納半導體晶片20的更多的I/O墊A以及避免相鄰的導電連接34之間的短路。
另外，由於全部的I/O墊係位於半導體晶片20的第一表面22的周邊邊緣的附近，因此半導體晶片20需要形成更加複雜的互連結構，以連接主動或被動元件(例如位於半導體晶片20的中央部分)與I/O墊A，這意味著半導體晶片20的製造將變得更加複雜並且主動或被動元件同I/O墊A之間的路徑的長度將會太長，其中主動或被動元件形成於半導體晶片20中，I/O墊A位於半導體晶片20的第一表面22的周邊邊緣附近。因此，例如位於半導體封裝10的半導體晶片20的中央部分處的主動或被動元件將會出現非期望的電壓(IR)降效應，如此，將影響半導體封裝10的性能。
如此，需要一種改善的能夠降低電壓降效應的半導體封裝。
第3圖示出了一種示范性的能夠降低電壓降效應的半導體封裝100，其包括：一電路板112、一半導體晶片120、一包封層130、一散熱層132以及複數個導電元件136。
如第3圖所示，該半導體晶片120例如為一功能 性晶片，諸如微處理器晶片、記憶體晶片、邏輯晶片或者其他的功能性晶片，並且該半導體晶片120具有一主動的第一表面122和一鈍性的第二表面124。可以通過磨光該第二表面124來使該半導體晶片120變薄。在一個實施例中，該半導體晶片120可以具有大約4~18密耳(mil)的厚度。
電路板112具有相對的第一和第二表面114和116，並且附著層118和半導體晶片120順序地形成於電路板112的第一表面114的中央部分上。電路板112主要由樹脂層(未示出)構成，該樹脂層由BT(bismaleimide triazine，雙馬來醯亞胺三嗪)板、FR4板、FR5板或者一些其他類的用來製作用於半導體封裝的PCB基底的填充有玻璃纖維的有機(如環氧樹脂)層壓板形成。另外，複數層導電線路(conductive trace)及導電互連(均未示出)也形成於電路板112中，從而在半導體晶片120與導電元件136之間提供合適的電連接。附著層118可以包括：環氧樹脂或類似物。
如第3圖所示，半導體晶片120通過附著層118安置於電路板112的中央部分上，並且半導體晶片120的第一表面122面向電路板112。半導體晶片120的第一表面122包括：複數個I/O墊A'，其不僅位於第一表面的周邊邊緣處，而且也位於第一表面122的中央部分處。
另外，於電路板112中設置複數個通孔(through hole)150以穿過電路板112的中央和周邊部分。另外，通孔150也穿過附著層118的一部分以露出形成於半導體晶片120的第一表面122上的I/O墊A'。如第3圖所示，將電路板112 的周邊部分(接近半導體晶片120的第一表面122的周邊邊緣)設計為包括：梯狀(stair-like)部分112a。該梯狀部分112a具有複數個次層160，垂直地形成於第一表面114和第二表面116之間並且由通孔150露出。另外，梯狀部分112的次層160與電路板112的第一表面114和第二表面116不共平面。通孔150也露出電路板120的複數個次層160中形成的導電線路和導電互連(均未示出)，並且複數個接合墊B'形成於該導電線路和導電互連(均未示出)上，其中該導電線路和導電互連(均未示出)形成於電路板120的由通孔150露出的複數個次層160中的每一個中。導電元件136形成於電路板112的第二表面116上。
另外，在通孔150中設置一條或者複數條導電連接134，並且該一條或者複數條導電連接134跨越在I/O墊A'和接合墊B'之間，以電性連接半導體晶片120與電路板112。如第3圖所示，導電連接134可以為由金或者鋁形成的接合線。
另外，包封層130覆蓋半導體晶片120的第二表面124及散熱層132的部分，從而露出半導體晶片20的散熱層132的頂面的位於半導體晶片120上方的部分。包封層130也填充散熱層132與半導體晶片20之間的空間。另外，包封層130也填充通孔150並且覆蓋通孔150露出的導電連接134，接合墊B'以及I/O墊A'。通過使樹脂材料(如環氧樹脂)成型和固化，或者通過澆注並固化液體樹脂材料(如環氧樹脂)來形成包封層130。散熱層132例如可以形成第3圖所示的像Ω一樣的形狀，該散熱層32具有接觸電路板12的部分並且可 以由銅、鋁或者另一金屬合金形成。需要說明的是，在一些實施例中，散熱層32可以省略或者採用其他的形狀或設置方式等。
如第3圖所示，由於半導體晶片120通過將主動的第一表面122(也可稱為主動面)面向電路板112的方式安裝於電路板112上，使得散熱層132可以直接設置在半導體晶片132的鈍性的第二表面124的上方，而無需在散熱層132和第二表面124之間形成額外的熱傳導(thermal conductive)襯墊。相應地，可以降低半導體封裝100的厚度。另外，導電元件136例如可以由鉛錫焊料或者一些其他的金屬製成，並且作為半導體封裝110的I/O端。每個導電元件136通過導電連接134和接合墊B'而分別電性連接至半導體晶片120的I/O墊A'及接合墊B'，其中接合墊B'形成於導電線路與導電互連(均未示出)上，而該導電線路與導電互連(均未示出)形成於電路板112的梯狀部分112a的次層160，並且該次層160由通孔150露出。導電元件136允許半導體封裝110安置在母板(未示出)上。其他組態的I/O端的也是可能的。
在第3圖所示的示範性的半導體封裝100中，由於至少在第一表面122的中央部分提供了額外的I/O墊A，因此可以降低半導體晶片120中的電壓降效應，並且使得在I/O墊A'與電路板112的梯狀部分112a的次層160之間可以提供諸如接合線等導電連接134，其中I/O墊A'位於半導體晶片120的第一表面122的中央和周邊部分上，並且通孔150露出次層160。
另外，由於I/O墊A'位於半導體晶片120的第一表面122的中央並周邊部分，使得可以使用相對簡單的佈線結構來設計半導體晶片120中提供的互連結構，以連接主動或被動元件(位於半導體晶片120的中央部分)與I/O墊A'。因此，當趨勢是形成更有影響的半導體晶片120時，可以簡化半導體晶片120的製造，以及減少半導體晶片120的第一表面122的周邊邊緣附近的I/O墊A'的數量。
第4圖示出了第3圖所示的半導體晶片120的第一表面122的平面示意圖。如第4圖所示，出於簡化目的，僅示意了半導體晶片120的第一表面122上形成的I/O墊A'。
如第4圖所示，可以在半導體晶片120的第一表面122的周邊邊緣附近提供寬松的導電連接134(見第3圖)，以連接半導體晶片120的I/O墊A'和封裝基底112上形成的接合墊B'。另外，由於在半導體晶片120的第一表面122的中央部分提供額外的I/O墊A'，因此可以降低半導體封裝100的尺寸以在I/O墊A'和接合墊B'之間容納更多的連接，由於收縮半導體封裝100的尺寸的趨勢，因此這是受歡迎的。
另外，在半導體封裝100中，如第3~4圖中所示的I/O墊A'的組態允許更短的線迴路(wire loop)和降低電壓降效應，因此可以得到I/O墊的更靈活的IC設計。
第5~7圖為電路板112中形成的通孔的佈侷的各種實施例的示意圖，其中示意了電路板112的第二表面116，其上具有凸塊(如前述的導電元件136)。
如第5圖所示，提供一個具有矩形形狀的通孔150 來作為電路板112的中心，並且其他的通孔150形成連續的矩形溝道來圍繞該具有矩形形狀的通孔150，並且與該具有矩形形狀的通孔150脫離開。
另外，如第6圖所示，在電路板112的第二表面116上設置為十字交叉的構造的通孔150。
另外，如第7圖所示，通孔150設置為通過電路板112彼此隔離的複數個溝道。如第7圖所示，通孔150之一可以形成為第一溝道，而其他的通孔可以在第一溝道的相對側上形成為第二溝道。
在其他的實施例中，根據半導體晶片120的I/O墊A'的各種設計，可以進一步調整通孔150的組態並且通孔150可以為其他形狀，而不限制於第5~7圖所示的組態和形狀。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
100‧‧‧半導體封裝
112‧‧‧電路板
120‧‧‧半導體晶片
130‧‧‧包封層
132‧‧‧散熱層
136‧‧‧導電元件
122、114‧‧‧第一表面
124、116‧‧‧第二表面
A'‧‧‧I/O墊
118‧‧‧附著層
B'‧‧‧接合墊
134‧‧‧導電連接
130‧‧‧包封層
132‧‧‧散熱層
150‧‧‧通孔
112a‧‧‧梯狀部分
160‧‧‧次層

Claims (16)

  1. 一種半導體封裝，包括：一電路板，包括：相對的第一和第二表面，以及複數個通孔；一半導體晶片，形成於該電路板的該第一表面上，並且該半導體晶片的主動面朝向該電路板的該第一表面；以及複數個導電連接，穿過該等通孔並且將該半導體晶片與該電路板電性連接；其中，該等導電連接為接合線。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一附著層，形成於該電路板的該第一表面與該半導體晶片的該主動面之間；其中，該等通孔穿透該附著層以露出該主動面的部分。
  3. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一第一包封層，填充該等通孔並且覆蓋該等導電連接。
  4. 如申請專利範圍第1項所述的半導體封裝，其中，該等通孔包括：一第一通孔，露出該半導體晶片的該主動面的中央部分；以及一第二通孔，露出該半導體晶片的該主動面的周邊部分。
  5. 如申請專利範圍第1項所述的半導體封裝，其中，該電路板包括：一梯狀部分，具有複數個次層，並且該等次層形 成於該電路板的該第一表面和該第二表面之間，並且該等通孔將該等次層露出。
  6. 如申請專利範圍第5項所述的半導體封裝，其中，該梯狀部分設置於該電路板的位置鄰近該半導體晶片的該主動面的周邊部分。
  7. 如申請專利範圍第4項所述的半導體封裝，其中，於該電路板的該第二表面上，該第一通孔形成為第一溝道，並且該第二通孔形成複數個彼此隔開的第二溝道，並且該等第二溝道分別位於該第一溝道的兩側。
  8. 如申請專利範圍第4項所述的半導體封裝，其中，於該電路板的該第二表面上，該第一和第二通孔形成為十字交叉結構。
  9. 如申請專利範圍第4項所述的半導體封裝，其中，於該電路板的該第二表面上，該第一通孔包括：一矩形通孔，並且該第二通孔形成連續的矩形溝道，其中，該連續的矩形溝道圍繞該第一通孔。
  10. 如申請專利範圍第5項所述的半導體封裝，其中，該梯狀部分的該等次層與該電路板的該第一表面和該第二表面均不共平面。
  11. 如申請專利範圍第5項所述的半導體封裝，其中，該等導電連接之一還電性連接設置於該等次層之一上的接合墊。
  12. 如申請專利範圍第1項所述的半導體封裝，其中，該半導體晶片的該主動面上的中央部分和周邊部分均設置有複數個接合墊，並且該等通孔露出該等接合墊，並且該等導電 連接分別電性連接至該等接合墊。
  13. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一散熱層，形成於該半導體晶片的上方，並且於該散熱層與該半導體晶片之間沒有設置任何襯墊；以及一第二包封層，形成於該電路板上，並且覆蓋該散熱層、該半導體晶片和該電路板。
  14. 如申請專利範圍第13項所述的半導體封裝，其中，該第二包封層不物理接觸該半導體晶片的該主動面。
  15. 一種半導體封裝，包括：一電路板，包括：相對的第一和第二表面，以及複數個通孔；一半導體晶片，形成於該電路板的該第一表面上，並且該半導體晶片的主動面朝向該電路板的該第一表面；以及複數個導電連接，穿過該等通孔並且將該半導體晶片與該電路板電性連接；其中，該電路板包括：一梯狀部分，具有複數個次層，並且該等次層形成於該電路板的該第一表面和該第二表面之間，並且該等通孔將該等次層露出。
  16. 一種半導體封裝，包括：一電路板，包括：相對的第一和第二表面，以及複數個通孔；一半導體晶片，形成於該電路板的該第一表面上，並且該半導體晶片的主動面朝向該電路板的該第一表面；以及 複數個導電連接，將該半導體晶片與該電路板電性連接；其中，該電路板包括：一梯狀部分，具有複數個次層，並且該等次層形成於該電路板的該第一表面和該第二表面之間，並且該等通孔將該等次層露出；其中，該等導電連接之一電性連接設置於該等次層之一上的接合墊以及該半導體晶片的I/O墊。
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