TWI587759B - 三維空間封裝結構及其製造方法 - Google Patents

三維空間封裝結構及其製造方法 Download PDF

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TWI587759B
TWI587759B TW103143915A TW103143915A TWI587759B TW I587759 B TWI587759 B TW I587759B TW 103143915 A TW103143915 A TW 103143915A TW 103143915 A TW103143915 A TW 103143915A TW I587759 B TWI587759 B TW I587759B
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electronic component
electronic components
disposed
dimensional space
electronic
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TW103143915A
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TW201543971A (zh
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呂保儒
吳明佳
呂紹維
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乾坤科技股份有限公司
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Description

三維空間封裝結構及其製造方法
本發明係有關於一種封裝結構，特別是有關於一種三維空間封裝結構。
電子封裝結構藉由複雜的封裝製程所形成。不同的電子封裝結構具有不同的電性和散熱能力，因此設計者根據設計需求可選擇具有理想電性和散熱能力的電子封裝結構。
第1圖例示傳統電子封裝結構100的示意圖。參閱第1圖，傳統電子封裝結構100包含一印刷電路板(PCB)110和複數個電子元件120。電子元件120配置在印刷電路板110的表面112上且電性連接印刷電路板110。印刷電路板110具有從印刷電路板110的另一面114向外延伸的複數個引腳(pin)116以電性連接一電子裝置，例如主機板(motherboard)(未圖示)。
第2圖例示另一個傳統電子封裝結構200的剖面示意圖。參閱第2圖，傳統電子封裝結構200包含一線路基板210和複數個電子元件220。電子元件220配置在線路基板210的表面212上且透過打線(wire bond)技術、覆晶(flip-chip)結合技術或表面黏著技術(surface mount technology)電性連接線路基板210。此外，傳統電子封裝結構200透過焊料膠(solder paste)或複數個焊球(solder ball)(未圖示)可電性連接一電子裝置(例如主機板)(未圖示)。
應該要注意的是，傳統電子封裝結構100的電子元件120全配置在印刷電路板110的表面112上，且傳統電子封裝結構200的電子元件220全配置在線路基板210的表面212上。因此，在傳統電子封裝結構100、200中，印刷電路板110和線路基板210具有較低的空間使用，使得傳統電子封裝結構100、200具有較大的尺寸。
傳統上，單列直插式封裝(SIP : Single Inline Package）、柵格陣列(LGA : Land Grid Array)和球格陣列(BGA : Ball Grid Array)廣泛使用於封裝結構中，例如電力元件/模組(像用於個人電腦、筆記型電腦、伺服機等等的直流轉直流轉換器)的封裝結構。然而，單列直插式封裝需要焊接、大面積和手動點膠；柵格陣列和球格陣列需要用於內部元件電性連接的焊接。因此，這種封裝具有許多缺點，包含：較高的成本(大面積和/或手動點膠、焊接)、較低的可靠度(焊料融化)和不佳的熱散逸。
因此，本發明提出了一封裝結構及其製造方法以克服上述的缺點。
本發明的一個目的係提供一種三維空間封裝結構以降低電子模組的尺寸。
在一個實施例中，揭露一種三維空間封裝結構，該三維空間封裝結構包含：一第一電子元件，具有一上表面和一下表面；複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及一連接結構，配置在該第一電子元件的該上表面上方，用以包覆(encapsulate)該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的複數個導電圖案，其中該複數個導電圖案配置在該複數個第二電子元件上方，用以電性連接該複數個第二電子元件和該第一電子元件。
在一個實施例中，一絕緣層配置在該第一電子元件上以形成在該複數個第二電子元件上方的一實質水平面，其中該複數個導電圖案配置在該實質水平面上方。在一個實施例中，該複數個第二電子元件的至少一接點配置在該實質水平面上。
在一個實施例中，該第一電子元件的該上表面包含一凹洞(cavity)，其中該複數個第二電子元件中至少一個配置在該凹洞中。因此，相較於傳統的電子封裝結構，三維空間封裝結構的空間可更有效率地使用。
在一個實施例中，複數個第二電子元件包含電容、電阻、二極體、金氧半場效電晶體(MOSFET)、裸晶片和積體電路中至少一個。
在一個實施例中，第一電子元件可為一分離式(discrete)電子元件；分離式電子元件可為一電感或任何其它電子元件(例如電容)；電感可為一低溫共燒陶瓷(LTCC)電感。
在一個實施例中，複數個第二電子元件包含至少一電力模組。
在一個實施例中，進一步包含配置在該第一電子元件旁的至少一第二電子元件。
在本發明的一個實施例中，該複數個導電圖案進一步包含一屏蔽層。
在一個實施例中，該至少一絕緣層包含一ABF(Ajinomoto Build-up Film)。
在一個實施例中，一環氧模造物(EMC/epoxy molding compound)層配置在該第一電子元件的該上表面上，其中該複數個第二電子元件和該複數個導電圖案中至少一個配置在該環氧模造物層上。
在一個實施例中，該複數個導電圖案藉由黃光薄膜製程所形成。
本發明的一個實施例係提供製造三維空間封裝結構的一方法。該方法包含：(a)提供具有一上表面和一下表面的一第一電子元件；(b)在該第一電子元件的該上表面上方配置複數個第二電子元件；以及(c)在該複數個第二電子元件上方形成複數個導電圖案以電性連接該複數個第二電子元件和該第一電子元件。
本發明的一個實施例係提供製造複數個三維空間封裝模組的一方法。該方法包含：(a)在一載板上提供複數個第一電子元件，其中各個該第一電子元件具有一上表面和一下表面；(b)在各個該第一電子元件的該上表面上方配置複數個第二電子元件；(c)在各個該第一電子元件上的該複數個第二電子元件上方形成複數個導電圖案以電性連接該複數個第二電子元件和該第一電子元件；以及(d)形成該複數個三維空間封裝模組，其中各個該三維空間封裝模組分別包含一對應的第一電子元件和配置在該對應的第一電子元件上的該複數個第二電子元件。
在參閱接下來的段落及所附圖式所描述之本發明的實施例及詳細技術之後，該技術領域具有通常知識者便可瞭解本發明之技術特徵及實施態樣。
本發明的詳細說明於隨後描述，這裡所描述的較佳實施例是作為說明和描述的用途，並非用來限定本發明之範圍。
下面的多個實施例揭露一三維空間封裝模組和用於製造該三維空間封裝模組的一方法。三維空間封裝係指一封裝結構，在該封裝結構上的導電元件不僅建構成為平面且在高度上堆積，用以增進空間效率。
本發明的一個實施例揭露了一三維空間封裝結構，該三維空間封裝結構包含：一第一電子元件，具有一上表面和一下表面；複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及一連接結構，配置在該第一電子元件的該上表面上方，用以包覆(encapsulate)該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的複數個導電圖案，其中該複數個導電圖案配置在該複數個第二電子元件上方，用以電性連接該複數個第二電子元件和該第一電子元件。
第3A圖和第3B圖根據本發明的第一實施例例示一三維空間封裝結構的剖面示意圖。參閱第3A圖和第3B圖，三維空間封裝結構300包含配置在第一電子元件320的上表面上方的一連接結構330，用以包覆複數個第二電子元件310；第一電子元件320具有一上表面320a和一下表面320b；複數個第二電子元件310(如第3A圖和第3B圖所示的三個電子元件)配置在第一電子元件320的上表面320a上方；複數個導電圖案(例如複數個導孔331和線路層332)配置在複數個第二導電元件310上方，用以電性連接複數個第二導電元件310和第一電子元件320。在一個實施例中，複數個第二電子元件310中至少兩個透過複數個導電圖案(例如複數個導孔331和線路層332)電性連接。換句話說，連接結構330配置在第一電子元件的上表面上方以包覆複數個第二電子元件，其中該連接結構330包含導電圖案(例如複數個導孔331和線路層332)以電性連接複數個第二電子元件310和第一電子元件320，其中至少一絕緣層(例如ABF(Ajinomoto Build-up Film)333)用來分離複數個導電圖案。在一個實施例中，ABF 333藉由壓至以包覆複數個第二電子元件310而附在第一電子元件320的上表面。請注意可使用非ABF 333的其它絕緣材料，且不同層可包含不同的絕緣材料。
導電圖案可藉由任何適合的圖案化製程(例如黃光製程)形成。導電圖案可包含在連接結構之上表面上的一些墊片，用以連接其它電路。導電圖案連接複數個第二電子元件310的至少一接點至三維空間封裝結構300之上表面上的墊片，用以連接一外部電路，例如印刷電路板。在一個實施例中，各個第二電子元件310的一或多個接點配置在對應電子元件的上表面上。換句話說，各個第二電子元件310的所有或一部分接點面向印刷電路板。
在一個實施例中，一絕緣層配置在第一電子元件320上以形成在複數個第二電子元件310上方的一實質水平面，其中導電圖案配置在該實質水平面上方。
為了方便在複數個第二電子元件310上方施加圖案化製程，複數個第二電子元件310在線路基板上的投影面積可小於第一電子元件320在線路基板上的投影面積。較佳來說，第一電子元件320的至少一接點和複數個第二電子元件310的至少一接點面向線路基板且透過導電圖案電性連接線路基板，該導電圖案形成在複數個第二電子元件310的至少一接點朝上之時(第一電子元件320的至少一接點可朝上)。
為了在第一電子元件320的上表面320a上使第一電子元件320的至少一接點和複數個第二電子元件310達到最佳的配置，複數個第二電子元件310配置在第一電子元件320的上表面320a之中央，且第一電子元件320的至少一接點配置在第一電子元件320的上表面320a之周圍。在一個實施例中，第一電子元件320可具有一第一接點(未圖示)和一第二接點(未圖示)；該第一接點配置在上表面320a的一第一邊緣且該第二接點配置在上表面320a的一第二邊緣(該第二邊緣相對於該第一邊緣)。
第一電子元件320可包含在其中的一凹洞(cavity)(未圖示)，且複數個第二電子元件310可配置在該凹洞中以進一步降低三維空間封裝結構的高度。凹洞係以不同的方式實現：在一個實施例中，凹洞係形成於第一電子元件320的內部；在另一個實施例中，凹洞的一邊和第一電子元件320的一邊對齊；在更另一個實施例中；凹洞的兩邊分別和第一電子元件320的兩邊對齊。
為了在第一電子元件320的上表面320a上使第一電子元件320的至少一接點和複數個第二電子元件310達到最佳的配置，凹洞配置在第一電子元件320的上表面320a之中央，複數個第二電子元件310配置在凹洞中，且第一電子元件320的至少一接點配置在凹洞周圍。在一個實施例中，第一電子元件320可具有一第一接點(未圖示)和一第二接點(未圖示)；該第一接點配置在凹洞的一第一側且該第二接點配置在在凹洞的一第二側(該第二側相對於該第一側)。
第3C圖至第3E圖例示另一三維空間封裝結構的剖面示意圖。導電圖案可透過在第一電子元件320之側表面320C旁的複數個貫穿孔351延伸至第一電子元件320的下表面320b以在第一電子元件320之下表面320b上形成複數個墊片352或以電性連接配置第一電子元件320之下表面320b上的一第三電子元件353。貫穿孔351可形成在第一電子元件320之側表面320C旁的第一絕緣材料356中。在一個實施例中，第一絕緣材料356和分離導電圖案的第二絕緣材料333可相同。較佳來說，第一絕緣材料356和第二絕緣材料333可由ABF(Ajinomoto Build-up Film)製成。在一個實施例中，第一絕緣材料356和分離導電圖案的第二絕緣材料333可不同。選擇性地，第一絕緣材料356和第二絕緣材料333的邊界可對齊第一電子元件320的上表面320a，但本發明並不侷限此案例。較佳來說，第一絕緣材料356可由環氧模造物(EMC/epoxy molding compound)製成，且第二絕緣材料333可由ABF製成。
三維空間封裝結構300一般應用在電壓調節器模組、電力模組、網路轉接器、繪圖處理單元、直流對直流轉換器、負載點轉換器。第一電子元件320可為一分離式(discrete)電子元件。分離式電子元件可為一電感或任何其它電子元件(例如電容)。電感可為一低溫共燒陶瓷(LTCC)型電感或任何其它種電感。如第3B圖所示，第一電子元件320的上表面320a可進一步包含一凹洞320c，且該複數個第二電子元件310中至少一個配置在該凹洞320c中以增加空間效率。
各個第二電子元件310可為一邏輯控制元件、一驅動元件或一被動元件。被動元件可為一電容、具有較小電感值的一電感或一電阻。各個第二電子元件310可為一電力元件，例如金氧半場效電晶體(MOSFET)、絕緣閘雙極電晶體(IGBT)、一裸晶片、一積體電路或一二極體。
複數個導電圖案可藉由薄膜技術(例如黃光、濺鍍、電鍍或化學氣相沉積製程)形成。複數個導電圖案也可以多層的型式存在。如第3A圖所示，複數個導電圖案包含複數個導孔331和線路層332。複數個導電圖案的導孔331和線路層332可提供所需的電性連接。在一個實施例中，絕緣層使用ABF 333以結合第一電子元件320、複數個第二電子元件310和複數個導電圖案330為一完整的本體。請注意可使用非ABF 333的其它絕緣材料，且不同層可包含不同的絕緣材料。
換句話說，一連接結構配置在第一電子元件的上表面上方，用以包覆複數個第二電子元件，其中該連接結構包含用以電性連接複數個第二電子元件和第一電子元件的複數個導電圖案(例如複數個導孔和線路層)和用以分離複數個導電圖案的至少一絕緣層(例如ABF)。
在一個實施例中，三維空間封裝結構300進一步包含配置在連接結構330中的一屏蔽層(未圖示)，用於電磁干擾屏蔽。在一個實施例中，一環氧模造物層配置在第一電子元件的上表面上，其中複數個第二電子元件和一些導電圖案可配置在該環氧模造物層上，其中連接結構330可配置在該環氧模造物層上以包覆複數個第二電子元件和該些導電圖案，其中該些導電圖案可電性連接在連接結構330中的導電圖案。在一個實施例中，至少一墊片可配置在連接結構330的上表面上，用以連接一外部印刷電路板。
由於本發明的實施例之故，對於線路和元件連接的強度和可靠度優於傳統的焊接和打線。可縮短佈線距離以降低電阻值並提升效率；此外，可進一步降低整體封裝結構的高度。
第4A圖至第4C圖根據本發明的第一實施例例示一三維空間封裝結構的製造方法。參閱第4A圖，說明提供具有一上表面420a和一下表面420b的一第一電子元件420之步驟。第一電子元件可為一分離式電子元件。分離式電子元件可為一電感或任何其它電子元件(例如電容)。電感可為一低溫共燒陶瓷(LTCC)型電感或任何其它種電感。第一電子元件420的上表面420a可露出第一電子元件420的電極421作為電性連接之用。為了大量生產和降低成本，複數個第一電子元件可同時提供且藉由膠帶(tape)(或治具(fixture))(未圖示)或環氧模造物(未圖示)以矩陣(matrix)配置。
參閱第4B圖，說明在該第一電子元件420的該上表面420a上方配置複數個第二電子元件410之步驟。第一電子元件420可包含一凹洞(未圖示)，且複數個第二電子元件410中至少一個配置在該凹洞中以進一步降低三維空間封裝結構的高度。在此步驟中，焊接、晶片附著膜或晶片結合漿可用於各個第二電子元件410的附著/定位。
各個第二電子元件410可為一邏輯控制元件、一驅動元件或一被動元件。被動元件可為一電容、具有較小電感值的一電感或一電阻。各個第二電子元件410可為一電力元件，例如金氧半場效電晶體、絕緣閘雙極電晶體、一積體電路或一二極體。
參閱第4C圖，說明在該複數個第二電子元件410上方配置複數個導電圖案(在連接結構430中)以電性連接該複數個第二電子元件410和該第一電子元件420之步驟。
在連接結構430中的複數個導電圖案可藉由薄膜技術(例如黃光、濺鍍、電鍍或化學氣相沉積製程)形成。在連接結構430中的複數個導電圖案也可以多層的型式配置(該多層具有由不同型式材料製成的多個絕緣層)且建構成不同功能。雷射可用來在複數個導電圖案中形成複數個導孔。線路層和導電材料可藉由電鍍製程配置。複數個導電圖案的導孔和線路層可提供所需的電性連接；絕緣層可使用ABF以結合第一電子元件420、複數個第二電子元件410和複數個導電圖案為一完整的本體。複數個導電圖案可進一步包含一屏蔽層(未圖示)，用於電磁干擾屏蔽。連接結構430可進一步包含的一環氧模造物層(未圖示)作為結合之用。
如第4C圖所示，可包含一切割製程(所示為破折線)以互相分離單一封裝模組。
第5A圖至第5C圖根據本發明的第二實施例例示一三維空間封裝結構的製造方法。此實施例和第一實施例的差別在於各個三維空間封裝結構模組進一步包含在第一電子元件520旁的至少一分離式電子元件510a。導電圖案530將分離式電子元件510a的至少一接點引導至三維空間封裝結構的上表面，用以結合至線路基板。分離式電子元件510a的至少一接點可配置在分離式電子元件510a的上表面上。換句話說，分離式電子元件510a的至少一接點面向線路基板。參閱第5A圖，說明提供具有一上表面520a和一下表面520b的一第一電子元件520之步驟。第一電子元件520可為一分離式電子元件。分離式電子元件可為一電感或任何其它電子元件(例如電容)。電感可為一低溫共燒陶瓷(LTCC)型電感或任何其它種電感。第一電子元件520的上表面520a可露出第一電子元件520的電極(未圖示)作為電性連接之用。為了大量生產和降低成本，複數個電感可同時提供且藉由膠帶(或治具)520c或環氧模造物(未圖示)以矩陣配置。
參閱第5B圖，說明在該第一電子元件520的該上表面520a上方配置複數個第二電子元件510，且在該第一電子元件520旁配置至少一第二電子元件510a(例如電容)。第一電子元件520可包含一凹洞(未圖示)，且複數個第二電子元件510中至少一個配置在該凹洞中以進一步降低三維空間封裝結構的高度。在此步驟中，焊接/晶片附著膜/晶片結合漿可用於各個第二電子元件510的附著/定位。
各個第二電子元件510、510a可為一邏輯控制元件、一驅動元件或一被動元件。被動元件可為一電容、具有較小電感值的一電感或一電阻。各個第二電子元件510、510a可為一電力元件，例如金氧半場效電晶體、絕緣閘雙極電晶體、一積體電路、一裸晶片或一二極體。
參閱第5C圖，說明在該複數個第二電子元件510、510a上方配置複數個導電圖案(在一連接結構530中)以電性連接該複數個第二電子元件510、510a和該第一電子元件520之步驟。
複數個導電圖案(例如複數個導孔531和線路層532)可藉由薄膜技術(例如黃光、濺鍍、電鍍或化學氣相沉積製程)形成。複數個導電圖案也可以多層的型式配置。雷射可用來形成複數個導孔531。線路層532可藉由電鍍製程配置。導孔531和線路層532可提供所需的電性連接；絕緣層(例如ABF)可結合第一電子元件520、複數個第二電子元件510、510a和複數個導電圖案為一完整的本體。複數個導電圖案可進一步包含一屏蔽層(未圖示)，用於電磁干擾屏蔽。連接結構530可進一步包含一環氧模造物層(未圖示)作為結合之用。
如第5C圖所示，可包含一切割製程(所示為破折線)以互相分離單一封裝模組。在本發明中，製造方法不侷限於電感，但也不侷限於電感元件。
從上面多個實施例的敘述中，本發明的結構及其製造方法可提供許多優點，包含：1.散熱和導電具有較佳的性能；2.藉由形成複數個導電圖案和使用薄膜技術和製程(藉由具有極薄的多個導電圖案的一導電圖案群以連接所有的導電元件)以達到較小的尺寸；3.較低成本、小尺寸和較佳的結合強度/可靠度。 【1】 【2】 【3】 【4】 【5】 【6】 【7】 【8】 【9】 【10】 【11】 【12】 【13】 【14】 【15】 【16】 【17】 【18】 【19】 【20】 【21】 【22】 【23】 【24】 【25】 【26】
雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。雖然在上述描述說明中並無完全揭露這些可能的更動與替代，而接著本說明書所附之專利保護範圍實質上已經涵蓋所有這些態樣。
100‧‧‧傳統電子封裝結構 110‧‧‧印刷電路板 112‧‧‧表面 114‧‧‧另一面 116‧‧‧引腳 120‧‧‧電子元件 200‧‧‧傳統電子封裝結構 210‧‧‧線路基板 212‧‧‧表面 220‧‧‧電子元件 300‧‧‧三維空間封裝結構 310‧‧‧第二電子元件 320‧‧‧第一電子元件 320a‧‧‧上表面 320b‧‧‧下表面 320c‧‧‧凹洞 320C‧‧‧側表面 330‧‧‧連接結構 331‧‧‧導孔 332‧‧‧線路層 333‧‧‧ABF 351‧‧‧貫穿孔 352‧‧‧墊片 353‧‧‧第三電子元件 356‧‧‧第一絕緣材料 410‧‧‧第二電子元件 420‧‧‧第一電子元件 420a‧‧‧上表面 420b‧‧‧下表面 421‧‧‧電極 430‧‧‧連接結構 510‧‧‧第二電子元件 510a‧‧‧分離式電子元件 520‧‧‧第一電子元件 520a‧‧‧上表面 520b‧‧‧下表面 520c‧‧‧膠帶 530‧‧‧連接結構 531‧‧‧導孔 532‧‧‧線路層
本發明之前面所述的態樣及所伴隨的優點將藉著參閱以下的詳細說明及結合圖式更加被充分瞭解，其中： 第1圖例示傳統電子封裝結構的示意圖； 第2圖例示另一個傳統電子封裝結構的剖面示意圖； 第3A圖和第3B圖根據本發明的第一實施例例示一三維空間封裝結構的剖面示意圖； 第3C圖至第3E圖例示另一三維空間封裝結構的剖面示意圖； 第4A圖至第4C圖根據本發明的第一實施例例示一三維空間封裝結構的製造方法； 第5A圖至第5C圖根據本發明的第二實施例例示一三維空間封裝結構的製造方法。
300‧‧‧三維空間封裝結構
310‧‧‧第二電子元件
320‧‧‧第一電子元件
320a‧‧‧上表面
320b‧‧‧下表面
330‧‧‧連接結構
331‧‧‧導孔
332‧‧‧線路層
333‧‧‧ABF

Claims (24)

  1. 一種三維空間封裝結構，包含：一第一電子元件，具有一上表面和一下表面；一複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及一連接結構，配置在該第一電子元件的該上表面上並包覆該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的一複數個第一導電圖案，其中該至少一絕緣層設置在該第一電子元件的該上表面上且至少一導電通孔設置在該至少一絕緣層中，該複數個第一導電圖案配置在該複數個第二電子元件上方且通過該至少一導電通孔以電性連接該複數個第二電子元件以及該第一電子元件。
  2. 如申請專利範圍第1項所述之三維空間封裝結構，其中一部分的該複數個第一導電圖案電性連接該複數個第二電子元件中至少兩個電子元件。
  3. 如申請專利範圍第1項所述之三維空間封裝結構，其中該第一電子元件為一電感。
  4. 如申請專利範圍第3項所述之三維空間封裝結構，其中該電感為一低溫共燒陶瓷(LTCC)電感。
  5. 如申請專利範圍第1項所述之三維空間封裝結構，其中一絕緣層配置在該第一電子元件上以形成在該複數個第二電子元件上方的一實質水平面，其中該複數個第一導電圖案配置在該實質水平面上方。
  6. 如申請專利範圍第5項所述之三維空間封裝結構，其中該複數個第二電子元件的至少一接點配置在該實質水平面上。
  7. 如申請專利範圍第5項所述之三維空間封裝結構，其中該複數個第二電子元件的所有接點配置在該實質水平面上。
  8. 如申請專利範圍第1項所述之三維空間封裝結構，其中至少一墊片配置在該連接結構的上表面上，用以連接外部電路。
  9. 如申請專利範圍第1項所述之三維空間封裝結構，其中該第一電子元件的該上表面包含一凹洞，其中該複數個第二電子元件中至少一個配置在該凹洞中。
  10. 如申請專利範圍第1項所述之三維空間封裝結構，進一步包含至少一第三電子元件和一環氧模造物層，其中該至少一第三電子元件配置在該第一電子元件旁，且該環氧模造物層包覆至少一部分的該第一電子元件和該至少一第三電子元件。
  11. 如申請專利範圍第10項所述之三維空間封裝結構，其中該至少一第三電子元件包含一電容。
  12. 如申請專利範圍第1項所述之三維空間封裝結構，其中各個該第二電子元件為一電容、一電阻、一二極體、一電晶體、一裸晶片或一積體電路。
  13. 如申請專利範圍第1項所述之三維空間封裝結構，其中該連接結構的該至少一絕緣層中每一層由ABF(Ajinomoto Build-up Film)製成。
  14. 如申請專利範圍第1項所述之三維空間封裝結構，進一步包含一環氧模造物層，其中該環氧模造物層配置在該第一電子元件的該上表面上，其中該複數個第二電子元件和一第二導電圖案配置在該環氧模造物層上，其中該第二導電圖案電性連接該複數個第一導電圖案。
  15. 如申請專利範圍第1項所述之三維空間封裝結構為一直流對直流轉換器或一電力模組。
  16. 如申請專利範圍第15項所述之三維空間封裝結構，其中該第一電子元件為一電感。
  17. 一種製造三維空間封裝結構的方法，包含：(a)提供具有一上表面和一下表面的一第一電子元件；(b)在該第一電子元件的該上表面上方配置複數個第二電子元件；以及 (c)在該第一電子元件的該上表面上方形成一連接結構，用以包覆該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的複數個導電圖案，其中該複數個導電圖案配置在該複數個第二電子元件上方，用以電性連接該複數個第二電子元件以及該第一電子元件。
  18. 如申請專利範圍第17項所述之方法，其中在步驟(c)中，該至少一絕緣層包含一ABF層，其中該ABF層被壓至該第一電子元件的該上表面，用以包覆該複數個第二電子元件。
  19. 如申請專利範圍第17項所述之方法，其中步驟(c)包含一薄膜製程以形成該複數個導電圖案。
  20. 一種製造複數個三維空間封裝模組的方法，包含：(a)在一載板上提供一複數個第一電子元件，其中各個該第一電子元件具有一上表面和一下表面；(b)在各個該第一電子元件的該上表面上方配置一複數個第二電子元件；(c)在各個該第一電子元件上的該複數個第二電子元件上方形成複數個導電圖案以電性連接該複數個第二電子元件及該第一電子元件；以及(d)形成該複數個三維空間封裝模組，其中各個該三維空間封裝模組分別包含一對應的第一電子元件和配置在該對應的第一電子元件上的該複數個第二電子元件。
  21. 如申請專利範圍第20項所述之方法，其中該載板包含膠帶、治具或環氧模造物中至少一個。
  22. 一種三維空間封裝結構，包含：一第一電子元件，具有一上表面和一下表面；一複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及 一連接結構，配置在該第一電子元件的該上表面上方，用以包覆該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的一複數個第一導電圖案，其中該複數個第一導電圖案配置在該複數個第二電子元件上方，用以電性連接該複數個第二電子元件以及該第一電子元件，其中該第一電子元件的該上表面包含一凹洞，其中該複數個第二電子元件中至少一個配置在該凹洞中。
  23. 一種三維空間封裝結構，包含：一第一電子元件，具有一上表面和一下表面；一複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及一連接結構，配置在該第一電子元件的該上表面上方，用以包覆該複數個第二電子元件，其中該連接結構包含至少一絕緣層和被該至少一絕緣層所分離的一複數個第一導電圖案，其中該複數個第一導電圖案配置在該複數個第二電子元件上方，用以電性連接該複數個第二電子元件以及該第一電子元件，其中一環氧模造物層配置在該第一電子元件的該上表面上，其中該複數個第二電子元件和一第二導電圖案配置在該環氧模造物層上，其中該第二導電圖案電性連接該複數個第一導電圖案。
  24. 一種三維空間封裝結構，包含：一第一電子元件，具有一上表面和一下表面；一複數個第二電子元件，配置在該第一電子元件的該上表面上方；以及至少一絕緣層，配置在該第一電子元件的該上表面上並包覆該複數個第二電子元件，其中至少一導電通孔設置在該至少一絕緣層中，一複數個第一導電圖案配置在該至少一絕緣層中並通過該至少一導電通孔以電性連接該複數個第二電子元件以及該第一電子元件。
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