WO2014171403A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2014171403A1
WO2014171403A1 PCT/JP2014/060466 JP2014060466W WO2014171403A1 WO 2014171403 A1 WO2014171403 A1 WO 2014171403A1 JP 2014060466 W JP2014060466 W JP 2014060466W WO 2014171403 A1 WO2014171403 A1 WO 2014171403A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
wiring board
semiconductor chip
insulating base
conductive pattern
Prior art date
Application number
PCT/JP2014/060466
Other languages
English (en)
French (fr)
Inventor
任志 友廣
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ピーエスフォー ルクスコ エスエイアールエル filed Critical ピーエスフォー ルクスコ エスエイアールエル
Priority to US14/784,632 priority Critical patent/US20160064301A1/en
Publication of WO2014171403A1 publication Critical patent/WO2014171403A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding

Definitions

  • the present invention relates to a semiconductor device having a semiconductor chip.
  • a plurality of heat radiating solder balls are provided in a central region of a connection surface (substrate connection surface) to a mounting substrate of a wiring board of a package. Since the semiconductor device disclosed in Patent Document 1 has a configuration in which heat is transmitted from a semiconductor chip to a plurality of heat radiating solder balls, heat generated from the semiconductor chip is transferred to the semiconductor chips via the heat radiating solder balls. It is transmitted to the connected mounting board and is released from the mounting board to the outside of the semiconductor device.
  • solder balls for heat radiation are arranged with a gap between the upper package and the lower package, the semiconductor chip of the lower package and the solder balls for heat radiation come into contact with each other, and the solder balls for heat radiation are mounted.
  • the substrate will not touch. As a result, there is a problem that heat generated from the semiconductor chip cannot be transmitted to the mounting substrate through the heat radiating solder balls and released, and the semiconductor device is heated.
  • the semiconductor device of the present invention includes a wiring board, a semiconductor chip, and a sealing body.
  • the wiring board includes an insulating base, a conductive pattern formed on one surface of the insulating base, and a heat dissipation via connected to the conductive pattern.
  • the heat dissipating via is exposed to the side of the insulating base material and is provided so as to penetrate from one surface of the insulating base material to the other surface.
  • the semiconductor chip is mounted on the wiring board so as to overlap the conductive pattern.
  • the sealing body is formed on the wiring board so as to cover the semiconductor chip.
  • the conductive pattern is formed on one surface of the insulating base, heat generated from the semiconductor chip mounted so as to overlap the conductive pattern is transmitted to the conductive pattern.
  • the heat transferred to the conductive pattern is connected to the conductive pattern, exposed to the side of the insulating base material, transferred to the heat dissipation via that penetrates from one surface of the insulating base material to the other surface, and from the heat dissipation via. Released to the outside of the semiconductor device. Therefore, it is not necessary to form a plurality of heat radiating solder balls in the central region of the wiring substrate of the semiconductor chip, and the manufacturing cost of the entire semiconductor device can be reduced.
  • the package made of the semiconductor device of the present invention can also be applied to a PoP type semiconductor device. Further, the heat generated from the semiconductor chip is released to the outside through the conduction pattern through the heat dissipation via exposed on the side of the insulating base, so that the semiconductor device generates heat by the heat generated by the semiconductor chip. The possibility of being charged is reduced, and the reliability of the semiconductor device is improved.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along line A-A ′ in FIG. 1.
  • FIG. 2 is a cross-sectional view taken along line B-B ′ in FIG. 1.
  • It is sectional drawing which shows the assembly process of the semiconductor device of 1st Embodiment.
  • It is sectional drawing which shows the assembly process of the semiconductor device of 1st Embodiment.
  • It is sectional drawing which shows the assembly process of the semiconductor device of 1st Embodiment.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • the semiconductor device 1 includes a wiring substrate comprising an insulating base material 2 a in which a conductive pattern 12 and a heat radiating via 13 that penetrates from one surface to the other surface and is exposed to the side are formed. 2 and a semiconductor chip 3 mounted in the central region of one surface of the wiring board 2. Further, the semiconductor device 1 has a sealing body 4 formed on one surface of the wiring board 2 so as to cover the semiconductor chip 3. In FIG. 1, the sealing body 4 is partially removed to show the internal structure.
  • the wiring board 2 is made of an insulating base material 2a such as a glass epoxy board, and predetermined wiring patterns (not shown) are formed on one surface and the other surface of the insulating base material 2a, respectively.
  • the insulating film 2b such as a solder resist film is covered.
  • the wiring pattern on one surface is formed at a position that does not overlap with the conductive pattern 12 in a plan view, and is not connected to the conductive pattern 12.
  • the insulating film 2b has an opening 11 at a position facing a connection pad 6 and a heat dissipation via 13 described later.
  • connection pads 6 connected to a wiring pattern formed on one surface of the wiring board 2 along a pair of opposing sides of the mounted semiconductor chip 3 are openings 11 of the insulating film 2b. Is exposed from. Further, as shown in FIGS. 2 a and 2 b, a plurality of lands 7 are exposed from the opening 11 of the insulating film 2 b formed on the other surface of the wiring board 2.
  • the connection pads 6 and lands 7 are made of Cu or the like and are electrically connected via through vias formed inside the wiring board 2.
  • a plurality of solder balls 5 respectively connected to the lands 7 are provided on the other side of the wiring board 2 except for the central region. It is provided in two rows along the side.
  • the semiconductor chip 3 is, for example, a DRAM (Dynamic Random Access Memory) memory chip, and is formed in a rectangular plate shape as shown in FIG.
  • a plurality of electrode pads 9 are provided on one surface of the semiconductor chip 3 along a pair of opposing sides, and the other surface (connection surface) of the semiconductor chip 3 is as shown in FIGS. 2a and 2b.
  • the central region of the wiring board 2 is connected via an adhesive member 8.
  • an adhesive member 8 for example, an insulating paste or DAF (Die Attached Film) is used.
  • the connection pad 6 and the electrode pad 9 are adjacent to each other and are electrically connected by a conductive wire 10.
  • a conductive pattern 12 having a shape larger than the semiconductor chip 3 in plan view is formed on one surface of the insulating base 2a of the wiring board 2. Yes.
  • a semiconductor chip 3 is mounted immediately above the conductive pattern 12.
  • the heat radiation vias 13 are arranged along a pair of opposite sides of the wiring board 2 parallel to the pair of sides where the electrode pads 9 of the semiconductor chip 3 are not formed, and are exposed to the side of the insulating base 2a. is doing.
  • the heat dissipation via 13 penetrates from one surface of the insulating base material 2a to the other surface.
  • the heat radiating via 13 is exposed from the opening 11 of the insulating film 2 b, and a plating layer 15 is formed on the surface of the heat radiating via 13.
  • the heat radiation via 13 may not be exposed from the opening 11 of the insulating film 2b as long as it is exposed to the side of the insulating base 2a.
  • the conductive pattern 12 and the heat radiation via 13 are connected by a connection wiring 14.
  • the conductive pattern 12, the heat radiation via 13, and the connection wiring 14 are made of Cu or the like having high thermal conductivity.
  • the heat dissipation via 13 and the through via 30 are formed in the same size.
  • the heat generated by the semiconductor chip 3 is easily transmitted to the heat dissipation via 13 via the conductive pattern 12.
  • the heat radiating via 13 is exposed to the side of the insulating base 2 a, heat is easily released from the exposed heat radiating via 13 to the outside of the semiconductor device 1.
  • the heat dissipation via 13 is disposed through the insulating base 2a, the surface area where the air and the heat dissipation via 13 are in contact with each other on the side of the insulating base 2a is increased. High heat dissipation effect.
  • the semiconductor chip 3 itself is less likely to be heated, and the reliability of the semiconductor device 1 is improved. Furthermore, in the semiconductor device 1, the plating layer 15 is formed on the surface of the heat dissipation via 13, so that the surface area of the metal pattern exposed to the side of the insulating base 2 a is increased by the plating layer 15. be able to. In addition, since it is not necessary to additionally form a heat radiating solder ball or the like, the manufacturing cost of the semiconductor device 1 can be reduced.
  • a mother board 23 having a plurality of product forming sections 24 (parts that become the wiring board 2 after cutting) divided in a matrix by dicing lines 25 is prepared.
  • a plurality of connection pads 6 (see FIG. 1) and a conductive pattern 12 are formed on one surface of the product formation portion 24 of the mother board 23, and a plurality of lands are formed on the other surface of the product formation portion 24. 7 is formed.
  • a heat radiation via 13 is formed in a portion including the dicing line 25 so as to penetrate from one surface of the mother board 23 to the other surface.
  • insulating films 2b are provided on both surfaces of the mother substrate 23, and the connection pads 6 (see FIG. 1), the conductive pattern 12, the heat radiation vias 13, and the lands 7 are exposed from the openings 11 of the insulating film 2b. is doing.
  • an adhesive member 8 such as an insulating paste or DAF is applied on the insulating film 2 b in the central region of one surface of the product forming portion 24, and a semiconductor is formed on the adhesive member 8.
  • the semiconductor chip 3 is mounted so that the connection surface of the chip 3 and one surface of the wiring board 2 face each other.
  • the semiconductor chip 3 has a Si substrate on which a DRAM memory circuit or the like is formed on one surface, and a plurality of electrode pads 9 (see FIG. 1) are provided on the Si substrate. Further, a passivation film (not shown) for protecting the circuit is formed on one surface of the semiconductor chip 3 so as not to cover the surface of the electrode pad 9.
  • the wire 10 is made of, for example, Au or Cu.
  • a wire bonding apparatus (not shown) is used for wire bonding in which the electrode pad 9 and the connection pad 6 are connected by the wire 10. Specifically, after one end of the wire 10 melted and formed into a ball shape is subjected to ultrasonic thermocompression bonding to the electrode pad 9 of the semiconductor chip 3, the other end of the wire 10 is connected to the connection pad 6 of the mother substrate 23. Ultrasonic thermocompression bonding.
  • the wire 10 is arranged to draw a predetermined loop shape in order to avoid contact with the edge of the end portion of the semiconductor chip 3.
  • the sealing body 4 is formed on one surface of the mother substrate 23 so as to collectively cover the plurality of product forming portions 24.
  • the sealing body 4 is formed using a molding apparatus such as a transfer mold apparatus having a molding die (not shown) composed of an upper mold and a lower mold.
  • a cavity having a size that covers a plurality of product forming portions 24 at a time is formed in the upper die, and a recess for arranging the mother substrate 23 is formed in the lower die.
  • the mother board 23 on which the wires 10 are arranged is set in the concave part of the lower mold, the peripheral part of the mother board 23 is clamped by the upper mold and the lower mold, and the mother board 23 is arranged in the cavity. Thereafter, a thermosetting sealing resin such as an epoxy resin is filled into the cavity and is thermally cured at a predetermined temperature (for example, 180 ° C.), so that the sealing resin is cured and the sealing body 4 becomes the mother substrate. It is formed on one surface of 23.
  • a thermosetting sealing resin such as an epoxy resin
  • the process proceeds to a ball mounting process in which the solder balls 5 are formed on the other surface of the mother substrate 23.
  • conductive solder balls 5 are bonded onto the plurality of lands 7 arranged for each product forming portion 24 on the other surface of the mother board 23.
  • the solder balls 5 are adsorbed and held by a ball mounter (not shown) in which a plurality of adsorbing holes are formed in accordance with the arrangement of the lands 7 and are collectively joined to the lands 7 via a flux.
  • the product forming unit 24 is cut and separated along the dicing line 25 by a dicing device (not shown), whereby the semiconductor device 1 is formed as shown in FIG. 5e.
  • the dicing line 25 is provided so as to pass through the center of the heat dissipation via 13, the heat dissipation via 13 is cut to the side of the semiconductor device 1 by being cut and separated along the dicing line 25. Exposed.
  • FIG. 4 is a cross-sectional view showing a PoP type semiconductor device having a configuration in which the semiconductor device having the configuration described above is used as the upper package 16 and the upper package 16 is stacked on the lower package 17 having the semiconductor chip 3.
  • the lower package 17 includes a wiring board 2 having a predetermined wiring pattern (not shown) formed on one surface, and a semiconductor chip 3 mounted on the central region of one surface of the wiring board 2 via an underfill material 20. And have. Both surfaces of the wiring substrate 2 are covered with an insulating film 2b, and an opening (not shown) is provided in the insulating film 2b.
  • connection lands 19 connected to the solder balls 5 of the upper package 16 and connection pads 6 connected to the semiconductor chip 3 of the lower package 17 are exposed from the openings. ing.
  • a plurality of lands 7 are exposed from the openings, and solder balls 5 are connected to the lands 7, respectively.
  • the solder balls 5 on the other surface of the wiring substrate 2 of the upper package 16 and the connection lands 19 on one surface of the wiring substrate 2 of the lower package 17 are connected to each other to form a PoP type having two different semiconductor chips 3.
  • a semiconductor device 1 is formed.
  • solder ball 5 is not provided in the central region of the other surface of the wiring substrate 2 of the upper package 16, the semiconductor chip 3 mounted on the lower package 17 and the other of the wiring substrates 2 of the upper package 16 are provided.
  • the solder balls 5 on the surface do not come into contact. That is, the solder balls 5 on the other surface of the wiring substrate 2 of the upper package 16 are in contact with the wiring substrate 2 of the lower package 17 without contacting the semiconductor chip 3 of the lower package 17.
  • FIG. 5 is a cross-sectional view illustrating a state where the semiconductor device having the above-described configuration is mounted on a mounting board of an electronic device.
  • a mounting substrate 29 such as a mother board provided in the electronic device is made of an insulating base material 2a, and a predetermined wiring pattern (not shown) is formed on one surface and the other surface of the insulating base material 2a. .
  • These wiring patterns are covered with an insulating film 2b such as a solder resist film.
  • the insulating film 2b on one surface has an opening (not shown), and a plurality of mounting substrate-side lands 28 connected to the wiring pattern formed on one surface of the wiring substrate 2 include an insulating film. It is exposed from the opening 2b.
  • the mounting board side land 28 arranged immediately below the semiconductor device 1 to be mounted is connected to the land of the semiconductor device 1 to be mounted.
  • the mounting board side land 28 arranged around the semiconductor device 1 to be mounted is connected to the heat dissipation via 13 via the solder 30.
  • the heat generated by the semiconductor chip 3 is released to the outside of the semiconductor device 1 from the side of the insulating substrate 2a through the conductive pattern 12 and the heat dissipation via 13.
  • the solder 30 is connected to the heat radiating via 13 penetrating from one surface of the insulating substrate 2a to the other surface, and the air and the solder 30 connected to the heat radiating via 13 are in contact with each other. Since the surface area is large, a large amount of heat is easily released from the heat radiation via 13 via the solder 30. In addition, heat is easily transferred to the mounting substrate 29 through the heat dissipation via 13 and the solder 30.
  • the heat radiation vias 13 are disposed in the upper package 16 of the PoP type semiconductor device 1 formed by stacking the upper package 16 and the lower package 17 so as to be exposed to the side of the conductive pattern 12 and the insulating base 2a. Can be used effectively. Therefore, the heat of the semiconductor chip 3 of the upper package 16 is easily released to the outside of the semiconductor device 1 from the heat radiation via 13 exposed to the side of the insulating base 2a, and the reliability of the PoP type semiconductor device 1 is improved. Will improve.
  • connection pad 6 and the conductive pattern 12 are formed in the same layer sandwiched between the insulating base 2a and the insulating film 2b has been described.
  • the connection pad 6 and the conductive pattern 12 are different from each other. It may be formed in a layer.
  • the connection pad 6 and the conductive pattern 12 may be formed of different materials.
  • the case where the heat radiation via 13 is formed in the same size as the through via that connects the connection pad 6 and the land 7 has been described. 7 may be formed to be larger than the through via that connects 7.
  • FIG. 6 is a plan view showing a semiconductor device according to the second embodiment of the present invention.
  • the width of the connection wiring 14 that connects the conductive pattern 12 and the heat dissipation via 13 of the semiconductor device 1 of the present embodiment is formed wider than the width of the connection wiring of the first embodiment.
  • Other configurations and manufacturing processes of the semiconductor device 1 of the present embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.
  • the width of the connection wiring 14 is wide, the area connecting the conductive pattern 12 and the heat dissipation via 13 is increased, and heat transmitted from the conductive pattern 12 to the heat dissipation via 13 is increased. Increase.
  • the heat generated by the semiconductor chip 3 is transmitted from the heat radiation vias 13 arranged to be exposed to the side of the insulating base 2 a via the conductive pattern 12, the connection wiring 14, and the heat radiation via 13. Heat is easily released to the outside. As a result, the semiconductor chip 3 itself of the semiconductor device 1 is less likely to be heated, and the reliability of the semiconductor device 1 is improved. In addition, the same effect as the first embodiment can be obtained. In addition, a configuration may be adopted in which a plurality of connection wires 14 having a narrow width are provided so that the total surface area in plan view is equal to that of the connection wires 14 having a wide width.
  • FIG. 7 is a sectional view showing a semiconductor device according to the third embodiment of the present invention.
  • the semiconductor device 1 of the present embodiment has a configuration in which a heat radiating plate 26 is provided via an adhesive member 8 on the side surface of the semiconductor device 1 of the first embodiment where the heat radiating vias 13 are disposed.
  • the heat sink 26 is bonded onto the adhesive member 8 applied to the side surface of each semiconductor device 1 after the semiconductor devices 1 are cut and separated.
  • the heat dissipation plate 26 is formed of a material having excellent heat conductivity, and is configured to have a large surface area in contact with air.
  • FIG. 8 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention.
  • the semiconductor device 1 of this embodiment has a configuration in which a recess 27 is formed in the heat dissipation via 13 exposed on the side surface of the insulating base 2a of the semiconductor device of the first embodiment.
  • the recess 27 of the heat dissipation via 13 may be formed when the semiconductor device 1 is cut, or may be formed by additional machining after being separated into each semiconductor device 1.
  • the concave portion 27 of the heat radiating via 13 is configured to have a large surface area in contact with air in order to enhance the heat radiating effect.
  • FIG. 9 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention.
  • the conductive pattern 12 and the connection pads 6 connected to the power supply and GND are electrically connected via the wiring 21. It is a configuration.
  • Other configurations and manufacturing processes of the semiconductor device 1 of the present embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.
  • the conductive pattern 12 is electrically connected to the connection pads 6 connected to the power supply and GND via the wiring 21, so that the conductive pattern 12 is a part of the wiring pattern of the wiring board 2.
  • the manufacturing process is simplified. As a result, the manufacturing cost of the semiconductor device 1 can be suppressed.
  • the same effect as the first embodiment can be obtained.
  • FIG. 10 is a plan view showing a semiconductor device according to the sixth embodiment of the present invention.
  • the semiconductor device 1 of the present embodiment includes a wiring board 2, a semiconductor chip 3 mounted in a central region on one surface of the wiring board 2, and a sealing body 4 formed on one surface of the wiring board 2. Have. In FIG. 10, the sealing body 4 is partially removed to show the internal structure. Both surfaces of the wiring board 2 are covered with an insulating film 2 b having an opening 11, and the opening 11 of the insulating film 2 b on one surface of the wiring board 2 is attached to each side of the mounted semiconductor chip 3. A plurality of connection pads 6 are exposed along the line.
  • the semiconductor chip 3 is formed in a rectangular plate shape, and a plurality of electrode pads 9 are provided along one side of the semiconductor chip 3 on one surface of the semiconductor chip 3.
  • the connection pads 6 of the wiring board 2 and the electrode pads 9 of the semiconductor chip 3 are electrically connected by conductive wires 10.
  • a conductive pattern 12 is formed between one surface of the insulating base 2a of the wiring board 2 and the insulating film 2b.
  • a semiconductor chip 3 is formed immediately above the conductive pattern 12.
  • heat radiation vias 13 are formed on the sides of the insulating base material 2 a so as to sandwich the four corners of the wiring board 2.
  • the heat radiating via 13 is exposed from the opening 11 of the insulating film 2 b, and a plating layer 15 is formed on the surface of the heat radiating via 13.
  • connection wirings 14 Since the manufacturing process of the semiconductor device 1 of this embodiment is the same as that of the first embodiment, the description thereof is omitted. As described above, since the heat radiation vias 13 are formed so as to sandwich the four corners of the wiring board 2, the wiring on the wiring board 2 can be made efficient. Therefore, the connection pads 6 and the electrode pads 9 can be formed along each side of the semiconductor chip 3, and many electrode pads 9 are provided on the semiconductor chip 3. In addition, the same effect as the first embodiment can be obtained.
  • FC-BGA Flip Chip Ball Grid Array
  • the present invention is applied to a CoC (Chip on Chip) type semiconductor device in which a through-electrode is provided in a semiconductor chip and a semiconductor chip is mounted by stacking the semiconductor chips electrically connected to each other. May be.

Abstract

　本発明の半導体装置１は、配線基板２と、半導体チップ３と、封止体４とを有する。配線基板２は、絶縁基材２ａと、絶縁基材２ａの一方の面に形成された導通パターン１２と、導通パターン１２と接続されている放熱用ビア１３とを有する。放熱用ビア１３は、絶縁基材２ａの側方に露出するとともに、絶縁基材２ａの一方の面から他方の面まで貫通するように設けられている。半導体チップ３は、導通パターン１２に重なるように配線基板２上に搭載されている。封止体４は、半導体チップ３を覆うように配線基板２に形成されている。

Description

半導体装置
　本発明は、半導体チップを有する半導体装置に関する。
　近年、メモリチップやロジックチップ等の半導体チップを有する半導体装置の高速化が進み、そのため半導体チップの稼働率等が増加し、半導体チップが発熱しやすくなっている。よって、半導体チップの熱を半導体装置の外部に放出する構成が求められている。特に、ＢＧＡ（Ball　Grid　Array）タイプの半導体装置では、伝熱性の乏しい有機部材が多く使用されているため、半導体装置の半導体チップから空気中へ熱が放出されにくい。
　特許文献１に記載の半導体装置では、配線基板と封止体とからなり、配線基板が半導体チップ（半導体素子）を保持した構成を有するパッケージが、実装基板に実装されている。半導体装置には、パッケージの配線基板の、実装基板との接続面（基板接続面）の中央領域に、複数の放熱用半田ボール（半田バンプ）が設けられている。特許文献１に開示された半導体装置は、半導体チップから複数の放熱用半田ボールに熱が伝わる構成を有しているため、半導体チップから発生した熱が、放熱用半田ボールを介して半導体チップに接続されている実装基板に伝わり、実装基板から半導体装置の外部に放出される。
特開２０００－６８４０３号公報
　しかしながら、特許文献１に開示された発明では、半導体装置に放熱用半田ボールを別途設ける必要があり、そのため、半導体装置全体の製造コストが増加する。
　特許文献１に開示されたパッケージを用いて、異なる種類の半導体チップを有する複数のパッケージを重ねるＰｏＰ（Package　on　Package）を構成する場合について説明する。ＰｏＰ型半導体装置では、上方に積層されるパッケージの中央領域の直下に、下方に位置するパッケージの半導体チップが位置するため、上方に積層されるパッケージの接続面の中央領域に複数の放熱用半田ボールを配置するスペースが存在しない。仮に、上方のパッケージと下方のパッケージとの間に隙間を設けて放熱用半田ボールを配置した場合には、下方のパッケージの半導体チップと放熱用半田ボールとが接触し、放熱用半田ボールと実装基板が接触しなくなる。その結果として、半導体チップから発生した熱を放熱用半田ボールを介して実装基板に伝えて放出することができず、半導体装置が熱を帯びるという課題がある。
　前記した目的を達成するために、本発明の半導体装置は、配線基板と、半導体チップと、封止体とを有する。配線基板は、絶縁基材と、絶縁基材の一方の面に形成された導通パターンと、導通パターンと接続されている放熱用ビアとを有する。放熱用ビアは、絶縁基材の側方に露出するとともに、絶縁基材の一方の面から他方の面まで貫通するように設けられている。半導体チップは、導通パターンに重なるように配線基板上に搭載されている。封止体は、半導体チップを覆うように配線基板に形成されている。
　本発明によれば、絶縁基材の一方の面に導通パターンが形成されているため、導通パターンに重なるように搭載された半導体チップから発生した熱が導通パターンに伝わる。導通パターンに伝わった熱は、導通パターンに接続され、絶縁基材の側方に露出し、絶縁基材の一方の面から他方の面まで貫通している放熱用ビアに伝わり、放熱用ビアから半導体装置の外部に放出される。そのため、半導体チップの配線基板の中央領域に複数の放熱用半田ボールを形成する必要がなく、半導体装置全体の製造コストが抑えられる。また、放熱用半田ボールを形成しなくてもよいため、ＰｏＰ型半導体装置にも、本発明の半導体装置からなるパッケージが適用できる。
　また、半導体チップから発生した熱が、導通パターンを介して、絶縁基材の側方に露出している放熱用ビアから外部へ放出されることで、半導体チップが発する熱によって半導体装置が熱を帯びるおそれが小さくなり、半導体装置の信頼性が向上する。
本発明の第１の実施形態の半導体装置を示す平面図である。 図１におけるＡ－Ａ’線断面図である。 図１におけるＢ－Ｂ’線断面図である。 第１の実施形態の半導体装置の組立工程を示す断面図である。 第１の実施形態の半導体装置の組立工程を示す断面図である。 第１の実施形態の半導体装置の組立工程を示す断面図である。 第１の実施形態の半導体装置の組立工程を示す断面図である。 第１の実施形態の半導体装置の組立工程を示す断面図である。 第１の実施形態のＰｏＰ型の半導体装置を示す断面図である。 第１の実施形態の半導体装置を電子機器内部の実装基板に実装した状態を示す断面図である。 本発明の第２の実施形態の半導体装置を示す平面図である。 本発明の第３の実施形態の半導体装置を示す断面図である。 本発明の第４の実施形態の半導体装置を示す平面図である。 本発明の第５の実施形態の半導体装置を示す平面図である。 本発明の第６の実施形態の半導体装置を示す平面図である。
　以下、本発明の実施の形態について図面を参照して説明する。
　（第１の実施形態）
　図１は、本発明の第１の実施形態の半導体装置を示す平面図である。
　図１に示すように、半導体装置１は、導通パターン１２と、一方の面から他方の面まで貫通するとともに側方に露出する放熱用ビア１３とが形成された絶縁基材２ａからなる配線基板２と、配線基板２の一方の面の中央領域に搭載された半導体チップ３と、を有する。さらに、この半導体装置１は、半導体チップ３を覆うように、配線基板２の一方の面に形成された封止体４を有している。図１では封止体４を部分的に取り去って、内部構造が示されている。
　配線基板２はガラスエポキシ基板等の絶縁基材２ａからなり、絶縁基材２ａの一方の面と他方の面とに所定の配線パターン（不図示）がそれぞれ形成されており、これらの配線パターンは、ソルダーレジスト膜等の絶縁膜２ｂに覆われている。一方の面の配線パターンは、導通パターン１２と平面的に重なり合わない位置に形成されており、導通パターン１２と接続されていない。図１と図２ａに示すように、絶縁膜２ｂは、後述する接続パッド６及び放熱用ビア１３と対向する位置に開口部１１を有している。搭載されている半導体チップ３の対向する一対の辺に沿って、配線基板２の一方の面に形成されている配線パターンに接続されている複数の接続パッド６が、絶縁膜２ｂの開口部１１から露出している。また、図２ａ、２ｂに示すように、配線基板２の他方の面に形成されている絶縁膜２ｂの開口部１１から、複数のランド７が露出している。この接続パッド６とランド７はＣｕ等で形成されており、配線基板２の内部に形成されている貫通ビアを介して電気的に接続されている。配線基板２の他方の面には、ランド７とそれぞれ接続されている複数の半田ボール５（金属ボール）が、配線基板２の他方の面の中央領域を除いた領域に、配線基板２の各辺に沿って二列に設けられている。
　半導体チップ３は、例えばＤＲＡＭ（Dynamic　Random　Access　Memory）のメモリチップであり、図１に示すように、長方形の板状に形成されている。半導体チップ３の一方の面には、対向する一対の辺に沿って複数の電極パッド９が設けられており、半導体チップ３の他方の面（接続面）が、図２ａ、２ｂに示すように、配線基板２の中央領域に接着部材８を介して接続されている。接着部材８としては、例えば絶縁ペースト或いはＤＡＦ（Die　Attached　Film）等が用いられる。図１と図２ａに示すように、接続パッド６と電極パッド９とは隣接しており、導電性のワイヤ１０によって電気的に接続されている。
　また、図１と図２ａ、２ｂに示すように、平面的にみて、半導体チップ３よりサイズの大きい形状を有する導通パターン１２が、配線基板２の絶縁基材２ａの一方の面に形成されている。導通パターン１２の直上には、半導体チップ３が搭載されている。さらに、放熱用ビア１３が、半導体チップ３の電極パッド９が形成されていない一対の辺に平行な配線基板２の対向する一対の辺に沿って配置され、絶縁基材２ａの側方に露出している。この放熱用ビア１３は、絶縁基材２ａの一方の面から他方の面まで貫通している。そして、放熱用ビア１３は絶縁膜２ｂの開口部１１から露出しており、放熱用ビア１３の表面上にはめっき層１５が形成されている。ただし、放熱用ビア１３は、絶縁基材２ａの側方に露出されていれば、絶縁膜２ｂの開口部１１から露出していなくともよい。導通パターン１２と放熱用ビア１３とは、接続用配線１４によって接続されている。導通パターン１２と放熱用ビア１３と接続用配線１４とは、熱伝導率の高いＣｕ等で形成されている。放熱用ビア１３と貫通ビア３０とは、同じ大きさに形成されている。
　このように、半導体チップ３の直下に設けられた導通パターン１２と放熱用ビア１３とが接続されていることによって、半導体チップ３が発する熱が導通パターン１２を介して放熱用ビア１３へ伝わりやすくなる。そして、放熱用ビア１３が絶縁基材２ａの側方に露出していることで、露出している放熱用ビア１３から半導体装置１の外部に熱が放出されやすくなる。本実施形態においては、放熱用ビア１３が絶縁基材２ａを貫通して配置されていることで、絶縁基材２ａの側方にて空気と放熱用ビア１３とが接触する表面積が広くなるため、放熱効果が高い。そのため、半導体チップ３自体が熱を帯びにくくなり、半導体装置１の信頼性が向上する。さらに、半導体装置１において、放熱用ビア１３の表面上にめっき層１５が形成されていることで、絶縁基材２ａの側方に露出するメタルパターンの表面積を、めっき層１５の分だけ大きくすることができる。
　加えて、放熱用半田ボール等を追加で形成する必要がないため、半導体装置１の製造コストを抑えることができる。
　以下に、図３ａ～３ｅを用いて、本発明の第１の実施形態の半導体装置１の製造工程を説明する。
　初めに、図３ａに示すように、ダイシングライン２５によってマトリックス状に区画された複数の製品形成部２４（切断後に配線基板２となる部分）を有する母基板２３が準備される。母基板２３の製品形成部２４の一方の面には、複数の接続パッド６（図１参照）と導通パターン１２とが形成されており、製品形成部２４の他方の面には、複数のランド７が形成されている。また、母基板２３の一方の面から他方の面に貫通するように、ダイシングライン２５を含む部分に放熱用ビア１３が形成されている。さらに、母基板２３の両面には絶縁膜２ｂが設けられており、絶縁膜２ｂの開口部１１から、接続パッド６（図１参照）と導通パターン１２と放熱用ビア１３とランド７とが露出している。
　次に、図３ｂに示すように、製品形成部２４の一方の面の中央領域の絶縁膜２ｂの上に、絶縁ペースト或いはＤＡＦ等の接着部材８が塗布され、接着部材８の上に、半導体チップ３の接続面と配線基板２の一方の面とが対向するように、半導体チップ３が搭載される。この半導体チップ３は、一方の面にＤＲＡＭのメモリ回路等が形成されたＳｉ基板を有しており、このＳｉ基板には複数の電極パッド９（図１参照）が設けられている。また、半導体チップ３の一方の面には、回路を保護するためのパッシベーション膜（不図示）が、電極パッド９の表面は被覆しないように形成されている。
　各製品形成部２４に半導体チップ３がそれぞれ搭載された後に、搭載された半導体チップ３の電極パッド９と母基板２３の接続パッド６とが、導電性のワイヤ１０（図１参照）によって接続される。このワイヤ１０は、例えばＡｕやＣｕ等からなる。電極パッド９と接続パッド６とをワイヤ１０で接続するワイヤボンディングには、不図示のワイヤボンディング装置が用いられる。具体的には、溶融されてボール状に形成されたワイヤ１０の一端が、半導体チップ３の電極パッド９に超音波熱圧着された後に、ワイヤ１０の他端が、母基板２３の接続パッド６に超音波熱圧着される。ワイヤ１０は、半導体チップ３の端部のエッジとの接触を避けるために所定のループ形状を描くように配置される。
　続けて、図３ｃに示すように、複数の製品形成部２４を一括的に覆うように、母基板２３の一方の面に封止体４が形成される。具体的には、上型と下型からなる成形金型（不図示）を有するトランスファモールド装置等の成形装置を用いて封止体４が形成される。上型には複数の製品形成部２４を一括して覆う大きさのキャビティが形成されており、下型には母基板２３を配置するための凹部が形成されている。ワイヤ１０が配置された母基板２３が下型の凹部にセットされ、上型と下型とで母基板２３の周縁部をクランプして、母基板２３がキャビティ内に配置される。その後、エポキシ樹脂等の熱硬化性の封止樹脂をキャビティ内へ充填させて、所定の温度（例えば１８０℃）で熱硬化させることで、封止樹脂が硬化して封止体４が母基板２３の一方の面に形成される。
　母基板２３の一方の面に封止体４が形成された後に、母基板２３の他方の面に半田ボール５を形成するボールマウント工程に移行する。具体的には、図３ｄに示すように、母基板２３の他方の面の製品形成部２４毎に配置された複数のランド７の上に、導電性の半田ボール５が接合される。半田ボール５は、ランド７の配置にあわせて複数の吸着孔が形成された不図示のボールマウンターによって吸着保持され、フラックスを介してランド７に一括的に接合される。
　最後に、不図示のダイシング装置によって、製品形成部２４同士の間をダイシングライン２５に沿って切断して分離することで、図５ｅに示すように、半導体装置１が形成される。このとき、ダイシングライン２５は放熱用ビア１３の中心を通るように設けられているため、ダイシングライン２５に沿って切断されて分離されることで、半導体装置１の側方に放熱用ビア１３が露出する。
　図４は、上記に説明した構成の半導体装置を上段パッケージ１６として、上段パッケージ１６が、半導体チップ３を有する下段パッケージ１７に積層された構成を有するＰｏＰ型の半導体装置を示す断面図である。
　下段パッケージ１７は、一方の面に所定の配線パターン（不図示）が形成された配線基板２と、配線基板２の一方の面の中央領域にアンダーフィル材２０を介して搭載された半導体チップ３と、を有している。配線基板２の両面には、絶縁膜２ｂが被覆され、絶縁膜２ｂには開口部（不図示）が設けられている。配線基板２の一方の面には、上段パッケージ１６の半田ボール５と接続される接続用ランド１９と、下段パッケージ１７の半導体チップ３と接続されている接続パッド６とが、開口部から露出している。配線基板２の他方の面では、複数のランド７が開口部から露出しており、これらのランド７にそれぞれ半田ボール５が接続されている。
　上段パッケージ１６の配線基板２の他方の面の半田ボール５と、下段パッケージ１７の配線基板２の一方の面の接続用ランド１９とが接続されて、異なる二つの半導体チップ３を有するＰｏＰ型の半導体装置１が形成されている。このとき、上段パッケージ１６の配線基板２の他方の面の中央領域に半田ボール５が設けられていないため、下段パッケージ１７に搭載されている半導体チップ３と、上段パッケージ１６の配線基板２の他方の面の半田ボール５とが接触しない。即ち、上段パッケージ１６の配線基板２の他方の面の半田ボール５は、下段パッケージ１７の半導体チップ３に接触せずに、下段パッケージ１７の配線基板２と接触している。
　図５は、上記に説明した構成の半導体装置が電子機器の実装基板に実装されている状態を示す断面図である。
　電子機器の内部に備えられたマザーボード等の実装基板２９は、絶縁基材２ａからなり、絶縁基材２ａの一方の面と他方の面とに所定の配線パターン（不図示）が形成されている。これらの配線パターンは、ソルダーレジスト膜等の絶縁膜２ｂに覆われている。一方の面の絶縁膜２ｂは開口部（不図示）を有しており、配線基板２の一方の面に形成されている配線パターンに接続されている複数の実装基板側ランド２８が、絶縁膜２ｂの開口部から露出している。実装される半導体装置１の直下に配置された実装基板側ランド２８は、実装される半導体装置１のランドと接続される。平面的にみて、実装される半導体装置１の周囲に配置された実装基板側ランド２８は、半田３０を介して放熱用ビア１３と接続されている。このように、実装基板側ランド２８と放熱用ビア１３とが半田３０を介して接続されることによって、放熱用ビア１３に伝わった熱が、放熱用ビア１３から空気中へ放出されると共に、実装基板２９に伝わりやすくなる。さらには、実装基板側ランド２８と放熱用ビア１３とが半田３０にて固定されることによって、半導体装置１と実装基板２９との接続強度が高められ、それぞれの半田ボール５にかかる応力を低減できるため、二次実装の信頼性が向上する。
　以上のように、半導体チップ３が発した熱が、導通パターン１２及び放熱用ビア１３を介して絶縁基材２ａの側方から半導体装置１の外部に放出される。特に、絶縁基材２ａの一方の面から他方の面まで貫通している放熱用ビア１３に半田３０が接続されており、空気と、放熱用ビア１３に接続している半田３０とが接触する表面積が大きいため、放熱用ビア１３から半田３０を介して多くの熱が放出されやすい。加えて、放熱用ビア１３と半田３０を介して、熱が実装基板２９に伝達されやすくなる。そのため、配線基板２の他方の面の中央領域に放熱用の半田ボールを設けて実装基板に熱を放出する必要がなくなる。よって、上段パッケージ１６と下段パッケージ１７とを積層して形成するＰｏＰ型の半導体装置１の上段パッケージ１６に、導通パターン１２と絶縁基材２ａの側方に露出して配置された放熱用ビア１３とを有する構成を有効に用いることができる。従って、上段パッケージ１６の半導体チップ３の熱が、絶縁基材２ａの側方に露出している放熱用ビア１３から半導体装置１の外部に放出されやすくなり、ＰｏＰ型の半導体装置１の信頼性が向上する。
　本実施形態では、接続パッド６と導通パターン１２とが、絶縁基材２ａと絶縁膜２ｂに挟まれた同じ層に形成された場合について説明したが、接続パッド６と導通パターン１２とが別の層に形成されてもよい。また、接続パッド６と導通パターン１２とが異なる材料から形成されていてもよい。
　さらには、本実施形態では、放熱用ビア１３を、接続パッド６とランド７とを接続する貫通ビアと同じ大きさに形成する場合について説明したが、放熱用ビア１３は、接続パッド６とランド７とを接続する貫通ビアより大きく形成されていてもよい。
　（第２の実施形態）
　図６は、本発明の第２の実施形態の半導体装置を示す平面図である。
　本実施形態の半導体装置１の導通パターン１２と放熱用ビア１３とを繋ぐ接続用配線１４の幅は、第１の実施形態の接続用配線の幅より広く形成されている。本実施形態の半導体装置１のその他の構成や製造工程は、第１の実施形態と同様のため説明を省略する。
　このように、接続用配線１４の幅が広く形成されていることによって、導通パターン１２と放熱用ビア１３との間を繋いでいる領域が増え、導通パターン１２から放熱用ビア１３に伝わる熱が増える。そのため、半導体チップ３が発する熱が、導通パターン１２と接続用配線１４と放熱用ビア１３とを介して、絶縁基材２ａの側方に露出して配置された放熱用ビア１３から半導体装置１の外部に熱が放出されやすくなる。この結果として、半導体装置１の半導体チップ３自体が熱を帯びにくくなり、半導体装置１の信頼性が向上する。加えて、第１の実施形態と同様の効果が得られる。
　なお、幅の狭い接続用配線１４を複数設けることによって、平面的にみた表面積の合計が、前記した幅の広い接続用配線１４と等しくなるようにした構成にしてもよい。
　（第３の実施形態）
　図７は、本発明の第３の実施形態の半導体装置を示す断面図である。
　本実施形態の半導体装置１は、第１の実施形態の半導体装置１の放熱用ビア１３が配置されている側面に、接着部材８を介して放熱板２６を備えた構成を有している。放熱板２６は、半導体装置１がそれぞれ切断され分離された後に、各半導体装置１の側面に塗布された接着部材８の上に接着される。この放熱板２６は、放熱効果を高めるために、伝熱性に優れた材料で形成され、空気と接触する表面積が広くなるように構成されている。本実施形態の半導体装置１のその他の構成や製造工程は、第１の実施形態と同様のため説明を省略する。
　このように、放熱用ビア１３に放熱板２６が接続されていることによって、空気と接触する半導体装置１の側面の表面積が増える。そのため、半導体チップ３が発して導通パターン１２に伝わった熱が、接続用配線１４と放熱用ビア１３と放熱板２６とを介して、半導体装置１の側方に配置された放熱板２６から半導体装置１の外部に放出されやすくなる。この結果として、半導体装置１の半導体チップ３自体が熱を帯びにくくなり、半導体装置１の信頼性が向上する。加えて、第１の実施形態と同様の効果が得られる。
　（第４の実施形態）
　図８は、本発明の第４の実施形態の半導体装置を示す断面図である。
　本実施形態の半導体装置１は、第１の実施形態の半導体装置の絶縁基材２ａの側面に露出する放熱用ビア１３に凹部２７が形成された構成を有している。放熱用ビア１３の凹部２７は、半導体装置１がそれぞれ切断される際に形成されてもよく、各半導体装置１に分離された後に追加工で形成されてもよい。この放熱用ビア１３の凹部２７は、放熱効果を高めるために空気と接触する表面積が広くなるように構成されている。本実施形態の半導体装置１のその他の構成や製造工程は、第１の実施形態と同様のため説明を省略する。
　このように、放熱用ビア１３に凹部２７が形成されていることによって、空気と接触する放熱用ビア１３の表面積が増える。そのため、半導体チップ３が発して導通パターン１２に伝わった熱が、接続用配線１４と放熱用ビア１３と介して、絶縁基材２ａの側方に露出して配置された凹部２７を有する放熱用ビア１３から半導体装置１の外部に放出されやすくなる。この結果として、半導体装置１の半導体チップ３自体が熱を帯びにくくなり、半導体装置１の信頼性が向上する。加えて、第１の実施形態と同様の効果が得られる。
　（第５の実施形態）
　図９は、本発明の第５の実施形態の半導体装置を示す平面図である。
　本実施形態の半導体装置１は、第１の実施形態の構成に加えて、導通パターン１２と、電源やＧＮＤと接続されている接続パッド６とが、配線２１を介して電気的に接続された構成である。本実施形態の半導体装置１のその他の構成や製造工程は、第１の実施形態と同様のため説明を省略する。
　このように、導通パターン１２が、電源やＧＮＤと接続されている接続パッド６と、配線２１を介して電気的に接続されていることによって、導通パターン１２が配線基板２の配線パターンの一部として利用できる。そして、配線基板２の配線パターンと共に導通パターン１２を形成することで、製造工程が簡略化される。この結果として、半導体装置１の製造コストが抑えられる。加えて、第１の実施形態と同様の効果が得られる。
　（第６の実施形態）
　図１０は、本発明の第６の実施形態の半導体装置を示す平面図である。
　本実施形態の半導体装置１は、配線基板２と、配線基板２の一方の面の中央領域に搭載された半導体チップ３と、配線基板２の一方の面に形成された封止体４とを有する。図１０では封止体４を部分的に取り去って、内部構造が示されている。配線基板２の両面は、開口部１１を有する絶縁膜２ｂに覆われており、配線基板２の一方の面の絶縁膜２ｂの開口部１１には、搭載されている半導体チップ３の各辺に沿って、複数の接続パッド６が露出している。半導体チップ３は四角形の板状に形成されており、半導体チップ３の一方の面には、半導体チップ３の各辺に沿って複数の電極パッド９が設けられている。配線基板２の接続パッド６と半導体チップ３の電極パッド９とは、導電性のワイヤ１０によって電気的に接続されている。また、導通パターン１２が、配線基板２の絶縁基材２ａの一方の面と絶縁膜２ｂとの間に形成されている。導通パターン１２の直上には、半導体チップ３が形成されている。さらに、放熱用ビア１３が、配線基板２の四つのそれぞれの角部を挟み込むように、絶縁基材２ａの側方に形成されている。放熱用ビア１３は絶縁膜２ｂの開口部１１から露出しており、放熱用ビア１３の表面上にはめっき層１５が形成されている。導通パターン１２と放熱用ビア１３とは、複数の接続用配線１４によって接続されている。
　本実施形態の半導体装置１の製造工程は、第１の実施形態と同様であるため説明を省略する。
　このように、放熱用ビア１３が、配線基板２の四つのそれぞれの角部を挟み込むように形成されていることによって、配線基板２上の配線を効率化することができる。そのため、半導体チップ３の各辺に沿って接続パッド６と電極パッド９とを形成することができ、半導体チップ３に電極パッド９が数多く設けられる。加えて、第１の実施形態と同様の効果が得られる。
　以上、本発明の半導体装置の具体的な構成について各実施形態に基づき説明したが、本発明は、前述した実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲で、前述の実施形態に対する種々の変更が可能であることは言うまでもない。例えば、前記した各実施形態では、一つの配線基板上に一つの半導体チップを搭載した半導体装置について説明したが、一つの配線基板上に複数の半導体チップを並置或いは積層したＭＣＰ（Multi　Chip　Package）型の半導体装置に適用してもよい。
　また、本実施形態では、電極パッドと接続パッドとをワイヤで接続した半導体装置を説明したが、電極パッドと接続パッドとを直接接続して半導体チップを搭載したＦＣ－ＢＧＡ（Flip　Chip　Ball　Grid　Array）型の半導体装置に適用してもよい。
　さらには、半導体チップに貫通電極が設けられ、半導体チップ同士が、互いの電極パッド同士と電気的に接続されて積層されたチップ積層体を搭載したＣｏＣ（Chip　on　Chip）型の半導体装置に適用してもよい。

Claims (10)

  1. 　絶縁基材と、前記絶縁基材の一方の面に形成された導通パターンと、前記導通パターンと接続されており、前記絶縁基材の側方に露出するとともに、前記絶縁基材の前記一方の面から他方の面まで貫通するように設けられた放熱用ビアと、からなる配線基板と、
    　前記導通パターンに重なるように前記配線基板上に搭載された半導体チップと、
    　前記半導体チップを覆うように前記配線基板に形成された封止体と、を有することを特徴とする半導体装置。
  2. 　前記配線基板は、前記導通パターンを覆い、かつ前記放熱用ビアを露出するように、前記絶縁基材の前記一方の面に形成された絶縁膜を有していることを特徴とする請求項１に記載の半導体装置。
  3. 　前記配線基板は接続パッドを有しており、前記絶縁膜は前記接続パッドと対向する位置に開口部を有しており、
    　前記導通パターンは前記接続パッドと接続されていることを特徴とする請求項２に記載の半導体装置。
  4. 　前記絶縁基材の前記一方の面に露出している前記放熱用ビアの表面には、めっき層が設けられていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置。
  5. 　前記導通パターンと前記放熱用ビアとが、接続用配線によって接続されていることを特徴とする請求項１から４のいずれか１項に記載の半導体装置。
  6. 　前記放熱用ビアに接続する放熱板を有する請求項１から５のいずれか１項に記載の半導体装置。
  7. 　前記放熱用ビアに、空気と接触する表面積を広くするための凹部が設けられていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。
  8. 　請求項１から７のいずれか１項に記載の半導体装置と、一方の面に複数のランドが形成された実装基板と、を含み、
    　前記半導体装置の前記放熱用ビアと前記実装基板の前記ランドとが、電気的に接続されつつ固定されていることを特徴とする電子機器。
  9. 　絶縁基材と、前記絶縁基材の一方の面に形成された導通パターンと、前記導通パターンと接続されており、前記絶縁基材の側方に露出するとともに、前記絶縁基材の前記一方の面から他方の面まで貫通するように設けられた放熱用ビアとからなる配線基板と、前記導通パターンに重なるように前記配線基板上に搭載された半導体チップと、前記半導体チップを覆うように前記配線基板に形成された封止体と、前記配線基板の他方の面に、前記配線基板の中央領域を除くようにして前記配線基板の各辺に沿って設けられた金属ボールと、を有する上段パッケージと、
    　絶縁基材を含む配線基板と、前記配線基板の一方の面に搭載された半導体チップと、前記配線基板の他方の面に搭載された金属ボールとを有する下段パッケージと、を有し、
    　前記上段パッケージの前記金属ボールが、前記下段パッケージの前記半導体チップと接触せず、前記下段パッケージの前記配線基板と接触するように、前記上段パッケージと前記下段パッケージとが積層されていることを特徴とする半導体装置。
  10. 　前記下段パッケージの前記配線基板の前記一方の面には接続用ランドが設けられており、前記上段パッケージの前記金属ボールと前記下段パッケージの前記接続用ランドとが接続されていることを特徴とする請求項９に記載の半導体装置。
PCT/JP2014/060466 2013-04-17 2014-04-11 半導体装置 WO2014171403A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/784,632 US20160064301A1 (en) 2013-04-17 2014-04-11 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-086447 2013-04-17
JP2013086447 2013-04-17

Publications (1)

Publication Number Publication Date
WO2014171403A1 true WO2014171403A1 (ja) 2014-10-23

Family

ID=51731345

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/060466 WO2014171403A1 (ja) 2013-04-17 2014-04-11 半導体装置

Country Status (3)

Country Link
US (1) US20160064301A1 (ja)
TW (1) TW201511191A (ja)
WO (1) WO2014171403A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170372989A1 (en) * 2016-06-22 2017-12-28 Qualcomm Incorporated Exposed side-wall and lga assembly

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031331A (ja) * 1998-07-14 2000-01-28 Hitachi Ltd 電力増幅器
JP2004221248A (ja) * 2003-01-14 2004-08-05 Citizen Electronics Co Ltd 半導体装置
JP2007027684A (ja) * 2005-06-15 2007-02-01 Kyocera Corp 電子部品モジュール
JP2007134427A (ja) * 2005-11-09 2007-05-31 Matsushita Electric Ind Co Ltd モジュールパッケージ及びモジュールパッケージの製造方法
JP2008211254A (ja) * 2008-05-23 2008-09-11 Shinko Electric Ind Co Ltd 部品内蔵多層回路基板
WO2008111408A1 (ja) * 2007-03-09 2008-09-18 Murata Manufacturing Co., Ltd. 多層配線基板及びその製造方法
JP2009117489A (ja) * 2007-11-02 2009-05-28 Sharp Corp 半導体素子パッケージ及び実装基板
JP2010073851A (ja) * 2008-09-18 2010-04-02 Denso Corp 半導体装置
WO2013015327A1 (ja) * 2011-07-25 2013-01-31 京セラ株式会社 配線基板、電子装置および電子モジュール

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447908B2 (ja) * 1997-02-13 2003-09-16 富士通株式会社 ボールグリッドアレイパッケージ
US6092281A (en) * 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6331451B1 (en) * 1999-11-05 2001-12-18 Amkor Technology, Inc. Methods of making thin integrated circuit device packages with improved thermal performance and substrates for making the packages
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6664864B2 (en) * 2001-10-31 2003-12-16 Cts Corporation Cavity design printed circuit board for a temperature compensated crystal oscillator and a temperature compensated crystal oscillator employing the same
JP2003318361A (ja) * 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
TWI269414B (en) * 2005-06-20 2006-12-21 Via Tech Inc Package substrate with improved structure for thermal dissipation and electronic device using the same
JP5135828B2 (ja) * 2007-02-28 2013-02-06 ソニー株式会社 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法
US8188379B2 (en) * 2008-07-04 2012-05-29 Unimicron Technology Corp. Package substrate structure
US8592973B2 (en) * 2009-10-16 2013-11-26 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031331A (ja) * 1998-07-14 2000-01-28 Hitachi Ltd 電力増幅器
JP2004221248A (ja) * 2003-01-14 2004-08-05 Citizen Electronics Co Ltd 半導体装置
JP2007027684A (ja) * 2005-06-15 2007-02-01 Kyocera Corp 電子部品モジュール
JP2007134427A (ja) * 2005-11-09 2007-05-31 Matsushita Electric Ind Co Ltd モジュールパッケージ及びモジュールパッケージの製造方法
WO2008111408A1 (ja) * 2007-03-09 2008-09-18 Murata Manufacturing Co., Ltd. 多層配線基板及びその製造方法
JP2009117489A (ja) * 2007-11-02 2009-05-28 Sharp Corp 半導体素子パッケージ及び実装基板
JP2008211254A (ja) * 2008-05-23 2008-09-11 Shinko Electric Ind Co Ltd 部品内蔵多層回路基板
JP2010073851A (ja) * 2008-09-18 2010-04-02 Denso Corp 半導体装置
WO2013015327A1 (ja) * 2011-07-25 2013-01-31 京セラ株式会社 配線基板、電子装置および電子モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170372989A1 (en) * 2016-06-22 2017-12-28 Qualcomm Incorporated Exposed side-wall and lga assembly

Also Published As

Publication number Publication date
TW201511191A (zh) 2015-03-16
US20160064301A1 (en) 2016-03-03

Similar Documents

Publication Publication Date Title
TWI587759B (zh) 三維空間封裝結構及其製造方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
JP5215605B2 (ja) 半導体装置の製造方法
US7928590B2 (en) Integrated circuit package with a heat dissipation device
TWI506743B (zh) 半導體裝置的熱能管理結構及其製造方法
US9496210B1 (en) Stackable package and method
US20150221625A1 (en) Semiconductor package having a dissipating plate
US20070069371A1 (en) Cavity chip package
TWI811383B (zh) 半導體封裝
KR20120010616A (ko) 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
US9666506B2 (en) Heat spreader with wiring substrate for reduced thickness
JP2012094592A (ja) 半導体装置及びその製造方法
JP2019071412A (ja) チップパッケージ
TW201533882A (zh) 覆晶堆疊封裝
TWI531283B (zh) 連接基板及層疊封裝結構
US10517176B2 (en) Semiconductor device
KR20180002913A (ko) 반도체 패키지 및 그 제조방법
TWI416700B (zh) 晶片堆疊封裝結構及其製造方法
JP5767695B2 (ja) 半導体装置
TW201929163A (zh) 電子封裝件及其製法
TWI495078B (zh) 連接基板及層疊封裝結構
WO2014171403A1 (ja) 半導体装置
KR101459566B1 (ko) 히트슬러그, 그 히트슬러그를 포함한 반도체 패키지 및 그 제조방법
US11417581B2 (en) Package structure
TWI423405B (zh) 具載板之封裝結構

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14785407

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14784632

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14785407

Country of ref document: EP

Kind code of ref document: A1