WO2008111408A1 - 多層配線基板及びその製造方法 - Google Patents

多層配線基板及びその製造方法 Download PDF

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Publication number
WO2008111408A1
WO2008111408A1 PCT/JP2008/053609 JP2008053609W WO2008111408A1 WO 2008111408 A1 WO2008111408 A1 WO 2008111408A1 JP 2008053609 W JP2008053609 W JP 2008053609W WO 2008111408 A1 WO2008111408 A1 WO 2008111408A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
laminated body
multilayer wiring
via hole
hole conductor
Prior art date
Application number
PCT/JP2008/053609
Other languages
English (en)
French (fr)
Inventor
Yoshikazu Oikawa
Hideyuki Morimoto
Original Assignee
Murata Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Priority to JP2009503965A priority Critical patent/JP5212359B2/ja
Publication of WO2008111408A1 publication Critical patent/WO2008111408A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

　電子部品の集積度が高くなっても、実装面積を犠牲にすることなく、放熱特性を格段に高めることができ、もって信頼性を向上させることができる多層配線基板及びその製造方法を提供する。 　本発明の多層配線基板１０は、複数のセラミック層１１Ａを積層してなる積層体１１と、この積層体１１の側面に形成された端子電極１３と、を備え、更に、積層体１１に搭載される第１、第２、第３の電子部品５１、５２、５３に接続するために積層体１１の上面からその内部の複数のセラミック層１１Ａを貫通する放熱用ビアホール導体１７と、この放熱用ビアホール導体１７に接続され且つ積層体１１内で放熱用ビアホール導体１７と端子電極１３とを接続するように一つのセラミック層１１Ａ内で面方向にビア導体が連設されてなる連続ビアホール導体１８と、を備えている。
PCT/JP2008/053609 2007-03-09 2008-02-29 多層配線基板及びその製造方法 WO2008111408A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009503965A JP5212359B2 (ja) 2007-03-09 2008-02-29 多層配線基板及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007060765 2007-03-09
JP2007-060765 2007-03-09

Publications (1)

Publication Number Publication Date
WO2008111408A1 true WO2008111408A1 (ja) 2008-09-18

Family

ID=39759351

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053609 WO2008111408A1 (ja) 2007-03-09 2008-02-29 多層配線基板及びその製造方法

Country Status (2)

Country Link
JP (1) JP5212359B2 (ja)
WO (1) WO2008111408A1 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4942862B1 (ja) * 2011-07-29 2012-05-30 日本碍子株式会社 積層焼結セラミック配線基板、及び当該配線基板を含む半導体パッケージ
WO2014171403A1 (ja) * 2013-04-17 2014-10-23 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
WO2015181976A1 (ja) * 2014-05-30 2015-12-03 株式会社メイコー プリント配線基板及びその製造方法
WO2016080333A1 (ja) * 2014-11-21 2016-05-26 株式会社村田製作所 モジュール
JPWO2016052284A1 (ja) * 2014-09-30 2017-06-22 株式会社村田製作所 多層基板
WO2019034562A1 (en) * 2017-08-14 2019-02-21 Tdk Electronics Ag LED MODULE
JP7450063B2 (ja) 2020-06-17 2024-03-14 珠海越亜半導体股▲分▼有限公司 多層基板及びその製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952666U (ja) * 1982-09-28 1984-04-06 富士通株式会社 ３次元多層構造をもつ半導体装置
JPH1154939A (ja) * 1997-07-31 1999-02-26 Kyocera Corp 配線基板
JP2003197810A (ja) * 2001-12-26 2003-07-11 Kyocera Corp 電子部品
JP2003347746A (ja) * 2002-05-28 2003-12-05 Kyocera Corp 多層回路基板
JP2005159039A (ja) * 2003-11-26 2005-06-16 Kyocera Corp 回路形成用積層体および回路基板
WO2007007451A1 (ja) * 2005-07-12 2007-01-18 Murata Manufacturing Co., Ltd. 多層配線基板及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952666U (ja) * 1982-09-28 1984-04-06 富士通株式会社 ３次元多層構造をもつ半導体装置
JPH1154939A (ja) * 1997-07-31 1999-02-26 Kyocera Corp 配線基板
JP2003197810A (ja) * 2001-12-26 2003-07-11 Kyocera Corp 電子部品
JP2003347746A (ja) * 2002-05-28 2003-12-05 Kyocera Corp 多層回路基板
JP2005159039A (ja) * 2003-11-26 2005-06-16 Kyocera Corp 回路形成用積層体および回路基板
WO2007007451A1 (ja) * 2005-07-12 2007-01-18 Murata Manufacturing Co., Ltd. 多層配線基板及びその製造方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013018172A1 (ja) * 2011-07-29 2013-02-07 日本碍子株式会社 積層焼結セラミック配線基板、及び当該配線基板を含む半導体パッケージ
US8487439B2 (en) 2011-07-29 2013-07-16 Ngk Insulators, Ltd. Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board
JP4942862B1 (ja) * 2011-07-29 2012-05-30 日本碍子株式会社 積層焼結セラミック配線基板、及び当該配線基板を含む半導体パッケージ
WO2014171403A1 (ja) * 2013-04-17 2014-10-23 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
WO2015181976A1 (ja) * 2014-05-30 2015-12-03 株式会社メイコー プリント配線基板及びその製造方法
JP5859678B1 (ja) * 2014-05-30 2016-02-10 株式会社メイコー プリント配線基板の製造方法
JPWO2016052284A1 (ja) * 2014-09-30 2017-06-22 株式会社村田製作所 多層基板
WO2016080333A1 (ja) * 2014-11-21 2016-05-26 株式会社村田製作所 モジュール
US10535581B2 (en) 2014-11-21 2020-01-14 Murata Manufacturing Co., Ltd. Module for heat generating electronic component
WO2019034562A1 (en) * 2017-08-14 2019-02-21 Tdk Electronics Ag LED MODULE
JP2020530665A (ja) * 2017-08-14 2020-10-22 ティーディーケイ・エレクトロニクス・アクチェンゲゼルシャフトＴｄｋ Ｅｌｅｃｔｒｏｎｉｃｓ Ａｇ Ｌｅｄモジュール
US11417583B2 (en) 2017-08-14 2022-08-16 Tdk Electronics Ag LED module
JP7450063B2 (ja) 2020-06-17 2024-03-14 珠海越亜半導体股▲分▼有限公司 多層基板及びその製造方法

Also Published As

Publication number Publication date
JP5212359B2 (ja) 2013-06-19
JPWO2008111408A1 (ja) 2010-06-24

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