TW201929163A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201929163A
TW201929163A TW106144592A TW106144592A TW201929163A TW 201929163 A TW201929163 A TW 201929163A TW 106144592 A TW106144592 A TW 106144592A TW 106144592 A TW106144592 A TW 106144592A TW 201929163 A TW201929163 A TW 201929163A
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layer
item
electronic package
scope
heat
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TW106144592A
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TWI659509B (zh
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許詩濱
許哲瑋
楊智貴
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英屬開曼群島商鳳凰先驅股份有限公司
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Priority to TW106144592A priority Critical patent/TWI659509B/zh
Priority to US16/354,267 priority patent/US10896882B2/en
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Publication of TW201929163A publication Critical patent/TW201929163A/zh

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Abstract

一種電子封裝件及其製法，係將電子元件以部分非作用面結合散熱件之導熱層，再以包覆層包覆該電子元件與該導熱層，之後於該包覆層上形成線路結構，使該線路結構電性連接該電子元件，故該散熱件係藉由該導熱層結合該電子元件，因而能提升散熱效果。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件，尤指一種側面呈非平直面之封裝基板。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，其中，球柵陣列式(Ball grid array，簡稱BGA)，例如PBGA、EBGA、FCBGA等，為一種先進的半導體封裝技術，其特點在於採用一封裝基板來安置半導體元件，並於該封裝基板背面植置多數個成柵狀陣列排列之銲球(Solder ball)，並藉該些銲球將整個封裝單元銲結並電性連接至外部電子裝置，使相同單位面積之承載件上可容納更多輸入/輸出連接端(I/O connection)以符合高度集積化(Integration)之半導體晶片之需求。
第1A至1E圖係為習知半導體封裝件1之製法之剖視示意圖。
如第1A圖所示，於一銅箔基板10上形成一增層線路結構11，其中，該增層線路結構11具有相對之第一側11a 與第二側11b，且該增層線路結構11以其第一側11a結合於該銅箔基板10上，並於該增層線路結構11之第二側11b上形成一防焊層12b。
如第1B圖所示，移除該銅箔基板10，並於該增層線路結構11之第一側11a形成另一防焊層12a。
如第1C圖所示，以覆晶方式將半導體晶片13藉由複數焊錫凸塊130設於該增層線路結構11之第一側11a上，再以封裝膠體14包覆該半導體晶片13與該些焊錫凸塊130。
如第1D圖所示，將複數散熱片15藉由黏著膠16設於該封裝膠體14上。
如第1E圖所示，沿如第1D圖所示之切割路徑L進行切單製程，以取得複數半導體封裝件1，且可形成複數焊球17於該增層線路結構11之第二側11b之外露線路表面上。
如第1F圖所示，於第1C圖之製程中，亦可以底膠18包覆該些焊錫凸塊130而免用封裝膠體14，以外露出該半導體晶片13之背面，故於第1D圖之製程中，該散熱片15可藉由黏著膠16設於該半導體晶片13之背面上。
惟，習知半導體封裝件1中，該增層線路結構11之線路材質通常為銅材，故該焊錫凸塊130結合異質金屬，因而會影響該增層線路結構11與該半導體晶片13之間的散熱及電性。
再者，該半導體晶片13之背面需黏著該散熱片15， 致使製程繁雜。
又，該散熱片15係以該黏著膠16作為導熱介面，致使散熱效果不佳。
另外，如第1E圖所示，該半導體封裝件1之散熱作用除了透過該散熱片15與該黏著膠16之外，還需透過該封裝膠體14，因而大幅降低散熱之效果。
因此，習知半導體封裝件1不適用高功率電源管理晶片(Power Management IC，簡稱PMIC)或高散熱需求的相關產品，故業界遂開發出另一種半導體封裝件，以配合高功率電源管理晶片(PMIC)或高散熱需求的相關產品。
第2A至2C圖係為習知半導體封裝件2之另一製法之剖視示意圖。
如第2A圖所示，置放複數半導體晶片23於一散熱片25之黏著膠(adhesion film tap)26上，再形成一封裝膠體24於該黏著膠26上，以包覆該半導體晶片23。
如第2B圖所示，形成一增層線路結構21於該封裝膠體24與該半導體晶片23上，以令該增層線路結構21透過雷射(laser)鑽孔製作導電盲孔之方式電性連接該半導體晶片23。接著，形成一防焊層22於該增層線路結構21上，且該防焊層22係露出該增層線路結構21之部分線路表面。
如第2C圖所示，沿如第2B圖所示之切割路徑L進行切單製程，以取得複數半導體封裝件2，且形成複數焊球27於該增層線路結構21之外露線路表面上。因此，該增層線路結構21之線路係直接結合該半導體晶片23，而無 需透過該焊錫凸塊，故該增層線路結構21與該半導體晶片23之間的散熱及電性能大幅提升，以配合高功率電源管理晶片(PMIC)或高散熱需求的相關產品。
惟，習知半導體封裝件2中，該半導體晶片23之背面仍需黏著該散熱片25，致使製程繁雜，且該散熱片25仍以該黏著膠26作為導熱介面，致使散熱效果不佳。
再者，該半導體晶片23之背面係全部黏滿該黏著膠26以貼固該散熱片25，且由於該半導體晶片23與該黏著膠26之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)，因而容易發生熱應力不均勻之情況，致使於後續進行加熱或烘烤等熱循環(thermal cycle)相關製程時，該黏著膠26會因翹曲(warpage)而分離(peeling)，導致該散熱片25之脫層(delaminating)問題。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：散熱件，係具有導熱層；電子元件，係設於該散熱件上，以於該電子元件與該散熱件之間形成一空間，使該導熱層形成於該空間中以接觸該散熱件與該電子元件；包覆層，係形成於該散熱件上及該空間中，以包覆該電子元件；以及線路結構，係設於該包覆層上並電性連接該電子元件。
本發明復提供一種電子封裝件之製法，係包括：將電 子元件設於一具有導熱層之散熱件上，以於該電子元件與該散熱件之間形成一空間，且該導熱層位於該空間中以接觸該散熱件與該電子元件；形成包覆層於該散熱件上及該空間中，以包覆該電子元件；以及形成線路結構於該包覆層上，並使該線路結構電性連接該電子元件。
前述之電子封裝件及其製法中，該散熱件之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
前述之電子封裝件及其製法中，該導熱層係為金屬層。
前述之電子封裝件及其製法中，該電子元件之其中一表面之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
前述之電子封裝件及其製法中，該包覆層係為鑄模化合物或底層塗料。
前述之電子封裝件及其製法中，該線路結構係包含形成於該包覆層中並電性連接該電子元件之第一線路部、形成於該包覆層上之絕緣層、及埋設於該絕緣層中之第二線路部。例如，該絕緣層係為鑄模化合物或底層塗料。
由上可知，本發明之電子封裝件及其製法，主要藉由於該電子元件與該散熱件之間的空間中形成該導熱層與該包覆層，使該包覆層僅結合該電子元件之部分背面，而其它背面部分則結合該導熱層，故相較於習知技術之黏著膠，本發明能大幅提升該電子封裝件之散熱效果。
再者，雖然該電子元件與該導熱層之間的附著力不 佳，但藉由該包覆層包覆該導熱層，不僅能增強該電子元件與該導熱層之間的附著力，且能以該導熱層分散該包覆層之熱應力，故相較於習知技術，本發明之電子封裝件於後續進行熱循環製程時，能避免該空間中之導熱層與包覆層發生翹曲，因而能避免該導熱層發生分離，進而能防止該散熱件發生脫層。
1,2‧‧‧半導體封裝件
10‧‧‧銅箔基板
11,21‧‧‧增層線路結構
11a‧‧‧第一側
11b‧‧‧第二側
12a,12b,22‧‧‧防焊層
13,23‧‧‧半導體晶片
130‧‧‧焊錫凸塊
14,24‧‧‧封裝膠體
15,25‧‧‧散熱片
16,26‧‧‧黏著膠
17,27‧‧‧焊球
18‧‧‧底膠
3‧‧‧電子封裝件
31‧‧‧線路結構
310‧‧‧絕緣層
311‧‧‧第一線路部
312‧‧‧第二線路部
312a‧‧‧線路層
312b‧‧‧導電柱
33‧‧‧電子元件
33a‧‧‧作用面
33b‧‧‧非作用面
330‧‧‧電極墊
34‧‧‧包覆層
35‧‧‧散熱件
350‧‧‧鋼板
351‧‧‧銅層
36‧‧‧導熱層
L‧‧‧切割路徑
S‧‧‧空間
第1A至1E圖係為習知半導體封裝件之製法之剖視示意圖；第1F圖係為第1E圖之另一態樣；第2A至2C圖係為習知半導體封裝件之另一製法之剖視示意圖；第3A至3D圖係為本發明之電子封裝件之剖視示意圖；第4A圖係為第3A圖之局部上視平面示意圖；以及第4B至4H圖係為第4A圖之其它態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第3A至3D圖係為本發明之電子封裝件3之剖視示意圖。
如第3A圖所示，將複數電子元件33設於一具有導熱層36之散熱件35上，以於該電子元件33與該散熱件35之間形成一空間S，且該導熱層36位於該空間S中。
於本實施例中，該電子元件33係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件33係具有相對之作用面33a與非作用面33b，該作用面33a具有複數電極墊330，且該電子元件33以其非作用面33b結合該導熱層36。
再者，該散熱件35係為金屬板材或其它導熱板材，例如鋼板350表面鍍附銅層351，並無特別限制。
又，該導熱層36可依需求選擇金屬材、非金屬、有機或無機材料等。具體地，該導熱層36選擇金屬材，例如，採用銀膏、銅膏或錫膏印刷成任意圖案(如第4A圖所示之對應單一電子元件33之複數點狀、如第4B圖所示之對 應單一電子元件33之單一片狀、如第4C與4D圖之點狀一致化或不同化、如第4E與4F圖之對稱之非連續圖形或對稱之連續圖形、如第4G與4H圖之非對稱圖形)，以結合單一該電子元件33之部分該非作用面33b，故藉由印刷方式製作該導熱層36，因而能於整版面(Panel)上形成該導熱層36，以利於快速生產該電子封裝件3。
另外，該導熱層36結合於該非作用面33b上之面積係佔該非作用面33b之面積20%至80%。
如第3B圖所示，形成一包覆層34於該散熱件35上以包覆該些電子元件33，並使該包覆層34填入該空間S中以包覆該導熱層36，以使單一該電子元件33之部分該非作用面33b接觸該包覆層34，其中，該包覆層34之材質不同於該導熱層36之材質。
於本實施例中，該包覆層34係以鑄模方式、塗佈方式或壓合方式形成於該散熱件35上，且形成該包覆層34之材質係為介電材料，該介電材料可為環氧樹脂(Epoxy)，且該環氧樹脂更包含鑄模化合物(Molding Compound)或底層塗料(Primer)，如環氧模壓樹脂(Epoxy Molding Compound，簡稱EMC)，其中，該環氧模壓樹脂係含有充填物(filler)，且該充填物含量為70至90wt%，使該包覆層34能抗翹曲，因而可無需藉由其它構件防翹曲。
如第3C圖所示，形成一線路結構31於該包覆層34上，使該線路結構31電性連接該些電子元件33。
於本實施例中，該線路結構31係包含一形成於該包 覆層34中之第一線路部311、至少一形成於該包覆層34上之絕緣層310、及至少一埋設於該絕緣層310中之第二線路部312。具體地，該第一線路部311係為複數個盲孔體或銅柱體，其電性連接該電子元件33之電極墊330，且該第二線路部312係包含相堆疊結合之一線路層312a及複數導電柱312b，其中，該線路層312a電性連接該第一線路部311，且該些導電柱312b係電性連接該線路層312a，並使該導電柱312b之端面外露於該絕緣層310以作為植球墊，俾供結合焊球(圖略)。
再者，該絕緣層310係以鑄模方式、塗佈方式或壓合方式形成於該包覆層34上，且形成該絕緣層310之材質係為介電材料，該介電材料可為環氧樹脂(Epoxy)，且該環氧樹脂更包含鑄模化合物或底層塗料，如環氧模壓樹脂(EMC)，其中，該環氧模壓樹脂係含有充填物，且該充填物含量為70至90wt%，使該絕緣層310能抗翹曲，因而該線路結構31可無需藉由其它構件防翹曲。應可理解地，該絕緣層310之材質與該包覆層34之材質可相同或不相同。
又，有關該線路結構31之製程種類繁多，例如增層(build-up)製程、重佈線路(Redistribution Layer，簡稱RDL)製程等，並無特別限制，特此述明。
如第3D圖所示，沿如第3C圖所示之切割路徑L進行切單製程，以取得該電子封裝件3。
本發明之製法係藉由金屬印刷方式製作該導熱層 36，以於該電子元件33之部分非作用面33b上結合該導熱層36，而無需於全部該非作用面33b上形成該導熱層36，故相較於習知技術之黏著膠製程，本發明之製法不僅速度快，且能節省該導熱層36之材料以降低製程成本。
再者，該散熱件35與該電子元件33之非作用面33b藉由該導熱層36作為導熱介面，故相較於習知技術，本發明之製法能大幅提升該電子封裝件3之散熱效果。
又，於該電子元件33與該散熱件35之間的空間S中係形成有該導熱層36與該包覆層34，以藉由該導熱層36分散該包覆層34之熱應力，故相較於習知技術，本發明之電子封裝件3於後續進行加熱或烘烤等熱循環相關製程時，能避免該空間S中之導熱層36與包覆層34發生翹曲，因而能避免該導熱層36發生分離，進而能防止該散熱件35發生脫層。
另外，該電子元件33與該導熱層36之間的附著力不佳，因而本發明之製法係藉由該包覆層34整體包覆該導熱層36，以增加附著力，故能穩定該電子封裝件3之結構強度。
因此，本發明之電子封裝件3適用高功率電源管理晶片(PMIC)或高散熱需求的相關產品。
本發明亦提供一種電子封裝件3，係包括：一散熱件35、一電子元件33、一包覆層34以及一線路結構31。
所述之散熱件35之表面上係具有導熱層36，如金屬層。
所述之電子元件33係設於該散熱件35上，以於該電子元件33與該散熱件35之間形成一空間S，使該導熱層36形成於該空間S中以接觸該散熱件35與該電子元件33。
所述之包覆層34係為鑄模化合物或底層塗料，其形成於該散熱件35上及該空間S中，以包覆該電子元件33與該導電層36。
所述之線路結構31係設於該包覆層34上並電性連接該電子元件33。
於一實施例中，該散熱件35之其中一部分接觸該導熱層36，而另一部分接觸該包覆層34。
於一實施例中，該電子元件33之其中一表面(即該非作用面33b)之其中一部分接觸該導熱層36，而另一部分接觸該包覆層34。
於一實施例中，該線路結構31係包含一形成於該包覆層34中並電性連接該電子元件33之第一線路部311、至少一形成於該包覆層34上之絕緣層310、及至少一埋設於該絕緣層310中之第二線路部312，且該絕緣層310係為鑄模化合物或底層塗料。
綜上所述，本發明之電子封裝件及其製法，係藉由該電子元件與該散熱件之間的部分空間中形成導熱層，使整體製法不僅速度快，且能降低製程成本，並能提升散熱效果。
再者，於該電子元件與該散熱件之間的空間中，以包覆層包覆導熱層，不僅能避免該導熱層發生分離，且能增 加該導熱層與該電子元件之間的附著力。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (24)

  1. 一種電子封裝件，係包括：散熱件，係具有導熱層；電子元件，係設於該散熱件上，以於該電子元件與該散熱件之間形成一空間，使該導熱層形成於該空間中以接觸該散熱件與該電子元件；包覆層，係形成於該散熱件上及該空間中，以包覆該電子元件；以及線路結構，係設於該包覆層上並電性連接該電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該散熱件之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該導熱層係為金屬層。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該導熱層係為銀膏、銅膏或錫膏。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該導熱層之圖形係為複數點狀或單一片狀。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該些點狀之圖形係為一致化或不同化。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該導熱層之圖形係為對稱圖形或非對稱圖形。
  8. 如申請專利範圍第1項所述之電子封裝件，其中，該導 熱層之圖形係為非連續圖形或連續圖形。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件之其中一表面之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層係為鑄模化合物或底層塗料。
  11. 如申請專利範圍第1項所述之電子封裝件，其中，該線路結構係包含形成於該包覆層中並電性連接該電子元件之第一線路部、形成於該包覆層上之絕緣層、及埋設於該絕緣層中之第二線路部。
  12. 如申請專利範圍第11項所述之電子封裝件，其中，該絕緣層係為鑄模化合物或底層塗料。
  13. 一種電子封裝件之製法，係包括：將電子元件設於一具有導熱層之散熱件上，以於該電子元件與該散熱件之間形成一空間，且該導熱層位於該空間中以接觸該散熱件與該電子元件；形成包覆層於該散熱件上及該空間中，以包覆該電子元件；以及形成線路結構於該包覆層上，並使該線路結構電性連接該電子元件。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該散熱件之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
  15. 如申請專利範圍第13項所述之電子封裝件之製法，其 中，該導熱層係為金屬層。
  16. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該導熱層係為銀膏、銅膏或錫膏。
  17. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該導熱層之圖形係為複數點狀或單一片狀。
  18. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該些點狀之圖形係為一致化或不同化。
  19. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該導熱層之圖形係為對稱圖形或非對稱圖形。
  20. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該導熱層之圖形係為非連續圖形或連續圖形。
  21. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該電子元件之其中一表面之其中一部分接觸該導熱層，而另一部分接觸該包覆層。
  22. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該包覆層係為鑄模化合物或底層塗料。
  23. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該線路結構係包含形成於該包覆層中並電性連接該電子元件之第一線路部、形成於該包覆層上之絕緣層、及埋設於該絕緣層中之第二線路部。
  24. 如申請專利範圍第23項所述之電子封裝件之製法，其中，該絕緣層係為鑄模化合物或底層塗料。
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