TWI290762B - Semiconductor chip embedded in carrier board and method for fabricating the same - Google Patents

Semiconductor chip embedded in carrier board and method for fabricating the same Download PDF

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Publication number
TWI290762B
TWI290762B TW095100836A TW95100836A TWI290762B TW I290762 B TWI290762 B TW I290762B TW 095100836 A TW095100836 A TW 095100836A TW 95100836 A TW95100836 A TW 95100836A TW I290762 B TWI290762 B TW I290762B
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Taiwan
Prior art keywords
semiconductor wafer
carrier
layer
trench
dielectric layer
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TW095100836A
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Chinese (zh)
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TW200727434A (en
Inventor
Zhao-Chong Zeng
Shih-Ping Hsu
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Phoenix Prec Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

A semiconductor chip embedded in carrier board and a method for fabricating the same are proposed. A carrier board with the first and second surfaces is provided, and at least one opening is formed and penetrates the first and the second surfaces. The first trench is formed on the first surface of carrier board around the opening while the first trench does not penetrate the carrier board. The first dielectric layer is formed on the first surface of carrier board to seal the first trench and the opening. A semiconductor chip with an active surface and a non-active surface opposite to the active surface is received in the opening. An adhering layer is formed on the non-active surface of the semiconductor chip, and the first dielectric layer is filled in the first trench and the opening for immobilizing the semiconductor chip. The second trench is formed on the second surface of carrier board and opposite to the first trench to form a trench penetrating the carrier board. Afterwards, the cutting operation is performed via the narrower trench. Therefore, space usage and layout density are improved and the heat is dissipated more efficiently.

Description

1290762 九、發明說明： 【發明所屬之技術領域】 一種谈埋半導體晶片之承載板結構及其製法，尤指一 種同時整合有散熱件、半導體晶片及線路結構之嵌埋^導 體晶片之承載板結構及其製法。 、 【先前技術】1290762 IX. Description of the invention: [Technical field of invention] A structure of a carrier plate for burying a semiconductor wafer and a method for manufacturing the same, in particular, a carrier plate structure in which a heat sink, a semiconductor wafer and a wiring structure are embedded And its method of production. [Prior Art]

隨著電子產業的蓬勃發展，電子產品亦朝輕、薄、短、 ='土高集積度 '多功能化方向發展。為滿i半導體封二 向積集度（Integration)以及微型化（Minton)、的 封裝需求，半導體晶片之封裝形逐漸由單-晶片之球栅陣 歹! (BGA)封裝或覆晶式（FlipChip，FC)封裝演進到3D 封裝和模組化缝形態，使得封裝之結構產生了不同的面 貌例如 siP(SysteminPackage)，SIp(SystemintegratedWith the booming development of the electronics industry, electronic products are also developing in the direction of lightness, thinness, shortness, and 'high accumulation of soil'. For the integration and miniaturization of the semiconductor package, the package shape of the semiconductor wafer is gradually formed by a single-chip ball grid array (BGA) package or flip chip (FlipChip). , FC) package evolution to 3D packaging and modular seam form, resulting in a different look of the package structure such as siP (SysteminPackage), SIp (Systemintegrated

Package) ，SiB(SysteminB〇ard)等多種形式。 惟，該些3D及模組化封裝形態係以覆晶技術（叫 〇 Φ ，或打線接合（wire b〇nding；)將# 一 s 個接一個的連接至曰Η 7并4 士 ]千¥遠日日片一 板表面’亦或以表面黏貼技術 C SA1T )黏貼於晶片. 」载板表面。如此，雖可達到高腳數 、垂、三、旦疋在更高頻使用時或高速操作時，其將因導線 ^~忮之效能無法提昇，而有所限 制，另外，因傳餅封获兩西夕l 生產製造成本。、、、， 八的連接介面，相對地增加 ub ’為了能有效地提昇電性品質以符合下世品 之應用，業界紛紛研究接 木用將日日片埋入承載板内之直接的 18886 6 1290762 電性連接，以用來縮短電性傳導路徑， 訊號失真及提昇在高速操作之能力。 貝失、 如第1圖所示，係為習知的體 之剖面示意圖。如圖所示，該封裝件係包括封 至少且-該半表面1〇。形成有至少-開，a; + V肢日日片11，且該半導體晶片u上形 J極墊110’係接置於該承載板10上且收納於該開口夕1〇〇 中尽線路增層結構12係形成於該承載板1G上 a 增層結構12係藉由满赵道+亡 ^、、泉路 晶片u上之電盲孔12。電性連接叫^ •相對=2晶片11係具有一主動面lla及與該主動面 墊110,該非主面動Ub’且該主動面以上形成有多數電極 板開口⑽中。面㈣係透過黏著材料13接置於該承載 線路增層結構12係包括至少一介電層⑵ •t電層121上之線路層122,以及形成於該介電 中亚電性連接該線路層122之導電盲孔120，且該等多數 得以電性連接至收納於該承載板開口 之-^ = 4 11的電極塾11G°而在該線路增層結構12 取表面之線路層上則形成有多數電性連接端123， 該最外層線路層上係形成有—係如防焊層之絕緣保護声 =㈣緣保護層124係具有多數開口以外露出該電㈣ 用以提供植置導電元件，例如為谭球（Solder 5俾供收納於該承載板1 〇中之該半導體晶片11 18886 7 1290762 知以透過其表面之電極熱 125電性導接至外部元件。、為增層結構12以及焊球 惟，為節省封裝成本，半導體 2版面之基板中同時埋設多數個半導體 半;=片基體晶片上進行線路製程以形成與該此 線路’以完成該㈣體晶片向i 電=接’之後可藉由切割作業以形成具單_半導體晶 件 '然’上述習知製程中，於該基板上進行 切割作業，由於銑刀之刀具體積大，於 對應大小的空間，因而浪費基板峨 工間，進而ν致基板之排版率降低。 再者，上述之封裝結構雖然提高了晶片的封參穷产及 電性功能，但半導體W 11透㈣著_13接置:^承 ^板10開π 100a中’因在半導體晶片u與承載板1〇間 玉隙之填膠控制困難，容易於半導體晶片u之邊緣產生* 穴（Void)現象。同時，將半導體晶片n里於承載板工 i〇内之結構，若無时效逸散熱量，㈣行高溫製程或可 罪度測試時，將產生結構剝離（Peeling)或爆板現象。 因此，如何提供一種後埋半導體晶片之承载板結構及 其製法’以避免習知技術中基板使用空間浪費、基板排版 率低、基板散熱效果差及結構剝離等缺失，實已成爲目矿 業界待解決之難題。 爲則 【發明内容】 18886 8 1290762 鑒於上述習知技術之缺失，本發明之主要目的在於提 供一種嵌埋半導體晶片之承載板結構及其製法，得以增加 基板排版率。 曰σ 本發明之另一目的在於提供一種嵌埋半導體晶片之 承載板結構及其製法，藉以提升基板之散熱效果。 本發明之再一目的在於提供一種嵌埋半導體晶片之 承載板結構及其製法，可避免結構剝離並提升產品良率。 為達上述及其他目的，本發明提供一種嵌埋半導體晶 片之承載板結構之製法，係包括··提供一具第一表面及相 對於第-表面之第二表面之承載板，於該承載板中形成至 ^貝牙该第一及第二表面之開口，且於該承載板第一表 面升y成至 圍繞该開口且未貫穿該承載板之第一溝样· 於該承載板之第一表面形成一第一介電層，以藉由該 介電層封住談第一溝槽及該開口；於該開口中容置至少一 半導體晶片，且使該第一介電層填充於該第一溝槽中及該 翁半導體晶片之開口中，以將該半導體晶片固定在該開口 Λ 中，其中，该半導體晶片係具有一主動面及相對之非主動 面，且於該半導體晶片之非主動面形成一黏著層；以及於 該承载第二表面對應該第一溝槽位置形成第二溝檜，且使 該第二溝槽與該第-溝槽相連通，藉以形成貫穿該承載板 之溝槽。 本發明之嵌埋半導體晶片之承載板結構之製法復包 2 ·於该承載板第二表面及該半導體晶片之主動面形成一 第二介電層，使該第二介電層填充於該第二溝槽中，且該 18886 9 1290762 f導體晶片之作用面具有複數 ，形成-線路層，且該線路層藉由形成 ¥電結構電性連接至該半導體晶片之電極墊了 另，上述製程復包括於該第二介 行線路增層萝裎以艰& rt 电層及5亥，泉路層上進 姓槿士Γ 該線路層電性連接之線路增声 :該在進行線路增層製程的同時，； 板。 电曰外表面形成一具多層金屬結構之金屬 -係如又線路增層結構最外“形* 声中針庳：ΐ 且於該金屬板及該第-介電 半導體晶片之非主動面之黏著層成 :形成的溝槽進行切割作業以形成一嵌埋;= 片之承載板結構。 千^肢日日 保嗜ί者’上述製法復包括移除該半導體晶片非主動面之 ”叹曰，且於貫穿該第一介電層及金屬板之開口中形 導熱可於該金屬板及該導熱膠上接置—散熱板。 包括：，供一職埋半導體晶片之承載板結構，係 及第二表面之承載板’該承載板令形成有至 二牙：―及第二表面之開口’且該承載板中形成有 二開口之溝槽；至少一半導體晶片，係容設於 ，該半導體晶片係具有-主動面及相對 面’且該半導體晶片之非主動面具有一黏著層； 以及一第一介電層，係形成於該承載板之第一表面，i填 18886 10 1290762 充於該承載板之開口中以固定該半導體晶片及填充於該溝 槽中。 Λ〆 本發明之嵌埋半導體晶片之承載板結構復包括：一形 成於該承載板第二表面及該半導體晶片主動面之第二介電 層，且該第二介電層係填充於該溝槽中；以 二介電層讀該半導體晶片電性連接之線路層。$ ^ μ上述嵌埋半導體晶片之承載板結構復包括一形成於 4第一介電層及該線路層上之線路增層結構，且該線路增 a…構係電丨生連接至該線路層，此外，該線路增層結構外 表面復形成有一絕緣保護層。 又，上述該第一介電層外表面復形成一具多層金屬結 構之孟屬板’且该第一介電層及該金屬板中對應該承載板 位置形成貫穿之開口以露出該半導體晶片非主動面之 後續可移除該黏著層，並進行切割作 -w刮仆杲，亚於頁穿該 厂"電層及金屬板之開口中形成—導熱膠’且於該金屬 反及5亥導熱膠上接置-散熱板’以形成-具有半導體晶片 =载板結構，至此形成—具散熱板、半導體晶片及線i 結構之承載板結構。 結二本發明之嵌埋半導體晶片之承載板 切割作於製程過程切形成可供後續進行 所而之見度車父小之溝槽（第一及第二溝槽），該 之=之溝槽佔據該承載板較小之使用㈣，可以-般 /、達仃切割(Saw)即可完成切割作業，而無須使用銑刀 18886 11 1290762 (uter)切須佔據該承載板較大之使用 而可提升承载板之排版帛。 毛月口 毛月係可由承載板上下表面分別形成線路及旦 多數層金屬層之冬屋4c , ” +、、， 之1屬板，以完成容置於該承載板開口中之 半導體晶片向外之雷祕、击 Q — 連接，且可猎由該金屬板作爲半導 體晶片散熱用。 本I月中’可於該金屬板上接置一散熱板以一 步增強散熱效果，從& π、杀、風》人歷， 、… 攸而可透過該金屬板及散熱板之組合將 半導體晶片運作時產+ &為旦 ' 俾可提升晶片埋入式封炎έ士嬙夕士处 卜界 飞封衣、…構之功此’而使此類型之封裝 °構知以進步發展，藉以避免習知技術中半導體晶片埋 入封裝基板，由於無法控制半導體晶片散熱所引起 缺失。 【實施方式】 、以下藉由#寸疋的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。本發明亦可藉由其他不同 的具體實施例純應用或騎，本料書巾的各項細節亦 可基於不同的觀點與制，在料離本發明之精神下 各種修飾與變更。 請參閱第2Α圖至第21圖係顯示本發明之後埋半導 體晶片之承載板結構之製法流程圖。須注意的是，該等圖 式均為簡化之示意圖，僅以示意方式說明本發明之電路板 之製程。惟該等圖式僅顯示與本發明有關之元件，其所顯 18886 12 1290762 I之際實施時之態樣，其實際實施時之元件數 型態可能更形複:例為一種選擇性之設計，且其元件佈局 儀且右I Μ圖所不，首先提供一承載板20，該承載板20 〜、 弟一表面2〇a及與該第一表面20a相對之第二表 =且於該承载板2。中形成至少一貫穿該第一及；二 繞該也Γ 200，以及於該承載板20第一表面2〇a形成圍 幵口 200且未貫穿該承載板20之第一溝槽201 姑上述承載板2G係可為金屬材料所製成之散熱板， 承載板亦可為BT樹脂、腿樹脂、環氧樹脂、 亦：糸維、聚乙醯胺或氰脂等樹脂材料所製成的絕緣板， 亦或為形成有線路結構之電路板。 Π:利用例Μ刻一製程形成 1 4成於邊承載板第—表面之介電層可填滿該 溝槽之深度爲基專。 镇- t ί 2B圖所示，於承載板2G之第-表面加形成-笔層210以封住該承載板開口 200 —端及該第一溝 且忒第一介電層21 〇未與該承載板2〇接觸的一側 成有一金屬薄層211。該金屬薄層211之形成方 ^ 於该金屬薄層211上依序疊合第一介電層210及承 載板2〇;或於該金屬薄層211先壓合或沉積於該第一介電 210上’再將該承載板20疊合於該第一介電層210未形 成有f屬薄層211之表面，以封住該承載板開口 200 -端 第溝槽201。纟於為有效提供後續於該金屬薄層上 18886 13 1290762 電鍵金f層^合性，較佳之具體實_係於該金屬薄層 盆先將第—介電層21G之表面^以粗糙化。 ，t ’該第一介電層210可為環氧樹脂（EP〇xyresin)、聚 ^胺（olyimide)、氰g旨（Cyanate如⑻、玻璃纖維、雙順 丁烯一酸酉&亞胺/三氮啡（Bismaleimide Triazine, BT)或混 合環氧樹脂與玻璃纖維之FR5等材質所製成；該金屬薄層 2二：般係以導電性較佳之銅(CU)為主，以作為訊號傳遞 籲、、‘材料同日守，本貫施例採用一樹脂壓合銅箔（Resin Coated C〇Pper，RCC)為例進行說明。 —如第2C圖所示’接著，於該承載板開口 200中分別 容置-半導體晶片22’並透過例如壓合製程使該第一介電 層填充於該第一溝槽2〇1中，並填充於該開口 中， 以將該半導體晶片22固定於該承載板別之開口 中。 該半導體晶片22儀具有一主動面❿及與該主動面 22a相對之非主動面22b’於該主動面仏形成有多數電極 φ墊221 ’而该非主動面形成有—係如離型臈之黏著層⑵〇 以供半導體晶片22容設固定於開口 。該半導體晶片u 於其非主動面22b以-黏著層221〇接置於該第一介電層 210上，且容設於該承載板2〇之開口 2⑽中。 如第2D圖所示，於該承载板2〇第二表面鳩對應該 第-溝槽加的位置形成第二溝槽2〇2,且使該第二溝槽 202與該第-溝槽201相連通以形成貫穿該承載板汕之 槽203，以供後續進行利用切割工具進行切割作業之用 其中該第一溝槽201與第二溝槽202之形成方式;利用圖 18886 14 1290762 案化钱刻製程即可形成相連通之第—溝槽训與第 202 ’蝕刻製程為習知技術，於此不再贅述。 曰 ^因此’本發明主要係於半導體晶/ 之封裝製程中，即 於该承載板2 0中預先开；成可徂％ @ 較小之貫*、盖描。、Λ (、後、，，進行切割作業且寬度 提升排可有效利用承載板之使用空間， =非=率’同時可藉由該溝槽203利用一般刀具進行簡 :之切吾j(Saw)即可形成具單一半導體晶片之承載板么士 構，該寬度較小之溝槽2G3佔據該承餘較小之使用^ 用銑刀(Router)切割須佔據該承載板較：之 使用二=，本發明因而可提升承载板之排版率。 如第2E圖所示’於該承載板2()第二表面鳥及 導體晶片22上依序形成一第二介電層以及線路層μ，、 線路層24係、電性連接至該半導體晶片22主動面22a之： 極墊221 人且該第二介電層23係填充於該第二溝槽加-中並於，亥第一介電層23中形成有多數開孔挪以露 半導體晶片22主動面22a之電極墊221。該第二介電層;； 係透過壓合方式形成於該承載板及該些半㈣晶片表^ 且填充於該第二溝槽搬中。該第二介電層23可為環 脂（Epoxy resin)、聚乙醯胺（p〇lyimide)、氰酯3 Ester)、玻璃纖雄、雙順丁烯二酸醯亞胺/三氮阱 (Bi_leimide Triazine，BT)或混合環氧樹脂與玻螭纖維之 FR5等材質所製成。該線路層24係為圖案化金屬層（例如 金屬銅層），該線路層24係透過形成於該第二介^層 之開孔230中的導電結構24〇 (例如導電盲孔）電=生^接 18886 15 1290762 至°亥半導體晶片之電極墊221。 於該程以形成該線路層24的同時， 一與線路㉟24相同材質之金屬層2i2 (例如金屬鋼2另 本發明係採用於該承載板相對—及 。 金屬制妒Κ Μ 汉弟一表面问時進行 該承：：ΐ路製程，因而可於進行線路製程的同時，於 ::俾：：弟二表面形成可供半導體晶片散熱用之金屬、 数效果差==產品之散熱絲，以避Η知技術中散 功料似晶片埋人式縣結構發展受到限制 帛2F圖所不’之後復可於該第二介電層23及亨線 “二上，線路增層製程以形成所需電性嫩 該線路增層結構25得以電性連接至該線 該線路增層結構25係包括介電層250、疊置於該介電 “ 250上之線路層252、以及穿過該介電層2兄以供該線 路層252電性連接至介電層下方線路層24之導電結構^ 252a。 此外’本發明中，亦可依據實際設計需要在形成線路 層252的同時於上述金屬層212上進行多次電鍍以堆疊多 層金^^該第-介電層21Q外表面生成具多層金屬結構 且^定厚度之金屬板213，惟若該金屬板213於先前電 鑛衣私中已達預定厚度時，係可在該金屬板上覆蓋— 阻層以防止其持續生成。此金屬板213可作爲半導體晶片 16 18886 1290762 22散熱用之散熱板。 如弟2 G圖所示，禮可於兮 ^ 了於该線路增層結構25之外声& 形成-係如防焊層之絕緣保之外表面 構最外#而々綠於 6以保禮该線路增層結 構取外表面之線路’且該絕緣保護層2 出該線路增層結構25最外 /、 4孔261以路 之後復可於露出該絕緣保護層之之， 上接置導電元件（圖式中未表;·、孔261之電性連接塾251 9?,. 、不）至此完成該半導體晶月 22向外之電性連接。接著， V體日日片 213 ϊ 、以弟一，1電層210及金屬板 τ對應该承載板20之開口 2〇λ 形成貫φ夕„ ^ 位置以蝕刻或雷射方式 ZD衣面的黏著層2210。 =2H圖所示，移除該黏著層221〇，之後，復可藉 ^槽2〇1及第二溝槽202所形成 =切吾|H乍業，以形成一具有至少一半導體晶片以Package), SiB (SysteminB〇ard) and other forms. However, these 3D and modular package configurations are based on flip chip technology (called 〇Φ, or wire b〇nding;) #一s one by one connected to 曰Η 7 and 4 士] thousand ¥ On the surface of a board of the far-day film, or by surface-adhesive technology C SA1T, it is adhered to the wafer. In this way, although it can achieve high number of feet, vertical, three, and dan, when it is used at a higher frequency or at a high speed, it will be limited due to the performance of the wire, and it is limited. Two Xixi l production costs. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Electrical connection to shorten electrical conduction paths, signal distortion and enhance the ability to operate at high speeds. Bellows, as shown in Fig. 1, is a schematic cross-sectional view of a conventional body. As shown, the package includes at least and - the half surface 1 〇. Forming at least an open, a; + V limb day piece 11 , and the semiconductor chip u upper J pole pad 110 ′ is attached to the carrier plate 10 and received in the opening 夕 1〇〇 The layer structure 12 is formed on the carrier plate 1G. The buildup structure 12 is an electric blind hole 12 on the wafer u of the full Zhao Road + dead ^, and the spring road. The electrical connection is called a relative-to-two wafer 11 having an active surface 11a and the active surface pad 110. The non-primary surface movement Ub' is formed in a plurality of electrode plate openings (10) above the active surface. The surface (4) is connected to the load-bearing line through the adhesive material 13 and the wiring layer 12 includes at least one dielectric layer (2), the circuit layer 122 on the electrical layer 121, and is electrically connected to the circuit layer in the dielectric. a conductive blind hole 120 of 122, and the plurality of electrodes are electrically connected to the electrode 塾 11G of -^= 4 11 accommodated in the opening of the carrier, and formed on the circuit layer of the surface of the line build-up structure 12 a plurality of electrical connection terminals 123, the outermost circuit layer is formed with an insulation protection sound such as a solder mask layer. (4) The edge protection layer 124 has a plurality of openings to expose the electricity (4) for providing a conductive component, for example For the ball (Solder 5), the semiconductor wafer 11 18886 7 1290762 for storage in the carrier 1 is electrically conductively connected to the external component through the electrode 125 of the surface. The build-up structure 12 and the solder ball However, in order to save the packaging cost, a plurality of semiconductor halves are simultaneously buried in the substrate of the semiconductor 2 layout; = the line process is performed on the wafer base wafer to form the line 'to complete the (four) body wafer to the i-electricity= connection' Shaped by cutting operation In the above-mentioned conventional process, the cutting operation is performed on the substrate. Since the cutter of the milling cutter has a large volume and a space corresponding to the size, the substrate is wasted, and the layout of the substrate is further In addition, although the above-mentioned package structure improves the sealing function and electrical function of the wafer, the semiconductor W 11 is transparent (4) with _13 connection: ^ board 10 is opened in π 100a 'because of the semiconductor wafer u is difficult to control the filling of the jade gap between the carrier and the carrier, and it is easy to generate a Void phenomenon at the edge of the semiconductor wafer u. At the same time, the structure of the semiconductor wafer n in the carrying board is not aged. The heat dissipation, (4) high temperature process or sinus test, will result in structural peeling or blasting. Therefore, how to provide a carrier plate structure of the buried semiconductor wafer and its manufacturing method 'to avoid the prior art The lack of space for substrate use, low substrate layout rate, poor substrate heat dissipation and structural peeling have become a difficult problem to be solved in the mining industry. For the purpose of this article 18886 8 1290762 The main purpose of the present invention is to provide a carrier board structure for embedding a semiconductor wafer and a method for manufacturing the same, which can increase the substrate layout rate. 曰σ Another object of the present invention is to provide a carrier board structure for embedding a semiconductor wafer and The method of the invention is to improve the heat dissipation effect of the substrate. A further object of the present invention is to provide a carrier plate structure for embedding a semiconductor wafer and a manufacturing method thereof, which can avoid structural peeling and improve product yield. To achieve the above and other objects, the present invention Providing a method for fabricating a carrier plate structure for embedding a semiconductor wafer, comprising: providing a carrier plate having a first surface and a second surface opposite to the first surface, wherein the first plate is formed in the carrier plate And the opening of the second surface, and the first surface of the carrier plate is raised to a first groove around the opening and not extending through the carrier plate. A first dielectric layer is formed on the first surface of the carrier plate. The first trench and the opening are sealed by the dielectric layer; at least one semiconductor wafer is accommodated in the opening, and the first dielectric layer is filled in the first And a recess in the opening of the semiconductor wafer to fix the semiconductor wafer in the opening, wherein the semiconductor wafer has an active surface and a relatively inactive surface, and the inactive surface of the semiconductor wafer Forming an adhesive layer; and forming a second trench at the first trench corresponding to the second surface of the carrier, and connecting the second trench to the first trench to form a trench penetrating the carrier . The method for fabricating the carrier plate structure of the embedded semiconductor wafer of the present invention is as follows: forming a second dielectric layer on the second surface of the carrier substrate and the active surface of the semiconductor wafer, and filling the second dielectric layer with the second dielectric layer In the two trenches, the active surface of the 18886 9 1290762 f-conductor wafer has a plurality of layers forming a circuit layer, and the circuit layer is electrically connected to the electrode pads of the semiconductor wafer by forming a photovoltaic structure, and the process is completed. Including the second intervening line, the layer is added with a hard & rt electric layer and a 5 hai, the spring road layer is entered into the surname of the gentleman. The line connecting the electrical connection of the line is increased: the line is added. At the same time; board. The outer surface of the electric raft forms a metal with a multi-layered metal structure - such as the outermost layer of the wire-added structure, the shape of the sound is 庳: and the adhesion of the non-active surface of the metal plate and the first-dielectric semiconductor wafer Layering: forming a groove to perform a cutting operation to form an embedded layer; = a carrier plate structure of the piece. The method of the above-mentioned method includes removing the inactive surface of the semiconductor wafer. The heat conduction in the opening of the first dielectric layer and the metal plate can be connected to the metal plate and the thermal conductive adhesive. The method includes: a carrier board structure for burying a semiconductor wafer, and a carrier board for the second surface. The carrier board is formed with two openings: “the opening of the second surface” and two openings are formed in the carrier board a trench; at least one semiconductor wafer is disposed on the semiconductor wafer having an active surface and an opposite surface and the non-active mask of the semiconductor wafer has an adhesive layer; and a first dielectric layer is formed on The first surface of the carrier is filled with 18886 10 1290762 to fill the opening of the carrier to secure the semiconductor wafer and fill the trench. The carrier board structure of the embedded semiconductor wafer of the present invention further comprises: a second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor wafer, and the second dielectric layer is filled in the trench In the trench; the circuit layer electrically connected to the semiconductor wafer is read by two dielectric layers. The carrier structure of the embedded semiconductor wafer includes a line build-up structure formed on the first dielectric layer and the circuit layer, and the line is electrically connected to the circuit layer. In addition, an outer insulating layer is formed on the outer surface of the line build-up structure. In addition, the outer surface of the first dielectric layer is formed into a multilayer metal structure of a plurality of metal structures, and the first dielectric layer and the corresponding opening of the metal plate corresponding to the position of the carrier plate are formed to expose the semiconductor wafer. After the active surface, the adhesive layer can be removed, and the cutting is performed as a -w scraping sputum, which is formed in the opening of the factory"electric layer and the metal plate - the thermal conductive adhesive is used and the metal is reversed The thermal paste is attached to the heat sink to form a semiconductor wafer=carrier structure, and thus a carrier plate structure having a heat sink, a semiconductor wafer and a wire i structure is formed. The second embodiment of the embedded semiconductor wafer of the present invention is cut into a trench for forming a trench (the first and second trenches) for the subsequent process. Occupying the small use of the carrier plate (4), the cutting operation can be completed by the general/saw cutting (Saw) without using the milling cutter 18886 11 1290762 (uter) to occupy the larger use of the carrier plate. Improve the layout of the carrier board. Maoyuekou Maoyue can form a winter house 4c, "+,," of the metal plate of the carrier board and the metal layer of the majority of the metal layer to complete the semiconductor wafers accommodated in the opening of the carrier plate. The thunder, hit Q-connection, and can be used for the heat dissipation of the metal plate as a semiconductor wafer. In this I month, a heat sink can be attached to the metal plate to enhance the heat dissipation effect from & π, kill , the wind, the calendar, ..., and through the combination of the metal plate and the heat sink, the semiconductor wafer is operated when the production of the semiconductor wafer is + amp 俾 俾 提升 提升 提升 提升 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The sealing and the construction of this type have led to the development of this type of packaging, in order to avoid the semiconductor chip embedded in the package substrate in the prior art, and the lack of heat dissipation of the semiconductor wafer can be controlled. The embodiments of the present invention are described in the following by means of a specific embodiment of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present specification. The various embodiments are purely applied or ridiculous, and the details of the book towel may be based on different viewpoints and systems, and various modifications and changes are possible in the spirit of the present invention. Please refer to Fig. 2 to Fig. 21 The flow chart of the structure of the carrier plate for embedding the semiconductor wafer after the present invention is shown. It is to be noted that the drawings are simplified schematic diagrams, and the process of the circuit board of the present invention is only illustrated in a schematic manner. The components related to the present invention are shown as being implemented at the time of 18886 12 1290762 I, and the number of components in actual implementation may be more complex: an example of a selective design and a component layout device And the right side is not provided, firstly, a carrier board 20 is provided, and the carrier board 20~, the second surface 2〇a and the second surface opposite to the first surface 20a are formed in the carrier board 2. The first groove is inserted through the first and second sides, and the first groove 2 is formed on the first surface 2〇a of the carrier plate 20 and the first groove 201 is not penetrated through the carrier plate 20. a heat sink made of a metal material The board may also be an insulating board made of a BT resin, a leg resin, an epoxy resin, a resin material such as a bismuth, a polyethyleneamine or a cyanide, or a circuit board formed with a wiring structure. For example, a process is formed to form a dielectric layer on the first surface of the edge carrier to fill the depth of the trench. The town-t ί 2B is shown on the first surface of the carrier 2G. Forming a pen layer 210 to seal the end of the carrier opening 200 and the first trench and the side of the first dielectric layer 21 that is not in contact with the carrier 2 is formed with a thin metal layer 211. The metal thin The layer 211 is formed on the metal thin layer 211 to sequentially overlap the first dielectric layer 210 and the carrier plate 2; or the metal thin layer 211 is first pressed or deposited on the first dielectric 210. The carrier 20 is then superposed on the surface of the first dielectric layer 210 where the thin layer 211 is not formed to seal the carrier opening 200 - the end trench 201. In order to effectively provide the subsequent bonding of the gold layer of the 18886 13 1290762, it is preferable to roughen the surface of the first dielectric layer 21G in the thin layer of the metal. , t 'the first dielectric layer 210 may be epoxy resin (EP〇xyresin), polyamine (olyimide), cyanide (Cyanate such as (8), glass fiber, bis-succinic acid oxime & imine /Bismaleimide Triazine (BT) or mixed epoxy resin and glass fiber FR5 and other materials; the thin metal layer 2: generally based on copper (CU) with better conductivity, as a signal Passing the call, 'the material is the same as the day's guard, the present example uses a resin laminated copper foil (Resin Coated C〇Pper, RCC) as an example. - as shown in Figure 2C 'Next, the carrier plate opening 200 The semiconductor wafer 22' is received in the semiconductor wafer 22', and the first dielectric layer is filled in the first trench 2'1, for example, by a bonding process, and is filled in the opening to fix the semiconductor wafer 22 to the semiconductor wafer 22 The semiconductor wafer 22 has an active surface and an inactive surface 22b' opposite to the active surface 22a. The active surface is formed with a plurality of electrodes φ 221 ′ and the non-active surface is formed. - an adhesive layer (2) such as a release liner for semiconductor wafer 22 to be fixed to the opening The semiconductor wafer u is disposed on the first dielectric layer 210 by an adhesive layer 221 on the non-active surface 22b, and is received in the opening 2 (10) of the carrier board 2''. As shown in FIG. 2D Forming a second trench 2〇2 at a position corresponding to the first trench in the second surface 该 of the carrier board 2, and connecting the second trench 202 to the first trench 201 to form a through surface The groove 203 of the carrier plate is used for subsequent cutting operation by the cutting tool, wherein the first groove 201 and the second groove 202 are formed; and the process can be formed by using the method of 18886 14 1290762 The first-trench training and the 202th etching process are conventional techniques, and will not be described here. Therefore, the present invention is mainly used in a semiconductor crystal/packaging process, that is, in advance in the carrier board 20 Open; Cheng can 徂% @ 最小分*, cover drawing., Λ (, after,,, cutting operation and width lifting row can effectively use the space of the carrier board, = non = rate ' at the same time The trench 203 is formed by a general tool: Saw can be formed into a single semiconductor wafer. The carrier plate structure, the smaller groove 2G3 occupies the smaller use of the bearing ^The cutting with the cutter must occupy the carrier plate: the use of the second =, the invention can thus enhance the carrier plate As shown in FIG. 2E, a second dielectric layer and a wiring layer μ are sequentially formed on the second surface bird and the conductor wafer 22 of the carrier board 2, and the circuit layer 24 is electrically connected to The active surface 22a of the semiconductor wafer 22 has: a pad 221 and the second dielectric layer 23 is filled in the second trench, and a plurality of openings are formed in the first dielectric layer 23 The electrode pad 221 of the active surface 22a of the semiconductor wafer 22 is exposed. The second dielectric layer is formed on the carrier plate and the half (four) wafers by press bonding and filled in the second trench. The second dielectric layer 23 may be an Epoxy resin, a p〇lyimide, a cyanoester 3 Ester, a glass fiber, a bis-succinimide/triazo trap ( Bi_leimide Triazine, BT) or mixed epoxy resin and glass fiber FR5 and other materials. The circuit layer 24 is a patterned metal layer (for example, a metal copper layer), and the circuit layer 24 is transmitted through the conductive structure 24 (for example, a conductive blind hole) formed in the opening 230 of the second dielectric layer. ^ 18886 15 1290762 to the electrode pad 221 of the semiconductor chip. In the process to form the circuit layer 24, a metal layer 2i2 of the same material as the line 3524 (for example, metal steel 2, the present invention is used in the opposite side of the carrier plate - and metal 妒Κ Μ Handi one surface At the same time: the winding process, so that the line process can be carried out at the same time:: 俾:: The second surface forms a metal for heat dissipation of the semiconductor wafer, the difference in the number of effects == the heat sink of the product, to avoid In the knowing technology, the development of the scattered material-like wafer-buried county structure is limited. After the 2F map is not, the second dielectric layer 23 and the Heng line can be re-applied to form the required electricity. The line build-up structure 25 is electrically connected to the line. The line build-up structure 25 includes a dielectric layer 250, a wiring layer 252 stacked on the dielectric "250, and a dielectric layer 2 passing through the dielectric layer 2. The conductor layer 252 is electrically connected to the conductive structure 252a of the circuit layer 24 under the dielectric layer. In addition, in the present invention, the circuit layer 252 may be formed on the metal layer 212 while forming the circuit layer 252 according to actual design requirements. Multiple plating to stack multiple layers of gold ^^ The outer surface of the layer 21Q is formed with a metal plate 213 having a plurality of metal structures and having a predetermined thickness. However, if the metal plate 213 has reached a predetermined thickness in the prior electric ore coating, the metal plate may be covered with a resist layer to prevent The metal plate 213 can be used as a heat sink for heat dissipation of the semiconductor wafer 16 18886 1290762 22. As shown in the figure 2 G, the sound can be formed outside the line build-up structure 25 For example, the outer surface of the insulation layer of the solder resist layer is the outermost #, and the green layer is 6 to protect the line of the outer layer of the line build-up structure', and the insulating protective layer 2 is the outermost layer of the line build-up structure 25 After the 4 holes 261 are in the way, the insulating protective layer is exposed, and the conductive element is connected to the upper surface (not shown in the figure; the electrical connection of the hole 261 is 251 9?, . , no). The semiconductor crystal moon 22 is electrically connected to the outside. Then, the V body day piece 213 ϊ , the brother 1 , the 1 electric layer 210 and the metal plate τ correspond to the opening 2 〇 λ of the carrier plate 20 to form a position φ „ ^ position The adhesive layer 2210 of the ZD clothing surface is etched or lasered. The adhesive layer 221 is removed as shown in the figure 2H. After re ^ grooves may by 2〇1 second trench 202 is formed and cut I = | H industry at first, to form a semiconductor wafer having at least one

咳導敎^ 所示，於該開口 27中形成一導熱膠28，且 ^ 28係接著於該半導體晶片22之非主動面 金屬板加及該導熱膠28上形成—散熱板29。 椹^發明中’亦揭示有-種嵌埋半導體晶片之承載板結 構，如下所示。 如第2C圖所示’一種嵌埋半導體晶片之承載板結構， 相紫 承載板20，係具有第一表面20a及與第一表面 目，^第二表面2〇b，該承載板中形成有至少一貫穿其第 一及第二表面2〇a，2〇b之開口 200,且該承載板第一表面 18886 17 1290762 2^)a七成有至少一圍繞該些開口 2〇〇且未貫穿該承載板之 弟一溝槽201 ;至少一半導體晶片22，係容設於該承載板 之開口 200中’該半導體晶片22係具有一主動面22a及與 主動面22a相對之非主動面22b，且該半導體晶片之主動 面22^具有複數電極墊221;以及一第一介電層210,係形 成於σ亥承載板之第一表面20a，且填充於該第一溝槽201 中及該^載板之開口 200中以固定該半導體晶片22。 ^勺如弗2D圖所示，一種嵌埋半導體晶片之承載板結構， 復匕括·金屬板213，係形成於該第一介電層2丨〇外表 二第—溝槽202，係形成於該承載板第二表面20b 忐:亥第，冓槽201的位置；以及一第二介電層23,係形 =於該承載板之第二表面勘，第二表面咖上之第二溝 ιΓ?及該些半導體晶片22之主動面22a。如前所述，談 至屬板213係可為一多層結構。 ^第2E圖所示，—㈣埋半導體晶片之承載板結構， 设包括一線路層24，係形成於該第二 線路屄24盐丄 |电層23上，且该 電性、;技 形成於該第二介電層23中之導電結構24。 連接至該半導體晶片之電極墊221。 復包圖所示’一種後埋半導體晶片之承載板結構， 層結構25，係形成於該第二介電層^及 Si 且該線路增層結構25係電性連接至該線 復包：第二圖所示，一種喪埋半導體晶片之承載板結構， 是匕括緣保護層26’係形成於該線路增層結構2”卜 18886 18 1290762 表面’且该金屬板213及第一介電層210具有一開口 27 以露出该半導體晶片22非主動面之黏著層2210。 如第2H圖所示，一種嵌埋半導體晶片之承載板結構， 其中，該金屬板及第一介電層210具有一開口 27以露出該 半導體晶片22之非主動面22b。 如第21圖所示，一種嵌埋半導體晶片之承載板結構， 復包括一導熱膠28，係形成於該金屬板213表面及半導體 晶片22非主動面⑽；α及一散熱板29，係形成於該導熱 膠28表面。 錄上所述 不贫明之嵌埋半導體日日门〈枣戰板結構及 -製法n係於—承載板巾形成至少—貫穿之開口及形 成圍繞該些開口之笫一、、盖播，廿收斗7 & 一μ一人 之弟溝槽，亚將该承載板第一表面形成 乐；丨電層，之後於該些開口中分別接置一半導體晶片 ==電層填充於該開口與該半導體晶片之間之間 之第'1 體晶片於該開口中，再相對於該承載板 弟一表面上相對於第一溝槽之位置 於該承载板第-矣AΑ 风弟一溝槽，復可 y 妾之後可藉由該第一、第二、、盖描 行切割作業以形成至一曰弟—溝扣的位置進 相較於習知枯卞/、早一日日片之承載板結構。 ,, 、 技術’本發明之嵌埋半導髀曰μ 、 ^構及其製法，主要係於製程過 开^之承載板 切割作業所需之寬度較小之溝槽（第—Ρ:士可供後續進行 以—般刀具進行切 弟一溝槽），再 小之溝槽伯據該承完成切割作業，該寬度較 载板較小之使用空間，而無須使用銳刀 19 18886 1290762 (Router)切剎須佔據該承載板較大之使用空 而可提升承载板之排版率。 本發明因 多數由承載板上下表面分別形成線路及具 半導二屬板，以完成容置於該承载板開口中之 ^體阳片向外之電性連接，且可藉由該金 體晶片之散熱用。 邛4+導 牛二:ί發明中’可於該金屬板上接置一散熱板以進- 二ΪΓ文果，從而可透過該金屬板及散熱板之组合將 + ¥體日a片運作時產生的熱量快速、有效的傳遞至 式封裝結構之功能，而使此類型之:裝 、、σ冓付以進一步發展，藉以避免習知技術中半導體晶片埋 入封裝基板，無法有效逸散半導體晶片運作時之熱量 成的缺失。 ° ^上述實施例僅為例示性說明本發明之原理及其功 放而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範嘴下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1圖係為習知晶片埋入封裝基板結構之剖面示意 圖；以及 第2Α至2 I圖係為嵌埋半導體晶片之承載板結構及 其製法流程圖。 【主要元件符號說明】 18886 20 121 、 250 122 、 24 、 252 123 124 ^ 26 125 1290762 10 ^ 20 27 100a > 200 100 11、22 110 、 221 11a、22a lib 、 22b 0 12 、 25 120 φ 13 > 2210 201 202 203 20a 20b 210 211 212 承載板 開口 承載板開口 表面 半導體晶片 電極墊 主動面 非主動面 線路增層結構 導電盲孔 介電層 線路層 電性連接端 絕緣保護層 焊球 黏著材料 第一溝槽 第二溝槽 溝槽 第一表面 第二表面 第一介電層 金屬薄層 金屬層 21 18886 1290762 213 金屬板 230 ^ 261 開孔 23 第二介電層 240 ^ 252a 導電結構 251 電性連接墊 261 絕緣保護層開孔 28 導熱膠 29 散熱板 22 18886A heat conductive adhesive 28 is formed in the opening 27, and a heat dissipation plate 29 is formed on the non-active surface metal plate of the semiconductor wafer 22 and the thermal conductive paste 28. The invention also discloses a carrier structure for embedding a semiconductor wafer as shown below. As shown in FIG. 2C, a carrier plate structure for embedding a semiconductor wafer, the phase violet carrier plate 20 has a first surface 20a and a first surface, a second surface 2b, formed in the carrier plate At least one opening 200 extending through the first and second surfaces 2〇a, 2〇b, and the first surface of the carrier plate 18886 17 1290762 2^)a has at least one surrounding the openings 2 and does not penetrate The carrier chip is a trench 201; at least one semiconductor wafer 22 is received in the opening 200 of the carrier plate. The semiconductor wafer 22 has an active surface 22a and an inactive surface 22b opposite to the active surface 22a. The active surface 22 of the semiconductor wafer has a plurality of electrode pads 221; and a first dielectric layer 210 is formed on the first surface 20a of the σH carrier plate and filled in the first trench 201 and the ^ The semiconductor wafer 22 is fixed in the opening 200 of the carrier. As shown in FIG. 2D, a carrier plate structure in which a semiconductor wafer is embedded, and a metal plate 213 is formed on the outer surface of the first dielectric layer 2, and is formed in The second surface 20b of the carrier plate is: 亥:, the position of the groove 201; and a second dielectric layer 23, the shape of the second surface of the carrier plate, and the second groove of the second surface And the active surface 22a of the semiconductor wafers 22. As mentioned above, the sub-plate 213 can be a multi-layer structure. ^ Figure 2E, - (d) the carrier plate structure of the buried semiconductor wafer, comprising a circuit layer 24 formed on the second circuit 屄 24 salt 丄 | electrical layer 23, and the electrical, The conductive structure 24 in the second dielectric layer 23. Connected to the electrode pad 221 of the semiconductor wafer. As shown in the multi-package diagram, a carrier structure for a buried semiconductor wafer, a layer structure 25 is formed on the second dielectric layer and Si, and the line build-up structure 25 is electrically connected to the line package: As shown in FIG. 2, a carrier board structure for burying a semiconductor wafer is formed on the surface of the line build-up structure 2"18886 18 1290762" and the metal plate 213 and the first dielectric layer The 210 has an opening 27 to expose the adhesive layer 2210 of the inactive surface of the semiconductor wafer 22. As shown in FIG. 2H, a carrier substrate structure embedding a semiconductor wafer, wherein the metal plate and the first dielectric layer 210 have a The opening 27 is formed to expose the inactive surface 22b of the semiconductor wafer 22. As shown in Fig. 21, a carrier substrate structure embedding a semiconductor wafer further includes a thermal conductive paste 28 formed on the surface of the metal plate 213 and the semiconductor wafer 22 The non-active surface (10); α and a heat dissipation plate 29 are formed on the surface of the thermal conductive adhesive 28. The undead embedded semiconductor is recorded on the surface of the Japanese-style door and the method of manufacturing the slab. At least - through the opening and Forming a circle around the openings, covering the cover, picking up the bucket 7 & a μ-person of the younger brother, the first surface of the carrier plate is formed into a music layer; the electrical layer is then connected in the openings Forming a semiconductor wafer == an electrical layer is filled in the opening between the opening and the semiconductor wafer, and then the surface of the carrier is opposite to the first trench The carrier plate - 矣AΑ Α 一 沟槽 , , , , 复 复 复 复 复 复 复 复 复 复 复 复 复 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可The structure of the load-bearing plate of the Japanese film, the technology of the invention, the embedded semi-conducting 髀曰μ, structure and its preparation method are mainly used in the cutting operation of the carrier plate The groove with a smaller width is required (the first one can be used for the subsequent cutting with a general tool), and the smaller groove is used to complete the cutting operation, which is smaller than the carrier. Use space without the use of sharp knives 19 18886 1290762 (Router) cutting brakes must occupy the larger size of the carrier Empty and can improve the layout rate of the carrier board. The invention is formed by a plurality of lines on the lower surface of the carrier board and a semi-conducting two-plate, so as to complete the electrical properties of the body-positive piece accommodated in the opening of the carrier board. Connected, and can be used for heat dissipation of the gold body wafer. 邛4+ guide cow 2: 发明In the invention, a heat sink can be attached to the metal plate to enter the second slab, so that the metal plate can be penetrated The combination of the heat sink and the heat generated by the operation of the body is quickly and efficiently transferred to the function of the package structure, so that the type: the installation, the σ 冓 payment for further development, to avoid the conventional technology The semiconductor wafer is buried in the package substrate, and the loss of heat during operation of the semiconductor wafer cannot be effectively dissipated. The above-described embodiments are merely illustrative of the principles of the invention and its powers and are not intended to limit the invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a structure in which a conventional wafer is embedded in a package substrate; and Figs. 2 to 2I are a carrier plate structure in which a semiconductor wafer is embedded and a method of manufacturing the same. [Description of main component symbols] 18886 20 121 , 250 122 , 24 , 252 123 124 ^ 26 125 1290762 10 ^ 20 27 100a > 200 100 11, 22 110 , 221 11a , 22a lib , 22b 0 12 , 25 120 φ 13 > 2210 201 202 203 20a 20b 210 211 212 carrier plate open carrier plate opening surface semiconductor wafer electrode pad active surface inactive surface line build-up structure conductive blind hole dielectric layer circuit layer electrical connection end insulation protective layer solder ball adhesive material First trench second trench trench first surface second surface first dielectric layer metal thin metal layer 21 18886 1290762 213 metal plate 230 ^ 261 opening 23 second dielectric layer 240 ^ 252a conductive structure 251 Connection pad 261 Insulation protective layer opening 28 Thermal paste 29 Heat sink 22 18886

Claims (1)

1290762' 十、申請專利範圍： 1. -種嵌埋半導體晶片之承载板結構之製法，係包括： 提供-具第-表面及相對於第一表面之第二表面 之承載板，於該承載板中形成至少一貫穿該第一及第 二表面之開口，且於該承載板第一表面形成至少一圍 繞該些開口且未貫穿該承載板之第一溝槽； 於該承載板之第-表面形成一第一^電層，以藉由 該第一介電層封住該第一溝槽及該些開口； 於該些開口中分別容置一半導體晶片，且使該第一 介電層填充於該第-溝槽中及該半導體晶片之開口 中，以將該半導體晶片固定在該開口中；其冲，該半 導體晶片係具有-主動面及相對之非主動面；以及 於該承載第二表面對應該第一溝槽位置形成第二 溝槽，且使該第二溝槽與該第一溝槽相速通，藉以形 成貫穿該承载板之溝槽。 ⑩2.如申請專利範圍第j項之篏埋半導體晶片之承載板結 構之製法，其中，該半導體晶片之非主動面具有一黏 耆層。 3. ^請專利範圍第2項之㈣半導體晶之承載板結 構之製法，復包括： /於忒承载板之第二表面及該些半導體晶片之主動 面形成一第二介電層，並使該第二介電層填充於該第 溝才曰中，且該半導體晶片之主動面具有複數電極 墊；以及 18886 23 1290762 於该弟二介電層上形成—線 形成於該第二介電層中之導 :I錢路層猎由 體晶片之電極墊。 ’、、、。構電性連接至該半導 4. 如申請專利範圍第3項之嵌埋半導 構之製法，復包括於該第二介電層：=之承載板結 —線路增層結構，且該 θ Μ、、、路層上形成 線路層。 Μ”、曰$結構係電性連接至該 5·如申請專利範圍第4項之嵌 構之_、本十^ 、 卞等體日日片之承載板結 保護^设該線路增層結構外表形成一絕緣 6· 專利範圍第4項之嵌埋半導體晶片之承载板姓 層，以於形成線路層時復於今今屬續恩主 孟屬厚 另m、… 屬缚層表面同步形成 7 , ^，以形成具有複數金屬層所構成之金屬板。 ’如申請專利蘇（f|镇β xg七山 、’ 反 椹夕制 敢埋半導體晶片之承載板結 穿之：法’ ΐ包括於該第一介電層及金屬板中形成貫 8. = = f出該半導體晶片非主動面之黏著層。 構之第7項之嵌埋半導體晶片之承載板結 9 衣法，復包括移除該黏著層。 =睛專利範圍第8項之嵌埋半導體晶片之承載板結 製法’復包括於貫穿該第—介電層及金屬板之^ 中形成一導熱膠。 10·=申請專利範圍第9項之喪埋半導體晶片之承載板結 之製法，復包括該金屬板及該導熱膠上形成一散熱 18886 24 1290762 板。 11. 如申請專利範圍第8或1(]項之㈣半導體晶片之 ，結構之製法，復包括藉由該承載板中形成的第―及取 第二溝槽所構成之溝槽進行切割作業。 12. 如申請專利範圍第2項之後埋半導體晶片之承载板結 構之製法，其中，該黏著層係為一形成於該半導體曰^ 片非主動面之離型膜。 曰 1υ· —種嵌埋半導體晶片之承載板結構，係包括： -一承載板’係具有第一表面及與第一表面相對之第 二表面，該承载板中形成有至少—貫穿其第—及第二 表面之開口且该承載板第一表面形成有至少一圍銬 口亥些開口且未貫穿該承載板之第一溝槽； /至少—半導體晶片，係容設於該承載板之開口中， 该半導體晶片係具有—主動面及與主動面相對之非主 動面’且δ亥半導體晶片之主動面具有複數電極塾；以 一第一介電層，係形成於該承载板之第一表面，且 填充於該第-溝槽中及該承載板之開口 導體晶片。 U疋』牛 14·如申請專利範圍第 構，復包括·· 頁之甘人埋曰曰片之承載板結 一金屬板，係形成於該第一介電層外表面； 至少一第二溝槽，係形成於該承載板第二表面對岸 該第-溝槽的位置； 衣㈣應 18886 25 1290762 載板之第二表面，第 晶片之主動面；以 一第二介電層，係形成於該承 二表面上之第二溝槽及該些半導體 及 1且該線路層 f生連接至該 一線路層，係形成於該第二介電層上 藉由形成於該第二介電層中之導電結構電 半導體晶片之電極墊。 15. 16. 17. 18. :申圍第14項之後埋半導體晶片之承細 m板及第一介電層具有一開口以邏出該半導 體日日片之非主動面。 r請專利範圍第14項u埋半導體μ之承載板矣 構，设包括一線路增層結構，係形成於該第二介電声 2線路層上，且該線路增層結構係電轉接至該線 路層。 如申請專利範圍第16項之嵌埋半導體晶片之承載板 復包括-絕緣保護層’係形成於該線路增層結相 外表面。 :申5月專利範圍第15項之嵌埋半導體晶片之承載板結 構，復包括：-導熱朦，係形成於該金屬板表面及半 導體晶片非主動面；以及-散熱板’係形成於該導執 如申請專利範圍第14項之嵌埋半導體晶片之承載板結 構其中，该金屬板係為一多層結構。 18886 26 19.1290762' X. Patent Application Range: 1. A method of fabricating a carrier plate structure for embedding a semiconductor wafer, comprising: providing a carrier plate having a first surface and a second surface opposite to the first surface, the carrier plate Forming at least one opening extending through the first and second surfaces, and forming at least one first groove surrounding the opening and not penetrating the carrier plate on the first surface of the carrier plate; on the first surface of the carrier plate Forming a first electrical layer to seal the first trench and the openings by the first dielectric layer; respectively accommodating a semiconductor wafer in the openings, and filling the first dielectric layer In the first trench and in the opening of the semiconductor wafer, the semiconductor wafer is fixed in the opening; the semiconductor wafer has an active surface and a relatively inactive surface; and The surface corresponds to the first trench location to form a second trench, and the second trench is fast-passed to the first trench to form a trench extending through the carrier. 102. A method of fabricating a carrier wafer structure of a buried semiconductor wafer according to clause j of the patent application, wherein the non-active mask of the semiconductor wafer has an adhesive layer. 3. The method for manufacturing the semiconductor wafer carrier plate structure of the second aspect of the patent scope includes: forming a second dielectric layer on the second surface of the carrier substrate and the active surface of the semiconductor wafers, and The second dielectric layer is filled in the first trench, and the active surface of the semiconductor wafer has a plurality of electrode pads; and 18886 23 1290762 is formed on the second dielectric layer to form a line formed on the second dielectric layer The guide in the middle: I money road layer to hunt the electrode pad of the body wafer. ',,,. Electrically connected to the semiconducting 4. The method of embedding a semi-conductor according to claim 3 of the patent application is further included in the second dielectric layer: = carrier layer-line build-up structure, and the θ A circuit layer is formed on the Μ, ,, and road layers. Μ", 曰$ structure is electrically connected to the 5th. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Forming an insulation 6· The fourth layer of the embedded semiconductor wafer of the patent scope is the surname layer of the buried semiconductor wafer, so that when the formation of the circuit layer is repeated, the genus of the genus is thicker, and the surface of the occlusion layer is synchronously formed. To form a metal plate composed of a plurality of metal layers. 'If the patent application Su (f|Zheng β xg Qishan, 'anti-椹 制 敢 敢 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体A dielectric layer and a metal plate are formed to form an adhesive layer of the inactive surface of the semiconductor wafer. The seventh embodiment of the semiconductor wafer embedded carrier layer 9 is coated, including removing the adhesive The layered method of the embedded semiconductor wafer embedded in the eighth aspect of the patent scope includes a heat conductive adhesive formed through the first dielectric layer and the metal plate. 10·= Patent application scope 9 a method for fabricating a carrier chip of a semiconductor wafer, including the Forming a heat sink 18886 24 1290762 board on the heat sink and the heat conductive adhesive. 11. As claimed in claim 4 or claim 1 (4) of the semiconductor wafer, the method of fabricating the structure includes the first layer formed by the carrier board And taking a trench formed by the second trench to perform a cutting operation. 12. The method for fabricating a carrier chip structure of a semiconductor wafer after the second application of the patent application, wherein the adhesive layer is formed on the semiconductor chip The release sheet of the inactive surface. The carrier board structure for embedding the semiconductor wafer comprises: - a carrier board having a first surface and a second surface opposite to the first surface, the carrier board Forming at least the opening through the first and second surfaces thereof, and the first surface of the carrier plate is formed with at least one opening and not opening through the first groove of the carrier; / at least - a semiconductor wafer The semiconductor wafer has an active surface and an inactive surface opposite to the active surface, and the active surface of the semiconductor wafer has a plurality of electrodes; a first dielectric Formed on the first surface of the carrier plate and filled in the first trench and the open conductor wafer of the carrier plate. U疋』牛14·If the patent application scope is constructed, the a metal plate is formed on the outer surface of the first dielectric layer; at least one second groove is formed on the first groove of the second surface of the carrier; The second surface of the 18886 25 1290762 carrier board, the active surface of the first wafer, and a second dielectric layer formed by the second trench formed on the surface of the carrier and the semiconductor and the circuit layer The ferrite is connected to the one of the circuit layers, and is formed on the second dielectric layer by an electrode pad of the electrically conductive structured electric semiconductor wafer formed in the second dielectric layer. 15. 16. 17. 18. The thinned m-plate and the first dielectric layer of the buried semiconductor wafer after item 14 of the application have an opening to mark the inactive surface of the semiconductor day. rPlease refer to the 14th item of the patent range, the semiconductor board of the semiconductor μ, which comprises a line build-up structure formed on the second dielectric acoustic 2 circuit layer, and the line build-up structure is electrically transferred to The circuit layer. A carrier board embedding a semiconductor wafer as in claim 16 of the patent application includes an insulating layer formed on the outer surface of the wiring junction layer. The carrier board structure of the embedded semiconductor wafer of claim 15 of the patent scope of the fifth aspect of the invention includes: - a thermal conductive layer formed on the surface of the metal plate and an inactive surface of the semiconductor wafer; and - a heat dissipation plate is formed on the guide A carrier board structure for embedding a semiconductor wafer according to claim 14 of the patent application, wherein the metal sheet is a multilayer structure. 18886 26 19.
TW095100836A 2006-01-10 2006-01-10 Semiconductor chip embedded in carrier board and method for fabricating the same TWI290762B (en)

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TWI392073B (en) * 2008-06-17 2013-04-01 Unimicron Technology Corp Fabrication method of package substrate having semiconductor component embedded therein
TWI415234B (en) * 2009-05-25 2013-11-11 Nan Ya Printed Circuit Board Packing substrate with embedded chip
TWI659509B (en) * 2017-12-19 2019-05-11 英屬開曼群島商鳳凰先驅股份有限公司 Electronic package and method of manufacture

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Publication number Priority date Publication date Assignee Title
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