TWI355060B - Package substrate having semiconductor component e - Google Patents

Description

1355060 IX. Invention Description: *[The field of technology to which the invention belongs] Ben! X month relates to a substrate structure, especially a substrate structure of an inlay wafer. [Prior Art] Since electronic products are increasingly thin and short, the package substrate for carrying semiconductor wafers or % sub-components needs to be reduced, and the evolution of semiconductor technology has developed different package types, such as balls. Grid: grid array (BGA), an advanced semiconductor sealing technology that can accommodate more rounds of j-output connections (I/O c〇nnecti()n) on a package substrate of the same unit area to meet high-level accumulation. Required for semiconductor wafers. The traditional semiconductor package structure of the ball grid array type is attached to the package substrate, and then wire bonding or wire-bonding (FliPchiP) of the semiconductor wafer = (4) Mounting the substrate 'After the back of the package substrate, a solder ball is implanted to perform electricity, and the pro-products can achieve a high number of feet. 'When using at a higher frequency or higher = Xiao' because the wire connection path is too long The electrical characteristics can not be raised 2 and the performance is limited. In addition, because the traditional packaging requires multiple connections, the manufacturing cost is relatively increased. In order to effectively improve the electrical quality, it should meet the requirements of the next generation products: Researches have been carried out to embed semiconductor wafers in the agricultural substrate to directly charge electricity, and to reduce the signal loss and signal' to improve the ability to operate at high speed. 110591 5 1355060 .. , • See first The figure is a cross-sectional view of a conventional semiconductor chip embedded in a package substrate. The substrate structure embedded with a semiconductor wafer 10 includes at least a first substrate 1a and a second substrate 10b. a semiconductor BB sheet 11 , wherein the first substrate 1A has at least one first substrate opening 100 penetrating the substrate, and the first substrate 1A is used as a core plate to be bonded to the second substrate 10b And affixing a semiconductor wafer n ′ in the first substrate opening 1 并 and fixing the semiconductor wafer 11 in the first substrate opening 1 结合 by the bonding material iiq, the semiconductor wafer φ 11 having An active surface 11a and a non-active = lib opposite the active surface 11a, and the active surface Ua has a plurality of electrode pads m, and a line is formed on the active surface Ua of the first substrate 10a and the semiconductor wafer a layer structure 12 for embedding the semiconductor wafer in the first and second substrates 10a'10b, the line build-up structure 12 comprising at least one dielectric layer 120 stacked on the dielectric layer 12 a circuit layer ΐ2ι, and a plurality of conductive holes 122 formed in the dielectric layer 120 and electrically connected to the circuit layer i2i, and the conductive blind vias 22 are electrically connected to the electrodes of the semiconductor wafer ♦ 11 A plurality of electrical connection pads 123 are disposed on the line build-up structure 12, The electrical connection (four) 123 is electrically connected to the circuit layer 121; and the anti-solder 3513 is formed on the circuit build-up structure 12, and the anti-tank layer 13 has a plurality of openings 13 〇 to correspondingly expose the electrical connection pad 123. The semiconductor wafer u is embedded in the first substrate opening 1〇〇' to solve the various defects caused by the long wire connection path of the prior art; however, since the semiconductor wafer u is disposed on the first substrate i 〇a Π0591 6 1355060 '中: and 5 hai second substrate 1 () b sealed the first substrate opening 100 - Shanghai, the heat generated by the wafer 11 is not easy to dissipate;; μ, ΓΓ片' The day is also enhanced, so that the heat generated is also effective to effectively dissipate heat, which will seriously affect the properties of the semiconductor wafer. The first-inverse-substrate of the substrate structure in which the semiconductor crystal moon is embedded has a considerable thickness, and is also thin and light. The short trend is that the substrate structure of the semiconductor wafer is embedded on one side of the core board to form a circuit layer or a build-up circuit layer. The symmetry of the substrate structure is good, possibly due to the core plate "electric layer and circuit layer, etc. Material thermal expansion coefficient difference Different, resulting in plate bending and affecting product reliability. /,. How to propose a semiconductor wafer embedded structure to overcome the problem of low heat dissipation and plate bending and effectively reduce the thickness of the structure has become a problem to be solved in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned conventional technical problems, it is an object of the present invention to provide eight substrate structures in which a semiconductor wafer is buried, which is an inactive surface of a bare semiconductor wafer to achieve a heat dissipation effect. Another object of the present invention is to provide a substrate structure in which a semiconductor wafer is embedded in a reduced thickness. In order to achieve the above object, the present invention provides a substrate structure embedded with an I-conductor wafer, comprising: a semiconductor wafer having a driving surface: a corresponding inactive surface, and the active surface has a plurality of electrode pads; The electric layer is formed by the first dielectric layer and the second dielectric laminate to fix the semiconductor wafer, and has a corresponding first surface and a second surface, and has a dielectric 0-layer opening 110591 7 to expose the The semiconductor wafer - the first surface of the dielectric layer, and the right moving surface 'dipole layer' is formed in the blind via, and has a first conductive layer disposed in the dielectric layer, the system: Connected to the second line. The surface of the substrate is electrically connected to the first circuit layer, and the first circuit layer and the second via hole are connected to each other by electrical or non-conducting (four) conductive vias. The conductive via is a solid conductor = the space inside the electrical via hole - the screen - the other dielectric layer and the first "electric layer" are thermosetting materials or photosensitive materials. Description: Γ: the first circuit layer is composed of a first metal layer, a conductive connection:::, the first circuit layer includes a plurality of the dielectric solder resist layers, which are i-F1 is disposed on the first circuit layer, and the first solder resist layer has a plurality of first-opening holes corresponding to exposing the first electrical surface to provide a first table on the first electrical connection pad. A first conductive element is disposed on the first surface metal layer, and the second circuit layer is composed of a second metal layer and a conductive acoustic layer, and the second circuit layer includes a complex (four) two (four) The connection substrate structure further includes a second solder resist layer disposed on the surface of the second circuit layer, and the second solder resist::: A portion of the surface of the second electrical connection pad should be exposed, and the first layer of the second surface metal layer has a first conductive member, and the second anti-corrosion layer has a corresponding Electrical layer 110591 8 1355060 · The first opening of the opening to expose the: .... 3 according to the above structure, including the moving surface. In 1 into + a ten ^ 栝 have the first line 増 layer structure, tie . 钂 钂 丨 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The second circuit layer and the plural are disposed in the third dielectric: the hole, the second conductive blind hole is electrically connected to the first _f-guide house%-4S, ΛΧ4Λ*苐-circuit layer' The surface of the layered structure of the younger and the spring road has a third-stage build-up structure with a first-pre-solder layer, and the j-connected ^'in the young-line:: to correspond to the surface of the three-electrical connection pad On the second electrical connection pad of the present generation, the first conductive element is provided on the layer, and the first conductive element is layered on the layer. The structure of the metal substrate of the Leyi surface includes the first layer of the electric layer. The surface and the second upper spring road two-layer junction: 'the fourth dielectric layer on the dielectric layer including at least the fourth dielectric layer, the second two-layer build-up structure, and the dielectric layer The fourth dielectric® Φ 银 silver three-conductivity blind via is electrically connected to the fourth pen blind hole 'the fourth line of the surface of the first build-up structure and:: the circuit layer, and the second line % - ® s There are a plurality of fourth electrical connection pads, the first ▲ road build-up structure has a corresponding dielectric port 'to expose the non-pores of the material conductor W, and the second solder resist layer has a plurality of second openings. The fourth electrical connection is provided on the surface of the P-blade. The surface of the P-knife is provided with a metal layer on the fourth electrode, the second surface metal layer is re-opened and the second solder-proof layer has a pair. The first opening of the dielectric layer should be exposed to expose the inactive surface of the semiconductor wafer. Π0591 9

DDDUOU 此 ' ' ' ' ' ' ' ' 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The non-active surface is semi-conducting, and the heat generated by the oblique-conductor wafer is exposed, and the heat-dissipating effect is further obtained. The substrate embedded with the semiconductor wafer, . The structure is formed on each side of the semiconductor wafer with a circuit layer, the symmetry of the slab structure is good, the board material can be reduced, and the substrate structure is pressed by the dielectric material to form a 'compared with the conventional structure, The core sheet has a low overall thickness. [Embodiment] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings, so that those skilled in the art can easily understand the technical features and the effects of the present invention. 2A to 2M are schematic cross-sectional views showing a substrate structure in which a semiconductor wafer is embedded in the present invention. As shown in FIG. 2A, first, a first dielectric layer 21 and a second dielectric layer 21" are provided, wherein a second dielectric layer opening 210 is formed in the second dielectric layer 21" As shown in FIG. 2B, in the second dielectric layer opening 21, a semiconductor wafer 22' is disposed in the semiconductor wafer 22, and the active surface 22a and the corresponding active surface 22b' thereof are active. The surface 22a has a plurality of electrodes 221, as shown in FIGS. 2C and 2C', and a first metal layer 23a is disposed on the outer side of the first dielectric layer 21, and the second dielectric layer 21 is disposed on the outer side. And the 110591 10 1355060 • the inactive surface 22b of the semiconductor wafer 22 is provided with a second metal layer 23b, wherein the first and second metal layers 23a, 23b are copper foil, as shown in FIG. 2c; In combination with the steps shown in FIGS. 2A to 2C, the first metal layer 23 and the first dielectric layer 21 are laminated directly on the active surface 22a of the semiconductor wafer 22, and the backing copper foil (Resin c〇ated) C〇pper

Foil) and the non-active surface 2 of the semiconductor wafer 22 is further laminated with a second backing copper foil having a second metal layer 23b and a second dielectric layer 21", wherein the second dielectric layer 21 The second dielectric layer opening 210"' has a through structure to form the same structure, as shown in FIG. 2C. As shown in FIG. 2D, the first metal layer and the first dielectric layer are bonded. 21, the second dielectric layer 21, and the second metal layer are torn, the first dielectric layer 21' and the second dielectric layer 21 are combined to form a dielectric layer 2ι to the semiconductor H 22 ^ The dielectric layer 21 is defined as a first surface 21 on the first metal dome 3 side and a corresponding second surface 21 b on the second metal layer 2 side. - metal: the first surface 21a of the upper dielectric layer 21 is 221, m is formed with a dielectric layer opening 211a on the electrode pad of the semiconductor wafer 22, and the layer 23a and the dielectric layer 21 are printed by human beings.夕贝穿.Hai Di ^ as shown in Figure 2F, followed by ^ = layer of coffee through hole Μ. (sputter i ng) or chemical deposition of electroless plating 7 accumulation of the de-plating layer 23a, the second metal layer 23b, pass Hole 2l"lh 1 'to The "first gold" and the electrode pad 221 are formed in a wide shape, and the dielectric layer is opened. The electroplating full material 后4' is described later. The conductive layer 24 is the main current conduction path for the metal material. 110591 11 Meng orgt; a plurality of layers of metal; a layer of tantalum, such as selected from the group consisting of copper, tin, zinc, chromium, titanium, and copper-chromium alloys; and the conductive layer 24 of the stupid m2 is an amine or an organic polymer The same conductive polymer material. The second =%, as shown in the figure, formed on the surface of the conductive layer 24 -

The second and second tiling layers 23c' are formed with conductive vias W in the via holes, wherein the third metal layer 23 is formed. The materials are such as lead, tribute, silver, copper, jin, name, / 〗 〖 耸 ^, '锑, zinc, nickel, bismuth, magnesium, indium, bismuth and the basin of the metal Φ__..., However, according to the experience of the actual operation, since the copper is made into a non-plated material and the cost is low, the 5th second metal layer 23c is free from copper, but it is not limited thereto. After that, a filling, a conductive or non-conductive filling material 260 (such as copper or epoxy resin) is filled to fill the space of the conductive via 26, or the thunder is solid in the through hole 211b. Thunder donation! 9β, , Μ,

_ 6 ' is shown in Fig. 2G'; the structure shown in Fig. 2G is used for explanation. As shown in FIG. 2H, a first resist layer 27 is formed on the surface of the third metal layer 23c by printing, such as red coating or lamination, and the first resist layer is a dry film or a liquid photoresist. a first resistive layer, and the first resistive layer 27 is further formed with a plurality of resistive first openings 〇a and at least one resistive second opening 27〇b via a patterning process such as a rayon shirt, wherein the resistive layer is first The opening 270a exposes a portion of the surface of the third metal layer 23c, and the second opening 270b of the resist layer corresponds to the inactive surface 221 of the semiconductor wafer 22, as shown in FIG. 21, by etching to remove the resist a second metal layer 23c, a conductive layer 24 and a first metal layer 23 in the first opening 270a, a third metal layer 23c in the second opening 270b, a conductive layer 24110591 12 1355060 - and a second metal layer 23b, wherein the first and second surfaces of the dielectric layer 21 are formed with first and second circuit layers 28a and 28b, respectively, and a first conductive blind is formed in the dielectric layer opening 211a. The hole 280a is electrically connected to the electrode pad 221 of the semiconductor wafer 22, and the conductive via 26 is electrically connected to the first circuit layer 28 a and second circuit layer 28b, the first circuit layer 28a is formed with a plurality of first electrical connection pads 281a, and the second circuit layer 28b is formed with a plurality of second electrical connection pads 281b; A circuit layer 28a is composed of the first metal layer 23a, the conductive layer % and the third metal layer 23c, and the second circuit layer 28b is composed of the second metal layer

Mb, conductive layer 24 and third metal layer 23c are formed. The third metal layer 23c, the conductive layer 24 and the first metal layer 23a of the second opening 270b are removed to expose the dielectric layer 21 on the inactive surface of the semiconductor wafer 22. As shown in FIG. 2J, the first resist layer 27 is removed to expose the first wiring layer of the first surface 21a of the dielectric layer 21, and the second surface 2ib of the dielectric layer 21 is exposed. Circuit layer 28b.

As shown in FIG. 2K, 'the dielectric layer 21' located on the semiconductor wafer 22 is removed to form a dielectric layer opening 210 and exposed to the inactive surface 22b of the conductor wafer 22; When the dielectric layer 21 is a solid material material, the light portion dielectric layer 21 is removed by f-ray or plasma (pia_); and the dielectric layer 21 is, for example, a touch: The engraving process removes the second table: a portion of the dielectric layer 21' to form an inactive surface of the semiconductor wafer 22 that is open to the semiconductor wafer. Fu 乂 110591 13 1355060 . Please refer to the 2L · picture, the first surface 21 a of the dielectric layer 21 is formed: a minus the first circuit layer 28a surface to form a first solder resist layer 29a, and a plurality of openings 29〇a are formed in the layer 29a to expose a portion of the surface of the first turtle-connecting pad 281a, and a first surface 21b of the dielectric layer 21 and the first circuit layer 28b are formed. The second solder resist layer forms a first opening Mb adjacent to the second solder resist layer 29b to expose the inactive surface 22b' of the semiconductor wafer 22, and the second solder resist layer 29b is formed with a plurality of second openings 292b to A portion of the surface of the second electric 281b is exposed. The reverse connection is as shown in FIG. 2M, forming a shape layer 281a on the first electrical connection pattern 2, and on the first surface metal layer I, an upper power supply member 281a"; and the second The electrical connection 塾 281b / is formed into the second surface metal layer 281b, and the second conductive element 281b" is formed on the second surface gold 281b'.曰Please also refer to the _'connected' (4) (4), which can be added to the first surface 21a and the first circuit layer 28 • the layer structure 29, and the first line is added to the first line. A line build-up structure 29 includes at least one electric layer 290', a layer 291 stacked on the third dielectric layer 29, and a second line hole on the moon, and a third medium in the basin. The second conductive blind layer % and the -f % of the electrical layer 29 are connected to the first line having a plurality (2) and the first line build-up structure (2), and the upper surface is configured to be a surface; 293, 'repeating the first-line build-up junction has a number of first opening-opening 290a to expose the third electrical connection = 110591 14

部分JJ JUVJU 293 part of the surface; another 兮 兮 二 线路 线路 HI HI HI 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二The non-active surface 22b, = open: two structures 29, includes at least one fourth dielectric layer 2

s 第四 第四 第四 第四 第四 Q 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 The circuit layer m and the fourth circuit layer - * pad 29 ^ brother - line build-up structure 29" have a plurality of fourth electrical connection Mm complex ^ 2 line build-up structure 29, formed with a second anti-pair该 'The second solder mask layer is formed with a first opening _, a half-body 1 ΓΓ two-layer structure 29, the second opening 294 ′ and exposing the opening to the right moving surface 22 b, and the second solder resist layer In 29b, there is a second opening 292b to expose a portion of the surface of the fourth electric 293". The present invention includes a substrate structure in which a semiconductor wafer is buried, and the non-master wafer 22' has an active surface and a corresponding inactive surface 22b' and the active surface 22a has a first dielectric layer. 21, and a second dielectric layer 四 (4) 半导体 a semiconductor wafer 22 ′ having a corresponding first surface called a first surface training, and having a dielectric layer opening 21 〇 to expose the semiconductor crystal: 2 non-active surface a first circuit layer is formed on the first surface 21a of the dielectric layer, and has a first conductive via hole 280a'' disposed in the dielectric layer 21 to electrically connect the semiconductor wafer The electrode pads 110591 15 1355060 • 221, and the second circuit layer 28 b ′ are formed on the second surface of the dielectric layer 21 b and electrically connected to the circuit layer 2 ga. The substrate structure further includes at least one conductive via hole for electrically connecting the first wiring layer 28a and the second wiring layer; the first electrical layer 21 and the second dielectric layer 2i" It is a thermosetting material or a photosensitive material, and the first circuit layer 28a is composed of a first metal layer 23a and a conductive layer 24 = a second metal layer 23C; the first circuit layer 28a includes a double-electrical connection pad. 281a, on the first surface of the dielectric layer 21 (4) a first solder resist layer ... is disposed on the first-circuit layer 28a, and the first anti-knowledge layer 29a has a plurality of first-opening holes to expose the first a portion of the surface of the f 281a is connected to the surface of the first electrical layer 281a, and the first surface metal layer 281a is provided with a conductive element 281a, ??? The second circuit layer 28b is composed of a second metal layer 23b, a conductive layer 24 and a second metal layer 23c; the second circuit layer 2 includes a second electrical connection port 281b, and the second dielectric layer 21 The second solder resist layer 2 is disposed on the surface of the circuit layer 28b, and the second solder mask/there is a plurality of second openings 292b to expose a portion of the surface of the second electrical connection _ is disposed on the second electrical connection = = = surface metal layer 281 b ′ ′′, the second surface metal layer 281 b ′ is provided with a first element 彳 281 b, and The second solder mask carries a first opening 291b corresponding to the "曰幵d 21G" to expose the inactive surface 22b of the semiconductor wafer 22. 110591 16 1355060 ' Or on the first surface of the dielectric layer 21? R Μ Seven Walls & and Brother One Circuit Layer 28a: · The right has a first line build-up structure 29, 兮筮咏k • ^ ^ ^. Xuandi—the line build-up structure 29, . (4) has at least one dielectric layer, and is stacked on the “three dielectric layer”, and a plurality of layers are disposed in the third dielectric layer. a blind hole 292', the second conductive wire 222 is electrically connected to the first and third circuit layers 28a, 291, and the first tamper is in the road layer structure 29, The surface has a third electrical connection 塾 293, and a first solder resist layer 29a is disposed on the first-layer build-up structure ,, and the first solder mask has a plurality of first spring holes 290a to expose the first a portion of the surface of the third electrical connection 塾m, the third electrical connection 塾 293, is provided with a first surface metal layer, for example, the first surface metal layer 281a is provided with a first conductive element 281 & The second surface 21b of the dielectric layer 21 and the second circuit layer are topped with a second line build-up structure 2.9, and the second line build-up structure 209 includes at least one fourth a dielectric layer 29〇,, a fourth wiring layer 291 stacked on the fourth dielectric layer, and a plurality of second conductive mesh holes 292 disposed in the fourth dielectric layer The third conductive via 292" is electrically connected to the second and fourth circuit layers 28b, 291", and the second circuit buildup structure 29, the fourth circuit layer 291" of the surface has a plurality of fourth electrical properties. a second surface metal layer 281b is disposed on the fourth connection metal pad 281b, and the second surface metal layer 281b is provided with a second conductive element 281b" The second line = the prior structure 29" has a second second corresponding to the opening of the dielectric layer to expose the inactive surface 22b of the semiconductor crystal 22, and the second solder resist is provided on the second line build structure 29" a layer 29b, and the second solder resist 29b has a plurality of first openings 292b to expose the fourth electrical port 110591 17 1355060. -29:: 'partial surface' and the second solder resist 2 The first opening 291b of the layer opening 210 should be dielectric to expose the semiconductor wafer; the inactive surface 22b. Referring to Figures 3A to 3D in May, it is a schematic diagram of a stack of substrate structures in which a semiconductor germanium is embedded in the present invention. For example, as shown in FIG. 3A, 'at least two substrate structures 0, 31' as shown in FIG. 2L are provided, wherein the second solder resist layer of the I 28U system and the other substrate structure 31 of the first electrical connection pad of the substrate structure 30 29b Φ敫敫^Electrical connection 塾2m are stacked and electrically connected to each other to enhance the electrical quality of the biliary and ancient structures. As shown in FIG. 3B, the stack structure is different from the fourth item in that the first solder resist layer 29a of the substrate structure 31 is connected to another semiconductor wafer and the side semiconductor wafer 22 is connected by a wire 33 (_bonding). The technology is electrically connected to the first electrical connection pad 281a' of the first solder mask layer, and the semiconductor wafer 22, the wire is implicated on the first electrical f connection pad 281a, and the encapsulation material 32' is disposed on the substrate. The structure is spliced and electrically connected to the semiconductor wafer having the wire bonding, and the substrate structures 3 are stacked on each other to form a high-density stacked substrate structure. As shown in FIG. 3C, the stacked structure is different from the 帛3β pattern in that the semiconductor wafer 22' is electrically connected to the substrate junction (4) 2 and the first conductive member 281a on the connection 281a. For the two-plate structure 3G on the stack # and electrically connected to the substrate structure 31 electrically connected to another semiconductor wafer 22 in a flip chip manner. As shown in FIG. 3D, 'providing at least two, for example, flip chip The splicing of 110591 18 丄 〇 60 · • the other semiconductor wafer 22, the substrate structure 3i, 3r, and the stack and the sturdy connection of the substrate structures 31, 31, to enhance the overall electrical function. The body structure of the semiconductor device is embedded in the dielectric layer, and the first and second surfaces are respectively formed on the first and second surfaces of the dielectric layer. The circuit layer is such that the first circuit layer is electrically = the semiconductor wafer' and the inactive surface of the semiconductor wafer is exposed, so that the heat generated by the conductor mountain chip can be effectively dissipated to achieve a heat dissipation effect, and then respectively ^IV"conductor The substrate structure of w is formed on both sides of the semiconductor wafer to form a wiring layer 'this substrate The structure symmetry is good, the plate bender can be reduced, and the substrate structure is formed by the combination of the 铋 铋 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The overall thickness of the substrate is reduced; in addition, the substrate structure of the present invention can be stacked to enhance the electrical function. The specific embodiments described in the above are only used to illustrate the special features of the present invention: The invention can be implemented by Fan Ming. Any use of the present invention without departing from the spirit and technology: [:::: 4 effect change and modification] should still be the following patent application [simple description of the schema] 2 is a schematic cross-sectional view showing the structure of the structure of the present invention; 4, the second C-layer of the substrate in which the semiconductor wafer is buried is the 2nd to 2C diagram. A schematic view of another embodiment: a cross section of another embodiment 110591 19 1355060, a second embodiment of the second GD; and a third embodiment of the present invention, showing a substrate structure in which a semiconductor wafer is embedded in the present invention. Stacking diagram. [Main component symbol description] 10, 30, 31 ' 31 Substrate structure 100 First substrate opening 10b Second substrate 110 Bonding material 11a, 22a Active surface 12 Line build-up structure 121 Circuit layer 123 Electrical connection pad 130 Opening L 21, First dielectric layer 210" Second dielectric Layer opening 211b through hole 21a first surface 23a first metal layer 23c third metal layer 26 conductive via 260 filling material 270a resistive layer first opening 280a' first conductive blind hole 281a' first surface metal layer 10a first substrate 11, ί 12 ' 2V semiconductor crystal 111, 221 electrode 塾 lib, 22b inactive surface 120, 21 dielectric layer 122 conductive blind hole 13 anti-mite layer 21, first dielectric layer 210 dielectric layer opening 211a dielectric layer Hole 212 resistive frame 21b second surface 23b second metal layer 24 conductive layer 26, through-hole conductive via 27 first resist layer 270b resistive second opening 281a first electrical connection mark 281a, 'first conductive element 110591 20 1355060 -281b second electrical connection pad 281b, •.281b" second conductive element 28a · · 28b second circuit layer 29, 29" second line build-up structure 290, 290" fourth dielectric Layer 290a 291' third circuit layer 291" 291b first opening 292, 292" third conductive blind hole 292b 293' third electrical connection pad 293" • 294 second opening 29a 29b second solder mask 32 33 wire Two surface metal layer first circuit layer first line build-up structure third dielectric layer first opening fourth circuit layer second conductive blind hole second opening fourth electrical connection 塾 first solder mask encapsulation material

21 110591

Claims (1)

1355060 X. Patent application scope: 1. A substrate structure embedded with a semiconductor wafer, comprising: a semi-body, a Ba-shaped film having an active surface and a corresponding inactive, and the active surface has a plurality of electrodes Pad: ~:: The electrical layer' is composed of a first dielectric layer and a second dielectric laminate to form a solid semiconductor chip, and has a first surface and a second surface of the second surface and has - The dielectric layer is opened to expose the inactive surface of the semiconductor wafer; the first wiring layer is formed on the first surface of the dielectric layer and has a first conductive blind via semiconductor chip disposed in the dielectric layer The electrode pad; and the W-connected second circuit layer are formed on the second surface of the dielectric layer and electrically connected to the circuit layer. 2. Γ:!=6 The substrate of the semiconductor wafer embedded in the first item is replaced by a conductive via ’α electrically connected to the first wiring layer and the second wiring layer. 3. : Shen 2 Patent Model! No. 2, the substrate material of the semiconductor wafer is buried, and the electrical via hole is filled with a conductive or non-conductive filling material to fill the space inside the conductive via. 4. The embedded semiconductor is embedded in the second aspect of the patent application, wherein the conductive via is a solid conductive via. Earth anti-, '° 5. If the application of the scope of the third paragraph of the embedded eight, the first dielectric layer and the second dielectric # 丨 electric layer ten Ding 'is a thermo-curable material, Ganzi. A substrate material or photosensitive material 110591 22 1355060 structure of the Japanese version of the Japanese version, the substrate of the semiconductor wafer embedded in the η:': and the third metal::: the circuit layer is made of the first metal The layer and the conductive layer are in the form of a semiconductor wafer embedded in the first item of the benefit range: The first circuit layer includes a plurality of first electrical connections: as described in claim 7 of the patent scope, the complex includes a first solder mask, and the second layer; the board surface and the first circuit layer And the first solder mask; 2 = - Table 9. The part of the surface of the electrical connection pad of the younger brother. As the application of the eighth scope of the patent application, the first surface includes all 7 cattle. The substrate of the conductor chip is bonded to the substrate. The surface metal layer is disposed in the first electrical connection. 10. The semiconductor u embedded in the ninth aspect of the patent application is applied to the '(four)-surface metal layer. The first layer is provided with a semiconductor wafer line build-up structure embedded in the dielectric layer: including: one less:: 3 upper line build-up structure The second conductive oblate second conductive blind via is disposed in the third dielectric layer and electrically connected to the first and third circuit layers, and (4) the surface of the buildup structure has a third electrical property塾 塾 】 】 】 】 】 】 】 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体11059] 9^ 丄JJJUOU ^ and 'the first solder mask has a plurality of first-opening holes to expose a part of the surface of the third electrical connection pad. The structure 12 of the substrate connection pad embedded with the semiconductor wafer is included a first surface metal layer is disposed on the substrate of the third semiconductor 14:: a substrate embedded with a semiconductor wafer; wherein the first surface conductive layer is provided with a first conductive Yuan 15: Shen:: The range of the semiconductor substrate embedded with the semiconductor wafer and the second second layer are composed of the second metal layer, the conductive layer and the second metal layer. The item is embedded with a semiconductor wafer L: wherein the second circuit layer includes a plurality of second electrodes: a: 17:: please: ==16 of the substrate surface on which the semiconductor wafer is embedded and the first Second line: η: the second two openings provided in the dielectric layer have a plutonium potential θ and the second solder resist layer has a plurality of surfaces of the first and second electrical connection pads, and the surface One solder layer has a non-active surface corresponding to the dielectric layer of the semiconductor wafer. The semiconductor device of the seventh aspect is embedded in the semiconductor structure, and includes a second surface metal; ς is connected to the pad. The a is in the second electrical property. 19. The semiconductor wafer substrate 11059 is embedded in claim 18 24 20. Structure, wherein one piece is 。. The second surface of the surface metal layer is provided with a second conductive element == the second circumference of the substrate: the second surface and the second line embedded with the semiconductor The build-up structure is provided on the dielectric layer for each of at least one of four cores 1 'the second line build-up structure package 'the circuit layer, and the plurality of V on the first stack of four:: two four dielectric... Reading the second line c::;, connecting the second and fourth circuit layers, electrically connecting the 塾, and the fourth circuit layer of the ^ has a plurality of fourth electrical layer openings - the line buildup structure has a corresponding interface . The younger brother opens an opening to expose the semiconductor wafer. The substrate embedded with the semiconductor wafer of the 20th item includes a second solder mask layer, which is added to the second line. In the layer structure, the first solder mask has a plurality of second openings to expose a portion of the surface of the four electrical connections, and the second solder mask has a sub-dipole opening. a first opening to expose the inactive surface of the semiconductor wafer. 22·^ Patent Application No. 21, the substrate embedded with the semiconductor crystal moon, comprising a second surface metal layer The fourth electrical connection pad. 23. The substrate structure embedded in the semiconductor wafer of claim 22, wherein the second surface metal layer is provided with a second conductive element. 25 110591