TWI358115B - Embedded semiconductor package structure - Google Patents

Embedded semiconductor package structure Download PDF

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Publication number
TWI358115B
TWI358115B TW097108388A TW97108388A TWI358115B TW I358115 B TWI358115 B TW I358115B TW 097108388 A TW097108388 A TW 097108388A TW 97108388 A TW97108388 A TW 97108388A TW I358115 B TWI358115 B TW I358115B
Authority
TW
Taiwan
Prior art keywords
flexible substrate
layer
wafer
package structure
semiconductor package
Prior art date
Application number
TW097108388A
Other languages
Chinese (zh)
Other versions
TW200939436A (en
Inventor
Wei Hua Lu
Hsun Heng Tsai
Yung Chuan Chen
Original Assignee
Univ Nat Pingtung Sci & Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Pingtung Sci & Tech filed Critical Univ Nat Pingtung Sci & Tech
Priority to TW097108388A priority Critical patent/TWI358115B/en
Publication of TW200939436A publication Critical patent/TW200939436A/en
Application granted granted Critical
Publication of TWI358115B publication Critical patent/TWI358115B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1358115 r 100年9月30日替換頁 九、發明說明 【發明所屬之技術領域】 本發明係關於一種嵌入式半導體封裝構造，特別是關於一 種將晶片設置於軟性基板一側之導熱通道之外唇緣上，並在軟 性基板另一侧設置散熱板’以簡化製程及提高良率的嵌入式半 導體封裝構造。 【先前技術】 近年來，高效能、高積集度、低成本、輕薄短小一直為長 久以來電子產品設計製造上所追尋之目標。為了達成上述目 標’積體電路封裝技術也跟著朝向微型化、高密度化發展，其 中常見的封裝技術包含雙列直插式封裝(Dual In_Hne Package ’ DIP)、四方扁平封裝(Quacj Fiat pack，QFp)、四方形 扁平無引腳封裝(Quad Flat No-lead，QFN)、針腳陣列式構裝 (Pin Grid Array ’ PGA)、球格陣列式構裝(Ball Grid ， BGA)、嵌入式晶圓級封裝(Embedded Wafcr Uvd paeka@， EWLP)及晶片尺寸級構裝(Chip_Scale package，csp)等。以嵌 入式晶圓級封裝(EWLP)構造為例’其係將至少—晶片包埋嵌 入至-多層電路基㈣，並在該多層電路基板之—表面固設數 個銲球(S〇lder ball)。_是，由於EWLP封裝構造能在該多層 電路基板之同-簡或不_層設置數個晶片，崎—步整合 數個晶片關-封裝體巾，因此有利於構成具多功能的系統級 5 100年9月30日替換頁 封裝一祕峨，剛’是以成為^^11 片構裝技術。因此，如何將晶片㈣在多層電路基板内，及如 何絲進行嵌人式^之散解技術問題亦成為紐封裝技 術成敗與否之關鍵因素之一。 舉例而言，中華民國專利公告第124地號則公開一種「結 合有可撓性軟板之散熱型半_裝置」，其包含：一散熱f -絕緣板’結合在該散熱片之表面，且具有至少—開口；至少 一料體树，埋設在該絕緣板之開σ内，並結合在該散熱片 的表面“X及至}—可撓性軟板，係接置並電性連接該半導體 件，以供承縣_電子元件，該可雜軟祕可彎折固定 於該散熱片上。上述絕緣板及轉體元件表面形成一線路增層 結構，並於線路增層結構表面形成導電元件。然而，該半導體 元件及該絕緣板之開口的尺寸公差必需精密控制，尺寸公差過 大則該半導體元件無法嵌入該開口，尺寸公差過小則該半導體 元件及開π之㈣存在H可能在後續供乾製程造成爆孔。 再者，中華民國專利公告第588445號則公開一種「無凸塊 晶片封裝構造」，其包含：一载板，其上表面具有一開口、數 個第-接點及數個第二接點，至少該第—接點之—係與該第二 接點之-電性連接；-晶片，其主動表面具有數個晶級點， 且該主動表面係背向該下表面容置於該開口中；一導電層設置 於該晶片主動表面上及該基板上表面，該導電層係在該晶片主 100年9月30日替換頁 表面上及在錄板上表面延伸，以使該^與該載板電性連 :及保魏設置於該導電層上以暴露出該第二接點。然 而該曰曰片及該載板之開口仍存在尺寸公差需精密控制之相關 問題。 a另外’中華民國專利公告第顧_號則公開一種「具有 散熱金屬層之直接導通式半導體树結構」，其包含：-金屬 平板，至少-接置於該金屬平板上之半導體晶片；—形成於該 表面接置有半導體晶片之金屬平板上之絕緣層，且該絕緣層覆 蓋該半導體晶片；以及至少—形成於該絕緣層上之贿化線路 層’且該圖案化線路層係藉由複數形成於該絕緣層中之導電結 構以電性連接至該半導體晶&gt;；。在餘上，該抖體晶片係先 利用導熱黏膠固定於該金屬平板上，接著再利用該絕緣層覆蓋 該半導體晶片。然而。直接利用導熱黏膠將該半導體晶片固定 於該金屬平板上，該半導體晶片容易發生縱向及橫向之水平位 移，進而造成水平對位上之困難。 除此之外，相關於嵌入式晶圓級封裝之先前技術尚有中華 民國專利公告第546999號「半導體元件、半導體元件之製造 方法、多層印刷配線板及多層印刷配線板之製造方法」等。然 而’其電子元件仍是嵌入於一基板之開口内，該電子元件及該 基板之開口仍存在尺寸公差需精密控制之相關問題。 由於嵌入式晶圓級封裝(EWLP)構造具有微型化的趨勢，因 100年9月30日替換頁 此必需設法解決上述組裝尺寸公差及水平對位之問題，以便提 升產品製造良率。是故，確實有必要提供一種嵌入式半導體封 裝構造，以解決習知技術所存在的缺陷。 【發明内容】 本發明之主要目的在於提供一種喪入式半導體封裝構造， 其係將晶片設置於軟性基板一侧之導熱通道之外唇緣上，並在 軟性基板另一側設置散熱板，其有利於減少對於組裝公差精度 的要求，進而簡化製程及提高良率。 本發明之次要目的在於提供一種嵌入式半導體封裝構造， 其係在軟性基板之上形成外散(fan-outRDL)線路，以便提高晶 片之汛號連接端的數量及可佈局面積，進而增加訊號連接端之 球格陣列密度。 本發明之另一目的在於提供一種嵌入式半導體封裝構造， 其係在軟性基板設置電路層’其藉由連接導通孔及外散線路分 別連接晶片之焊墊及訊號連接端，進而提升訊號連接端之重佈 局設計裕度。 本發明之再一目的在於提供一種嵌入式半導體封裝構造， 其係在軟性基板之導熱通勒填充導歸，以便將晶片產生之 熱量傳導至散熱板，進而提升整體散熱效率。 本發明之再一目的在於提供一種嵌入式半導體封裝構造， 其係糊紐基板及域層縣晶#，以提㈣#之可挽性， 100年9月30日替換頁 進而增加抗翹曲性及防裂 並利用散熱板確保封裝構造之外形 性0 ▲ :、·甘述之目的’本發明提供一種嵌入式半導體封裝構 k八包3.-軟性基板、封裝層、—散熱板及數 錢接端。性基«設—導細道，其填充-導孰 膠。該晶片具有—主動表面、一背面及數個側表面，該背面之 β緣系點D於該軟性基板—側之導熱通道之外唇緣上。該散熱 板站接於錄性基板之另—侧。該封裝層倾練性基板之一 侧上，且包峨晶#之侧表面。龍號連接端設於該封裝層之 一外表面上，並藉由至少一外散線路電性連接至該晶片之主動 表面。 在本發明之一較佳實施例中，該軟性基板之表面或内部可 進一步依需麵擇設置至少―電路層，該晶狀絲表面先經 由-外散_紐連接練性基板之電路層，再經由該線路層 電〖生連接至該軟性基板上之訊號連接端。再者，該軟性基板係 可選自單層或绍之軟性基板。藉此 ’向外擴散該訊號連接端 之佈局面積’以增加球格陣列密度及重佈局裕度。 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更明顯易 懂’下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 說明如下。 1358115 6月參照第1至6圖所示，本發㈣-實施例之嵌入式半導 體封裝構造主要包含一軟性基板1、一晶片2、一散熱板3、 ,封裝層4及數個峨連接端5。該軟性基板丨開設—導熱通 道U，其填充一導熱膠12。該晶片2具有-主動表面2卜一 背面22及數個側表面23，該背㈣之唇緣(未標示)係黏合於 該軟性基板丨-侧之導熱通道„之外魏(未標示)上。該散孰 板3貼接於該軟性基板i之另一側，並可開設至少一通孔η。 該封裝層4位於該軟性基板丨之—側上，且包埋該晶片2之側 表面23。該峨連接端5設於該封裝層4之-外表面上，並 藉由至少—外散線路41電性連接至該晶片2之主動表面21。 請再參照第i至6 _示，本發明第—實施例之嵌入式半 導體封裝構造射齡下顺歸驟純製造，财並非用以 限制本發明。程步驟係包含：提供—雜基板卜 一導熱通道11;將一晶只）夕一此 ^ 1 之青面22之一唇緣(未標示)黏 °於該軟嶋1 i确顿魏(未標示)上； 將-導熱膠12填人該軟性基板丨之導舰道n⑴將一散熱 板2貼接於該軟性基板丨之另—侧；形成—封裝層4，以包埋 。亥曰曰片2之側表面23 ;在該封敦層*上形成數個導通孔42及 至少一外散線路41 ;以及’形成數個訊號連接端5於該封袭 層4之’面上，以電性連接至該導通孔似外散線路Μ。 請參照第1及2圖所示，本發明第一實施例之軟性基板！ 100年9月30日替換頁 較佳係由可触材t製成，例如粒雜㈣如此)等 。該軟 性基板1開設有—導熱通道11，其貫通該軟性基板1之二側。 該晶片2較佳係選自抑圓切割而成之晶片，其具有—主動表 面21、一背面22及數個側表面23。該背面22之一唇緣(未標 示)係利用-轉24黏合於該軟性基板i 一侧之導熱通道^ 之-外躲(未標#)上。雜膠24較佳傾自環紐脂(ep〇xy resin)。此時’該晶片2可藉由一般製程機台(未繪示)精準的放 置在該軟録板〗上，且該晶# 2之外徑僅需控制大於該導熱 通道11之陳即可’並不需要精密㈣其尺寸公差比例。隨 後’該軟性基板1之導熱通道11内係填入-導熱膝I2，其較 佳選自銀膠。 睛參照第3及4圖所示，本發明第一實施例之散熱板3較 佳係由導熱性佳之金屬材質製成’例如銅或紹等。該散熱板3 係適^貼接於該軟性基板1之另一側，其貼接的方式可利用一 黏膠(未繪示)完成，該黏膠較佳亦選自環氧樹脂(印〇兮疏）。 該散熱板3並可f姐至少—通孔η，其連通至該軟性基板】 之導熱通道11，赠使該輪通道u _導_ 12具有熱 脹冷縮之緩衝抑裕度。接著，軸該職層4於該軟性基板 1之一側上，以便包埋該晶片2之側表面23，但亦較佳選擇性 包埋該晶片2之主動表面2卜該封裝層4可選自各種封裝材 質，其較佳選自可撓性材質，例如聚亞醯胺等。在 1358115 100年9月30曰替換頁 進牛^f 5及6 ，本發明第—實施例之封裝層4係 進一料絲辦軌42㈣及至少—植魏 瞻心_孔42係__4，並_於該晶片21358115 r September 30, 2010 Replacement Page 9 Description of the Invention [Technical Field] The present invention relates to an embedded semiconductor package structure, and more particularly to an outer lip of a heat conduction channel on a side of a flexible substrate On the edge, and on the other side of the flexible substrate, a heat sink is provided to simplify the process and improve the yield of the embedded semiconductor package structure. [Prior Art] In recent years, high performance, high integration, low cost, light weight and shortness have been the goals pursued in the design and manufacture of electronic products for a long time. In order to achieve the above goal, the integrated circuit packaging technology has also been developed toward miniaturization and high density. Common packaging technologies include Dual In_Hne Package 'DIP, Quad Flat Pack (Quacj Fiat pack, QFp). ), Quad Flat No-lead (QFN), Pin Grid Array 'PGA, Ball Grid (BGA), Embedded Wafer Level Package (Embedded Wafcr Uvd paeka@, EWLP) and Chip size scale (Chip_Scale package, csp). Taking an embedded wafer level package (EWLP) structure as an example, it is embedded in at least a wafer embedded in a multi-layer circuit substrate (4), and a plurality of solder balls are fixed on the surface of the multilayer circuit substrate (S〇lder ball) ). _ Yes, since the EWLP package structure can set several wafers in the same-simplified or non-layer of the multi-layer circuit substrate, it is advantageous to integrate several wafer-package body towels, thereby facilitating the formation of a multi-functional system level 5 On September 30, 100, the replacement page encapsulation was a secret, just to become a ^^11 piece assembly technology. Therefore, how to apply the wafer (4) in the multi-layer circuit substrate and how to embed the embedded technology is one of the key factors for the success or failure of the package technology. For example, the Republic of China Patent Publication No. 124 discloses a "heat-dissipating half-device incorporating a flexible flexible board," comprising: a heat-dissipating fin-insulating plate bonded to the surface of the heat sink, and Having at least one opening; at least one material tree embedded in the opening σ of the insulating plate and coupled to the surface of the heat sink “X and to — the flexible flexible board is connected and electrically connected to the semiconductor piece For the Chengxian _ electronic component, the soft and flexible can be bent and fixed on the heat sink. The surface of the insulating plate and the rotating component form a line build-up structure, and a conductive component is formed on the surface of the line build-up structure. The dimensional tolerance of the opening of the semiconductor component and the insulating plate must be precisely controlled. If the dimensional tolerance is too large, the semiconductor component cannot be embedded in the opening. If the dimensional tolerance is too small, the semiconductor component and the opening π (4) may have H may be caused by the subsequent drying process. Further, the Republic of China Patent Publication No. 588445 discloses a "bumpless chip package structure" comprising: a carrier plate having an opening on the upper surface thereof and a plurality of - a contact and a plurality of second contacts, at least the first contact is electrically connected to the second contact; and the wafer has an active surface having a plurality of crystal level points, and the active surface is backed The lower surface is received in the opening; a conductive layer is disposed on the active surface of the wafer and the upper surface of the substrate, and the conductive layer is on the replacement page surface of the wafer main on September 30, 100 and on the recording board The surface extends such that the device is electrically connected to the carrier: and the security layer is disposed on the conductive layer to expose the second contact. However, there are still problems associated with the precise control of the dimensional tolerances of the cymbal and the opening of the carrier. a further 'Republic of China Patent Notice No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ An insulating layer on the metal plate of the semiconductor wafer is attached to the surface, and the insulating layer covers the semiconductor wafer; and at least a brittle circuit layer formed on the insulating layer and the patterned circuit layer is composed of a plurality A conductive structure formed in the insulating layer is electrically connected to the semiconductor crystal&gt;; In the remainder, the shaker wafer is first fixed to the metal plate by a thermally conductive adhesive, and then the semiconductor wafer is covered with the insulating layer. however. The semiconductor wafer is directly fixed to the metal flat plate by using a thermally conductive adhesive, and the semiconductor wafer is prone to horizontal displacement in the longitudinal direction and the lateral direction, thereby causing difficulty in horizontal alignment. In addition, the prior art related to the embedded wafer level package includes the "Semiconductor device, the method of manufacturing a semiconductor device, the method of manufacturing a multilayer printed wiring board, and a multilayer printed wiring board", and the like. However, the electronic component is still embedded in the opening of a substrate, and the electronic component and the opening of the substrate still have problems associated with precise control of dimensional tolerances. Due to the miniaturization of the embedded wafer level package (EWLP) construction, due to the replacement page on September 30, 100, it is necessary to solve the above-mentioned assembly dimensional tolerances and horizontal alignment problems in order to improve product manufacturing yield. Therefore, it is indeed necessary to provide an embedded semiconductor package structure to solve the drawbacks of the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a funnel-type semiconductor package structure in which a wafer is disposed on a lip outside a heat conduction channel on one side of a flexible substrate, and a heat dissipation plate is disposed on the other side of the flexible substrate. It helps to reduce the requirements for assembly tolerance accuracy, which simplifies the process and improves the yield. A secondary object of the present invention is to provide an embedded semiconductor package structure that forms a fan-out RDL line on a flexible substrate to increase the number of apostrophes and the layout area of the wafer, thereby increasing the signal connection. The density of the ball grid array at the end. Another object of the present invention is to provide an embedded semiconductor package structure in which a circuit layer is disposed on a flexible substrate, which is connected to a pad and a signal connection end of the wafer by connecting a via hole and an external diffusion line, thereby improving the signal connection end. The layout layout margin is heavy. It is still another object of the present invention to provide an embedded semiconductor package structure that is thermally conductively filled in a flexible substrate to conduct heat generated by the wafer to the heat sink, thereby improving overall heat dissipation efficiency. A further object of the present invention is to provide an embedded semiconductor package structure, which is a paste substrate and a domain layer county crystal #, to mention the (four) # can be pulled, and replace the page on September 30, 100 to increase the warpage resistance. And crack prevention and use the heat sink to ensure the shape outside the package structure. ▲ : · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Pick up. Sex-based «station-guide channel, its filling-guided glue. The wafer has an active surface, a back surface and a plurality of side surfaces, and the β edge point D of the back surface is on the outer edge of the thermal substrate of the flexible substrate. The heat sink is connected to the other side of the recording substrate. The encapsulating layer is on one side of the tempering substrate and is coated on the side surface of the twin. The horn connection is disposed on an outer surface of the encapsulation layer and is electrically connected to the active surface of the wafer by at least one external dispersion line. In a preferred embodiment of the present invention, at least a circuit layer may be further disposed on the surface or the inside of the flexible substrate, and the surface of the crystalline wire is first connected to the circuit layer of the practicable substrate via the external-external-distribution layer. Then, the circuit layer is electrically connected to the signal connection end on the flexible substrate. Further, the flexible substrate may be selected from a single layer or a flexible substrate. Thereby, the layout area of the signal connection end is diffused to increase the density of the grid array and the layout margin. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 1358115 June, as shown in FIGS. 1 to 6, the embedded semiconductor package structure of the present invention (4)-embodiment mainly includes a flexible substrate 1, a wafer 2, a heat dissipation plate 3, an encapsulation layer 4, and a plurality of germanium connection ends. 5. The flexible substrate is opened with a heat conducting channel U filled with a thermal conductive adhesive 12. The wafer 2 has an active surface 2, a back surface 22 and a plurality of side surfaces 23, and the lip (not labeled) of the back (4) is bonded to the heat conduction channel of the flexible substrate 之外-side (not labeled) The bulking plate 3 is attached to the other side of the flexible substrate i, and at least one through hole η can be formed. The encapsulating layer 4 is located on the side of the flexible substrate and encloses the side surface 23 of the wafer 2. The connection end 5 is disposed on the outer surface of the encapsulation layer 4, and is electrically connected to the active surface 21 of the wafer 2 by at least the external dispersion line 41. Please refer to the i- to 6- The embedded semiconductor package structure of the first embodiment of the invention is manufactured by the sequel, and is not intended to limit the invention. The process steps include: providing a hetero-substrate, a heat-conducting channel 11; One of the lips (not shown) of the green surface 22 of the ^ 1 is adhered to the soft 嶋 1 i sure Wei (not labeled); the conductive paste 12 is filled with the flexible substrate 丨 the guide channel n (1) will be one The heat sink 2 is attached to the other side of the flexible substrate; the encapsulating layer 4 is formed to be embedded. The side surface 23 of the sheet 2 is in the layer * A plurality of via holes 42 and at least one external bulk line 41 are formed on the surface; and a plurality of signal connection terminals 5 are formed on the surface of the seal layer 4 to be electrically connected to the via holes. Referring to Figures 1 and 2, the flexible substrate of the first embodiment of the present invention! The replacement page of September 30, 100 is preferably made of a contactable material t, such as a granular material (four), etc. The flexible substrate 1 is provided with a heat conduction channel 11 penetrating through the two sides of the flexible substrate 1. The wafer 2 is preferably selected from a wafer which is circularly cut and has an active surface 21, a back surface 22 and a plurality of side surfaces 23 One of the lips 22 (not shown) of the back surface 22 is bonded to the heat-conducting channel on the side of the flexible substrate i by using a turn-to-turn 24 (not labeled #). The glue 24 is preferably poured from the ring grease. (ep〇xy resin). At this time, the wafer 2 can be accurately placed on the soft recording board by a general processing machine (not shown), and the outer diameter of the crystal #2 only needs to be controlled to be larger than the thermal conductivity. The channel 11 can be 'without precision (4) its dimensional tolerance ratio. Then 'the flexible substrate 1 of the thermal substrate 11 is filled with - thermal knee I2, which is more The heat dissipating plate 3 of the first embodiment of the present invention is preferably made of a metal material having good thermal conductivity, such as copper or sho, etc. The heat dissipating plate 3 is suitable for the purpose of the present invention. Attached to the other side of the flexible substrate 1, the manner of bonding can be accomplished by using an adhesive (not shown), and the adhesive is preferably also selected from epoxy resin. 3 and f sister at least - through hole η, which is connected to the flexible substrate 11 of the heat conduction channel 11, the channel u _ _ 12 has a buffer expansion margin of thermal expansion and contraction. Then, the axis of the layer 4 on one side of the flexible substrate 1 to embed the side surface 23 of the wafer 2, but it is also preferred to selectively embed the active surface 2 of the wafer 2. The encapsulation layer 4 may be selected from various package materials. It is preferably selected from a flexible material such as polyamine. In 1358115, September 30, 100, replace the page into the cattle ^f 5 and 6, the encapsulation layer 4 of the first embodiment of the present invention is inserted into a wire rail 42 (four) and at least - 植魏心心_孔42系__4, and _ on the wafer 2

=動表面21的數個_211。該外散線路41係形成於該封 裝曰4之-外表面上，並連接於至少一個之該導通孔似。最 後，該數個峨連接端5係選擇直接焊接結合於該導通孔42， 或浮接結合於該外散線路41末端形成之一焊塾(未標示）。該 訊號連接端5触選自金麟體_、麵_ump)或針聊 (pin) 〇= several _211 of the moving surface 21. The external dispersion line 41 is formed on the outer surface of the package crucible 4 and is connected to at least one of the via holes. Finally, the plurality of 峨 connections 5 are selected to be directly soldered to the vias 42, or floatingly bonded to the ends of the external ray lines 41 to form a solder bump (not labeled). The signal connection terminal 5 is selected from a gold lining _, a surface _ump) or a pin ( (pin) 〇

製程上 藉由上述步驟，本發明第一實施例即可完成一歲入式半導 體封裝構造。由於本發明_^ 2設置_軟錄板】一側 之導熱通道11之外魏上，並在錄絲板i另—側設置散 熱板3 ’故有利於減少對於組裝公差精度的要求，可供簡化製 程及提高良率。再者，錄縣板i之上係軸料散線路 4卜以便提高該“ 2之訊號連接端5的數量及可佈局面積， 可供增加訊號連接端之球格陣列密度。該軟性基板丨之導熱通 道11内則可填充相對更多之該導熱膠12，以便將該晶片2產 生之熱量傳導至該散熱板3，進而提升整體散熱效率。由於利 12 100年9月30曰替換頁 用該軟性紐1及雜層績賴^ Γ— 撓性，同時該散熱板3則可確伴封料…喊供適當之可 翹曲性及防师以 外形’進而增加抗 =曲_雌。再者，該散熱板3之槪3 該導熱通道11内的導熱膠12 用確保 進而增加產品之可靠度及良率。有…服冷縮之緩衝空間裕度， 請參照第7及8圖所示，本發明第二實施例之嵌入式 體封裝構造係_於本㈣第—實施例，但該第二實施例之嵌 入式料體封裝構造係進一步於該軟性基板i之表面或内部 增設-電路層D，亦即該軟性基板！係可選自單層或多層之 軟性基板。同時，該晶片2之主動表面21的數個焊塾如係 先經由數個第-導通孔42電性連接至該封裝層4表面之外散 線路4卜接著該外散線路41經由數個第二導通孔43向内貫 穿5亥封裝層4 ’以電性連接該軟性基板丨之電路層13，最後該 電路層13再經由數個第三導通孔44向外貫穿該封裴層4，以 電性連接至該雜層4外表面上之外散線路或訊號連接端5， 進而提升該訊號連接端5之重佈局設計裕度。再者，該軟性基 板Ϊ之電路層13係可進一步選擇性設置至少一被動元件14， 例如電阻、電感或電容，且該被動元件14可利用表面固定(SMT) 或嵌入(embedded)的方式形成在該軟性基板1之表面或内部。 如上所述，相較於習用嵌入式晶圓級封裝構造容易因組裝 尺寸公差及水平對位之問題，而降低產品製造良率等缺點，第 13 1358115 . ‘ - 100年9月30日替換頁 . 5及7圖之本發明藉由將該晶片2設置於該軟性基板1 一側之. •. 導熱通道11之外唇緣上，並在該軟性基板1另一侧設置該散 熱板3，其確實有利於減少對於組裝公差精度的要求，進而簡 化製程及提向良率，同時亦能增加球格陣列密度、提升重佈局 設計裕度、提升整體散熱效率、增加抗龜曲性及防裂性。 雖然本發明已以健實施儀露，然錢_嫌制本發 明，任何熟習此項技藝之人士，在不脫離本發明之精神和範圍 馨 内’田可作各種更動與修倚’因此本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 【圖式簡單說明】 明第-實糊之嵌人式铸體魄構造將晶片結 合於軟性基板上之示意圖。 本發料—實施例之嵌人式轉體封 填入軟性基板之導熱通道内之示意圖。 料』 '敢構造將金屬板 第3圖.本發明第—實施例之嵌人式半導體封 結合於軟性基板另一侧之示意圖圖。 、 第4圖··本發明第—實施例之嵌 層覆蓋晶片之示意圖。 、展構造利用封裝 裝構造形成外散 第5圖：本發明第—實施例之嵌人式半導體封 線路及ifl说連接端之示意圖。 ， 第6圖：她W以構造之下視 14 1358115 - 100年9月30日替換頁 . 圖。 第7圖：本發明第二實施例之嵌入式半導體封裝構造之示意 » * 圖。 .. 第8圖：本發明第二實施例之嵌入式半導體封裝構造之下視 圖。In the process, the first embodiment of the present invention can complete the one-year-old semiconductor package structure by the above steps. Since the heat conduction channel 11 on one side of the _^2 setting_soft-recording board is on the other side, and the heat-dissipating plate 3 is disposed on the other side of the recording board i, it is advantageous to reduce the requirement for assembly tolerance precision, and is available for Simplify process and increase yield. Furthermore, on the recorded board i, the shaft-distribution line 4 is used to increase the number and layout area of the "signal connection end 5 of the 2", which can increase the density of the grid array of the signal connection end. The heat conducting channel 11 can be filled with a relatively large amount of the thermal conductive adhesive 12 to conduct the heat generated by the wafer 2 to the heat dissipating plate 3, thereby improving the overall heat dissipation efficiency. Since the replacement page is used on September 30, 2010 Soft New 1 and Miscellaneous Performance Γ - Flexibility, and the heat sink 3 can be accompanied by the sealing material... shouting for proper warpage and defense to shape 'and further increase resistance = _ female. Between the heat sink 3 and the heat conductive adhesive 12 in the heat conducting channel 11 ensure the reliability and yield of the product, and the buffer space margin for shrinking, please refer to the figures 7 and 8. The embedded body package structure of the second embodiment of the present invention is based on the fourth embodiment, but the embedded material package structure of the second embodiment further adds a circuit layer to the surface or inside of the flexible substrate i. D, that is, the flexible substrate! can be selected from a single layer or multiple layers of softness At the same time, the plurality of soldering pads of the active surface 21 of the wafer 2 are electrically connected to the surface of the encapsulation layer 4 via a plurality of first via vias 42 and then the interfering lines 4 are connected. The second via hole 43 penetrates the 5 IGBT layer 4 ′ inwardly to electrically connect the circuit layer 13 of the flexible substrate ,, and finally the circuit layer 13 extends through the sealing layer 4 through the plurality of third via holes 44 . Electrically connected to the external line on the outer surface of the hybrid layer 4 or the signal connection terminal 5, thereby increasing the layout margin of the signal connection terminal 5. Further, the circuit layer 13 of the flexible substrate can be Further, at least one passive component 14, such as a resistor, an inductor or a capacitor, is selectively disposed, and the passive component 14 can be formed on the surface or inside of the flexible substrate 1 by surface mount (SMT) or embedded. Compared with the conventional embedded wafer-level package structure, it is easy to reduce the manufacturing yield and other defects due to assembly dimensional tolerance and horizontal alignment. 13 1335815 . ' - September 30, replace page. 5 and Figure 7 of the present invention by using the wafer 2 Placed on the side of the flexible substrate 1 . . . on the outer lip of the heat-conducting channel 11 and disposed on the other side of the flexible substrate 1 , which is advantageous for reducing the accuracy of the assembly tolerance and simplifying Process and upgrade yield, while also increasing the density of the grid array, improving the layout margin of the heavy layout, improving the overall heat dissipation efficiency, increasing the resistance to tortuosity and cracking. Although the invention has been implemented with health, the money _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The definition is prevailing. [Simplified Schematic] The simplification of the stencil-solid paste structure is a schematic diagram of bonding a wafer to a flexible substrate. The present invention is a schematic diagram of the embedded flip-flop of the embodiment encapsulated in a thermally conductive channel of a flexible substrate. "Drawing the metal plate" Fig. 3 is a schematic view showing the incorporation of the embedded semiconductor package of the first embodiment of the present invention on the other side of the flexible substrate. Fig. 4 is a schematic view showing the embedded layer of the wafer of the first embodiment of the present invention. The structure is formed by the package structure. Fig. 5 is a schematic view showing the embedded semiconductor sealing circuit of the first embodiment of the present invention and the connection terminal of ifl. , Figure 6: Her W is replaced by a structural view 14 1358115 - September 30, 100. Figure 7: Schematic diagram of the embedded semiconductor package structure of the second embodiment of the present invention. Fig. 8 is a view showing the underlying semiconductor package structure of the second embodiment of the present invention.

【主要元件符號說明】 1 軟性基板 11 導熱通道 12 導熱膠 13 電路層 14 被動元件 2 晶片 21 主動表面 211焊墊 22 背面 23 側表面 24 黏膠 3 散熱板 31 通孔 4 封裝層 41 外散線路 42 (第一)導通孔 43 第二導通孔 44 第三導通孔 5 訊號連接端 15[Main component symbol description] 1 Flexible substrate 11 Thermal conduction channel 12 Thermal paste 13 Circuit layer 14 Passive component 2 Wafer 21 Active surface 211 pad 22 Back side 23 Side surface 24 Adhesive 3 Heat sink 31 Through hole 4 Encapsulation layer 41 External dispersion line 42 (first) via hole 43 second via hole 44 third via hole 5 signal connection terminal 15

Claims (1)

100年9月30曰替換頁 十、申請專利範圍： 1. 一種欲入式半導體封裳構造，其包含： 一軟性基板，其開設一導熱通道，該導熱通道内填充一導熱 膠； 一晶片，其具有一主動表面、一背面及數個側表面，該主動 表面設有數個焊墊，該背面之一唇緣係黏合於該軟性基板一 側之導熱通道之一外唇緣上； —散熱板，其貼接於該軟性基板之另一側； -封裝層，其位於該軟性基板之一側上，且包埋該晶片之側 表面；以及 數個訊號連接端，其設於賊裝層之—外表面上，並經由至 少一外散線路電性連接至該晶片之主動表面之焊墊。 2·如申請專利範圍第！項所述之嵌入式半導體封裝構造，其中 一部份之該訊號連接端係直接紐連接至該晶片之主動表 面之焊墊。 .如申請專利細第1項所述之嵌八式半導體封鱗造，其中 該軟性基板係聚亞醯胺之基板。 《如:請專利範圍第！項所述之嵌入式半導體封裝構造，其中 SI之背面之唇緣係由一黏膠黏合於該軟性基板-侧之 導”、、通道之外唇緣上。 構造，其中 5•如申請專·圍第4項所述之嵌人式轉體 該黏膠係環氧樹脂。 &quot; 1358115 1〇0年9月30曰替換育 6·如申請專利範圍第1項所述之嵌入式 該導熱膠係銀膠。 ’ 7. 如申請專利範圍第1項所述之嵌入式半導體封裂構造，其中 該政熱板係由一黏膠貼接於該軟性基板之另一側 8. 如申請專利範圍第7項所述之嵌入式半導體封裝構造，其中 該黏膠係環氧樹脂。 / 9.如申請專利範圍第1項所述之嵌入式半導體封裝構造，其中 該散熱板另開設至少-通孔’其連通至練性基板之導熱通 道。 ’ 10.如申請專利範圍帛1項所述之嵌人式半導體封裳構造，其中 該封裝層係聚亞醯胺。 11_如申請專利細第1項所述之狀式半導體封裝構造，其中 該封裝層另包埋該晶片之主動表面。 12. 如申請專利範圍帛η項所述之嵌入式半導體封裝構造，其 中該封裳層設有數個導通孔，其貫穿該雖層，並連^於該 晶片之焊墊與訊號連接端之間。 13. 如申請專利範圍第丨項所述之嵌入式半導體封衷構造，其中 該訊號連接端選自金屬球體、金屬凸塊或針腳。 14. 如申請專利範圍第1項所述之嵌入式半導體封裝構造，其中 該軟性基板另設一電路層，該晶片之焊墊經由該外散線路電 /·生連接該軟性基板之電路層，且該線路層電性連接至，’故 17 100年9月30日替換頁 基板上之訊號連接端。 〜------------------------------------ &amp;如申請專利細$141員所述之嵌入式，稱 尹該電路層形成在該軟性基板之表面朗今’ I構造，其 中另包含數個導通孔’以電性連接該外散線路/構:其 :另：：圍第14項所述之♦入式半導髓封裝構二其 μ如申孔’性連接該電路層及訊號連接端。 •^4利範圍第Μ項所述之钱入式半導體封裝構造，其 中該軟性基_選自單層或麵之軟性基板。 19=申請專利範圍第14項所述之嵌入式铸體封裝構造，其 中該軟性基板之電路層設有至少—被動元件。 20. 如申請專利範圍第19項所述之嵌入式半導體封褒構造，其 中該被動元件係固定在該軟性基板之表面。 21. 如申請專利範圍第19項所述之嵌入式半導體封錢造，其 中該被動元件健人在該軟性基板之内部。 1358115 100年9月30日替換頁 七、指定代表圖： (一）本案指定代表圖為：第（ 5 (二)本代表圖之元件符號簡單說明: 1 軟性基板 11 12 導熱膠 2 21 主動表面 211 22 背面 23 24 黏膠 3 31 通孔 4 41 外散線路 42 5 訊號連接端 )圖。 導熱通道 晶片 焊墊 側表面 散熱板 封裝層 導通孔 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式：100 September 30 曰 页 十 、 、 、 、 、 、 、 、 、 、 、 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. The utility model has an active surface, a back surface and a plurality of side surfaces. The active surface is provided with a plurality of solder pads, and one lip of the back surface is adhered to an outer lip of one of the heat conduction channels on one side of the flexible substrate; Attached to the other side of the flexible substrate; - an encapsulation layer on one side of the flexible substrate and embedding the side surface of the wafer; and a plurality of signal connection ends disposed in the thief layer An pad on the outer surface that is electrically connected to the active surface of the wafer via at least one externally dispersing line. 2. If you apply for a patent range! The embedded semiconductor package structure of the present invention, wherein a portion of the signal connection is directly connected to the pad of the active surface of the wafer. The embedded eight-type semiconductor scale according to the first aspect of the invention, wherein the flexible substrate is a substrate of polyamine. "If: please patent scope! The embedded semiconductor package structure of the present invention, wherein the lip of the back side of the SI is bonded to the soft substrate-side guide by a glue, and the lip outside the channel. The viscose epoxy resin is embedded in the fourth embodiment of the invention. &quot; 1358115 9 曰 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 7. The embedded semiconductor sealing structure according to claim 1, wherein the political heating plate is adhered to the other side of the flexible substrate by an adhesive. The embedded semiconductor package structure of claim 7, wherein the adhesive is an epoxy resin. The embedded semiconductor package structure according to claim 1, wherein the heat dissipation plate has at least a through hole. 'The heat conduction channel connected to the practicable substrate. ' 10. The embedded semiconductor sealing structure as described in claim 1, wherein the encapsulating layer is polyamine. 11_If the patent application is fine 1 The semiconductor package structure of the above, wherein the package The layer further embeds an active surface of the wafer. 12. The embedded semiconductor package structure of claim </ RTI> wherein the sealing layer is provided with a plurality of vias extending through the layer and connected to the layer 13. The embedded semiconductor sealing structure of the wafer, wherein the signal connection end is selected from a metal sphere, a metal bump or a pin. The embedded semiconductor package structure of claim 1, wherein the flexible substrate is further provided with a circuit layer, and the solder pad of the wafer electrically connects the circuit layer of the flexible substrate via the external diffusion line, and the circuit layer Electrically connected to, 'So the signal connection on the page substrate was replaced on September 30, 1100. ~-------------------------- ---------- &amp; as claimed in the patent application of the $ 141 member, said Yin circuit layer formed on the surface of the flexible substrate Lang Yi 'I structure, which contains several vias Electrically connecting the externally dispersing line/construction: its: another:: surrounding the semi-guided semi-guided encapsulation structure described in item 14 The hole is connected to the circuit layer and the signal connection end. The invention relates to the money-in semiconductor package structure described in the above item, wherein the soft base is selected from a single layer or a surface soft substrate. The embedded cast package structure of claim 14, wherein the circuit layer of the flexible substrate is provided with at least a passive component. 20. The embedded semiconductor package structure of claim 19, wherein the passive The component is fixed on the surface of the flexible substrate. 21. The embedded semiconductor package according to claim 19, wherein the passive component is inside the flexible substrate. 1358115 Replacement page on September 30, 100. Designated representative: (1) The representative representative of the case is: (5) The simple description of the symbol of the representative figure: 1 Flexible substrate 11 12 Thermal adhesive 2 21 Active surface 211 22 Back 23 24 Adhesive 3 31 Through Hole 4 41 External Dispersion Line 42 5 Signal Connection End) Figure. Thermal Conductive Channel Wafer Pad Side Surface Heat Sink Encapsulation Layer Via Hole 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention:
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