TWI402954B - Assembly board and semiconductor module - Google Patents

Assembly board and semiconductor module Download PDF

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TWI402954B
TWI402954B TW098136231A TW98136231A TWI402954B TW I402954 B TWI402954 B TW I402954B TW 098136231 A TW098136231 A TW 098136231A TW 98136231 A TW98136231 A TW 98136231A TW I402954 B TWI402954 B TW I402954B
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Taiwan
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wiring
layer
laminated
substrate
wiring layer
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TW098136231A
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TW201027697A (en
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Hiroshi Asami
Osamu Yamagata
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Sony Corp
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    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H05K2201/10371—Shields or metal cases

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  • Production Of Multi-Layered Print Wiring Board (AREA)
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Description

裝配基板及半導體模組
本發明係關於電子零件之裝配所使用之裝配基板，與使用該裝配基板所構成之半導體模組。
近年，包含LSI(Large Scale Integration，大型積體電路)等之半導體晶片之電子零件之裝配所使用的裝配基板，被要求需高密度化與低熱阻化。先前對高密度化之要求，係出自於以LSI之多接腳化或搭載複數之半導體晶片之多晶片化(模組化)等為背景。又，先前對低熱阻化之要求，係出自於以LSI之高耗電化或最終製品裝設之情況為背景。
通常，在與多晶片化對應之裝配基板中，必須依每個搭載於裝配基板之複數之半導體晶片個別設置電極端子。因此，搭載半導體晶片之側之配線層有多層化之趨勢。因此，作為裝配基板，使用被稱為增層基板之多層配線基板(例如，參照專利文獻1)。通常，增層基板之構造係在核心基板之兩面上下對稱地積層配線層者。
又，LSI等之半導體晶片或將其封止之半導體封裝，當對裝配基板進行裝配時，例如係介隔著凸塊電性且機械性連接於裝配基板之最上層配線層。又，在專利文獻2中，其揭示之構成為將半導體晶片以晶粒黏合材料固定於焊墊，且藉由打線接合而電性連接於最上層配線層。而且，在專利文獻2中，其揭示之構成為利用增層之最上層配線層將半導體晶片所產生之熱放散至大氣中。
在將複數之配線層積層而成之增層之最上層，裝配半導體晶片或半導體封裝等之半導體裝置之情形時，在半導體晶片或半導體封裝所產生之熱之一部分會從最上層之配線層向與其連接的內層(下層)之配線層傳達。
[專利文獻1]日本專利第2739726號公報
[專利文獻2]日本特開平7-176873號公報
然而，形成於半導體裝置搭載側之複數之配線層，由於分別以樹脂等之絕緣層覆蓋，故在該部分之熱阻將變高。又，若將最上層配線層用來放散熱，則可利用於電子零件之裝配的區域之大小將受到限制。因此，在先前，無法同時滿足高密度化與低熱阻化之要求。
本發明之目的在於提供一種進行電子零件之裝配時，可同時滿足高密度化與低熱阻化之要求之構造。
本發明之裝配基板係構成為，在一側之基板面上，具備包含以積層狀態而形成之複數之配線層的積層配線部，且將上述複數之配線層中除了最上層配線層外之內層配線層之一部分以露出至外部之狀態而配置。
在本發明之裝配基板中，可使用露出至外部之內層配線層之一部分，在裝配基板上裝配冷卻構造體。又，藉由冷卻構造體之裝配，可降低利用配線層之傳熱路線之熱阻。
根據本發明，可使用露出至外部之內層配線層之一部分，在裝配基板上裝配冷卻構造體。因此，可在不限制電子零件之裝配區域之情況下，降低利用配線層之傳熱路線之熱阻。其結果，當進行電子零件之裝配時，可同時滿足高密度化與低熱阻之要求。
以下，就本發明之具體的實施形態一面參照圖式一面作詳細之說明。再者，本發明之技術範圍不限定於如下所述之實施形態，亦包含在根據發明之構成要件或其組合所得到的特定效果之範圍內付諸各種之變更或改良之形態。
<實施形態> [裝配基板之構成]
圖1係顯示本發明之實施形態之裝配基板之構成例的剖面圖。裝配基板1之大致構成為具備核心基板2與積層配線部3。核心基板2其構造為，例如在平板狀之基材4之兩面形成配線層5、6，且將該配線層5、6以貫通導通路7而電性連接。基材4係例如使用環氧玻璃等之剛性基材而構成。配線層5、6例如使用銅等之配線材料而構成。貫通導通路7之構造為，在貫通基材4之貫通孔之側壁形成導電膜，且將該貫通孔以樹脂埋入。
核心基板2係例如以如下之方法而製造者。首先，如圖2(A)所示，準備使用玻璃纖維環氧樹脂等之基材之兩面銅箔積層板31。其次，如圖2(B)所示，藉由在兩面銅箔積層板31以鑽頭進行開孔加工，而形成貫通孔32。其次，如圖2(C)所示，在兩面銅箔積層板31之貫通孔32之側壁藉由銅電鍍而形成導電膜33。
其次，如圖2(D)所示，以樹脂34埋入以導電膜33而覆蓋之貫通孔32之內部。其次，如圖2(E)所示，在樹脂34之埋入部分之兩端面藉由電解銅電鍍而形成導電膜35。其次，如圖2(F)所示，藉由蝕刻法在兩面銅箔積層板31之兩面形成銅之配線圖案36。經由以上之步驟從而得到核心基板2。
積層配線部3其構造為，分別介隔著絕緣層14而積層複數之配線層(包含上述之配線層5)。積層配線部3在核心基板2上以島狀獨立之形式形成。因此，在核心基板2之最外周部，存在著形成積層配線部3之配線層及絕緣層未共同存在之區域，及基材4之表面(上面)露出至外部之區域2a。介於複數之配線層之層間的絕緣層14之端緣部係從上側(遠離核心基板2之側)向下側(接近核心基板2之側)，以底部漸寬之階梯狀而形成。且，在該階梯狀之最低之位置(最下層)形成有配線層5，該配線層5之一部分(端緣部)5a以露出至外部之狀態而配置。配線層5相當於除了最上層配線層以外之內層配線層。內層配線層是指在積層配線部3中除了最上層之配線層以外但不僅限於最下層之配線層5之、形成於該最上層配線層之下層的配線層。露出至外部之配線層5宜為接地用之配線層。
[裝配基板之製造方法]
圖3係顯示本發明之實施形態之裝配基板之製造方法的概略圖。首先，如圖3(A)所示，準備具有基材4與配線層5、6之核心基板2。該階段之核心基板2其構造為，將根據最終製品尺寸而切割之單片之核心基板於平面上複數並列並予一體化而成的大型之基板，此處為方便起見，將切割成單片之3個核心基板予以一體化之形態表現1個核心基板2。
準備好上述核心基板2後，如圖3(B)所示，在核心基板2之其中一面形成包含感光性之樹脂之樹脂層8。在將上述之複數之配線層以積層狀態而形成之基礎上，樹脂層8係介於上下之配線層間的絕緣層者。此處，作為一例，藉由貼付負型感光性樹脂薄膜而形成樹脂層8。
其次，如圖3(C)所示，藉由將上述樹脂層8曝光及顯影，而使樹脂層8在核心基板2上以複數之島狀獨立(分離)，且在各島之樹脂層8中形成複數之通路孔9。此時，在島狀分離之樹脂層8之端緣部之外側，使成為內層配線層之最下層配線層5的一部分(端緣部)5a露出。又，從製品尺寸外形端至隔開例如僅a=200μm之位置為止，將配線層5之一部分5a引出，且使該配線層5之一部分5a露出於外部例如僅b=0.5mm。
在此階段，藉由使樹脂層8島狀獨立，在基板面內相鄰之單片尺寸之核心基板之交界部(切割之切斷位置)，使樹脂層之物理性連接(連續性)被切斷。因此，樹脂層8之熱收縮所產生之應力會分散於基板整體。其結果，可降低伴隨著樹脂層8之熱收縮所致之核心基板2整體之翹曲。
其次，如圖3(D)所示，進行將樹脂層8之表面粗化之粗化處理。在該粗化處理中，例如使用過錳酸系樹脂粗化液，在樹脂層8之表面施加平均粗度Ra=0.5μm之粗度。其後，藉由化學鍍銅將電鍍基底膜(銅之種子層)10以例如0.5μm之厚度析出。
其次，如圖3(E)所示，在核心基板2之其中一面，以覆蓋島狀分離之各個樹脂層之狀態形成抵抗膜後，藉由將該抵抗膜曝光及顯影而圖案化，藉此，形成電鍍抵抗膜11。
其次，如圖3(F)所示，在未以鍍敷抗蝕膜11覆蓋之樹脂層8之表面，以電鍍法將銅之配線圖案12以例如15μm之厚度而形成。配線圖案12成為最下層配線層5之上一層配線層。其後，除去鍍敷抗蝕膜11及電鍍基底膜10。
以下，藉由重覆上述圖3(B)~圖3(F)之處理，而如圖3(G)所示，得到具有在核心基板2上積層複數之配線層之島狀之積層配線部3的增層構造之配線基板(增層基板)。此時，在核心基板上每積層1個配線層，便會將樹脂層8之面積階段性縮小，藉此，使介於複數之配線層之層間的絕緣層之端緣部形成階梯狀。樹脂層8之縮小係在沿著基板面方向之方向(圖之左右方向)，例如，於每1階將樹脂層8之形成長度兩側各縮短c=200μm而予實現。
其後，如圖3(H)所示，依每個積層配線部3之島，將核心基板2藉由進行切割加工或槽刨加工而切斷，藉此將核心基板2切割成單片。藉此，形成在核心基板2之其中一面上包含複數之配線層之積層配線部3，且可得到內層配線層5之一部分5a露出至外部之構造之裝配基板1。在該裝配基板1中，形成於核心基板2之上面側之配線層之層數，與形成於核心基板2之下面側之配線層之層數相異。具體而言，形成於核心基板2之上面側之配線層之層數係多於形成於同下面側之配線層之層數。因此，以核心基板2為中心來看，其構造為配線層之積層狀態為上下非對稱。
[半導體模組之構成]
圖4係顯示本發明之實施形態之半導體模組之構成例的剖面圖。半導體模組20其構成為具備上述之裝配基板1，與裝配於該裝配基板1之半導體裝置。作為半導體裝置，裝配有半導體晶片21與半導體封裝22。半導體晶片21與半導體封裝22係在形成於裝配基板1之其中一面上之複數之配線層上，與晶片零件23共同裝配。
半導體晶片21以裸晶之狀態藉由覆晶方式而裝配。又，半導體晶片21係電性且機械性連接於設置於裝配基板1之複數之配線層中最上層配線層。半導體封裝22係例如以樹脂封止未圖示之半導體晶片(例如記憶體用LSI晶片)之BGA(球柵陣列)類型之封裝構造。半導體封裝22介隔著焊錫球等之外部連接端子，與上述半導體晶片同樣，電性且機械性連接於最上層配線層。半導體封裝22在裝配基板1之基板面內以與半導體晶片21相鄰之位置關係而配置。晶片零件23係包含例如晶片電容器等被動零件。晶片零件23與上述半導體晶片21及半導體封裝22同樣，電性且機械性連接於最上層配線層。
又，在裝配基板1上，作為冷卻構造體之一例，裝配有冷卻鰭片24。冷卻鰭片24係在上述之露出於外部之最下層配線層5之一部分5a，例如介隔著包含熱傳導性之接著劑之接著層25而安裝。因此，冷卻鰭片24以熱連接於配線層5之一部分5a之狀態而裝配於裝配基板1。作為熱傳導性之接著劑，例如可使用使氧化矽、金屬粉末、陶瓷粉末等之無機填充劑分散於環氧樹脂等之有機材料中者。
又，作為冷卻鰭片24，可使用例如在熱傳導性高之金屬材料即銅之構造體的表面施加鍍鎳處理者。冷卻鰭片24其構造為，在圖之縱深方向將複數之鰭片部排列成梳齒狀。冷卻鰭片24係在裝配基板1上以從兩側包夾複數之配線層之島的位置關係而裝配2個。該等2個冷卻鰭片24係以將複數之配線層之島包夾於中間而相互對向之狀態配置。
冷卻構造體不僅限於冷卻鰭片24，例如亦可為散熱器。又，在裝配基板1上，除冷卻鰭片24等之冷卻構造體之外，亦可使用露出於外部之內層配線層5之一部分5a來裝配未圖示之電子零件。
[半導體模組之製造方法]
首先，如圖5所示，在以上述之製造方法所獲得之裝配基板1上裝配半導體晶片21、半導體封裝22及晶片零件23。其次，如上述圖4所示，在露出於外部之內層配線層5之一部分5a，介隔著接著層25而安裝冷卻鰭片24。藉此製得半導體模組20。該半導體模組20例如圖6所示，其係介隔著作為外部連接端子而形成於核心基板2之下面側之凸塊(例如焊錫凸塊)26而裝配於母板27。
在本發明之實施形態中，作為裝配基板1之構成，係使構成積層配線部3之複數之配線層中除了最上層配線層以外之內層配線層5之一部分5a露出至外部。因此，可利用配線層5之一部分5a，將冷卻鰭片24等之冷卻構造體裝配於裝配基板1上。因此，可無需限制電子零件之裝配區域，而降低利用配線層之傳熱路線之熱阻。其結果，在進行電子零件之裝配時，可同時滿足高密度化與低熱阻化之要求。
又，由於在核心基板2上將積層配線部3獨立形成為島狀，故將裝配基板1從更大型之基板切割成單片時，可在大型之核心基板上相鄰之裝配基板之間，將積層配線部3之物理性連接切斷。因此，可減少隨著積層配線部3之絕緣層14之熱收縮而在大型之基板中所產生之翹曲。
又，藉由將露出於外部之配線層5作為接地用之配線層，可獲得下述之效果。即，接地用之配線層係以在複數之配線層中較其他配線層更大之面積而形成。因此，基於裝配例如上述之冷卻構造體之目的，使接地用之配線層之一部分露出至外部，藉此，可有效地進行對冷卻構造體之熱傳導。
又，由於將介於複數之配線層之層間之絕緣層14之端緣部以階梯狀形成，故可使除了最上層配線層以外但不僅是最下層配線層之任意之內層配線層之端緣部引出到絕緣層之外側並露出至外部。
又，裝配基板1之配線層之積層狀態(積層數)為上下不對稱之構造。因此，在裝配基板1之上面側，根據裝配於其之半導體裝置(21、22)之端子之數量及配置，可形成所需層數之配線層。又，在裝配基板1之下面側，根據對母板27之裝配所需的端子數量及配置，可形成所需層數之配線層。藉此，相較於在裝配基板上下對稱地形成配線層之情況，可減少裝配於母板之側(下面側)之配線層之層數，進而使配線步驟數削減，而實現裝配基板之低成本化。
又，作為半導體模組之構成，其係在裝配基板1上裝配半導體晶片21或半導體封裝22等之半導體裝置，且在配線層5之一部分5a以熱連接之狀態將冷卻鰭片24裝配於裝配基板1。因此，可將半導體裝置(21、22)所產生之熱經由內層配線層5而有效地傳導至冷卻鰭片24。
[第1變形例]
圖7係顯示本發明之實施形態之裝配基板及半導體模組之第1變形例的剖面圖。在圖示之半導體模組20中，使最下層配線層5之一部分5a露出至外部，使用該露出部分在裝配基板1上裝配冷卻構造體28。冷卻構造體28以門型而形成。又，在裝配基板1上裝配有3個半導體封裝22。各個半導體封裝22之封裝面，分別介隔著包含熱傳導性之樹脂之樹脂層29而接著於冷卻構造體28。
在上述構成之半導體模組20中，作為各個半導體封裝22所產生之熱之傳達路線，確保有經由配線層5之路線，與經由接著層29之路線。因此，相較於確保僅經由配線層5之路線之情況，可將各個半導體封裝22所產生之熱有效地傳導至冷卻構造體28。
[第2變形例]
圖8係顯示本發明之實施形態之裝配基板及半導體模組之第2變形例的剖面圖。在圖示之半導體模組20中，使最下層配線層5之一部分5a露出至外部，使用該露出部分在裝配基板1上裝配冷卻鰭片24。又，將最上層之下一層配線層15之一部分15a以露出至外部之狀態配置，使用該露出部分在裝配基板1裝配門型之冷卻構造體16。該冷卻構造體16係以將裝配於2個半導體封裝22之間之半導體封裝17圍住的狀態配置。又，半導體封裝17之封裝面介隔著包含熱傳導性之樹脂之樹脂層18而接著於冷卻構造體16。因此，冷卻構造體16成為與半導體封裝17熱連接之狀態。
在上述構成之半導體模組20中，例如在半導體封裝17中將發熱量多之半導體晶片封止之情況時，可將該半導體封裝17所產生之熱有效地傳導至冷卻構造體16。此外，可減少半導體封裝17所產生之熱對周邊之半導體封裝22之影響。
1．．．裝配基板
2．．．核心基板
3．．．積層配線部
4．．．基材
5、6．．．配線層
20．．．半導體模組
21．．．半導體晶片
22．．．半導體封裝
24．．．冷卻鰭片(冷卻構造體)
圖1係顯示本發明之實施形態之裝配基板之構成例之剖面圖；
圖2(A)-(F)係說明核心基板之製造方法之一例；
圖3(A)-(H)係顯示本發明之實施形態之裝配基板之製造方法的概略圖；
圖4係顯示本發明之實施形態之半導體模組之構成例的剖面圖；
圖5係顯示本發明之實施形態之半導體模組之製造方法的剖面圖；
圖6係顯示本發明之實施形態之半導體模組之裝配例的剖面圖；
圖7係顯示本發明之實施形態之裝配基板及半導體模組之第1變形例的剖面圖；及
圖8係顯示本發明之實施形態之裝配基板及半導體模組之第2變形例的剖面圖。
1．．．裝配基板
2．．．核心基板
2a．．．露出區域
3．．．積層配線部
4．．．基材
5、6．．．配線層
5a．．．配線層之一部分
14．．．絕緣層

Claims (4)

  1. 一種裝配基板，其包含：配線層，其係配置於基板之兩面；及貫通導通路，其係將配置於該兩面之配線層加以電性連接；且於前述基板之其中一面所配置之配線層係形成島狀獨立之積層配線部，該積層配線部包含自最上層導通至最下層之部分，且包括以積層狀態而形成之複數個配線層；該積層配線部之除了最上層配線層以外的內層之配線層之一部分係露出於外部；該內層之配線層係接地用之配線層；前述積層配線部之配線層之積層狀態與於前述基板之另一面所配置之配線層之積層狀態係相對於前述基板為上下非對稱之構造。
  2. 如請求項1之裝配基板，其中介於前述積層配線部之前述複數之配線層之層間之絕緣層的端緣部係形成為階梯狀。
  3. 一種半導體模組，其包含：裝配基板；冷卻構造體，其係以熱連接於該裝配基板所包含之積層配線部之一部分的狀態而裝配於前述裝配基板；及半導體裝置，其係以電性連接於前述積層配線部上的狀態而裝配於前述裝配基板；且 前述裝配基板包含：配線層，其係配置於基板之兩面；及貫通導通路，其係將配置於該兩面之配線層加以電性連接；且於前述基板之其中一面所配置之配線層係形成島狀獨立之前述積層配線部，該積層配線部包含自最上層導通至最下層之部分，且包括以積層狀態而形成之複數個配線層；前述積層配線部之除了最上層配線層以外的內層之配線層之一部分係露出於外部；該內層配線層係接地用之配線層；前述積層配線部之配線層之積層狀態與於前述基板之另一面所配置之配線層之積層狀態係相對於前述基板形成上下非對稱之構造；前述冷卻構造體係連接於前述積層配線部之前述內層之配線層之一部分的露出於外部的部分。
  4. 如請求項3之半導體模組，其中前述冷卻構造體係以門型覆蓋前述積層配線部之方式而配置；前述半導體裝置係介隔著包含熱傳導性樹脂之樹脂層而接著於前述冷卻構造體。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102223753B (zh) * 2010-04-16 2013-08-28 富葵精密组件(深圳)有限公司 电路板及其制作方法
CN103022011B (zh) * 2011-09-23 2015-10-07 讯芯电子科技（中山）有限公司 半导体封装结构及其制造方法
US20130334168A1 (en) * 2012-06-16 2013-12-19 Leading Tech Communications Inc. Manufacturing method of circuit pattern
TW201507555A (zh) * 2013-08-09 2015-02-16 Bridge Semiconductor Corp 具有複合芯層及雙增層電路之線路板
JP6418757B2 (ja) * 2014-03-03 2018-11-07 新光電気工業株式会社 配線基板及びその製造方法と半導体装置
JP2016131245A (ja) * 2015-01-13 2016-07-21 デクセリアルズ株式会社 多層基板
KR20170002830A (ko) * 2015-06-30 2017-01-09 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
JP6251420B1 (ja) * 2016-05-30 2017-12-20 三菱電機株式会社 電子モジュールおよび電子モジュールの製造方法
KR102173615B1 (ko) * 2018-07-19 2020-11-03 스템코 주식회사 다층 회로 기판 및 그 제조 방법
EP3913661A4 (en) * 2019-01-16 2022-03-30 Toppan Printing Co., Ltd. HOUSING SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
JP2021108320A (ja) * 2019-12-27 2021-07-29 京セラ株式会社 印刷配線板及び印刷配線板の製造方法
JP7065908B2 (ja) * 2020-06-16 2022-05-12 株式会社日立製作所 ストレージ装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317582A (ja) * 1998-02-16 1999-11-16 Matsushita Electric Ind Co Ltd 多層配線基板およびその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61124196A (ja) * 1984-11-20 1986-06-11 松下電器産業株式会社 多層配線板
US5136471A (en) * 1987-02-26 1992-08-04 Nec Corporation Laminate wiring board
JPH02101794A (ja) * 1988-10-11 1990-04-13 Matsushita Electric Ind Co Ltd 多層プリント配線板
JP2739726B2 (ja) 1990-09-27 1998-04-15 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層プリント回路板
JP3207248B2 (ja) * 1992-06-24 2001-09-10 株式会社東芝 半導体装置
US5459368A (en) * 1993-08-06 1995-10-17 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device mounted module
JP3153062B2 (ja) 1993-12-17 2001-04-03 イビデン株式会社 電子部品搭載用基板
JP3982876B2 (ja) * 1997-06-30 2007-09-26 沖電気工業株式会社 弾性表面波装置
JP2000156564A (ja) * 1998-11-20 2000-06-06 Nec Corp プリント配線板及びその製造方法
JP2001111237A (ja) * 1999-10-04 2001-04-20 Mitsubishi Electric Corp 多層プリント基板及び電子機器
JP3783493B2 (ja) * 1999-11-04 2006-06-07 三菱マテリアル株式会社 積層セラミック基板及びこれを用いたパワーモジュール用基板
JP2002151634A (ja) * 2000-11-08 2002-05-24 Nissan Motor Co Ltd 基板放熱装置
JP3817453B2 (ja) * 2001-09-25 2006-09-06 新光電気工業株式会社 半導体装置
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
JP2003298234A (ja) * 2002-04-01 2003-10-17 Hitachi Cable Ltd 多層配線板及びその製造方法、ならびに配線基板
JP2005064357A (ja) * 2003-08-19 2005-03-10 Fujikura Ltd 多層配線板およびその製造方法
US20060180344A1 (en) * 2003-01-20 2006-08-17 Shoji Ito Multilayer printed wiring board and process for producing the same
US20050057906A1 (en) * 2003-09-12 2005-03-17 Seiichi Nakatani Connector sheet and wiring board, and production processes of the same
CN100370580C (zh) * 2004-03-29 2008-02-20 雅马哈株式会社 半导体晶片及其制造方法
JP2005347353A (ja) * 2004-05-31 2005-12-15 Sanyo Electric Co Ltd 回路装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317582A (ja) * 1998-02-16 1999-11-16 Matsushita Electric Ind Co Ltd 多層配線基板およびその製造方法

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