CN108447857A - 三维空间封装结构及其制造方法 - Google Patents

三维空间封装结构及其制造方法 Download PDF

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Publication number
CN108447857A
CN108447857A CN201810327490.4A CN201810327490A CN108447857A CN 108447857 A CN108447857 A CN 108447857A CN 201810327490 A CN201810327490 A CN 201810327490A CN 108447857 A CN108447857 A CN 108447857A
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electronic component
electronic components
electronic
conductive pattern
inductance element
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CN108447857B (zh
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吕保儒
吴明佳
吕绍维
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Cyntec Co Ltd
Qiankun Science and Technology Co Ltd
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Qiankun Science and Technology Co Ltd
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Abstract

本发明提供一种三维空间封装结构及其制造方法，其可达到较高的内部空间使用，因此可降低电子封装结构的尺寸。该三维空间封装结构包含一第一电子元件、复数个第二电子元件和复数个导电图案。该第一电子元件具有一上表面和一下表面。该复数个第二电子元件配置在该第一电子元件的该上表面上方。该复数个第一导电图案配置在该复数个第二电子元件上方，用以电性连接该复数个第二电子元件和该第一电子元件。

Description

三维空间封装结构及其制造方法
本发明是申请日为2014年12月16日，申请号为201410781471.0，发明名称为“三维空间封装结构及其制造方法”的中国发明专利申请的分案申请。
技术领域
本发明涉及一种封装结构，特别涉及一种三维空间封装结构。
背景技术
电子封装结构凭借复杂的封装制程所形成。不同的电子封装结构具有不同的电性和散热能力，因此设计者根据设计需求可选择具有理想电性和散热能力的电子封装结构。
图1例示传统电子封装结构100的示意图。参阅图1，传统电子封装结构100包含一印刷电路板(PCB)110和复数个电子元件120。电子元件120配置在印刷电路板110的表面112上且电性连接印刷电路板110。印刷电路板110具有从印刷电路板110的另一面114向外延伸的复数个引脚(pin)116以电性连接一电子装置，例如主机板(motherboard)(未图示)。
图2例示另一个传统电子封装结构200的剖面示意图。参阅图2，传统电子封装结构200包含一线路基板210和复数个电子元件220。电子元件220配置在线路基板210的表面212上且通过打线(wire bond)技术、覆晶(flip-chip)结合技术或表面粘着技术(surfacemount technology)电性连接线路基板210。此外，传统电子封装结构200通过焊料胶(solder paste)或复数个焊球(solder ball)(未图示)可电性连接一电子装置(例如主机板)(未图示)。
应该要注意的是，传统电子封装结构100的电子元件120全配置在印刷电路板110的表面112上，且传统电子封装结构200的电子元件220全配置在线路基板210的表面212上。因此，在传统电子封装结构100、200中，印刷电路板110和线路基板210具有较低的空间使用，使得传统电子封装结构100、200具有较大的尺寸。
传统上，单列直插式封装(SIP:Single Inline Package)、栅格阵列(LGA:LandGrid Array)和球格阵列(BGA:Ball Grid Array)广泛使用于封装结构中，例如电力元件/模块(像用于个人电脑、笔记型电脑、伺服机等等的直流转直流转换器)的封装结构。然而，单列直插式封装需要焊接、大面积和手动点胶；栅格阵列和球格阵列需要用于内部元件电性连接的焊接。因此，这种封装具有许多缺点，包含：较高的成本(大面积和/或手动点胶、焊接)、较低的可靠度(焊料融化)和不佳的热散逸。
因此，本发明提出了一封装结构及其制造方法以克服上述的缺点。
发明内容
本发明的一个目的是提供一种三维空间封装结构及其制造方法，以降低电子模块的尺寸。
为实现上述目的，本发明采用的技术方案是：
一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；以及
一连接结构，配置在该第一电子元件的该上表面上方，用以包覆该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个第一导电图案，其中该复数个第一导电图案配置在该复数个第二电子元件上方，用以电性连接该复数个第二电子元件以及该第一电子元件。
所述的三维空间封装结构：一部分的该复数个第一导电图案电性连接该复数个第二电子元件中的至少两个电子元件。
所述的三维空间封装结构：该第一电子元件为一电感。
所述的三维空间封装结构：该电感为一低温共烧陶瓷(LTCC)电感。
所述的三维空间封装结构：一绝缘层配置在该第一电子元件上以形成在该复数个第二电子元件上方的一实质水平面，其中该复数个第一导电图案配置在该实质水平面上方。
所述的三维空间封装结构：该复数个第二电子元件的至少一接点配置在该实质水平面上。
所述的三维空间封装结构：该复数个第二电子元件的所有接点配置在该实质水平面上。
所述的三维空间封装结构：至少一垫片配置在该连接结构的上表面上，用以连接外部电路。
所述的三维空间封装结构：该第一电子元件的该上表面包含一凹洞，其中该复数个第二电子元件中至少一个配置在该凹洞中。
所述的三维空间封装结构，进一步包含至少一第三电子元件和一环氧模造物层，其中该至少一第三电子元件配置在该第一电子元件旁，且该环氧模造物层包覆至少一部分的该第一电子元件和该至少一第三电子元件。
所述的三维空间封装结构：该至少一第三电子元件包含一电容。
所述的三维空间封装结构：各个该第二电子元件为一电容、一电阻、一二极管、一电晶体、一裸晶片或一集成电路。
所述的三维空间封装结构：该连接结构的该至少一绝缘层中每一层由ABF(Ajinomoto Build-up Film)制成。
所述的三维空间封装结构：进一步包含一环氧模造物层，其中该环氧模造物层配置在该第一电子元件的该上表面上，其中该复数个第二电子元件和一第二导电图案配置在该环氧模造物层上，其中该第二导电图案电性连接该复数个第一导电图案。
所述的三维空间封装结构：该三维空间封装结构为一直流对直流转换器或一电力模块。
所述的三维空间封装结构：该第一电子元件为一电感。
一种制造三维空间封装结构的方法，包含：
(a)提供具有一上表面和一下表面的一第一电子元件；
(b)在该第一电子元件的该上表面上方配置复数个第二电子元件；以及
(c)在该第一电子元件的该上表面上方形成一连接结构，用以包覆该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个导电图案，其中该复数个导电图案配置在该复数个第二电子元件上方，用以电性连接该复数个第二电子元件以及该第一电子元件。
所述的方法：在步骤(c)中，该至少一绝缘层包含一ABF层，其中该ABF层被压至该第一电子元件的该上表面，用以包覆该复数个第二电子元件。
所述的方法：步骤(c)包含一薄膜制程，以形成该复数个导电图案。
一种制造复数个三维空间封装模块的方法，包含：
(a)在一载板上提供复数个第一电子元件，其中各个该第一电子元件具有一上表面和一下表面；
(b)在各个该第一电子元件的该上表面上方配置复数个第二电子元件；
(c)在各个该第一电子元件上的该复数个第二电子元件上方形成复数个导电图案，以电性连接该复数个第二电子元件及该第一电子元件；以及
(d)形成该复数个三维空间封装模块，其中各个该三维空间封装模块分别包含一对应的第一电子元件和配置在该对应的第一电子元件上的该复数个第二电子元件。
所述的方法：该载板包含胶带、治具或环氧模造物中至少一个。
与现有技术相比较，本发明具有的有益效果是：1.散热和导电具有较佳的性能；2.凭借形成复数个导电图案和使用薄膜技术和制程(凭借具有极薄的多个导电图案的一导电图案群以连接所有的导电元件)以达到较小的尺寸；3.较低成本、小尺寸和较佳的结合强度/可靠度。
在参阅接下来的段落及所附图式所描述的本发明的实施例及详细技术之后，该技术领域具有通常知识者便可了解本发明的技术特征及实施态样。
附图说明
图1例示传统电子封装结构的示意图；
图2例示另一个传统电子封装结构的剖面示意图；
图3a和图3b根据本发明的第一实施例例示一三维空间封装结构的剖面示意图；
图3c至图3e例示另一三维空间封装结构的剖面示意图；
图4a至图4c根据本发明的第一实施例例示一三维空间封装结构的制造方法；
图5a至图5c根据本发明的第二实施例例示一三维空间封装结构的制造方法。
附图标记说明：100传统电子封装结构；110印刷电路板；112表面；114另一面；116引脚；120电子元件；200传统电子封装结构；210线路基板；212表面；220电子元件；300三维空间封装结构；310第二电子元件；320第一电子元件；320a上表面；320b下表面；320c凹洞；320C侧表面；330连接结构；331导孔；332线路层；333ABF；351贯穿孔；352垫片；353第三电子元件；356第一绝缘材料；410第二电子元件；420第一电子元件；420a上表面；420b下表面；421电极；430连接结构；510第二电子元件；510a分离式电子元件；520第一电子元件；520a上表面；520b下表面；520c胶带；530连接结构；531导孔；532线路层。
具体实施方式
本发明的详细说明于随后描述，这里所描述的较佳实施例是作为说明和描述的用途，并非用来限定本发明的范围。
下面的多个实施例揭示一三维空间封装模块和用于制造该三维空间封装模块的一方法。三维空间封装系指一封装结构，在该封装结构上的导电元件不仅建构成为平面且在高度上堆积，用以增进空间效率。
本发明的一个实施例揭示了一三维空间封装结构，该三维空间封装结构包含：一第一电子元件，具有一上表面和一下表面；复数个第二电子元件，配置在该第一电子元件的该上表面上方；以及一连接结构，配置在该第一电子元件的该上表面上方，用以包覆(encapsulate)该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个导电图案，其中该复数个导电图案配置在该复数个第二电子元件上方，用以电性连接该复数个第二电子元件和该第一电子元件。
图3a和图3b根据本发明的第一实施例例示一三维空间封装结构的剖面示意图。参阅图3a和图3b，三维空间封装结构300包含配置在第一电子元件320的上表面上方的一连接结构330，用以包覆复数个第二电子元件310；第一电子元件320具有一上表面320a和一下表面320b；复数个第二电子元件310(如图3a和图3b所示的三个电子元件)配置在第一电子元件320的上表面320a上方；复数个导电图案(例如复数个导孔331和线路层332)配置在复数个第二导电元件310上方，用以电性连接复数个第二导电元件310和第一电子元件320。在一个实施例中，复数个第二电子元件310中至少两个通过复数个导电图案(例如复数个导孔331和线路层332)电性连接。换句话说，连接结构330配置在第一电子元件的上表面上方以包覆复数个第二电子元件，其中该连接结构330包含导电图案(例如复数个导孔331和线路层332)以电性连接复数个第二电子元件310和第一电子元件320，其中至少一绝缘层(例如ABF(Ajinomoto Build-up Film)333)用来分离复数个导电图案。在一个实施例中，ABF 333凭借压至以包覆复数个第二电子元件310而附在第一电子元件320的上表面。请注意可使用非ABF 333的其它绝缘材料，且不同层可包含不同的绝缘材料。
导电图案可凭借任何适合的图案化制程(例如黄光制程)形成。导电图案可包含在连接结构的上表面上的一些垫片，用以连接其它电路。导电图案连接复数个第二电子元件310的至少一接点至三维空间封装结构300的上表面上的垫片，用以连接一外部电路，例如印刷电路板。在一个实施例中，各个第二电子元件310的一或多个接点配置在对应电子元件的上表面上。换句话说，各个第二电子元件310的所有或一部分接点面向印刷电路板。
在一个实施例中，一绝缘层配置在第一电子元件320上以形成在复数个第二电子元件310上方的一实质水平面，其中导电图案配置在该实质水平面上方。
为了方便在复数个第二电子元件310上方施加图案化制程，复数个第二电子元件310在线路基板上的投影面积可小于第一电子元件320在线路基板上的投影面积。较佳来说，第一电子元件320的至少一接点和复数个第二电子元件310的至少一接点面向线路基板且通过导电图案电性连接线路基板，该导电图案形成在复数个第二电子元件310的至少一接点朝上的时(第一电子元件320的至少一接点可朝上)。
为了在第一电子元件320的上表面320a上使第一电子元件320的至少一接点和复数个第二电子元件310达到最佳的配置，复数个第二电子元件310配置在第一电子元件320的上表面320a的中央，且第一电子元件320的至少一接点配置在第一电子元件320的上表面320a的周围。在一个实施例中，第一电子元件320可具有一第一接点(未图示)和一第二接点(未图示)；该第一接点配置在上表面320a的一第一边缘且该第二接点配置在上表面320a的一第二边缘(该第二边缘相对于该第一边缘)。
第一电子元件320可包含在其中之一凹洞(cavity)(未图示)，且复数个第二电子元件310可配置在该凹洞中以进一步降低三维空间封装结构的高度。凹洞系以不同的方式实现：在一个实施例中，凹洞系形成于第一电子元件320的内部；在另一个实施例中，凹洞的一边和第一电子元件320的一边对齐；在更另一个实施例中；凹洞的两边分别和第一电子元件320的两边对齐。
为了在第一电子元件320的上表面320a上使第一电子元件320的至少一接点和复数个第二电子元件310达到最佳的配置，凹洞配置在第一电子元件320的上表面320a的中央，复数个第二电子元件310配置在凹洞中，且第一电子元件320的至少一接点配置在凹洞周围。在一个实施例中，第一电子元件320可具有一第一接点(未图示)和一第二接点(未图示)；该第一接点配置在凹洞的一第一侧且该第二接点配置在在凹洞的一第二侧(该第二侧相对于该第一侧)。
图3c至图3e例示另一三维空间封装结构的剖面示意图。导电图案可通过在第一电子元件320的侧表面320C旁的复数个贯穿孔351延伸至第一电子元件320的下表面320b以在第一电子元件320的下表面320b上形成复数个垫片352或以电性连接配置第一电子元件320的下表面320b上的一第三电子元件353。贯穿孔351可形成在第一电子元件320的侧表面320C旁的第一绝缘材料356中。在一个实施例中，第一绝缘材料356和分离导电图案的第二绝缘材料333可相同。较佳来说，第一绝缘材料356和第二绝缘材料333可由ABF(AjinomotoBuild-up Film)制成。在一个实施例中，第一绝缘材料356和分离导电图案的第二绝缘材料333可不同。选择性地，第一绝缘材料356和第二绝缘材料333的边界可对齐第一电子元件320的上表面320a，但本发明并不局限此案例。较佳来说，第一绝缘材料356可由环氧模造物(EMC/epoxy molding compound)制成，且第二绝缘材料333可由ABF制成。
三维空间封装结构300一般应用在电压调节器模块、电力模块、网路转接器、绘图处理单元、直流对直流转换器、负载点转换器。第一电子元件320可为一分离式(discrete)电子元件。分离式电子元件可为一电感或任何其它电子元件(例如电容)。电感可为一低温共烧陶瓷(LTCC)型电感或任何其它种电感。如图3b所示，第一电子元件320的上表面320a可进一步包含一凹洞320c，且该复数个第二电子元件310中至少一个配置在该凹洞320c中以增加空间效率。
各个第二电子元件310可为一逻辑控制元件、一驱动元件或一被动元件。被动元件可为一电容、具有较小电感值的一电感或一电阻。各个第二电子元件310可为一电力元件，例如金氧半场效电晶体(MOSFET)、绝缘闸双极电晶体(IGBT)、一裸晶片、一集成电路或一二极管。
复数个导电图案可凭借薄膜技术(例如黄光、溅镀、电镀或化学气相沉积制程)形成。复数个导电图案也可以多层的型式存在。如图3a所示，复数个导电图案包含复数个导孔331和线路层332。复数个导电图案的导孔331和线路层332可提供所需的电性连接。在一个实施例中，绝缘层使用ABF 333以结合第一电子元件320、复数个第二电子元件310和复数个导电图案330为一完整的本体。
请注意可使用非ABF 333的其它绝缘材料，且不同层可包含不同的绝缘材料。
换句话说，一连接结构配置在第一电子元件的上表面上方，用以包覆复数个第二电子元件，其中该连接结构包含用以电性连接复数个第二电子元件和第一电子元件的复数个导电图案(例如复数个导孔和线路层)和用以分离复数个导电图案的至少一绝缘层(例如ABF)。
在一个实施例中，三维空间封装结构300进一步包含配置在连接结构330中之一屏蔽层(未图示)，用于电磁干扰屏蔽。在一个实施例中，一环氧模造物层配置在第一电子元件的上表面上，其中复数个第二电子元件和一些导电图案可配置在该环氧模造物层上，其中连接结构330可配置在该环氧模造物层上以包覆复数个第二电子元件和该些导电图案，其中该些导电图案可电性连接在连接结构330中的导电图案。在一个实施例中，至少一垫片可配置在连接结构330的上表面上，用以连接一外部印刷电路板。
由于本发明的实施例的原因，对于线路和元件连接的强度和可靠度优于传统的焊接和打线。可缩短布线距离以降低电阻值并提升效率；此外，可进一步降低整体封装结构的高度。
图4a至图4c根据本发明的第一实施例例示一三维空间封装结构的制造方法。参阅图4a，说明提供具有一上表面420a和一下表面420b的一第一电子元件420的步骤。第一电子元件可为一分离式电子元件。分离式电子元件可为一电感或任何其它电子元件(例如电容)。电感可为一低温共烧陶瓷(LTCC)型电感或任何其它种电感。第一电子元件420的上表面420a可露出第一电子元件420的电极421作为电性连接之用。为了大量生产和降低成本，复数个第一电子元件
可同时提供且凭借胶带(tape)(或治具(fixture))(未图示)或环氧模造物(未图示)以矩阵(matrix)配置。
参阅图4b，说明在该第一电子元件420的该上表面420a上方配置复数个第二电子元件410的步骤。第一电子元件420可包含一凹洞(未图示)，且复数个第二电子元件410中至少一个配置在该凹洞中以进一步降低三维空间封装结构的高度。在此步骤中，焊接、晶片附着膜或晶片结合浆可用于各个第二电子元件410的附着/定位。
各个第二电子元件410可为一逻辑控制元件、一驱动元件或一被动元件。被动元件可为一电容、具有较小电感值的一电感或一电阻。各个第二电子元件410可为一电力元件，例如金氧半场效电晶体、绝缘闸双极电晶体、一集成电路或一二极管。
参阅图4c，说明在该复数个第二电子元件410上方配置复数个导电图案(在连接结构430中)以电性连接该复数个第二电子元件410和该第一电子元件420的步骤。
在连接结构430中的复数个导电图案可凭借薄膜技术(例如黄光、溅镀、电镀或化学气相沉积制程)形成。在连接结构430中的复数个导电图案也可以多层的型式配置(该多层具有由不同型式材料制成的多个绝缘层)且建构成不同功能。雷射可用来在复数个导电图案中形成复数个导孔。线路层和导电材料可凭借电镀制程配置。复数个导电图案的导孔和线路层可提供所需的电性连接；绝缘层可使用ABF以结合第一电子元件420、复数个第二电子元件410和复数个导电图案为一完整的本体。复数个导电图案可进一步包含一屏蔽层(未图示)，用于电磁干扰屏蔽。连接结构430可进一步包含的一环氧模造物层(未图示)作为结合之用。
如图4c所示，可包含一切割制程(所示为破折线)以互相分离单一封装模块。
图5a至图5c根据本发明的第二实施例例示一三维空间封装结构的制造方法。此实施例和第一实施例的差别在于各个三维空间封装结构模块进一步包含在第一电子元件520旁的至少一分离式电子元件510a。导电图案530将分离式电子元件510a的至少一接点引导至三维空间封装结构的上表面，用以结合至线路基板。分离式电子元件510a的至少一接点可配置在分离式电子元件510a的上表面上。换句话说，分离式电子元件510a的至少一接点面向线路基板。参阅图5a，说明提供具有一上表面520a和一下表面520b的一第一电子元件520的步骤。第一电子元件520可为一分离式电子元件。分离式电子元件可为一电感或任何其它电子元件(例如电容)。电感可为一低温共烧陶瓷(LTCC)型电感或任何其它种电感。第一电子元件520的上表面520a可露出第一电子元件520的电极(未图示)作为电性连接之用。为了大量生产和降低成本，复数个电感可同时提供且凭借胶带(或治具)520c或环氧模造物(未图示)以矩阵配置。
参阅图5b，说明在该第一电子元件520的该上表面520a上方配置复数个第二电子元件510，且在该第一电子元件520旁配置至少一第二电子元件510a(例如电容)。第一电子元件520可包含一凹洞(未图示)，且复数个第二电子元件510中至少一个配置在该凹洞中以进一步降低三维空间封装结构的高度。在此步骤中，焊接/晶片附着膜/晶片结合浆可用于各个第二电子元件510的附着/定位。
各个第二电子元件510、510a可为一逻辑控制元件、一驱动元件或一被动元件。被动元件可为一电容、具有较小电感值的一电感或一电阻。各个第二电子元件510、510a可为一电力元件，例如金氧半场效电晶体、绝缘闸双极电晶体、一集成电路、一裸晶片或一二极管。
参阅图5c，说明在该复数个第二电子元件510、510a上方配置复数个导电图案(在一连接结构530中)以电性连接该复数个第二电子元件510、510a和该第一电子元件520的步骤。
复数个导电图案(例如复数个导孔531和线路层532)可凭借薄膜技术(例如黄光、溅镀、电镀或化学气相沉积制程)形成。复数个导电图案也可以多层的型式配置。雷射可用来形成复数个导孔531。线路层532可凭借电镀制程配置。导孔531和线路层532可提供所需的电性连接；绝缘层(例如ABF)可结合第一电子元件520、复数个第二电子元件510、510a和复数个导电图案为一完整的本体。复数个导电图案可进一步包含一屏蔽层(未图示)，用于电磁干扰屏蔽。连接结构530可进一步包含一环氧模造物层(未图示)作为结合之用。
如图5c所示，可包含一切割制程(所示为破折线)以互相分离单一封装模块。在本发明中，制造方法不局限于电感，但也不局限于电感元件。
从上面多个实施例的叙述中，本发明的结构及其制造方法可提供许多优点，包含：1.散热和导电具有较佳的性能；2.凭借形成复数个导电图案和使用薄膜技术和制程(凭借具有极薄的多个导电图案的一导电图案群以连接所有的导电元件)以达到较小的尺寸；3.较低成本、小尺寸和较佳的结合强度/可靠度。
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离权利要求所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本发明的保护范围之内。

Claims (13)

1.一种三维空间封装结构，其特征在于，包含：
一第一电感元件，具有一上表面和一下表面，该第一电子元件的该上表面包含一凹洞；
复数个第二电子元件，配置在该第一电感元件的该凹洞中；
一绝缘层，配置在该第一电子元件的该上表面上方，以包覆该复数个第二电子元件；以及，
复数个导电图案，配置在该绝缘层上方，以电性连接该复数个第二电子元件以及该第一电感元件。
2.一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；以及，
一环氧模造物层，其中该环氧模造物层被设置在该第一电子元件的该上表面，以包覆该复数个第二电子元件；
复数个导电图案，配置在该环氧模造物层上方，以电性连接该复数个第二电子元件以及该第一电子元件。
3.一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；以及，
一ABF(Ajinomoto Build-up Film)层，其中该ABF层被设置在该第一电子元件的该上表面，以包覆该复数个第二电子元件；
复数个导电图案，配置在该ABF层上方，以电性连接该复数个第二电子元件以及该第一电子元件。
4.一种三维空间封装结构，其特征在于，包含：
一第一电感元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电感元件的该上表面上方；以及，
一连接结构，配置在该第一电子元件的该上表面上方，用以包覆该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个第一导电图案，其中该复数个第一导电图案配置在该复数个第二电子元件上方，以电性连接该复数个第二电子元件以及该第一电感元件，其中该复数个第一导电图案中的一导电图案通过导孔电性连接该复数个第二电子元件中的一电子元件与该第一电感元件，其中复数个垫片配置在该连接结构的上表面上且电性连接该复数个第一导电图案，用以连接外部电路。
5.一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面、一下表面以及一侧表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；
一环氧模造物层，包覆至少一部分的该第一电子元件、该复数个第二电子元件以及该至少一第三电子元件；
复数个导电图案，配置在该环氧模造物层上方且被至少一ABF(Ajinomoto Build-upFilm)层隔开，用以电性连接该第一电子元件、该复数个第二电子元件以及该至少一第三电子元件。
6.一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面、一下表面以及一侧表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；
至少一第三电子元件，配置在该第一电子元件该侧表面旁，
一环氧模造物层，包覆至少一部分的该第一电子元件、该复数个第二电子元件以及该至少一第三电子元件；
复数个导电图案，配置在该环氧模造物层上方，以电性连接该第一电子元件、该复数个第二电子元件以及该至少一第三电子元件。
7.一种三维空间封装结构，其特征在于，包含：
一第一电子元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电子元件的该上表面上方；
一绝缘层，配置在该第一电子元件上以形成在该复数个第二电子元件上的一实质水平面，该复数个第二电子元件的所有接点配置在该实质水平面上；以及，
复数个第一导电图案，配置在该实质水平面上方，以电性连接该复数个第二电子元件以及该第一电子元件，其中该复数个第一导电图案中的一导电图案通过导孔电性连接该复数个第二电子元件中的一电子元件与该第一电子元件。
8.一种直流对直流转换器，其特征在于，包含：
一第一电感元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电感元件的该上表面上方；以及，
一连接结构，配置在该第一电子元件的该上表面上方，用以包覆该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个第一导电图案，其中该复数个第一导电图案配置在该复数个第二电子元件上方，以电性连接该复数个第二电子元件以及该第一电感元件，其中该复数个第一导电图案中的一导电图案通过导孔电性连接该复数个第二电子元件中的一电子元件与该第一电感元件。
9.一种电力模块，其特征在于，包含：
一第一电感元件，具有一上表面和一下表面；
复数个第二电子元件，配置在该第一电感元件的该上表面上方；以及，
一连接结构，配置在该第一电子元件的该上表面上方，用以包覆该复数个第二电子元件，其中该连接结构包含至少一绝缘层和被该至少一绝缘层所分离的复数个第一导电图案，其中该复数个第一导电图案配置在该复数个第二电子元件上方，以电性连接该复数个第二电子元件以及该第一电感元件，其中该复数个第一导电图案中的一导电图案通过导孔电性连接该复数个第二电子元件中的一电子元件与该第一电感元件。
10.一种制造电感元件的方法，其特征在于，包含：
提供一第一电感元件，该第一电感元件具有一上表面和一下表面，该第一电子元件的该上表面包含一凹洞；
设置复数个第二电子元件在该第一电感元件的该凹洞中；
设置一绝缘层在该第一电子元件的该上表面上方以包覆该复数个第二电子元件；以及，
设置复数个导电图案在该绝缘层上方以电性连接该复数个第二电子元件以及该第一电感元件。
11.一种制造三维空间封装结构的方法，其特征在于，包含：
提供具有一上表面和一下表面的一第一电子元件；
在该第一电子元件的该上表面上方配置复数个第二电子元件；以及，
设置一环氧模造物层在该第一电子元件的该上表面上，以包覆该复数个第二电子元件；
设置复数个导电图案在该环氧模造物层上方，用以电性连接该复数个第二电子元件以及该第一电子元件。
12.一种制造三维空间封装结构的方法，其特征在于，包含：
提供具有一上表面和一下表面的一第一电子元件；
在该第一电子元件的该上表面上方配置复数个第二电子元件；以及，
设置一ABF层在该第一电子元件的该上表面上，以包覆该复数个第二电子元件；
设置复数个导电图案在该ABF层上方，用以电性连接该复数个第二电子元件以及该第一电子元件。
13.一种制造三维空间封装结构的方法，其特征在于，包含：
提供具有一上表面和一下表面的一第一电子元件；
在该第一电子元件的该上表面上方配置复数个第二电子元件；以及，
设置一绝缘层在该第一电子元件的该上表面上，以包覆该复数个第二电子元件；
使用薄膜制程以形成该复数个导电图案在该绝缘层上方以电性连接该复数个第二电子元件以及该第一电感元件。
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