WO2019037867A1 - Semiconductor module and method for manufacturing the same - Google Patents

Semiconductor module and method for manufacturing the same Download PDF

Info

Publication number
WO2019037867A1
WO2019037867A1 PCT/EP2017/071429 EP2017071429W WO2019037867A1 WO 2019037867 A1 WO2019037867 A1 WO 2019037867A1 EP 2017071429 W EP2017071429 W EP 2017071429W WO 2019037867 A1 WO2019037867 A1 WO 2019037867A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrates
semiconductor module
module
main surface
semiconductor
Prior art date
Application number
PCT/EP2017/071429
Other languages
French (fr)
Inventor
Hamit Duran
Hu JUNFU
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to EP17757547.9A priority Critical patent/EP3659177B1/en
Priority to CN201780065388.5A priority patent/CN109891576B/en
Priority to PCT/EP2017/071429 priority patent/WO2019037867A1/en
Publication of WO2019037867A1 publication Critical patent/WO2019037867A1/en
Priority to US16/799,399 priority patent/US11251116B2/en
Priority to US17/581,412 priority patent/US11823996B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor module, especially a power semiconductor module.
  • a power module has a cooling plate on the bottom side, and the electrical contacts on the top side.
  • the top side of the semiconductor device may also be used to remove heat by attaching a thermally conductive material, e.g. a copper block.
  • a thermally conductive material e.g. a copper block.
  • JP 2008/186890 A An example for such a module is described in JP 2008/186890 A.
  • two semiconductor devices are held between two heat dissipation plates whose inner faces face each other, and they are encapsulated by a mold resin in a manner that the heat dissipation plates and the semiconductor devices are enclosed. The outer faces of the heat dissipation plates are exposed from the mold resin.
  • the semiconductor elements are mounted on one of the heat dissipation plates and connected via a spacer to the other heat dissipation plate.
  • the power module combines dou ble sided chip cooling with electrical isolation of the heat sinks. Electrical isolation is provided by DCB (direct copper bonded) ceramic substrates. Heat is transported to the lower heat sink by soldering the chip directly onto the substrate, and to the upper heat sink by spacers which adjust the height of the module.
  • DCB direct copper bonded
  • a semiconductor module comprising at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface.
  • at least one semiconductor device is mounted on the first main surface of the corresponding su bstrate.
  • An external terminal is connected to the first main surface of at least one of the substrates.
  • the substrates are arranged opposite to each other so that their first main surfaces are facing each other.
  • the power density of a semiconductor module may be improved. Since the semiconductor devices are only attached single-sided to the substrates, cost and process complexity can be kept low. The modules can be manufactured using well established assembling technologies and therefore are potentially low-cost.
  • the semiconductor module further comprises an encapsulation, and the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.
  • the substrates are thermally conductive. Thereby it is possible, for example, to better conduct heat dissipated from the semiconductor devices to the outside of the module.
  • the at least one semiconductor device is a power semiconductor device.
  • a heat sink is mounted to at least one of the second main surfaces of the substrates.
  • the external terminal comprises at least two external leads. All the external leads protrude in a plane from two opposite sides of the module, or all the external leads protrude from a single side of the module, only.
  • connection to the module in a plane at two opposite sides, which is a commonly used arrangement for semiconductor devices, or to provide the connections to the module on one side, only, leaving the other sides free for means for dissipating the heat.
  • the external terminal is formed as a lead frame connected to at least two substrates.
  • the at least two substrates are electrically interconnected by means of bridges between individual leads of the lead frame.
  • the external terminal is formed as two separate lead frame s, each connected to one of the at least two substrates.
  • the at least two substrates are electrically interconnected by means of individual leads of the two separate lead frame s being connected to each other.
  • the external terminal is formed as pins connected to one of the at least two substrates and protruding from the module at the side opposite to the substrate to which the pins are connected.
  • the at least two substrates are electrically interconnected by means of an internal lead frame or by means of internal pins.
  • the at least two substrates are arranged spaced apart from each other.
  • the semiconductor module further comprises a printed circuit board including controllers and/or drivers for the semiconductor devices.
  • the printed circuit board is arranged in the space between the at least two su bstrates.
  • a method of manufacturing a semiconductor module comprises preparing at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface, mounting at least one semiconductor device on the first main surface of each of the substrates, connecting an external terminal to the first main surface of at least one of the substrates, and arranging the at least two substrates opposite to each other so that their first main surfaces are facing each other.
  • a semiconductor module in which heat generated by the semiconductor devices can efficiently be removed to both sides of the module. Further, by the improved heat dissipation and the arrangement of semiconductor devices at opposite sides of the module, the power density of a semiconductor module may be improved. Since the semiconductor devices are only attached single-sided to the substrates, cost and process complexity can be kept low. The modules can be manufactured using well established assembling technologies and therefore are potentially low-cost.
  • the semiconductor module is further provided with an encapsulation, arranged in a way that the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.
  • thermally conductive substrates are used as the substrates.
  • a power semiconductor device is used as the at least one semiconductor device.
  • the method further comprises mounting a heat sink to at least one of the second main surfaces of the substrates.
  • the external terminal comprises at least two external leads. All the external leads are arranged to protrude in a plane from two opposite sides of the module, or all the external leads are arranged to protrude from a single side of the module, only.
  • a lead frame is connected to at least two substrates as the external terminal.
  • bridges between individual leads of the lead frame are provided for interconnecting the at least two substrates.
  • two separate lead frame s, each connected to one of the at least two substrates are used as the external terminal.
  • individual leads of the two separate lead frame s are connected to each other for interconnecting the at least two substrates.
  • pins connected to one of the at least two substrates and protruding from the module at the side opposite to the su bstrate to which the pins are connected are used as the external terminal.
  • an internal lead frame or internal pins are used for interconnecting the at least two substrates.
  • the at least two substrates are arranged spaced apart from each other.
  • the method further comprises arranging a printed circuit board including driver circuits for the semiconductor devices in the space between the at least two substrates.
  • Fig. la is a side view of a semiconductor module according to a first embodiment of the present invention.
  • Fig. lb is a perspectivel view the semiconductor module according to the first embodiment.
  • Fig. 2a is a perspectivel view of a first variant of a semiconductor module according to any of the embodiments of the present invention.
  • Fig. 2b is a perspectivel view of a second variant of a semiconductor module according to any of the embodiments of the present invention.
  • Fig. 3a is a side view of a semiconductor module according to a second embodiment of the present invention.
  • Fig. 3b is a perspectivel view of the semiconductor module according to the second embodiment.
  • Fig. 4a is a side view of a semiconductor module according to a third embodiment of the present invention.
  • Fig. 4b is a perspectivel view of the semiconductor module according to the third embodiment.
  • Fig. 5a is a side view of a semiconductor module according to a fourth embodiment of the present invention.
  • Fig. 5b is a perspectivel view of the semiconductor module according to the fourth embodiment.
  • Fig. 6a is a side view of a semiconductor module according to a fifth embodiment of the present invention.
  • Fig. 6b is a perspectivel view of the semiconductor module according to the fifth embodiment.
  • Figs, la and lb show a semiconductor module 100 according to a first embodiment, Fig. la in a side view and Fig. lb in a naval view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. lb.
  • the semiconductor module 100 comprises two electrically insulating substrates 101a, 101b. Each substrate has two main surfaces opposite to each other. Preferably, the substrates are thermally conductive.
  • the thermal conductivity of the material used may for example be in the range from 25 to 200 W/mK.
  • ceramic may be used as a material for the substrates.
  • direct bonded copper (DBC) substrates may be used in which a sheet of copper is bonded to one or both sides of a ceramic su bstrate.
  • insulated metal substrates may be used which have a metal baseplate, for example made of aluminum, on which an insulating layer, for example a ceramic-filled polymer foil, and a metal foil, for example a copper foil, are stacked in this order.
  • a metal baseplate for example made of aluminum
  • an insulating layer for example a ceramic-filled polymer foil
  • a metal foil for example a copper foil
  • each of the substrates On a first main surface 102a, 102b of each of the substrates, one or more semiconductor device(s) 110 is or are mounted.
  • the semiconductor devices are power semiconductor devices such as, for example, IGBTs, MOSFETs or diodes.
  • the bottom surface of each of the semiconductor devices is die-bonded, for example by soldering or sintering, to a (not shown) wiring layer on the first main surface 102a, 102b of the corresponding substrate 101a, 101b, while (not shown) pads on the top surface of each of the semiconductor devices 110 are bonded to (not shown) pads of the (not shown) wiring layer via bond wires 111 or clips.
  • the substrates 101a, 101b are arranged in the semiconductor module 100 opposite to each other so that their first main surfaces 102a, 102b are facing each other.
  • the substrates 101a, 101b are arranged spaced apart from each other so that the semiconductor devices 110 and/or bond wires 111 do not contact each other.
  • an external terminal For supplying power and signals from outside, an external terminal is provided.
  • the external terminal comprises a lead frame 120.
  • a lead frame is an arrangement of leads within a plane, surrounded by a frame. Even if during manufacturing, the frame is cut away in order to separate the leads, the resulting arrangement of the external ends of the leads in a plane which is caused by their former connection to the planar frame also is generally called "lead frame" in the art. In this meaning, the term is also used in the present application. Only the relevant parts of the lead frame are shown in the figures, not the complete lead frame.
  • the lead frame has a predetermined number of leads 121.
  • some of the leads 121 are bent downwards and some are bent upwards. Downwards and upwards in this context refers to the arrangement shown in Fig. la with the first substrate 101a at the bottom and the second su bstrate 101b at the top of the module.
  • the leads 121a bent downwards are connected to the first substrate 101a and the leads bent upwards 121b to the second substrate 101b, for example by soldering or sintering.
  • each of the substrates 101a, 101b has an electrical connection to the outside.
  • the substrates 101a, 101b may also be electrically interconnected to each other by means of bridges 122 that may be provided between adjacent leads 121a, 121b.
  • Fig. lb shows some leads 121a, 121b being interconnected by a bridge 122 as well as some leads 121a, 121b without a bridge.
  • the semiconductor module 100 further comprises an encapsulation 130, forming a package for the module.
  • the encapsulation 130 is preferably made of a resin and formed, for example, by transfer molding or injection molding.
  • the encapsulation 130 is formed in a way that the second main surfaces 103a, 103b of each of the substrates 101a, 101b are exposed on opposite sides of the encapsulation.
  • a film-assisted molding method may be used.
  • the bridges 122 preferably are over-molded so that they are protected and cannot be seen on the outside of the module.
  • a respective heat sink 140a, 140b may be mounted in order to improve the heat dissipation.
  • the following effects can be achieved with a semiconductor module as described above: Providing the substrates on opposite sides of the module with their second main surfaces exposed from the encapsulation increases the cooling area of the module.
  • the second dissipating plate is connected via a spacer to the top side of the semiconductor devices on which connection pads are provided, the power dissipation can be improved because the bottom sides of the semiconductor devices are directly and without spacer mounted on each of the substrates.
  • the semiconductor devices are arranged on both sides of the module, i.e. on each of the substrates, the power density of the module can be increased. Still further, since the power semiconductor devices are only attached single-sided to the substrates, the module can be manufactured using well established assembly technologies, and therefore cost and process complexity can be kept low.
  • Fig. 2 schematically shows different variants of a semiconductor module 200.
  • the variants differ from each other in the arrangement of the leads of the external terminal.
  • the semiconductor module 200a shown in Fig. 2a corresponds to the arrangement shown in Fig. 1.
  • the two substrates 201a are exposed from the encapsulation 230a at the top and bottom of the module 200a (the bottom side is not shown in the figure).
  • the external terminal 220a comprises a predetermined number of leads 221a which protrude in a plane from two opposite lateral sides 231, 232 of the module 200a.
  • the semiconductor module 200b shown in Fig. 2b is a standing or vertical version.
  • the leads 221b of the external terminal 220b all protrude from a single side 233 of the module 200b, only.
  • This module can therefore vertically be inserted into a socket or a circuit board so that the two substrates 201b are exposed from the encapsulation 230b at a front and (not shown) rear side of the module 200b.
  • a lead frame is described above as a means for electrically connecting the substrates to the outside and/or to each other, the present invention is not restricted to this specific example. Any other suitable connecting technology may be used.
  • FIG. 3a and 3b show a semiconductor module 300 according to a second embodiment, Fig. 3a in a side view and Fig. 3b in a naval view.
  • Fig. 3a in a side view
  • Fig. 3b in a naval view
  • an encapsulation and a heat sink are omitted in Fig. 3b.
  • the semiconductor module 300 differs from the semiconductor module 100 shown in Fig. 1 in the arrangement of the external terminal.
  • the external terminal comprises two separate lead frames 320a, 320b, each connected to one of the substrates 301a, 301b.
  • each of the substrates 301a, 301b has an electrical connection to the outside.
  • the substrates 301a, 301b may also be electrically interconnected to each other by connecting individual leads 321a, 321b of the two separate lead frame s 320a, 320b to each other, for example by soldering or sintering.
  • Fig. 3b shows some leads 321a, 321b being connected to each other as well as some leads 321a, 321b not connected to each other.
  • each of the substrates 301a, 301b has semiconductor devices 310 mounted thereon and is arranged so that the sides bearing the semiconductor devices 310 are facing each other. The other sides of the two substrates are exposed from the encapsulation 330, and a heat sink 340a, 340b may be mounted thereon.
  • Figs. 4a and 4b show a semiconductor module 400 according to a third embodiment, Fig. 4a in a side view and Fig. 4b in a naval view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 4b.
  • the semiconductor module 400 differs from the semiconductor module 100 shown in Fig. 1 in the arrangement of the external terminal. Even if the external terminal also comprises a single lead frame 420, it is connected to one of the substrates (first substrate) 401a only. Thereby, this substrate 401a has an electrical connection to the outside. The other substrate (second substrate) 401b is connected to the first substrate 401a and via the first substrate 401a to the outside by an internal lead frame 450.
  • the internal lead frame 450 is first connected to one of the substrates, for example the second substrate 401b, by soldering or sintering. Then, the frame is cut away from the lead frame 450, the substrate 401b is flipped, and the lead frame 450 is connected to the other substrate, for example the first substrate 401a, by soldering or sintering.
  • each of the substrates 401a, 401b has semiconductor devices 410 mounted thereon and is arranged so that the sides bearing the semiconductor devices 410 are facing each other. The other sides of the two substrates are exposed from the encapsulation 430, and a heat sink 440a, 440b may be mounted thereon.
  • the single leads of the lead frame 450 preferably have an elastic property such as a blade spring.
  • the su bstrates thereby are elastically pressed against the walls of the mold, thus reducing the risk of mold resin bleeding on the exposed side of the substrates 401a, 401b on which the heat sink 440a, 440b may be mounted.
  • Figs. 5a and 5b show a semiconductor module 500 according to a fourth embodiment, Fig. 5a in a side view and Fig. 5b in a naval view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 5b.
  • the external terminal of the semiconductor module 500 also comprises a single lead frame 520, connected to one of the substrates (first substrate) 501a only.
  • the other substrate (second substrate) 501b is connected to the first substrate 501a and via the first substrate 501a to the outside by means of internal pins 560.
  • the internal pins 560 are first connected to one of the substrates, for example the second substrate 501b, by soldering or sintering. Then, the substrate 501b is flipped, and the internal pins 560 are connected to the other substrate, for example the first substrate 501a, by soldering or sintering.
  • each of the substrates 501a, 501b has semiconductor devices 510 mounted thereon and is arranged so that the sides bearing the semiconductor devices 510 are facing each other. The other sides of the two substrates are exposed from the encapsulation 530, and a heat sink 540a, 540b may be mounted thereon.
  • pins may also be used for the external terminal instead of or additionally to the lead frame(s).
  • the pins are then connected to one of the substrates in an area opposite to which the other substrate is not provided, and protrude from the module at the side opposite to the substrate to which they are connected.
  • Figs. 6a and 6b show a semiconductor module 600 according to a fifth embodiment, Fig. 6a in a side view and Fig. 6b in a naval view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 6b.
  • the external terminal of the semiconductor module 600 also comprises a single lead frame 620, connected to one of the substrates (first substrate) 601a only.
  • the semiconductor module 600 also comprises a printed circuit board 670 which is arranged in the space between the substrates 601a, 601b.
  • the printed circuit board 670 may for example include controllers and/or drivers for the semiconductor devices 610 as well as other active and/or passive elements.
  • the first substrate 601a is connected to the printed circuit board 670 by means of internal pins 661
  • the second su bstrate 601b is connected to the printed circuit board 670 by means of internal pins 662.
  • the two su bstrates 601a, 601b may be interconnected by means of internal pins at positions where the printed circuit board 670 is not provided or through holes in the printed circuit board 670.
  • the lead frame 620 may also be connected to the printed circuit board 670 instead of being connected to one of the substrates 601a, 601b.
  • internal lead frames may be used as in the semiconductor module 400.
  • each of the substrates 601a, 601b has semiconductor devices 610 mounted thereon and is arranged so that the sides bearing the semiconductor devices 610 are facing each other.
  • the other sides of the two substrates are exposed from the encapsulation 630, and a heat sink 640a, 640b may be mounted thereon.
  • an intelligent power module can be provided wherein controllers and/or drivers of the semiconductor devices are integrated in the semiconductor module.
  • the present invention relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased.
  • the semiconductor module comprises at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates.
  • the substrates are arranged opposite to each other so that their first main surfaces are facing each other.

Abstract

The present invention relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module (100) comprises at least two electrically insulating substrates (101a, 101b), each having a first main surface (102a, 102b) and a second main surface (103a, 103b) opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device (110) is mounted. An external terminal (120) is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.

Description

Semiconductor module and method for manufacturing the same
FIELD OF THE INVENTION
The present invention relates to a semiconductor module, especially a power semiconductor module.
BACKGROUND
One of the key issues of power modules is the heat removal from the semiconductor devices comprised therein such as IGBTs, MOSFETs, diodes etc. Usually, the top side of the semiconductor devices is used to make the electrical connection to the connection pads of the device whereas the bottom side is used to remove the heat by attaching it to a thermally conductive, but electrically isolating material like a ceramic substrate. In a classical setup, a power module has a cooling plate on the bottom side, and the electrical contacts on the top side.
To further reduce the thermal resistance of the module, the top side of the semiconductor device may also be used to remove heat by attaching a thermally conductive material, e.g. a copper block. An example for such a module is described in JP 2008/186890 A. In an embodiment thereof, two semiconductor devices are held between two heat dissipation plates whose inner faces face each other, and they are encapsulated by a mold resin in a manner that the heat dissipation plates and the semiconductor devices are enclosed. The outer faces of the heat dissipation plates are exposed from the mold resin. The semiconductor elements are mounted on one of the heat dissipation plates and connected via a spacer to the other heat dissipation plate.
Such a module is also described in Andreas Grassmann, Ottmar Geitner, Wolfram Hable, Christian Neugirg, Alexander Schwarz, Frank Winter, Inpil Yoo: "Double Sided Cooled Module concept for High Power Density in HEV Applications", PCIM Europe 2015, 19 - 21 May2015, Nuremberg, Germany, pages 442 to 448. The power module combines dou ble sided chip cooling with electrical isolation of the heat sinks. Electrical isolation is provided by DCB (direct copper bonded) ceramic substrates. Heat is transported to the lower heat sink by soldering the chip directly onto the substrate, and to the upper heat sink by spacers which adjust the height of the module.
However, the production of such double-sided cooled modules is pretty expensive and the actual reduction of the thermal resistance is only in the range of 20 to 30%. A reason is that the cooling through the top side of the semiconductor device is less efficient than through the bottom side since the top side is also used for electrical contact. Therefore, the spacer cannot be mounted across the entire top side of the semiconductor device. Care has to be taken while mounting the spacer not to damage the electrical connections on the top side of the semiconductor device.
SUMMARY It is therefore an object of the present invention to provide a semiconductor module, especially a power semiconductor module, having an improved heat dissipation and/or an increased power density.
The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the descriptions and the figures. According to a first aspect, a semiconductor module is provided, comprising at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. For each of the substrates, at least one semiconductor device is mounted on the first main surface of the corresponding su bstrate. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
By this arrangement, it is possible, for example, to efficiently dissipate heat generated by the semiconductor devices from the opposite sides of the module. Further, by the improved heat dissipation and the arrangement of semiconductor devices at opposite sides of the module, the power density of a semiconductor module may be improved. Since the semiconductor devices are only attached single-sided to the substrates, cost and process complexity can be kept low. The modules can be manufactured using well established assembling technologies and therefore are potentially low-cost.
In an implementation form of the first aspect, the semiconductor module further comprises an encapsulation, and the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.
Thereby it is possible, for example, to protect the devices by an encapsulation and nevertheless be able to efficiently dissipate heat generated by the semiconductor devices from the opposite sides of the module.
In a further implementation form of the first aspect, the substrates are thermally conductive. Thereby it is possible, for example, to better conduct heat dissipated from the semiconductor devices to the outside of the module.
In a further implementation form of the first aspect, the at least one semiconductor device is a power semiconductor device. Thereby it is possible, for example, to apply the invention to power modules for which efficiently dissipating heat is of a special importance.
In a further implementation form of the first aspect, a heat sink is mounted to at least one of the second main surfaces of the substrates.
Thereby it is possible, for example, to further increase the efficiency of dissipating heat from the semiconductor devices.
In a further implementation form of the first aspect, the external terminal comprises at least two external leads. All the external leads protrude in a plane from two opposite sides of the module, or all the external leads protrude from a single side of the module, only.
Thereby it is possible, for example, to provide the connections to the module in a plane at two opposite sides, which is a commonly used arrangement for semiconductor devices, or to provide the connections to the module on one side, only, leaving the other sides free for means for dissipating the heat.
In a further implementation form of the first aspect, the external terminal is formed as a lead frame connected to at least two substrates. Thereby it is possible, for example, to provide a variant of the semiconductor module according to the invention.
In a further implementation form of the first aspect, the at least two substrates are electrically interconnected by means of bridges between individual leads of the lead frame.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the first aspect, the external terminal is formed as two separate lead frame s, each connected to one of the at least two substrates. Thereby it is possible, for example, to provide another variant of the semiconductor module according to the invention.
In a further implementation form of the first aspect, the at least two substrates are electrically interconnected by means of individual leads of the two separate lead frame s being connected to each other.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the first aspect, the external terminal is formed as pins connected to one of the at least two substrates and protruding from the module at the side opposite to the substrate to which the pins are connected.
Thereby it is possible, for example, to provide another variant of the semiconductor module according to the invention.
In a further implementation form of the first aspect, the at least two substrates are electrically interconnected by means of an internal lead frame or by means of internal pins.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the first aspect, the at least two substrates are arranged spaced apart from each other.
Thereby it is possible, for example, to avoid that the semiconductor devices or other components at the first sides of the substrates contact each other and/or to arrange other components in a space between the substrates.
In a further implementation form of the first aspect, the semiconductor module further comprises a printed circuit board including controllers and/or drivers for the semiconductor devices. The printed circuit board is arranged in the space between the at least two su bstrates.
Thereby it is possible, for example, to provide an intelligent power module in which controllers and/or drivers of the semiconductor devices are integrated.
The above object is also achieved in accordance with a second aspect. According to the second aspect, a method of manufacturing a semiconductor module is provided. The method comprises preparing at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface, mounting at least one semiconductor device on the first main surface of each of the substrates, connecting an external terminal to the first main surface of at least one of the substrates, and arranging the at least two substrates opposite to each other so that their first main surfaces are facing each other.
With such a method it is possible, for example, to manufacture a semiconductor module in which heat generated by the semiconductor devices can efficiently be removed to both sides of the module. Further, by the improved heat dissipation and the arrangement of semiconductor devices at opposite sides of the module, the power density of a semiconductor module may be improved. Since the semiconductor devices are only attached single-sided to the substrates, cost and process complexity can be kept low. The modules can be manufactured using well established assembling technologies and therefore are potentially low-cost.
In an implementation form of the second aspect, the semiconductor module is further provided with an encapsulation, arranged in a way that the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.
Thereby it is possible, for example, to protect the devices by an encapsulation and nevertheless be able to efficiently dissipate heat generated by the semiconductor devices from the opposite sides of the module. In a further implementation form of the second aspect, thermally conductive substrates are used as the substrates.
Thereby it is possible, for example, to better conduct heat dissipated from the semiconductor devices to the outside of the module.
In a further implementation form of the second aspect, a power semiconductor device is used as the at least one semiconductor device.
Thereby it is possible, for example, to apply the invention to power modules for which efficiently dissipating heat is of a special importance.
In a further implementation form of the second aspect, the method further comprises mounting a heat sink to at least one of the second main surfaces of the substrates. Thereby it is possible, for example, to further increase the efficiency of dissipating heat from the semiconductor devices.
In a further implementation form of the second aspect, the external terminal comprises at least two external leads. All the external leads are arranged to protrude in a plane from two opposite sides of the module, or all the external leads are arranged to protrude from a single side of the module, only.
Thereby it is possible, for example, to provide the connections to the module in a plane at two opposite sides, which is a commonly used arrangement for semiconductor devices, or to provide the connections to the module on one side, only, leaving the other sides free for means for dissipating the heat. In a further implementation form of the second aspect, a lead frame is connected to at least two substrates as the external terminal.
Thereby it is possible, for example, to provide a variant of the semiconductor module according to the invention.
In a further implementation form of the second aspect, bridges between individual leads of the lead frame are provided for interconnecting the at least two substrates.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the second aspect, two separate lead frame s, each connected to one of the at least two substrates are used as the external terminal. Thereby it is possible, for example, to provide another variant of the semiconductor module according to the invention.
In a further implementation form of the second aspect, individual leads of the two separate lead frame s are connected to each other for interconnecting the at least two substrates.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the second aspect, pins connected to one of the at least two substrates and protruding from the module at the side opposite to the su bstrate to which the pins are connected are used as the external terminal. Thereby it is possible, for example, to provide another variant of the semiconductor module according to the invention.
In a further implementation form of the second aspect, an internal lead frame or internal pins are used for interconnecting the at least two substrates.
Thereby it is possible, for example, to easily provide interconnections between the at least two substrates.
In a further implementation form of the second aspect, the at least two substrates are arranged spaced apart from each other.
Thereby it is possible, for example, to avoid that the semiconductor devices or other components at the first sides of the substrates contact each other and/or to arrange other components in a space between the substrates.
In a further implementation form of the second aspect, the method further comprises arranging a printed circuit board including driver circuits for the semiconductor devices in the space between the at least two substrates.
Thereby it is possible, for example, to provide an intelligent power module in which controllers and drivers of the semiconductor devices are integrated.
It shall further be understood that an embodiment of the invention can also be any combination of the dependent claims or above implementation forms with the respective independent claims or above aspects.
These and other aspects of the invention will be apparent and elucidated with reference to the embodiments described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. la is a side view of a semiconductor module according to a first embodiment of the present invention.
Fig. lb is a perspectival view the semiconductor module according to the first embodiment.
Fig. 2a is a perspectival view of a first variant of a semiconductor module according to any of the embodiments of the present invention. Fig. 2b is a perspectival view of a second variant of a semiconductor module according to any of the embodiments of the present invention.
Fig. 3a is a side view of a semiconductor module according to a second embodiment of the present invention.
Fig. 3b is a perspectival view of the semiconductor module according to the second embodiment.
Fig. 4a is a side view of a semiconductor module according to a third embodiment of the present invention.
Fig. 4b is a perspectival view of the semiconductor module according to the third embodiment.
Fig. 5a is a side view of a semiconductor module according to a fourth embodiment of the present invention.
Fig. 5b is a perspectival view of the semiconductor module according to the fourth embodiment.
Fig. 6a is a side view of a semiconductor module according to a fifth embodiment of the present invention.
Fig. 6b is a perspectival view of the semiconductor module according to the fifth embodiment. DETAILED DESCRIPTION
In the following, embodiments of the invention are described with reference to the enclosed figures.
Figs, la and lb show a semiconductor module 100 according to a first embodiment, Fig. la in a side view and Fig. lb in a perspectival view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. lb.
The semiconductor module 100 comprises two electrically insulating substrates 101a, 101b. Each substrate has two main surfaces opposite to each other. Preferably, the substrates are thermally conductive. The thermal conductivity of the material used may for example be in the range from 25 to 200 W/mK. For example, ceramic may be used as a material for the substrates. As a specific example, direct bonded copper (DBC) substrates may be used in which a sheet of copper is bonded to one or both sides of a ceramic su bstrate. As another specific example, insulated metal substrates (IMS) may be used which have a metal baseplate, for example made of aluminum, on which an insulating layer, for example a ceramic-filled polymer foil, and a metal foil, for example a copper foil, are stacked in this order.
On a first main surface 102a, 102b of each of the substrates, one or more semiconductor device(s) 110 is or are mounted. Preferably, the semiconductor devices are power semiconductor devices such as, for example, IGBTs, MOSFETs or diodes. For example, the bottom surface of each of the semiconductor devices is die-bonded, for example by soldering or sintering, to a (not shown) wiring layer on the first main surface 102a, 102b of the corresponding substrate 101a, 101b, while (not shown) pads on the top surface of each of the semiconductor devices 110 are bonded to (not shown) pads of the (not shown) wiring layer via bond wires 111 or clips. According to the present invention, the substrates 101a, 101b are arranged in the semiconductor module 100 opposite to each other so that their first main surfaces 102a, 102b are facing each other. Thereby, a second main surface 103a, 103b of each substrates 101a, 101b, which is opposite to the first main surfaces 102a, 102b, faces towards the outside of the semiconductor module 100. The substrates 101a, 101b are arranged spaced apart from each other so that the semiconductor devices 110 and/or bond wires 111 do not contact each other.
For supplying power and signals from outside, an external terminal is provided. In the present embodiment, the external terminal comprises a lead frame 120. A lead frame is an arrangement of leads within a plane, surrounded by a frame. Even if during manufacturing, the frame is cut away in order to separate the leads, the resulting arrangement of the external ends of the leads in a plane which is caused by their former connection to the planar frame also is generally called "lead frame" in the art. In this meaning, the term is also used in the present application. Only the relevant parts of the lead frame are shown in the figures, not the complete lead frame.
The lead frame has a predetermined number of leads 121. In the present embodiment, some of the leads 121 are bent downwards and some are bent upwards. Downwards and upwards in this context refers to the arrangement shown in Fig. la with the first substrate 101a at the bottom and the second su bstrate 101b at the top of the module.
The leads 121a bent downwards are connected to the first substrate 101a and the leads bent upwards 121b to the second substrate 101b, for example by soldering or sintering. Thereby, each of the substrates 101a, 101b has an electrical connection to the outside. Additionally, the substrates 101a, 101b may also be electrically interconnected to each other by means of bridges 122 that may be provided between adjacent leads 121a, 121b. Fig. lb shows some leads 121a, 121b being interconnected by a bridge 122 as well as some leads 121a, 121b without a bridge. The semiconductor module 100 further comprises an encapsulation 130, forming a package for the module. The encapsulation 130 is preferably made of a resin and formed, for example, by transfer molding or injection molding. The encapsulation 130 is formed in a way that the second main surfaces 103a, 103b of each of the substrates 101a, 101b are exposed on opposite sides of the encapsulation. In order to avoid resin from coming into contact with the second main surfaces 103a, 103b, a film-assisted molding method may be used. During the molding, the bridges 122 preferably are over-molded so that they are protected and cannot be seen on the outside of the module.
On the exposed second main surfaces 103a, 103b of the substrates 101a, 101b, a respective heat sink 140a, 140b may be mounted in order to improve the heat dissipation. Among others, the following effects can be achieved with a semiconductor module as described above: Providing the substrates on opposite sides of the module with their second main surfaces exposed from the encapsulation increases the cooling area of the module. Compared to the prior art cited in the introductory portion of this description, in which the second dissipating plate is connected via a spacer to the top side of the semiconductor devices on which connection pads are provided, the power dissipation can be improved because the bottom sides of the semiconductor devices are directly and without spacer mounted on each of the substrates. Further, since the semiconductor devices are arranged on both sides of the module, i.e. on each of the substrates, the power density of the module can be increased. Still further, since the power semiconductor devices are only attached single-sided to the substrates, the module can be manufactured using well established assembly technologies, and therefore cost and process complexity can be kept low.
Fig. 2 schematically shows different variants of a semiconductor module 200. The variants differ from each other in the arrangement of the leads of the external terminal.
The semiconductor module 200a shown in Fig. 2a corresponds to the arrangement shown in Fig. 1. The two substrates 201a are exposed from the encapsulation 230a at the top and bottom of the module 200a (the bottom side is not shown in the figure). The external terminal 220a comprises a predetermined number of leads 221a which protrude in a plane from two opposite lateral sides 231, 232 of the module 200a.
The semiconductor module 200b shown in Fig. 2b is a standing or vertical version. The leads 221b of the external terminal 220b all protrude from a single side 233 of the module 200b, only. This module can therefore vertically be inserted into a socket or a circuit board so that the two substrates 201b are exposed from the encapsulation 230b at a front and (not shown) rear side of the module 200b. Even if a lead frame is described above as a means for electrically connecting the substrates to the outside and/or to each other, the present invention is not restricted to this specific example. Any other suitable connecting technology may be used. Some further examples are given in the following embodiments. Figs. 3a and 3b show a semiconductor module 300 according to a second embodiment, Fig. 3a in a side view and Fig. 3b in a perspectival view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 3b.
The semiconductor module 300 differs from the semiconductor module 100 shown in Fig. 1 in the arrangement of the external terminal. Instead of a single lead frame, the external terminal comprises two separate lead frames 320a, 320b, each connected to one of the substrates 301a, 301b. Thereby, each of the substrates 301a, 301b has an electrical connection to the outside. Additionally, the substrates 301a, 301b may also be electrically interconnected to each other by connecting individual leads 321a, 321b of the two separate lead frame s 320a, 320b to each other, for example by soldering or sintering. Fig. 3b shows some leads 321a, 321b being connected to each other as well as some leads 321a, 321b not connected to each other.
Other features of the second embodiment than those described above are the same as in the first embodiment. Especially, each of the substrates 301a, 301b has semiconductor devices 310 mounted thereon and is arranged so that the sides bearing the semiconductor devices 310 are facing each other. The other sides of the two substrates are exposed from the encapsulation 330, and a heat sink 340a, 340b may be mounted thereon.
With the semiconductor module 300, the same effects can be achieved as described above for the semiconductor module 100. Further, connecting the individual lead frames to the individual substrates is facilitated because the substrates need not be adjusted to each other during that process. Figs. 4a and 4b show a semiconductor module 400 according to a third embodiment, Fig. 4a in a side view and Fig. 4b in a perspectival view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 4b.
The semiconductor module 400 differs from the semiconductor module 100 shown in Fig. 1 in the arrangement of the external terminal. Even if the external terminal also comprises a single lead frame 420, it is connected to one of the substrates (first substrate) 401a only. Thereby, this substrate 401a has an electrical connection to the outside. The other substrate (second substrate) 401b is connected to the first substrate 401a and via the first substrate 401a to the outside by an internal lead frame 450.
During manufacturing, the internal lead frame 450 is first connected to one of the substrates, for example the second substrate 401b, by soldering or sintering. Then, the frame is cut away from the lead frame 450, the substrate 401b is flipped, and the lead frame 450 is connected to the other substrate, for example the first substrate 401a, by soldering or sintering.
Other features of the second embodiment than those described above are the same as in the first or second embodiment. Especially, each of the substrates 401a, 401b has semiconductor devices 410 mounted thereon and is arranged so that the sides bearing the semiconductor devices 410 are facing each other. The other sides of the two substrates are exposed from the encapsulation 430, and a heat sink 440a, 440b may be mounted thereon.
The single leads of the lead frame 450 preferably have an elastic property such as a blade spring. During molding, the su bstrates thereby are elastically pressed against the walls of the mold, thus reducing the risk of mold resin bleeding on the exposed side of the substrates 401a, 401b on which the heat sink 440a, 440b may be mounted.
With the semiconductor module 400, the same effects can be achieved as described above for the semiconductor module 100.
Figs. 5a and 5b show a semiconductor module 500 according to a fourth embodiment, Fig. 5a in a side view and Fig. 5b in a perspectival view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 5b.
Similar as the semiconductor module 400 shown in Fig. 4, the external terminal of the semiconductor module 500 also comprises a single lead frame 520, connected to one of the substrates (first substrate) 501a only. The other substrate (second substrate) 501b is connected to the first substrate 501a and via the first substrate 501a to the outside by means of internal pins 560. During manufacturing, the internal pins 560 are first connected to one of the substrates, for example the second substrate 501b, by soldering or sintering. Then, the substrate 501b is flipped, and the internal pins 560 are connected to the other substrate, for example the first substrate 501a, by soldering or sintering. Similar as the internal lead frame of the semiconductor module 400, the internal pins 560 may be provided with a spring functionality. Other features of the fourth embodiment than those described above are the same as in the first to third embodiment. Especially, each of the substrates 501a, 501b has semiconductor devices 510 mounted thereon and is arranged so that the sides bearing the semiconductor devices 510 are facing each other. The other sides of the two substrates are exposed from the encapsulation 530, and a heat sink 540a, 540b may be mounted thereon.
With the semiconductor module 500, the same effects can be achieved as described above for the semiconductor module 100.
In a variant (not shown in the figures), pins may also be used for the external terminal instead of or additionally to the lead frame(s). The pins are then connected to one of the substrates in an area opposite to which the other substrate is not provided, and protrude from the module at the side opposite to the substrate to which they are connected.
Figs. 6a and 6b show a semiconductor module 600 according to a fifth embodiment, Fig. 6a in a side view and Fig. 6b in a perspectival view. For the sake of clarity, an encapsulation and a heat sink are omitted in Fig. 6b. Similar as the semiconductor module 500 shown in Fig. 5, the external terminal of the semiconductor module 600 also comprises a single lead frame 620, connected to one of the substrates (first substrate) 601a only. In addition to the two substrates, 601a, 601b, the semiconductor module 600 also comprises a printed circuit board 670 which is arranged in the space between the substrates 601a, 601b. The printed circuit board 670 may for example include controllers and/or drivers for the semiconductor devices 610 as well as other active and/or passive elements.
Similar as in the semiconductor module 500, the first substrate 601a is connected to the printed circuit board 670 by means of internal pins 661, and the second su bstrate 601b is connected to the printed circuit board 670 by means of internal pins 662. As an alternative, also the two su bstrates 601a, 601b may be interconnected by means of internal pins at positions where the printed circuit board 670 is not provided or through holes in the printed circuit board 670. Further, the lead frame 620 may also be connected to the printed circuit board 670 instead of being connected to one of the substrates 601a, 601b. Instead of the internal pins, internal lead frames may be used as in the semiconductor module 400. Other features of the fifth embodiment than those described above are the same as in the first to fourth embodiment. Especially, each of the substrates 601a, 601b has semiconductor devices 610 mounted thereon and is arranged so that the sides bearing the semiconductor devices 610 are facing each other. The other sides of the two substrates are exposed from the encapsulation 630, and a heat sink 640a, 640b may be mounted thereon.
With the semiconductor module 600, the same effects can be achieved as described above for the semiconductor module 100. Further, an intelligent power module can be provided wherein controllers and/or drivers of the semiconductor devices are integrated in the semiconductor module.
The features of the embodiments described a bove may also be combined, where possible. For example, the different arrangements of the external leads shown in Figs. 2a and 2b may be applied to any of the above embodiments. As further examples, internal lead frames and/or internal and/or external pins as described with regard to the third and fourth embodiments and/or a printed circuit board as described with regard to the fifth embodiment may also be used in combination with any of the other embodiments.
In summary, the present invention relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module comprises at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
While the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The invention is not limited to the disclosed embodiments. From reading the present disclosure, other modifications will be apparent to a person skilled in the art. Such modifications may involve other features, which are already known in the art and may be used instead of or in addition to features already described herein.
The invention has been described in conjunction with various embodiments herein. However, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the present invention has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded simply as an illustration of the invention as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present invention.

Claims

1. A semiconductor module (100), comprising: at least two electrically insulating substrates (101a, 101b), each having a first main surface (102a, 102b) and a second main surface (103a, 103b) opposite to the first main surface (102a, 102b), for each of the substrates (101a, 101b), at least one semiconductor device (110) mounted on the first main surface (102a, 102b) of the corresponding substrate (101a, 101b), and an external terminal (120) connected to the first main surface (102a, 102b) of at least one of the substrates (101a, 101b), wherein the substrates (101a, 101b) are arranged opposite to each other so that their first main surfaces (102a, 102b) are facing each other.
2. The semiconductor module (100) according to claim 1, further comprising an
encapsulation (130), wherein the second main surfaces (103a, 103b) of each of the substrates (101a, 101b) are exposed on opposite sides of the encapsulation.
3. The semiconductor module (100) according to any of claim 1 or 2, wherein the substrates (101a, 101b) are thermally conductive.
4. The semiconductor module (100) according to any of claims 1 to 3, wherein the at least one semiconductor device (110) is a power semiconductor device.
5. The semiconductor module (100) according to any of claims 1 to 4, wherein a heat sink
(140a, 140b) is mounted to at least one of the second main surfaces (103a, 103b) of the substrates (101a, 101b).
6. The semiconductor module (200a, 200b) according to any of claims 1 to 5, wherein the external terminal (220a, 220b) comprises at least two external leads (221a, 221b), and wherein all the external leads (221a) protrude in a plane from two opposite sides (231, 232) of the module (200a), or all the external leads (221b) protrude from a single side (233) of the module (200b), only.
7. The semiconductor module (100) according to any of claims 1 to 6, wherein the external terminal is formed as a lead frame (120) connected to at least two substrates (101a, 101b).
8. The semiconductor module (100) according to claim 7, wherein the at least two substrates (101a, 101b) are electrically interconnected by means of bridges (122) between individual leads (121a, 121b) of the lead frame (120).
9. The semiconductor module (300) according to any of claims 1 to 6, wherein the external terminal is formed as two separate lead frames (320a, 320b), each connected to one of the at least two substrates (301a, 301b).
10. The semiconductor module (300) according to claim 9, wherein the at least two substrates (301a, 301b) are electrically interconnected by means of individual leads (321a, 321b) of the two separate lead frames (320a, 320b) being connected to each other.
11. The semiconductor module according to any of claims 1 to 6, wherein the external terminal is formed as pins connected to one of the at least two substrates and protruding from the module at the side opposite to the substrate to which the pins are connected.
12. The semiconductor module (400; 500) according to claim 7, 9, or 11, wherein the at least two substrates (401a, 401b; 501a, 501b) are electrically interconnected by means of an internal lead frame (450) or by means of internal pins (560).
13. The semiconductor module (100) according to any of claims 1 to 12, wherein the at least two substrates (101a, 101b) are arranged spaced apart from each other.
14. The semiconductor module (600) according to claim 13, further comprising a printed circuit board (670) including controllers and/or drivers for the semiconductor devices (610), wherein the printed circuit board (670) is arranged in the space between the at least two substrates (601a, 601b).
15. A method of manufacturing a semiconductor module (100), comprising: preparing at least two electrically insulating substrates (101a, 101b), each having a first main surface (102a, 102b) and a second main surface (103a, 103b) opposite to the first main surface, mounting at least one semiconductor device (110) on the first main surface (102a, 102b) of each of the substrates (101a, 101b), connecting an external terminal (120) to the first main surface (102a, 102b) of at least one of the substrates (101a, 101b), and arranging the substrates (101a, 101b) opposite to each other so that their first main surfaces (102a, 102b) are facing each other.
PCT/EP2017/071429 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same WO2019037867A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP17757547.9A EP3659177B1 (en) 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same
CN201780065388.5A CN109891576B (en) 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same
PCT/EP2017/071429 WO2019037867A1 (en) 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same
US16/799,399 US11251116B2 (en) 2017-08-25 2020-02-24 Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same
US17/581,412 US11823996B2 (en) 2017-08-25 2022-01-21 Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2017/071429 WO2019037867A1 (en) 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/799,399 Continuation US11251116B2 (en) 2017-08-25 2020-02-24 Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2019037867A1 true WO2019037867A1 (en) 2019-02-28

Family

ID=59699705

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2017/071429 WO2019037867A1 (en) 2017-08-25 2017-08-25 Semiconductor module and method for manufacturing the same

Country Status (4)

Country Link
US (2) US11251116B2 (en)
EP (1) EP3659177B1 (en)
CN (1) CN109891576B (en)
WO (1) WO2019037867A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3866192A1 (en) * 2020-02-13 2021-08-18 LG Electronics, Inc. Power module
US11469163B2 (en) * 2019-08-02 2022-10-11 Semiconductor Components Industries, Llc Low stress asymmetric dual side module

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109891576B (en) * 2017-08-25 2021-06-01 华为技术有限公司 Semiconductor module and method for manufacturing the same
US11282791B2 (en) * 2019-06-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a heat dissipation structure connected chip package
US11908840B2 (en) 2019-08-02 2024-02-20 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
US11462515B2 (en) * 2019-08-02 2022-10-04 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
CN110634818B (en) * 2019-09-25 2021-09-24 湖南大学 Packaging structure of hybrid power module composed of IGBT and MOSFET

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332921A (en) * 1992-04-27 1994-07-26 Kabushiki Kaisha Toshiba Resin-seal type semiconductor device
US20070099437A1 (en) * 2002-04-02 2007-05-03 Infineon Technologies Ag Power module having at least two substrates
US20080122075A1 (en) * 2006-11-29 2008-05-29 Infineon Technologies Ag Semiconductor module with at least two substrates
JP2008186890A (en) 2007-01-29 2008-08-14 Denso Corp Semiconductor device
DE102013200652A1 (en) * 2013-01-17 2014-07-17 Continental Automotive Gmbh Device for switching high currents in motor car, has power terminal connected with lead frame that is located in region of circuit board that is arranged in plane and arranged adjacent to plane of top face of circuit board
US20150187684A1 (en) * 2013-12-26 2015-07-02 Samsung Electro-Mechanics Co., Ltd. Semiconductor package
US20160064308A1 (en) * 2013-10-29 2016-03-03 Fuji Electric Co., Ltd. Semiconductor module
US20160381785A1 (en) * 2015-06-25 2016-12-29 Delta Electronics, Inc. Molding type power module

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1815989A1 (en) 1968-12-20 1970-07-02 Semikron Gleichrichterbau Semiconductor arrangement
US5798564A (en) 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
US6265769B1 (en) 1997-11-13 2001-07-24 Texas Instruments Incorporated Double-sided chip mount package
JP2004022601A (en) * 2002-06-12 2004-01-22 Mitsubishi Electric Corp Semiconductor device
JP4702279B2 (en) 2006-12-27 2011-06-15 株式会社デンソー Semiconductor device and manufacturing method thereof
JP5076549B2 (en) 2007-02-23 2012-11-21 株式会社デンソー Semiconductor device
JP4935783B2 (en) 2008-09-08 2012-05-23 株式会社デンソー Semiconductor device and composite semiconductor device
DE202009000615U1 (en) 2009-01-15 2010-05-27 Danfoss Silicon Power Gmbh Molding compound power semiconductor element
CN102024770A (en) * 2009-09-18 2011-04-20 中芯国际集成电路制造(上海)有限公司 Semiconductor chip package structure and package method
KR101321277B1 (en) * 2011-07-04 2013-10-28 삼성전기주식회사 Power module package and method for manufacturing the same
JP2014072423A (en) * 2012-09-28 2014-04-21 Aisin Aw Co Ltd Power module for power converter and power converter
JP5974988B2 (en) 2013-06-21 2016-08-23 株式会社デンソー Electronic equipment
US9859250B2 (en) * 2013-12-20 2018-01-02 Cyntec Co., Ltd. Substrate and the method to fabricate thereof
JP6295768B2 (en) 2014-03-26 2018-03-20 株式会社デンソー Manufacturing method of semiconductor device
US20160005675A1 (en) 2014-07-07 2016-01-07 Infineon Technologies Ag Double sided cooling chip package and method of manufacturing the same
JP6344215B2 (en) 2014-11-21 2018-06-20 株式会社デンソー Semiconductor device and power module
JP6489942B2 (en) * 2015-05-29 2019-03-27 東芝メモリ株式会社 Manufacturing method of semiconductor device
CN106298695B (en) * 2015-06-05 2019-05-10 台达电子工业股份有限公司 Encapsulation module, encapsulation module stacked structure and preparation method thereof
US20170047274A1 (en) 2015-08-12 2017-02-16 Texas Instruments Incorporated Double Side Heat Dissipation for Silicon Chip Package
CN109087908B (en) 2015-12-31 2020-10-27 华为技术有限公司 Packaging structure, electronic device and packaging method
CN109891576B (en) * 2017-08-25 2021-06-01 华为技术有限公司 Semiconductor module and method for manufacturing the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332921A (en) * 1992-04-27 1994-07-26 Kabushiki Kaisha Toshiba Resin-seal type semiconductor device
US20070099437A1 (en) * 2002-04-02 2007-05-03 Infineon Technologies Ag Power module having at least two substrates
US20080122075A1 (en) * 2006-11-29 2008-05-29 Infineon Technologies Ag Semiconductor module with at least two substrates
JP2008186890A (en) 2007-01-29 2008-08-14 Denso Corp Semiconductor device
DE102013200652A1 (en) * 2013-01-17 2014-07-17 Continental Automotive Gmbh Device for switching high currents in motor car, has power terminal connected with lead frame that is located in region of circuit board that is arranged in plane and arranged adjacent to plane of top face of circuit board
US20160064308A1 (en) * 2013-10-29 2016-03-03 Fuji Electric Co., Ltd. Semiconductor module
US20150187684A1 (en) * 2013-12-26 2015-07-02 Samsung Electro-Mechanics Co., Ltd. Semiconductor package
US20160381785A1 (en) * 2015-06-25 2016-12-29 Delta Electronics, Inc. Molding type power module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANDREAS GRASSMANN; OTTMAR GEITNER; WOLFRAM HABLE; CHRISTIAN NEUGIRG; ALEXANDER SCHWARZ; FRANK WINTER; INPIL YOO: "Double Sided Cooled Module concept for High Power Density in HEV Applications", PCIM EUROPE, 19 May 2015 (2015-05-19), pages 442 - 448

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469163B2 (en) * 2019-08-02 2022-10-11 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
US11948870B2 (en) 2019-08-02 2024-04-02 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
US11955412B2 (en) 2019-08-02 2024-04-09 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
EP3866192A1 (en) * 2020-02-13 2021-08-18 LG Electronics, Inc. Power module
US11756867B2 (en) 2020-02-13 2023-09-12 Lg Electronics Inc. Power module including lead frame unit connecting first substrate and second substrate

Also Published As

Publication number Publication date
US20220148959A1 (en) 2022-05-12
US11823996B2 (en) 2023-11-21
US20200194364A1 (en) 2020-06-18
CN109891576A (en) 2019-06-14
CN109891576B (en) 2021-06-01
EP3659177A1 (en) 2020-06-03
EP3659177B1 (en) 2023-10-25
US11251116B2 (en) 2022-02-15

Similar Documents

Publication Publication Date Title
EP3659177B1 (en) Semiconductor module and method for manufacturing the same
US10453802B2 (en) Semiconductor package structure, semiconductor device and method for manufacturing the same
US6737750B1 (en) Structures for improving heat dissipation in stacked semiconductor packages
US6724631B2 (en) Power converter package with enhanced thermal management
JP3526788B2 (en) Method for manufacturing semiconductor device
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
US20100019379A1 (en) External heat sink for bare-die flip chip packages
CN105612613B (en) Semiconductor device
KR20090036085A (en) Method of making thermally enhanced substrate-based array package
KR20060100250A (en) Semiconductor device
CN111261598A (en) Packaging structure and power module applicable to same
KR101706825B1 (en) Semiconductor Package
JP2000294723A (en) Stacked semiconductor device and its manufacture
WO2005086217A1 (en) Matrix-type semiconductor package with heat spreader
US9147630B2 (en) Power semiconductor assembly and module
US20070145576A1 (en) Power Semiconductor Circuit And Method Of Manufacturing A Power Semiconductor Circuit
JP2001085603A (en) Semiconductor device
US7253506B2 (en) Micro lead frame package
US7310224B2 (en) Electronic apparatus with thermal module
JP4759716B2 (en) Power semiconductor module
KR20030045950A (en) Multi chip package comprising heat sinks
US8471370B2 (en) Semiconductor element with semiconductor die and lead frames
US6057594A (en) High power dissipating tape ball grid array package
KR100220249B1 (en) Thermally enhanced thin ball grid array package
CN110676232B (en) Semiconductor device packaging structure, manufacturing method thereof and electronic equipment

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17757547

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2017757547

Country of ref document: EP

Effective date: 20200225