CN110634818B - Packaging structure of hybrid power module composed of IGBT and MOSFET - Google Patents

Packaging structure of hybrid power module composed of IGBT and MOSFET Download PDF

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CN110634818B
CN110634818B CN201910913759.1A CN201910913759A CN110634818B CN 110634818 B CN110634818 B CN 110634818B CN 201910913759 A CN201910913759 A CN 201910913759A CN 110634818 B CN110634818 B CN 110634818B
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electrode
copper
clad
mosfet
igbt
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CN110634818A (en
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王俊
曾重
付启卉
刘轶哲
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Hunan University
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Hunan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Abstract

The invention relates to the technical field of power electronic devices, in particular to a packaging structure of a hybrid power module consisting of an IGBT (insulated gate bipolar transistor) and an MOSFET (metal-oxide-semiconductor field effect transistor), which comprises a bottom metal plate and a top metal plate, wherein two DBC (direct bus) plates are respectively arranged on the bottom metal plate and the top metal plate in an isolated manner; the DBC board is provided with a Si IGBT, a MOSFET and a diode chip in parallel; the laminated busbar is respectively connected with corresponding copper-clad areas arranged on the surfaces of the bottom DBC plate and the top DBC plate; the outer shell is arranged along the periphery of the DBC plate and forms a closed structure with the four DBC plates in an enclosing mode; and each pin of the laminated busbar penetrates out of the side of the shell so as to be connected with an external circuit. Compared with the traditional packaging structure based on bonding wire interconnection and single-side heat dissipation, the packaging structure has the advantages that the advantages of low parasitic parameters of the laminated busbar are brought into play, the high-speed switching performance of the MOSFET is brought into play to the maximum, double-side heat dissipation can be realized to improve the power density, and the packaging structure has the characteristics of compact space, simplicity and quickness in assembly and the like.

Description

Packaging structure of hybrid power module composed of IGBT and MOSFET
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a packaging structure of a hybrid power module consisting of an IGBT and an MOSFET.
Background
An Insulated Gate Bipolar Transistor (IGBT) based on silicon (Si) material is a power electronic device that combines the advantages of Metal-oxide-semiconductor field effect transistors (MOSFETs) and Bipolar Junction Transistors (BJTs). The Si IGBT is used as a novel power semiconductor field control self-turn-off device, integrates the high-speed performance of the Si MOSFET and the low resistance of a bipolar device, has the characteristics of high input impedance, low voltage control power consumption, simple control circuit, high voltage resistance, large current bearing capacity and the like, is widely applied due to excellent performance, greatly improves the performance of power electronic devices and systems, and is widely applied to various power conversion.
The Si IGBT has one important feature when turned off: the collector current decays slowly, i.e. the tail current is significant. The collector tail current causes problems of increased switching loss and increased heat generation, particularly when used as a high frequency switch. Thus, as the power level of a Si IGBT increases, its switching operating frequency is significantly limited by its tail current, and it is difficult to further increase.
The Si MOSFET has the advantages of small driving power, high switching speed, high working frequency and low cost, the switching loss is small, the dynamic loss caused by the on-resistance is high, and the on-resistance of the Si MOSFET is required to be reduced in order to reduce the dynamic loss of the Si MOSFET. The breakdown voltage (Bv) and the on-resistance (Ron) of the Si MOSFET have
Figure 450862DEST_PATH_IMAGE001
The limit relationship (referred to as "silicon limit") of (a), which is generally used in low voltage applications, is weak in current-carrying withstand voltage.
The CoolMOS with the novel PN alternating structure can achieve lower dynamic loss and higher switching speed at the same time, the on-resistance of the CoolMOS is about one fifth of that of a common Si MOSFET, the contradiction between the on-resistance and the device voltage resistance is improved, and higher voltage resistance level can be achieved. But the body diode has poor reverse recovery characteristics and the manufacturing process is difficult.
The silicon material is not suitable for special application occasions such as high pressure, high temperature, high efficiency, high power density and the like due to the limitation of the physical properties of the silicon material. Since the nineties of the twentieth century, the related technologies of silicon carbide (SiC) materials and devices thereof have been rapidly developed. Compared with Si materials, the SiC materials have the characteristics of high current density due to the high thermal conductivity, and high voltage resistance and high temperature resistance due to the large forbidden band width. Compared with a Si MOSFET, the SiC MOSFET has smaller on-resistance and higher breakdown voltage; compared with the Si IGBT with the same power level, the blocking voltage level of the two is equivalent, but due to the excellent performance of the SiC material, the switching loss of the SiC MOSFET is obviously lower than that of the Si IGBT with obvious trailing current, and in addition, the working temperature of the SiC MOSFET is far higher than that of a Si device, so that the SiC MOSFET has better high-temperature working performance.
Currently, SiC MOSFETs face problems: the cost of the silicon carbide material is high, and the cost of the corresponding device is more than 5 times of that of a Si device with the same power grade; the defect density of the SiC material is still higher than that of the Si material, and the defect density is limited by the production yield, and the size of a single SiC MOSFET chip is still obviously smaller than that of the existing Si IGBT chip; the highest operable switching frequency of the SiC MOSFET is obviously higher than that of the Si IGBT, but the high-speed switching performance of the SiC MOSFET cannot be fully exerted due to the parasitic parameters brought by the traditional packaging technology and structure. Thus, to a certain extent, the higher device cost, smaller chip size and the lack of conventional packaging limit the popularization and application of SiC MOSFETs to higher power class, higher switching frequency power conversion devices.
Disclosure of Invention
The present invention is directed to a package structure of a hybrid power module including an IGBT and a MOSFET, in which a MOSFET having the same blocking voltage class is combined in parallel with a Si IGBT. Under the condition of lower voltage level, a Si MOSFET or CoolMOS and a Si IGBT can be selected and combined in parallel, and the MOSFET can fully exert the remarkable advantage of low switching loss by virtue of a packaging structure and a corresponding switching optimization technology, so that the defect of larger switching loss of the Si IGBT is overcome; under the condition of higher voltage level, the SiC MOSFET and the Si IGBT can be selected to be combined in parallel, and the two devices can work simultaneously under the coordination of the switch optimization technology, so that the power output capability of the composite device can reach the sum of the two devices on the whole, and the cost is far less than that of a full SiC MOSFET with the same power output capability. In addition, through further optimization of the packaging structure, the influence of space distribution parameters such as parasitic inductance and the like caused by packaging on the working performance of the MOSFET high-speed switch is reduced, and the high-speed switching performance of the MOSFET is exerted to the maximum extent. Therefore, the composite device packaging structure is matched with a corresponding switch optimization technology, the working capacity of the MOSFET high-speed switch can be exerted on the premise of no large-amplitude cost increase, the problem of large switching loss of the Si IGBT is solved, the Si IGBT is helped to improve the switching working frequency of the Si IGBT, and further technical support is brought to the high power density of the electric energy conversion device.
In order to solve the technical problems, the invention adopts a technical scheme that: the packaging structure of the hybrid power module formed by the IGBT and the MOSFET comprises a bottom metal plate and a top metal plate, wherein two DBC plates are respectively arranged on the bottom metal plate and the top metal plate in an isolated mode, and a first DBC plate and a second DBC plate are respectively arranged on the bottom metal plate and the top metal plate; the bottom first DBC plate and the bottom second DBC plate are fixedly arranged above the bottom metal plate at intervals, and the top first DBC plate and the top second DBC plate are fixedly arranged below the top metal plate at intervals; two MOSFETs are arranged on the top DBC plate in parallel, and two Si IGBTs and diode chips are arranged on the bottom DBC plate in parallel; the top metal plate is connected with the DBC plate on the bottom metal plate through a socket and a bus bar;
the first DBC plate at the bottom is provided with a first Si IGBT, a second Si IGBT and a first diode chip, the first DBC plate at the top is provided with a first MOSFET and a second MOSFET, the second DBC plate at the bottom is provided with a third Si IGBT, a fourth Si IGBT and a second diode chip, and the second DBC plate at the top is provided with a third MOSFET and a fourth MOSFET;
the upper surface of the first Si IGBT chip is provided with a G1 electrode and an E1 electrode, the lower surface of the first Si IGBT chip is provided with a C1 electrode, the upper surface of the second Si IGBT chip is provided with a G2 electrode and an E2 electrode, the lower surface of the second Si IGBT chip is provided with a C2 electrode, the upper surface of the first diode chip is provided with an A1 electrode, the lower surface of the first diode chip is provided with a K1 electrode, the upper surface of the first DBC plate at the bottom is provided with a C2/C2 copper-clad area connected with the C1 electrode, the C2 electrode and the K2 electrode, a G2/G2 copper-clad area connected with the G2 electrode and the G2 electrode, a first E2/E2 copper-clad area connected with the E2 electrode and the E2 electrode, a first G2/G2 copper-clad area, a first S2/S2 copper-clad area, a negative electrode, and a second E72/E2 copper-clad area connected with the E2 electrode; similarly, the third and fourth Si IGBTs and the second diode chip are arranged on the bottom second DBC plate, the upper surface of the third Si IGBT chip is provided with a G3 electrode and an E3 electrode, the lower surface is provided with a C3 electrode, the upper surface of the fourth Si IGBT chip is provided with a G4 electrode and an E4 electrode, the lower surface is provided with a C4 electrode, the upper surface of the second diode chip is provided with an a2 electrode, the lower surface is provided with a K2 electrode, the upper surface of the bottom second DBC plate is provided with a C4/C4 copper-clad region connected with the C3 electrode, the C4 electrode and the K4 electrode, a G4/G4 copper-clad region connected with the G4 electrode and the G4 electrode, a first E4/E4 copper-clad region connected with the E4 electrode and the E4 electrode, a first G4/G4 copper-clad region, a first S4/S4 copper-clad region connected with the E4 electrode, E4 electrode and a second electrode 4/E4.
Furthermore, the first Si IGBT, the second Si IGBT, the first diode chip, the first MOSFET and the second MOSFET are connected in parallel through bonding wires, pin headers and bus bars; and the third Si IGBT, the fourth Si IGBT, the second diode chip, the third MOSFET and the fourth MOSFET are connected in parallel through bonding wires, pin headers and bus bars.
As a further improvement, the first and second MOSFET chips are arranged on the top first DBC plate, the upper surface of the first MOSFET chip is provided with a G5 electrode and a S1 electrode, the lower surface of the first MOSFET chip is provided with a D1 electrode, the upper surface of the second MOSFET chip is provided with a G6 electrode and a S2 electrode, the lower surface of the second MOSFET chip is provided with a D2 electrode, the upper surface of the top first DBC plate is provided with a D1/D2 copper-clad region connected with the D1 electrode and the D2 electrode, a second G5/G6 copper-clad region connected with the G5 electrode and the G6 electrode, a second S1/S2 copper-clad region connected with the S1 electrode and the S2 electrode, and a third S1/S2 copper-clad region; similarly, the third and fourth MOSFET chips are arranged on the top second DBC plate, the upper surface of the third MOSFET chip is provided with a G7 electrode and a S3 electrode, the lower surface of the third MOSFET chip is provided with a D3 electrode, the upper surface of the fourth MOSFET chip is provided with a G8 electrode and a S4 electrode, the lower surface of the fourth MOSFET chip is provided with a D4 electrode, the upper surface of the top second DBC plate is provided with a D3/D4 copper-clad area connected with a D3 electrode and a D4 electrode, a second G7/G8 copper-clad area connected with a G7 electrode and a G8 electrode, a second S3/S4 copper-clad area connected with a S3 electrode and a S4 electrode, and a third S3/S4 copper-clad area.
Specifically, the C1 electrode, the C2 electrode and the K1 electrode are fixed with a C1/C2 copper-clad area through welding or sintering, the G1 electrode and the G2 electrode are fixed with a G1/G2 copper-clad area, the E1 electrode and the E2 electrode are connected with a first E1/E2 copper-clad area, and the E1 electrode, the E2 electrode and the A1 electrode are connected with a second E1/E2 copper-clad area through metal bonding wires; similarly, the C3 electrode, the C4 electrode and the K2 electrode are fixed with the C3/C4 copper-clad area through welding or sintering, the G3 electrode and the G4 electrode are fixed with the G3/G4 copper-clad area, the E3 electrode and the E4 electrode are connected with the first E3/E4 copper-clad area, and the E3 electrode, the E4 electrode and the A2 electrode are connected with the second E3/E4 copper-clad area through metal bonding wires; the D1 electrode and the D2 electrode are fixed with the D1/D2 copper-clad area through welding or sintering, the G5 electrode and the G6 electrode are connected with the second G5/G6 copper-clad area, and the S1 electrode and the S2 electrode are connected with the second S1/S2 copper-clad area and the third S1/S2 copper-clad area through metal bonding wires; similarly, the D3 electrode and the D4 electrode are fixed with the D3/D4 copper-clad area through welding or sintering, the G7 electrode and the G8 electrode are connected with the second G7/G8 copper-clad area, the S3 electrode and the S4 electrode are connected with the second S3/S4 copper-clad area and the third S3/S4 copper-clad area through metal bonding wires; furthermore, the C1/C2 copper-clad area and the D1/D2 copper-clad area, the first G5/G6 copper-clad area and the second G5/G6 copper-clad area, the first S1/S2 copper-clad area and the second S1/S2 copper-clad area, the second E1/E2 copper-clad area and the third S1/S2 copper-clad area, the C3/C4 copper-clad area and the D3/D4 copper-clad area, the first G7/G8 copper-clad area and the second G7/G8 copper-clad area, the first S3/S4 copper-clad area and the second S3/S4 copper-clad area, the second E3/E4 copper-clad area and the third S3/S4 copper-clad area are connected through a pin and a mother block.
As a modification, the parallel connection of the first Si IGBT, the second Si IGBT and the first diode chip is realized through the C1/C2 copper-clad area and the second E1/E2 copper-clad area, the parallel connection of the third Si IGBT, the fourth Si IGBT and the second diode chip is realized through the C3/C4 copper-clad area and the second E3/E4 copper-clad area, the parallel connection of the first MOSFET and the second MOSFET chip is realized through the D1/D2 copper-clad area and the second S1/S2 copper-clad area, the parallel connection of the third MOSFET and the fourth MOSFET chip is realized through the D3/D4 copper-clad area and the second S3/S4 copper-clad area, the parallel connection of the first Si IGBT, the second Si IGBT, the first MOSFET, the second MOSFET and the first diode chip is realized through the pin bank and the bank, the upper bridge arm pin of the half-bridge circuit is formed, and the parallel connection of the first IGBT and the bank is realized through the bank pin and the bank pin, The fourth Si IGBT, the third MOSFET, the fourth MOSFET and the second diode chip are connected in parallel to form a lower bridge arm of a half-bridge circuit, a second E1/E2 copper-clad area, a C3/C4 copper-clad area, a negative copper-clad area and a second E3/E4 copper-clad area are connected through metal bonding wires to realize series connection of the upper bridge arm and the lower bridge arm, and the copper-clad areas are connected with external pins as required through the metal bonding wires.
As a further improvement mode, the top metal plate, the bottom metal plate and the shell form a closed space, the top DBC plate, the bottom DBC plate, the top MOSFET, the bottom Si IGBT, the bottom diode chip, the pin header and the bus header are located in the closed space, and each pin is connected with the corresponding copper-clad area through a bonding wire and penetrates out from the side of the shell so as to be connected with an external circuit.
The technical scheme of the invention has the following advantages compared with the prior art: according to the packaging structure of the hybrid power module formed by the IGBT and the MOSFET, the Si IGBT and the MOSFET are connected in parallel, and an optimized switching mode is adopted, so that the problems of large switching loss and low switching frequency of the IGBT are solved; meanwhile, the packaging structure provided by the invention can obtain better module performance at lower cost, so that the overall performance of the composite device approaches to a single type device with the same power grade, but the price has obvious advantage compared with the latter; moreover, the packaging structure provided by the invention can reduce parasitic parameters and suppress the influence of space distribution parameters on the working performance of the MOSFET high-speed switch; in addition, the packaging structure has double-sided heat dissipation capacity, improves the power density of the module, and has the characteristics of compact space, simple and rapid assembly and the like.
Drawings
FIG. 1 is an electrical schematic diagram of a modular composite of a half-bridge circuit topology;
FIG. 2 is a front left top view of the module;
FIG. 3 is a top view of the bottom metal plate in the module;
FIG. 4 is a bottom view of the top metal plate in the module;
FIG. 5 is a front left plan view of a laminated busbar in the module;
FIG. 6 is a rear left plan view of a laminated busbar in the module;
FIG. 7 is a top view of the laminated busbar connected to the copper-clad region of the bottom metal plate. In the figure: 11: a bottom metal plate; 12: a top metal plate; 21: a bottom first DBC plate; 22: a bottom second DBC plate; 23: a top first DBC plate; 24: a top second DBC plate; 311: a first Si IGBT chip; 312: a second Si IGBT chip; 313: a third Si IGBT chip; 314: a fourth Si IGBT chip; 321: a first MOSFET chip; 322: a second MOSFET chip; 323: a third MOSFET chip; 324: a fourth MOSFET chip; 331: a first diode chip; 332: a second diode chip; 411: C1/C2 copper-clad area; 412: G1/G2 copper-clad area; 413: a first E1/E2 copper-clad zone; 414: a second E1/E2 copper-clad area; 415: a first G5/G6 copper-clad area; 416: a first S1/S2 copper-clad area; 417: a negative copper-clad area; 421: C3/C4 copper-clad area; 422: G3/G4 copper-clad area; 423: a first E3/E4 copper-clad zone; 424: a second E3/E4 copper-clad area; 425: a first G7/G8 copper-clad area; 426: a first S3/S4 copper-clad area; 431: D1/D2 copper-clad area; 432: a second G5/G6 copper-clad area; 433: a second S1/S2 copper-clad area; 434: a third S1/S2 copper-clad area; 441: D3/D4 copper-clad area; 442: a second G7/G8 copper-clad area; 443: a second S3/S4 copper-clad area; 444: a third S3/S4 copper-clad area; 501: arranging needles 1; 502: arranging needles 2; 503: a pin header 3; 504: a pin header 4; 505: a pin header 5; 506: a pin header 6; 511: arranging a mother 1; 512: arranging a mother 2; 513: arranging a mother board 3; 514: arranging a mother board 4; 515: arranging a mother 5; 516: arranging a mother 6; 601: an external pin 1; 602: an external pin 2; 603: an external pin 3; 604: an external pin 4; 605: an external pin 5; 606: an external pin 6; 607: an external pin 7; 608: an external pin 8; 609: an external pin 9; 610: an external pin 10; 611: an external pin 11; 612: an external pin 12; 613: an external pin 13; 614: external leads 14; 70: a housing.
Detailed description of the preferred embodiments
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are one embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, belong to the scope of the present invention.
It should be noted that the terms "first," "second," "third," "fourth," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. It is also to be understood that, unless otherwise explicitly specified or limited, the term "coupled" is to be interpreted broadly, e.g., as meaning either a fixed or removable connection, or an integral connection; can be mechanically or electrically connected; may be directly connected. Or indirectly through an intermediate. The specific meaning of the above terms in the present invention can be understood as appropriate to those of ordinary skill in the art.
The packaging structure of the hybrid power module composed of the IGBTs and the MOSFETs provided by the embodiment of the invention comprises a bottom metal plate 11, a top metal plate 12, a bottom first DBC plate 21, a bottom second DBC plate 22, a top first DBC plate 23, a top second DBC plate 24, a first Si IGBT chip 311, a second Si IGBT chip 312, a third Si IGBT chip 313, a fourth Si IGBT chip 314, a first MOSFET chip 321, a second MOSFET chip 322, a third MOSFET chip 323, a fourth MOSFET chip 324, a first diode chip 331, a second diode chip 332, a pin arrangement 1501, a pin arrangement 2502, a pin arrangement 3503, a pin arrangement 4504, a pin arrangement 5505, a pin arrangement 6506, a pin arrangement 1511, a pin arrangement 2512, a pin arrangement 3513, a pin arrangement 4514, a pin arrangement 5515, a pin arrangement 6516 and a housing 70; a bottom first DBC plate 21 and a bottom second DBC plate 22 are paved above the bottom metal plate 11 and are fixedly connected with the upper surface of the bottom metal plate 11 at a certain interval, a top first DBC plate 23 and a top second DBC plate 24 are paved below the top metal plate 12 at a certain interval and are fixedly connected with the lower surface of the top metal plate 12, and a shell 70 is arranged along the periphery of the DBC plates and forms a closed structure with the bottom first DBC plate 21, the bottom second DBC plate 22, the top first DBC plate 23 and the top second DBC plate 24; the first Si IGBT chip 311, the second Si IGBT chip 312 and the first diode chip 331 are arranged on the first DBC plate 21 at the bottom, the upper surface of the first Si IGBT chip 311 is provided with a G1 electrode and an E1 electrode, the lower surface is provided with a C1 electrode, the upper surface of the second Si IGBT chip is provided with a G2 electrode and an E2 electrode, the lower surface is provided with a C2 electrode, the upper surface of the first diode chip is provided with an A1 electrode, the lower surface is provided with a K1 electrode, the upper surface of the first DBC plate 21 at the bottom is provided with a C1/C2 copper-clad area 411 connected with a C1 electrode, a C2 electrode and a K1 electrode, a G1/G2 copper-clad area 412 connected with a G1 electrode and a G2 electrode, a first E1/E2 copper-clad area 413 connected with an E1 electrode and an E2 electrode, a first G5/G6 copper-clad area 415, a first S1/S2 copper-clad area 416, a negative copper-clad area 417, and a second E1/E2 copper-clad area 414 connected with an E1 electrode, an E2 electrode and an A1 electrode; similarly, a third Si IGBT chip 313, a fourth Si IGBT chip 314, and a second diode chip 332 are provided on the bottom second DBC plate 22, the upper surface of the third Si IGBT chip 313 is provided with a G3 electrode and an E3 electrode, the lower surface is provided with a C3 electrode, the upper surface of the fourth Si IGBT chip 314 is provided with a G4 electrode and an E4 electrode, the lower surface is provided with a C4 electrode, the upper surface of the second diode chip 332 is provided with an a2 electrode, the lower surface is provided with a K2 electrode, the upper surface of the second DBC plate 22 at the bottom is provided with a C3/C4 copper-clad area 421 connected with a C3 electrode, a C4 electrode and a K2 electrode, a G3/G4 copper-clad area 422 connected with a G3 electrode and a G4 electrode, a first E3/E4 copper-clad area 423 connected with an E3 electrode and an E4 electrode, a first G7/G8 copper-clad area 425, a first S3/S4 copper-clad area 426, and a second E3/E4 copper-clad area 424 connected with an E3 electrode, an E4 electrode and an A2 electrode; the first MOSFET chip 321 and the second MOSFET chip 322 are arranged on the top first DBC plate 23, the upper surface of the first MOSFET chip 321 is provided with a G5 electrode and a S1 electrode, the lower surface of the first MOSFET chip 321 is provided with a D1 electrode, the upper surface of the second MOSFET chip 322 is provided with a G6 electrode and a S2 electrode, the lower surface of the second MOSFET chip 322 is provided with a D2 electrode, the upper surface of the top first DBC plate 23 is provided with a D1/D2 copper-clad area 431 connected with a D1 electrode and a D2 electrode, a second G5/G6 copper-clad area 432 connected with a G5 electrode and a G6 electrode, a second S1/S2 copper-clad area 433 connected with a S1 electrode and a S2 electrode and a third S1/S2 copper-clad area 434; similarly, the third MOSFET chip 323 and the fourth MOSFET chip 324 are disposed on the top second DBC plate 24, the upper surface of the third MOSFET chip 323 is provided with a G7 electrode and a S3 electrode, the lower surface is provided with a D3 electrode, the upper surface of the fourth MOSFET chip 324 is provided with a G8 electrode and a S4 electrode, the lower surface is provided with a D4 electrode, the upper surface of the top second DBC plate 24 is provided with a D3/D4 copper-clad region 441 connected to the D3 electrode and the D4 electrode, a second G7/G8 copper-clad region 442 connected to the G7 electrode and the G8 electrode, a second S3/S4 copper-clad region 443 and a third S3/S4 copper-clad region 444 connected to the S3 electrode and the S4 electrode.
Further, the following operations were carried out: the C1 electrode, the C2 electrode and the K1 electrode are fixed with the C1/C2 copper-clad area 411 through welding or sintering; the G1 electrode and the G2 electrode are connected with the G1/G2 copper-clad area 412 through metal bonding wires; the E1 electrode and the E2 electrode are connected to the first E1/E2 copper-clad region 413 by a metal bonding wire; the E1 electrode, E2 electrode, and a1 electrode are connected to the second E1/E2 copper-clad region 414 by a metal bonding wire; c3 electrode, C4 electrode and K2 electrode are fixed with the C3/C4 copper-clad area 421 by welding or sintering; the G3 electrode and the G4 electrode are connected with the G3/G4 copper-clad area 422 through metal bonding wires; the E3 electrode and the E4 electrode are connected to the first E3/E4 copper metallization region 423 by a metal bonding wire; the E3 electrode, E4 electrode, and a2 electrode are connected to a second E3/E4 copper metallization region 424 by a metal bond wire; further, the following operations were carried out: the D1 electrode and the D2 electrode are fixed with the D1/D2 copper-clad area 431 by welding or sintering; b, a G5 electrode and a G6 electrode are connected to a second G5/G6 copper metallization region 432 by a metal bonding wire; the S1 electrode and the S2 electrode are connected with the second S1/S2 copper-clad area 433 and the third S1/S2 copper-clad area 434 through metal bonding wires; d3 electrode and D4 electrode are fixed with the D3/D4 copper-clad area 441 by welding or sintering; the G7 electrode and the G8 electrode are connected with the second G7/G8 copper-clad region 442 through metal bonding wires; the S3 electrode and the S4 electrode are connected to the second S3/S4 copper-clad region 443 and the third S3/S4 copper-clad region 444 through metal bonding wires; further, the following operations were carried out: the C1/C2 copper-clad area 411 and the D1/D2 copper-clad area 431 are connected through a pin bar 1501 and a female bar 1511; a first G5/G6 copper-clad zone 415 and a second G5/G6 copper-clad zone 432, a first S1/S2 copper-clad zone 416 and a second S1/S2 copper-clad zone 433 are connected by a pin header 2502 and a box header 2512; c, a second E1/E2 copper metallization zone 414 and a third S1/S2 copper metallization zone 434 are connected by a pin header 3503 and a box header 3503; the C3/C4 copper-clad area 421 and the D3/D4 copper-clad area 441 are connected through a pin 4504 and a female row 4514; the first G7/G8 copper metallization region 425 and the second G7/G8 copper metallization region 442, the first S3/S4 copper metallization region 426 and the second S3/S4 copper metallization region 443 are connected through the pin header 5505 and the box header 5515; a second E3/E4 copper metallization area 424 and a third S3/S4 copper metallization area 444 are connected by a pin header 6506 and a box header 6516.
Further, the parallel connection of the first Si IGBT chip 311, the second Si IGBT chip 312 and the first diode chip 331 is realized through the C1/C2 copper-clad area 411 and the second E1/E2 copper-clad area 414, the parallel connection of the third Si IGBT chip 313, the fourth Si IGBT chip 314 and the second diode chip 332 is realized through the C3/C4 copper-clad area 421 and the second E3/E4 copper-clad area 424, the parallel connection of the first MOSFET chip 321 and the second MOSFET chip 322 is realized through the D1/D2 copper-clad area 431 and the second S1/S2 copper-clad area 433, the parallel connection of the third MOSFET chip 323 and the fourth MOSFET chip 324 is realized through the D3/D4 copper-clad area 441 and the second S3/S4 copper-clad area 443, the parallel connection of the first Si IGBT chip 311, the second Si IGBT chip 312, the first MOSFET chip 331 and the second MOSFET chip 322 is realized through the pin bank 1501, the pin bank 1511 and the bank 3513, forming an upper bridge arm of the half-bridge circuit, similarly, realizing the parallel connection of a third Si IGBT chip 313, a fourth Si IGBT chip 314, a third MOSFET chip 323, a fourth MOSFET chip 324 and a second diode chip 331 through a pin bank 4504, a pin bank 6506, a pin bank 4514 and a pin bank 5515, forming a lower bridge arm of the half-bridge circuit, realizing the series connection of the upper bridge arm and the lower bridge arm through connecting a second E1/E2 copper-clad area 414 and a C3/4 copper-clad area 421, a negative copper-clad area 417 and a second E3/E4 copper-clad area 424 through metal bonding wires, and connecting a C1/C2 copper-clad area 411 and an external pin 1601, a G1/G2 copper-clad area 412 and an external pin 2602, a first E1/E2 copper-clad area 413 and an external pin 3603, a first G5/G6 copper-clad area 415 and an external pin 4604, a first S1/S2 and an external pin 5965 and an external pin 4, and a C366/E6615 and an external pin-clad area 421 and a C6606, G3/G4 copper-clad area 422 and external pin 7607, first E3/E4 copper-clad area 423 and external pin 8608, first G7/G8 copper-clad area 425 and external pin 9609, first S3/S4 copper-clad area 426 and external pin 10610, C3/C4 copper-clad area 421 and external pin 11611 and external pin 12612, negative copper-clad area 417 and external pin 13613, C1/C2 copper-clad area 411 and external pin 14614, and each pin passes out from the side of the housing 70 to be connected with an external circuit.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (7)

1. A packaging structure of a hybrid power module composed of an IGBT and an MOSFET is characterized by comprising a bottom metal plate and a top metal plate, wherein the bottom metal plate and the top metal plate are respectively provided with two DBC plates in an isolated mode, and the first DBC plate and the second DBC plate are respectively arranged on the bottom metal plate and the top metal plate; the bottom first DBC plate and the bottom second DBC plate are fixedly arranged above the bottom metal plate at intervals, and the top first DBC plate and the top second DBC plate are fixedly arranged below the top metal plate at intervals; two MOSFETs are arranged on the top DBC plate in parallel, and two Si IGBTs and diode chips are arranged on the bottom DBC plate in parallel; the top metal plate is connected with the DBC plate on the bottom metal plate through a socket and a bus bar;
the first DBC plate at the bottom is provided with a first Si IGBT, a second Si IGBT and a first diode chip, the first DBC plate at the top is provided with a first MOSFET and a second MOSFET, the second DBC plate at the bottom is provided with a third Si IGBT, a fourth Si IGBT and a second diode chip, and the second DBC plate at the top is provided with a third MOSFET and a fourth MOSFET;
the upper surface of the first Si IGBT chip is provided with a G1 electrode and an E1 electrode, the lower surface of the first Si IGBT chip is provided with a C1 electrode, the upper surface of the second Si IGBT chip is provided with a G2 electrode and an E2 electrode, the lower surface of the second Si IGBT chip is provided with a C2 electrode, the upper surface of the first diode chip is provided with an A1 electrode, the lower surface of the first diode chip is provided with a K1 electrode, the upper surface of the first DBC plate at the bottom is provided with a C2/C2 copper-clad area connected with the C1 electrode, the C2 electrode and the K2 electrode, a G2/G2 copper-clad area connected with the G2 electrode and the G2 electrode, a first E2/E2 copper-clad area connected with the E2 electrode and the E2 electrode, a first G2/G2 copper-clad area, a first S2/S2 copper-clad area, a negative electrode, and a second E72/E2 copper-clad area connected with the E2 electrode; similarly, the third and fourth Si IGBTs and the second diode chip are arranged on the bottom second DBC plate, the upper surface of the third Si IGBT chip is provided with a G3 electrode and an E3 electrode, the lower surface is provided with a C3 electrode, the upper surface of the fourth Si IGBT chip is provided with a G4 electrode and an E4 electrode, the lower surface is provided with a C4 electrode, the upper surface of the second diode chip is provided with an a2 electrode, the lower surface is provided with a K2 electrode, the upper surface of the bottom second DBC plate is provided with a C4/C4 copper-clad region connected with the C3 electrode, the C4 electrode and the K4 electrode, a G4/G4 copper-clad region connected with the G4 electrode and the G4 electrode, a first E4/E4 copper-clad region connected with the E4 electrode and the E4 electrode, a first G4/G4 copper-clad region, a first S4/S4 copper-clad region connected with the E4 electrode, E4 electrode and a second electrode 4/E4.
2. The package structure of a hybrid power module composed of an IGBT and a MOSFET according to claim 1, wherein the first Si IGBT, the second Si IGBT, the first diode chip, the first MOSFET, and the second MOSFET are connected in parallel by a bonding wire, a pin bar, and a bus bar; and the third Si IGBT, the fourth Si IGBT, the second diode chip, the third MOSFET and the fourth MOSFET are connected in parallel through bonding wires, pin headers and bus bars.
3. The package structure of a hybrid power module composed of an IGBT and a MOSFET according to claim 2, wherein the first and second MOSFET chips are provided on the top first DBC plate, the first MOSFET chip is provided at an upper surface thereof with a G5 electrode and a S1 electrode, and at a lower surface thereof with a D1 electrode, the second MOSFET chip is provided at an upper surface thereof with a G6 electrode and a S2 electrode, and at a lower surface thereof with a D2 electrode, and the top first DBC plate is provided at an upper surface thereof with a D1/D2 copper-clad region connected to the D1 electrode and the D2 electrode, a second G5/G6 copper-clad region connected to the G5 electrode and the G6 electrode, a second S1/S2 copper-clad region and a third S1/S2 copper-clad region connected to the S1 electrode and the S2 electrode; similarly, the third and fourth MOSFET chips are arranged on the top second DBC plate, the upper surface of the third MOSFET chip is provided with a G7 electrode and a S3 electrode, the lower surface of the third MOSFET chip is provided with a D3 electrode, the upper surface of the fourth MOSFET chip is provided with a G8 electrode and a S4 electrode, the lower surface of the fourth MOSFET chip is provided with a D4 electrode, the upper surface of the top second DBC plate is provided with a D3/D4 copper-clad area connected with a D3 electrode and a D4 electrode, a second G7/G8 copper-clad area connected with a G7 electrode and a G8 electrode, a second S3/S4 copper-clad area connected with a S3 electrode and a S4 electrode, and a third S3/S4 copper-clad area.
4. The package structure of a hybrid power module composed of an IGBT and a MOSFET according to claim 3, wherein the C1 electrode, the C2 electrode, and the K1 electrode are fixed to the C1/C2 copper-clad region by welding or sintering, the G1 electrode and the G2 electrode are connected to the G1/G2 copper-clad region, the E1 electrode and the E2 electrode are connected to the first E1/E2 copper-clad region, and the E1 electrode, the E2 electrode, and the a1 electrode are connected to the second E1/E2 copper-clad region by metal bonding wires; similarly, the C3 electrode, the C4 electrode and the K2 electrode are fixed with the C3/C4 copper-clad area through welding or sintering, the G3 electrode and the G4 electrode are fixed with the G3/G4 copper-clad area, the E3 electrode and the E4 electrode are connected with the first E3/E4 copper-clad area, and the E3 electrode, the E4 electrode and the A2 electrode are connected with the second E3/E4 copper-clad area through metal bonding wires; the D1 electrode and the D2 electrode are fixed with the D1/D2 copper-clad area through welding or sintering, the G5 electrode and the G6 electrode are connected with the second G5/G6 copper-clad area, and the S1 electrode and the S2 electrode are connected with the second S1/S2 copper-clad area and the third S1/S2 copper-clad area through metal bonding wires;
similarly, the D3 electrode and the D4 electrode are fixed with the D3/D4 copper-clad area through welding or sintering, the G7 electrode and the G8 electrode are connected with the second G7/G8 copper-clad area, and the S3 electrode and the S4 electrode are connected with the second S3/S4 copper-clad area and the third S3/S4 copper-clad area through metal bonding wires.
5. The package structure of a hybrid power module composed of IGBTs and MOSFETs according to claim 4, wherein the C1/C2 copper-clad area and the D1/D2 copper-clad area, the first G5/G6 copper-clad area and the second G5/G6 copper-clad area, the first S1/S2 copper-clad area and the second S1/S2 copper-clad area, the second E1/E2 copper-clad area and the third S1/S2 copper-clad area, the C3/C4 copper-clad area and the D3/D4 copper-clad area, the first G7/G8 copper-clad area and the second G7/G8 copper-clad area, the first S3/S4 copper-clad area and the second S3/S4 copper-clad area, the second E3/E4 copper-clad area and the third S3/S4 copper-clad area are arranged by female needles and female needles.
6. The package structure of a hybrid power module composed of IGBTs and MOSFETs, according to claim 5, wherein the parallel connection of the first Si IGBT, the second Si IGBT and the first diode chip is realized by the C1/C2 copper-clad region and the second E1/E2 copper-clad region, the parallel connection of the third Si IGBT, the fourth Si IGBT and the second diode chip is realized by the C3/C4 copper-clad region and the second E3/E4 copper-clad region, the parallel connection of the first MOSFET and the second MOSFET chip is realized by the D1/D2 copper-clad region and the second S1/S2 copper-clad region, the parallel connection of the third MOSFET and the fourth MOSFET chip is realized by the D3/D4 copper-clad region and the second S3/S4 copper-clad region, the parallel connection of the first Si IGBT, the second Si IGBT, the first MOSFET and the second MOSFET chip is realized by the pin bar and the bar, and the half bridge circuit is formed on the first bridge arm chip, similarly, the third Si IGBT, the fourth Si IGBT, the third MOSFET, the fourth MOSFET and the second diode chip are connected in parallel through pin headers and bus headers to form a lower bridge arm of a half-bridge circuit, a second E1/E2 copper-clad area, a C3/C4 copper-clad area, a negative copper-clad area and a second E3/E4 copper-clad area are connected through metal bonding wires to realize the series connection of an upper bridge arm and the lower bridge arm, and the copper-clad areas are connected with external pins as required through the metal bonding wires.
7. The package structure of a hybrid power module consisting of an IGBT and a MOSFET according to claim 6, wherein the top metal plate, the bottom metal plate and the housing form a closed space, the top DBC plate, the bottom DBC plate, the top MOSFET, the bottom Si IGBT, the bottom diode chip, the pin header and the bus header are located in the closed space, and each pin is connected to a corresponding copper-clad area through a bonding wire and is extended out from the side of the housing to be connected to an external circuit.
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