JP3701228B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device module used for a power inverter.
[0002]
[Prior art]
FIG. 13 shows a circuit configuration of a semiconductor device module 80 having a half-bridge circuit. In FIG. 13, between the collector terminal C1 and the emitter terminal E2, power transistors T1 and T3 such as IGBT (Insulated Gate Bipolar Transistor) are totem-pole connected to constitute a half bridge inverter. The transistors T1 and T3 are respectively connected in reverse parallel with diodes (freewheel diodes) D1 and D3 for circulating current.
[0003]
The connection node of the transistors T1 and T3 is connected to the output terminal OT and also connected to the control emitter terminal CE1. The emitter of the transistor T3 is connected to the emitter terminal E2 and also to the control emitter terminal CE2.
[0004]
Further, between the collector terminal C1 and the emitter terminal E2, power transistors T2 and T4 are totem pole connected, and freewheel diodes D2 and D4 are connected in antiparallel to each other.
[0005]
The connection node of the transistors T2 and T4 is connected to the output terminal OT and also to the control emitter terminal CE1. The emitter of the transistor T4 is connected to the emitter terminal E2 and also to the control emitter terminal CE2.
[0006]
The control emitter terminals CE1 and CE2 are used for driving the transistors T1 to T4. For example, the transistor T1 is driven by applying a gate-emitter voltage (for example, about 15 V) between the control emitter terminal CE1 and the gate terminal G1. can do.
[0007]
The gates of the transistors T1 and T2 are commonly connected to the gate terminal G1, and the transistors T1 and T2 are configured to operate in parallel. The gates of the transistors T3 and T4 are commonly connected to the gate terminal G2, and the transistors T3 and T4 are configured to operate in parallel.
[0008]
The transistors T1 and T2 are devices that perform a switching operation between the collector potential and the potential of the output terminal OT as a reference potential. The transistors T3 and T4 are devices that perform switching operation with respect to the potential of the output terminal OT using the ground potential as a reference potential.
[0009]
Thus, transistors that operate with the same potential as a reference are referred to as transistors of the same arm. Transistors T1 and T2 are connected to the transistor on the P side arm. The Transistors T3 and T4 may be referred to as N-side arm transistors.
[0010]
FIG. 14 shows a planar layout in the package of the semiconductor device module 80. In FIG. 14, conductor patterns P10 and P30 having a rectangular shape in plan view are arranged in parallel on a rectangular circuit board BS. Then, a conductor pattern P20 having an L-shape in plan view is disposed on the outer periphery of the conductor pattern P10 so as to surround approximately half of the outer periphery, and the outer periphery of the conductor pattern P30 is surrounded by approximately half of the outer periphery. In addition, a conductor pattern P40 having an L shape in plan view is disposed. Conductor patterns P20 and P 40 Are arranged so as to have a rotationally symmetrical positional relationship.
[0011]
Transistors T1 and T2 are alternately arranged on the upper portion of the conductor pattern P10 so as to have a rotationally symmetrical positional relationship, and the free wheel diodes D1 and D2 are rotationally symmetric adjacent to the transistors T1 and T2. Are arranged in a staggered manner so as to achieve a proper positional relationship.
[0012]
Similarly, transistors T3 and T4 are alternately arranged above the conductor pattern P30 so as to have a rotationally symmetric positional relationship, and free wheel diodes D3 and D4 are adjacent to the transistors T3 and T4. These are arranged alternately so as to have a rotationally symmetric positional relationship.
[0013]
A collector terminal C1 and an emitter terminal E2 are disposed outside one long side of the circuit board BS. The collector terminal C1 is disposed so as to correspond to the region where the conductor pattern P10 is disposed, and the emitter terminal E2 is disposed so as to correspond to the region where the conductor pattern P30 is disposed.
[0014]
Further, an output terminal OT is disposed outside the other long side of the circuit board BS. The output terminal OT is disposed along the long side so as to correspond to the region where the conductor patterns P10 and P30 are disposed.
[0015]
Furthermore, outside the short side of the circuit board BS on which the conductor pattern P10 is disposed, the control emitter terminal CE1 and the gate terminal G1 are disposed, and the circuit board BS on which the conductor pattern P30 is disposed. A control emitter terminal CE2 and a gate terminal G2 are disposed outside the short side.
[0016]
The collector terminal C1 is electrically connected to the conductor pattern P10 by a wire line WR such as aluminum. The collectors of the transistors T1 and T2 and the cathodes of the freewheel diodes D1 and D2 are respectively arranged on the lower surface side so as to face the conductor pattern P10. The emitters of the transistors T1 and T2, the freewheel diodes D1 and The anodes of D2 are respectively disposed on the upper surface side.
[0017]
The emitters of the transistors T1 and T2 and the anodes of the freewheel diodes D1 and D2 are electrically connected to the output terminal OT by the wire line WR, and the gates of the transistors T1 and T2 are connected to the conductor pattern P20 via the wire line WR. And electrically connected to the gate terminal G1 via the conductor pattern P20. The emitter of the transistor T1 is electrically connected to the control emitter terminal CE1 through the wire line WR.
[0018]
The output terminal OT is electrically connected to the conductor pattern P30 by a wire line WR such as aluminum. The collectors of the transistors T3 and T4 and the cathodes of the freewheel diodes D3 and D4 are arranged on the lower surface side so as to face the conductor pattern P30, respectively. The emitters of the transistors T3 and T4, the freewheel diodes D3 and The anodes of D4 are respectively disposed on the upper surface side.
[0019]
The emitters of the transistors T3 and T4 and the anodes of the freewheel diodes D3 and D4 are electrically connected to the emitter terminal E2 by the wire line WR, and the gates of the transistors T3 and T4 are connected to the conductor pattern P40 via the wire line WR. And is electrically connected to the gate terminal G2 via the conductor pattern P40. The emitter of the transistor T4 is electrically connected to the control emitter terminal CE2 via the wire line WR.
[0020]
As described above, the semiconductor device module 80 has a plurality of IGBTs in one arm, and the IGBTs in the same arm, that is, the transistors T1 and T2 and the transistors T3 and T4 rotate on the conductor patterns P10 and P30, respectively. They were arranged alternately so as to have a symmetrical positional relationship.
[0021]
This is because the ratio of power loss is different between the IGBT and the free wheel diode.
[0022]
FIG. 15 shows an example of a simulation result regarding power loss between the IGBT and the free wheel diode.
[0023]
In FIG. 15, the horizontal axis indicates the current (A) flowing through the arm, the vertical axis indicates the power loss (W), the IGBT characteristics are indicated by thick lines, and the free wheel diode (FWDi) characteristics are indicated by thin lines.
[0024]
As can be seen from FIG. 15, the power loss of the IGBT is at most 6 times that of the free wheel diode. As described above, the IGBT has a larger power loss, that is, a larger amount of heat generation, and thus has become a heat generation source. This is because in the inverter, the transistor mainly contributes to the power conversion, whereas the diode has a small power loss because the paired transistors only flow the reflux current while the pair of transistors is at rest.
[0025]
Therefore, rather than arranging IGBTs in parallel and concentrating the heat sources, the temperature distribution on the circuit board BS is made uniform by distributing the heat sources by staggering the free wheel diodes. The IGBTs were arranged alternately.
[0026]
[Problems to be solved by the invention]
However, by arranging the IGBTs and free wheel diodes alternately, the conductor pattern does not have an equal positional relationship with each chip, and even within the same arm, including differences in wiring length due to wire bonding. A situation occurs in which the wiring inductance of each chip becomes uneven.
[0027]
FIG. 16 shows an equivalent circuit in the P-side arm as an example. As shown in FIG. 16, there are wiring inductances WL between the transistors T1 and T2, the freewheel diodes D1 and D2, and the terminals (C1, E1, G1, and OT), respectively. There are only two inductances WL between the collector of T1 and the collector terminal C1, whereas there are three inductances WL between the transistor T2 and the collector terminal C1.
[0028]
As a result, the collector currents of the transistors T1 and T2 that operate in parallel at the time of switching do not flow evenly, causing a problem that the power loss is biased to a specific IGBT. Needless to say, the wiring inductance includes not only the inductance of the wire line but also the inductance of the configuration serving as a current path, such as the inductance of the conductor pattern.
[0029]
Here, FIG. 17 shows the characteristics of the collector current that flows when the transistors T1 and T2 are switched.
[0030]
In FIG. 17, the horizontal axis indicates time (μsec), the vertical axis indicates the collector current Ic (A), the characteristics of the transistor T1 are indicated by thick lines, and the characteristics of the transistor T2 are indicated by thin lines.
[0031]
As can be seen from FIG. 17, the maximum value of the collector current of the transistor T1 is higher than that of the transistor T2, and the collector currents of the transistors T1 and T2 are unbalanced.
[0032]
In this way, collector current imbalance occurs between transistors in the same arm, so in module design, the current rating can simply be set to a multiple of the number of transistors in the module in parallel. First, there was a problem that the module rating had to be lowered in anticipation of imbalance. In addition, in the inverter, when a short circuit between the phases occurs, there is a problem that current is concentrated on a specific transistor due to an imbalance of the collector current, and a malfunction is likely to occur.
[0033]
The present invention has been made to solve the above-described problems. The temperature distribution in the circuit board of the semiconductor device module can be made uniform, and the transistor collector current imbalance can be eliminated, thereby simplifying the module design. Another object of the present invention is to prevent the occurrence of transistor malfunctions due to current concentration.
[0034]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a circuit board having a conductor pattern; and a structure of a transistor and a diode disposed on a main surface of the conductor pattern and in an electrically antiparallel relationship. A plurality of composite transistors, a collector terminal disposed around the circuit board, and an emitter terminal disposed around the circuit board, wherein the plurality of composite transistors are provided on one main surface thereof. A first main electrode corresponding to the collector of the transistor and a cathode of the diode, and an emitter of the transistor and an anode of the diode provided on the other main surface opposite to the one main surface. A second main electrode that is arranged so as to face the main surface of the conductor pattern, and the conductor pattern The collector terminal, the second main electrode and the emitter terminal are electrically connected by wire wires, respectively, a wiring inductance between the first main electrode and the collector terminal, and the second main electrode The plurality of composite transistors are arranged so that the wiring inductances with the emitter terminals are the same.
[0035]
In a semiconductor device according to a second aspect of the present invention, the plurality of composite transistors are composite transistors of the same arm that operate on the basis of a common potential, and are electrically connected in parallel.
[0036]
According to a third aspect of the present invention, in the semiconductor device according to the present invention, the plurality of composite transistors includes a first arm composite transistor that operates on the basis of the first potential and a second potential that is lower than the first potential. A second-arm composite transistor that operates as an inverter circuit in series connection of the first-arm composite transistor and the second-arm composite transistor, and the first-arm composite transistor, With the second-arm composite transistor, the layout of the collector terminal and the emitter terminal is rotation Target position They are arranged in a relationship.
[0037]
According to a fourth aspect of the present invention, in the semiconductor device according to the fourth aspect of the present invention, each of the plurality of composite transistors includes a gate pad that is electrically insulated from the second main electrode at an edge portion of the second main electrode. The plurality of composite transistors are arranged so that the gate pads are arranged in a line.
[0038]
In the semiconductor device according to claim 5 according to the present invention, the plurality of composite transistors are A first-arm composite transistor that operates with a first potential as a reference; and a second-arm composite transistor that operates with a second potential lower than the first potential as a reference, the first-arm composite transistor A transistor and a composite transistor of the second arm; Each said gate pad line They are arranged in a symmetrical positional relationship.
[0039]
According to a sixth aspect of the present invention, the plurality of composite transistors further include a temperature detecting diode disposed on the second main electrode.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
<1. Device configuration>
FIG. 1 shows a circuit configuration of a semiconductor device module 100 including a plurality of composite transistors CT10, CT20, and CT30 electrically connected in parallel in the same arm as an embodiment of a semiconductor device according to the present invention.
[0041]
The composite transistors CT10 to CT30 are transistors in which a freewheel diode is built in a power transistor such as an IGBT, and the freewheel diode is connected in antiparallel to the power transistor.
[0042]
In FIG. 1, composite transistors CT10 to CT30 are electrically connected in parallel between the collector terminal C1 and the emitter terminal E1, and the gates of the composite transistors CT10 to CT30 are connected in common to the gate terminal G1. CT10 to CT30 are configured to operate in parallel.
[0043]
The emitters of the composite transistors CT10 to CT30 are connected to the emitter terminal E1 and also to the control emitter terminal CE1.
[0044]
The control emitter terminal CE1 is used when driving the composite transistors CT10 to CT30. For example, by applying a gate-emitter voltage (for example, about 15 V) between the control emitter terminal CE1 and the gate terminal G1, the composite transistors CT10 to CT30 are used. The transistor can be driven.
[0045]
FIG. 2 shows a planar layout in the package of the semiconductor device module 100. In FIG. 2, a conductor pattern P9 similar to the circuit board BS1 is disposed on the circuit board BS1 having a rectangular shape in plan view. A conductor pattern P91 having an L shape in plan view is disposed on the outer periphery of the conductor pattern P9. The conductor pattern P91 is arranged so that its long axis extends along the long side of the circuit board BS1.
[0046]
The composite transistors CT10 to CT30 are arranged in parallel on the conductor pattern P9. The composite transistors CT10 to CT30 have a rectangular shape in plan view, and a gate pad GP is provided on an edge portion of the upper main surface thereof.
[0047]
In the composite transistors CT10 to CT30, the gate pads GP are arranged in a row in parallel with the long axis of the conductor pattern P91, and the arrangement of the gate pads GP is such that the distance from the gate pad GP to the conductor pattern P91 is shortened. It arrange | positions so that it may be near the arrangement | positioning side of P91.
[0048]
And the collector terminal C1 is arrange | positioned on the outer side of the long side by which the long axis of the conductor pattern P91 of circuit board BS1 is arrange | positioned. The collector terminal C1 is arranged so as to correspond to the arrangement area of the conductor pattern P9.
[0049]
In addition, an emitter terminal E1 is disposed outside the other long side of the circuit board BS1. The emitter terminal E1 is arranged so as to correspond to the arrangement area of the conductor pattern P9.
[0050]
Further, a control emitter terminal CE1 and a gate terminal G1 are disposed outside the short side of the circuit board BS1 on the side where the short axis of the conductor pattern P91 is disposed.
[0051]
The collector terminal C1 is electrically connected to the conductor pattern P9 by a wire line WR such as aluminum. The collectors of the composite transistors CT10 to CT30 (including the cathode of the built-in freewheel diode) are respectively arranged on the lower surface side so as to face the conductor pattern P9, and the emitter (the anode of the built-in freewheel diode). Are also disposed on the upper surface side.
[0052]
The emitters of the composite transistors CT10 to CT30 are electrically connected to the emitter terminal E1 by the wire line WR, the gate pad GP is electrically connected to the conductor pattern P91 by the wire line WR, and the conductor pattern P91 is the wire line WR. Is electrically connected to the gate terminal G1. The emitter of the composite transistor CT10 is also electrically connected to the control emitter terminal CE1 via the wire line WR.
[0053]
The collector terminal C1 and the emitter terminal E1 extend above the circuit board BS1 so as to protrude from an insulating case (not shown) disposed so as to surround the circuit board BS1, and are connected to an external device. . The same applies to the other control emitter terminal CE1 and gate terminal G1.
[0054]
Here, the configuration of the composite transistor including the free wheel diode will be described with reference to FIGS. 3 and 4.
[0055]
FIG. 3 shows a cross-sectional configuration of a composite transistor CT incorporating a freewheel diode. As shown in FIG. 3, in the composite transistor CT, a p-type base region 8 is formed in the upper main surface of the n-type silicon substrate 1, and a plurality of composite transistors CT penetrate the p-type base region 8 in the depth direction. Trench-type gate electrodes 11 are formed in parallel. A p-type semiconductor region 12 containing a p-type impurity at a relatively high concentration is selectively formed in the surface of the p-type base region 8 between the gate electrodes 11. The p-type semiconductor region 12 is provided for the purpose of good electrical connection between the p-type base region 8 and the emitter electrode 19.
[0056]
An n-type emitter region 9 containing an n-type impurity at a relatively high concentration is formed so as to sandwich the p-type semiconductor region 12 from both sides. The n-type emitter region 9 is in contact with a gate insulating film (not shown) formed on the surface of the gate electrode 11. Here, the silicon substrate 1 becomes an n-type base layer of the IGBT.
[0057]
An emitter electrode 19 is formed on a part of the surface of the n-type emitter region 9.
[0058]
These regions where the p-type base region 8, the n-type emitter region 9, and the gate electrode 11 are formed are referred to as a cell region 2TC.
[0059]
In addition, a plurality of p-type semiconductor regions 28 having a floating potential are formed concentrically so as to surround the cell region 2TC, thereby forming an electric field relaxation ring region 2TG. The structures of the cell region 2TC and the electric field relaxation ring region 2TG are collectively referred to as the emitter side structure 2.
[0060]
An n-type buffer layer 3 is disposed on the entire lower main surface of the silicon substrate 1, and a p-type collector layer 4 is formed in a region where the p-type base region 8 is formed in the main surface of the n-type buffer layer 3. That is, the n-type cathode region 6 is selectively formed substantially corresponding to the cell region 2TC), and is selectively formed so as to surround the p-type collector layer 4 at a distance from the p-type collector layer 4. ing. A collector electrode 5 is formed in contact with the n-type buffer layer 3, the p-type collector layer 4, and the n-type cathode region 6.
[0061]
In the operation of the composite transistor CT, two current paths a and b are formed, that is, the current path a includes the emitter electrode 19, the p-type semiconductor region 12, the p-type base region 8, Silicon substrate ( n-type base layer ) 1 is a current path that flows through a free wheel diode composed of an n-type buffer layer 3, an n-type cathode region 6, and a collector electrode 5, and a current path b is a collector electrode 5, a p-type collector layer 4, and an n-type buffer layer 3. , An n-type base layer 1, a p-type base region 8, an n-type emitter region 9, and an emitter electrode 19.
[0062]
In the composite transistor CT having such a configuration, when a positive voltage (meaning positive compared to the emitter electrode) is applied to the collector electrode 5 and the voltage of the gate electrode 11 is off-potential, The voltage is held at the pn junction with the mold base layer 1, and the current is cut off by the depletion layer. On the other hand, when a positive voltage is applied to the collector electrode 5 and the voltage of the gate electrode 11 becomes an on-voltage, a current flows through the current path b and operates as an IGBT.
[0063]
When a negative voltage is applied to the collector electrode 5, no current flows along the current path b because of the pn junction formed by the p-type collector layer 4 and the n-type buffer layer 3. A current flows along the path a and performs diode operation.
[0064]
Here, FIG. 4 shows a planar configuration of the composite transistor CT as viewed from the emitter electrode side. As shown in FIG. 4, the composite transistor CT is formed on a rectangular substrate, and the rectangular cell region 2TC is formed into a rectangular electric field relaxation ring region. Area It has a surrounding shape. And electric field relaxation ring area Area An n-type semiconductor region 27 having a floating potential is formed so as to surround it.
[0065]
A plurality of gate lines GL are formed in parallel in the cell region 2TC, and ends of the gate lines GL are connected to a gate ring region GR that defines the outer edge of the cell region 2TC, and all the gate lines GL have a common potential. It has become. A gate pad GP for electrically connecting the gate line GL and the outside is partially provided.
[0066]
The gate line GL is covered with an emitter electrode 19 and is covered with an upper emitter electrode 190 that electrically connects the emitter electrodes 19. In FIG. 4, for convenience, the upper emitter electrode 190 is covered. A part of is omitted.
[0067]
Note that the cross-sectional configuration of the composite transistor CT shown in FIG. 3 shows a cross section taken along line AA in FIG. 4, and the gate electrode 11 shown in FIG. 3 is perpendicular to the longitudinal direction of the gate line GL. It is only a part of the plurality of gate electrodes 11 provided.
[0068]
The planar view shapes of the composite transistors CT10 to CT30 shown in FIG. 2 are slightly different from those in FIG. 4, but are basically the same, and diode operation and IGBT operation are alternately performed in one chip. Therefore, the heat generated by the power loss raises the chip temperature as a whole, and the temperature distribution is not biased.
[0069]
Therefore, as shown in FIG. 2, the temperature distribution in the circuit board BS1 can be prevented by simply disposing the composite transistors CT10 to CT30 almost at the center of the circuit board BS1.
[0070]
<2. Effect>
As described above, in the semiconductor device module 100, the use of the composite transistors CT10 to CT30 in which the IGBT includes a freewheel diode causes the power loss ratio to be different between the IGBT and the freewheel diode. In order to prevent uneven temperature distribution, it is not necessary to arrange the IGBTs alternately on the circuit board. As a result, each chip can be arranged so that the conductor pattern has an equal positional relationship with respect to each chip, and at least in the same arm, the wiring inductance of each chip can be made equal.
[0071]
For example, in FIG. 2, the lengths of the respective wire lines WR that electrically connect the emitter terminal E1 and the emitters of the composite transistors CT10 to CT30 are the same, and from the collector terminal C1 to the wire line WR and the conductor pattern P9. The current path lengths until the respective collectors of the composite transistors CT10 to CT30 are reached through the same.
[0072]
By equalizing the wiring inductance, there is no collector current imbalance between transistors in the same arm, so there is no need for consideration such as lowering the module rating in anticipation of imbalance. Can be simplified.
[0073]
Further, by using a composite transistor in the inverter, even when a short circuit between phases occurs, it is possible to prevent a current from being concentrated on a specific transistor and causing a problem.
[0074]
<3. Application example for inverter>
Hereinafter, an example in which an inverter is configured using a composite transistor will be described with reference to FIGS.
[0075]
FIG. 5 shows a circuit configuration of a semiconductor device module 200 having a half bridge circuit. In FIG. 5, composite transistors CT1 and CT3 are connected to a totem pole between a collector terminal C1 and an emitter terminal E2, thereby constituting a half-bridge inverter.
[0076]
The connection node of the composite transistors CT1 and CT3 is connected to the output terminal OT and also to the control emitter terminal CE1. The emitter of the composite transistor CT3 is connected to the emitter terminal E2 and also to the control emitter terminal CE2.
[0077]
Further, the composite transistors CT2 and CT4 are connected to the totem pole between the collector terminal C1 and the emitter terminal E2, thereby constituting a half-bridge inverter.
[0078]
The connection node of the composite transistors CT2 and CT4 is connected to the output terminal OT and also to the control emitter terminal CE1. The emitter of the composite transistor CT4 is connected to the emitter terminal E2 and also to the control emitter terminal CE2.
[0079]
The composite transistors CT1 and CT2 may be referred to as P-side arm transistors, and the composite transistors CT3 and CT4 may be referred to as N-side arm transistors.
[0080]
The output terminal OT is also an emitter terminal for the P-side arm composite transistor and a collector terminal for the N-side arm composite transistor.
[0081]
The gates of the composite transistors CT1 and CT2 are commonly connected to the gate terminal G1, and the composite transistors CT1 and CT2 are configured to operate in parallel. The gates of the composite transistors CT3 and CT4 are commonly connected to the gate terminal G2, and the composite transistors CT3 and CT4 are configured to operate in parallel.
[0082]
The composite transistors CT1 and CT2 are devices that switch between the collector potential and the potential of the output terminal OT as the reference potential, and the composite transistors CT3 and CT4 have the ground potential as the reference potential. It is a device that switches between potentials.
[0083]
FIG. 6 shows a planar layout in the package of the semiconductor device module 200. In FIG. 6, conductor patterns P1 and P2 having a rectangular shape in plan view are arranged in parallel on a rectangular circuit board BS2. Then, a conductor pattern P11 having a C-shaped plan view is disposed on the outer periphery of the conductor pattern P1 so as to surround approximately half of the outer periphery, and the outer periphery of the conductor pattern P2 is surrounded by approximately half of the outer periphery. In addition, a conductor pattern P21 having a C-shaped plan view is disposed. The conductor patterns P11 and P21 are arranged so as to have a rotationally symmetrical positional relationship with each other.
[0084]
Composite transistors CT1 and CT2 are arranged in parallel above the conductor pattern P1. The composite transistors CT1 and CT2 have a rectangular shape in plan view, and a gate pad GP is provided at the edge of one upper side of the upper main surface.
[0085]
In the composite transistors CT1 and CT2, the long sides on the side where the gate pad GP is not disposed are opposed to each other so that the respective gate pads GP are located close to the C-shaped end portions of the conductor pattern P11. It is arranged.
[0086]
Similarly, composite transistors CT3 and CT4 are arranged in parallel on the conductor pattern P2. The composite transistors CT3 and CT4 have a rectangular shape in plan view, and a gate pad GP is provided at the edge of one upper side of the upper main surface.
[0087]
In the composite transistors CT3 and CT4, the long sides on which the gate pad GP is not disposed are opposed to each other so that the respective gate pads GP are positioned close to the C-shaped end portions of the conductor pattern P21. It is arranged.
[0088]
A collector terminal C1 and an emitter terminal E2 are disposed outside one long side of the circuit board BS2. The collector terminal C1 is disposed so as to correspond to the region where the conductor pattern P1 is disposed, and the emitter terminal E2 is disposed so as to correspond to the region where the conductor pattern P2 is disposed.
[0089]
Circuit board BS 2 An output terminal OT is disposed outside the other long side. The output terminal OT is disposed along the long side so as to correspond to the region where the conductor patterns P1 and P2 are disposed.
[0090]
Further, on the outside of the short side of the circuit board BS2 on which the conductor pattern P1 is disposed, the control emitter terminal CE1 and the gate terminal G1 are disposed, and the circuit board BS2 on which the conductor pattern P2 is disposed. A control emitter terminal CE2 and a gate terminal G2 are disposed outside the short side.
[0091]
The collector terminal C1, the emitter terminal E2, and the output terminal OT extend above the circuit board BS2 so as to protrude from an insulating case (not shown) disposed so as to surround the circuit board BS2, and are connected to an external device. Connected. The same applies to the other terminals.
[0092]
The collector terminal C1 is electrically connected to the conductor pattern P1 by a wire line WR such as aluminum. The collectors of the composite transistors CT1 and CT2 (including the cathode of the built-in freewheel diode) are respectively arranged on the lower surface side so as to face the conductor pattern P1, and the emitter (the anode of the built-in freewheel diode). Are also disposed on the upper surface side.
[0093]
The emitters of the composite transistors CT1 and CT2 are electrically connected to the output terminal OT by the wire line WR, and the gates of the composite transistors CT1 and CT2 are electrically connected to the conductor pattern P11 via the wire line WR. It is configured to be electrically connected to the gate terminal G1 via the conductor pattern P11. The emitter of the composite transistor CT1 is also electrically connected to the control emitter terminal CE1 via the wire line WR.
[0094]
The output terminal OT is electrically connected to the conductor pattern P2 by a wire line WR such as aluminum. The collectors of the composite transistors CT3 and CT4 (including the cathode of the built-in freewheel diode) are arranged on the lower surface side so as to face the conductor pattern P2, and the emitter (the anode of the built-in freewheel diode). Are also disposed on the upper surface side.
[0095]
The emitters of the composite transistors CT3 and CT4 are electrically connected to the emitter terminal E2 by the wire line WR, and the gates of the composite transistors CT3 and CT4 are electrically connected to the conductor pattern P21 via the wire line WR. It is configured to be electrically connected to the gate terminal G2 via the conductor pattern P21. The emitter of the composite transistor CT4 is also electrically connected to the control emitter terminal CE2 via the wire line WR.
[0096]
Thus, even when an inverter is configured using a composite transistor, each chip can be arranged so that the conductor pattern has an equal positional relationship with respect to each chip, and at least in the same arm, The wiring inductance of each chip can be made uniform.
[0097]
<4. Further advantages when using composite transistors>
In the embodiment described above, the use of the composite transistor has shown the effect that the temperature distribution can be prevented from being biased on the circuit board. However, the use of the composite transistor further improves the configuration in the module. There is an advantage that it can be simplified.
[0098]
FIG. 7 shows a circuit configuration of a semiconductor device module 90 having a half bridge circuit. In FIG. 7, power transistors T11 and T12 such as IGBTs are connected to a totem pole between a collector terminal C1 and an emitter terminal E2, thereby forming a half-bridge inverter. In addition, free wheel diodes D11 and D12 are connected in reverse parallel to the transistors T11 and T12, respectively.
[0099]
The connection node of the transistors T11 and T12 is connected to the output terminal OT and is also connected to the control emitter terminal CE1. The emitter of the transistor T12 is connected to the emitter terminal E2 and also to the control emitter terminal CE2.
[0100]
The temperature detection diodes X1 and X3 are attached to the transistors T11 and T12, respectively. The cathode and anode of the temperature detection diode X1 are connected to the cathode terminal K1 and the anode terminal A1, respectively, and the cathode and anode of the temperature detection diode X3. Are respectively connected to the cathode terminal K3 and the anode terminal A3.
[0101]
Further, temperature detection diodes X2 and X4 are attached to the freewheel diodes D11 and D12, respectively. The cathode and anode of the temperature detection diode X2 are connected to the cathode terminal K2 and the anode terminal A2, respectively, and the cathode of the temperature detection diode X4. And the anode are connected to the cathode terminal K4 and the anode terminal A4, respectively.
[0102]
Temperature detection diodes X1 to X4 detect temperature rises associated with abnormal operation of IGBTs and freewheeling diodes, and feed back the information to the control system for IGBTs and freewheeling diodes to prevent serious problems from occurring Is to do.
[0103]
FIG. 8 shows a planar layout in the package of the semiconductor device module 90. In FIG. 8, conductor patterns P50 and P60 having a rectangular shape in plan view are arranged in parallel on a rectangular circuit board BS3. A conductor pattern P51 having an L shape in plan view is disposed on the outer periphery of the conductor pattern P50, and a conductor pattern P56 is disposed along the major axis direction of the conductor pattern P51. In addition, conductor patterns P52, P53, P54, and P55 are sequentially arranged on the inner side of the long axis of the conductor pattern P51.
[0104]
On the outer periphery of the conductor pattern P60, a conductor pattern P61 having an L shape in plan view is disposed, and a conductor pattern P66 is disposed along the major axis direction of the conductor pattern P61. In addition, conductor patterns P62, P63, P64, and P65 are sequentially arranged on the inner side of the long axis of the conductor pattern P61.
[0105]
The conductor patterns P51 to P56 and P61 to P66 are arranged so as to have a rotationally symmetrical positional relationship.
[0106]
A transistor T11 and a freewheel diode D11 are disposed above the conductor pattern P50, and temperature detection diodes X1 and X2 are disposed on the upper main surfaces of the transistor T11 and the freewheel diode D11, respectively.
[0107]
Similarly, a transistor T12 and a free wheel diode D12 are disposed above the conductor pattern P60, and temperature detection diodes X3 and X4 are disposed on the upper main surface of the transistor T12 and the free wheel diode D12, respectively. Yes.
[0108]
The transistors T11 and T12 are arranged so as to have an alternate positional relationship, and the free wheel diodes D11 and D12 are also arranged so as to have an alternate positional relationship.
[0109]
A collector terminal C1 and an emitter terminal E2 are disposed outside one side of the circuit board BS3. The collector terminal C1 is disposed so as to correspond to the region where the conductor pattern P50 is disposed, and the emitter terminal E2 is disposed so as to correspond to the region where the conductor pattern P60 is disposed.
[0110]
Further, an output terminal OT is disposed outside one side of the circuit board BS3 opposite to the side where the collector terminal C1 and the emitter terminal E2 are disposed. The output terminal OT is disposed along the side so as to correspond to the region where the conductor patterns P50 and P60 are disposed.
[0111]
Furthermore, on the outside of one side along the long side of the conductor pattern P50 of the circuit board BS3, in order from the collector terminal C1 side, the gate terminal G1, the cathode terminal K1, the anode terminal A1, the control emitter terminal CE1, the cathode terminal K2, and Anode terminals A2 are arranged.
[0112]
Further, outside the one side along the long side of the conductor pattern P60 of the circuit board BS3, in order from the emitter terminal E2 side, the anode terminal A4, the cathode terminal K4, the control emitter terminal CE2, the anode terminal A3, the cathode terminal K3, and Gate terminals G2 are arranged.
[0113]
The collector terminal C1 is electrically connected to the conductor pattern P50 by a wire line WR such as aluminum. The emitter of the transistor T11 and the anode of the freewheel diode D11 are electrically connected to the output terminal OT by the wire line WR, and the gate of the transistor T11 is electrically connected to the conductor pattern P51 via the wire line WR. In addition, it is configured to be electrically connected to the gate terminal G1 via the conductor pattern P51. The emitter of the transistor T11 is also electrically connected to the control emitter terminal CE1 via the conductor pattern P56.
[0114]
Further, the cathode and anode of the temperature detection diode X1 on the transistor T11 are electrically connected to the cathode terminal K1 and the anode terminal A1 via the conductor patterns P52 and P53, respectively, and the temperature detection diode on the freewheel diode D11. The cathode and anode of X2 are electrically connected to cathode terminal K2 and anode terminal A2 via conductor patterns P54 and P55, respectively.
[0115]
The output terminal OT is electrically connected to the conductor pattern P60 by a wire line WR such as aluminum. The emitter of the transistor T12 and the anode of the freewheel diode D12 are electrically connected to the emitter terminal E2 by the wire line WR, and the gate of the transistor T12 is electrically connected to the conductor pattern P61 via the wire line WR. In addition, it is configured to be electrically connected to the gate terminal G2 via the conductor pattern P61. The emitter of the transistor T12 is also electrically connected to the control emitter terminal CE2 via the conductor pattern P66.
[0116]
Further, the cathode and anode of the temperature detection diode X3 on the transistor T12 are electrically connected to the cathode terminal K3 and the anode terminal A3 via the conductor patterns P62 and P63, respectively, and the temperature detection diode on the freewheel diode D12. The cathode and anode of X4 are electrically connected to cathode terminal K4 and anode terminal A4 via conductor patterns P64 and P65, respectively.
[0117]
As described above, in the semiconductor device module 90, the transistor T11 and the free wheel diode D11 are separately disposed on the conductor pattern P50, and the temperature detection diodes X1 and X2 are disposed on the upper main surface of each. Further, the transistor T12 and the free wheel diode D12 are separately provided on the conductor pattern P60, and the temperature detection diodes X3 and X4 are provided on the upper main surface of each.
[0118]
Therefore, wire wires, conductor patterns, and terminals are required for each of the temperature detection diodes X1 to X4, and the configuration in the module is complicated.
[0119]
Further, since detection means are required corresponding to the number of temperature detection diodes, if the number of temperature detection diodes is large, the number of detection means increases, and a space for providing the detection means needs to be widened.
[0120]
FIG. 9 shows an example of detection means attached to the temperature detection diodes X1 and X2. As shown in FIG. 9, the temperature detection diodes X1 and X2 are configured such that the anodes and the cathodes are connected to the amplifiers F3 and F4, respectively, and the outputs of the amplifiers F3 and F4 are supplied to the detection circuits F5 and F6, respectively. . Note that the power supply voltage V is applied to the inputs of the amplifiers F3 and F4. _D Are connected to constant current power supplies F1 and F2 for supplying a constant current.
[0121]
The detection circuits F5 and F6 have a function of removing noise from the outputs of the amplifiers F3 and F4 and outputting a predetermined signal when a predetermined threshold is reached. The outputs of the detection circuits F5 and F6 are given to an OR gate F7, and when at least one of the temperature detection diodes X1 and X2 detects a temperature abnormality, an alarm or the like is output.
[0122]
Thus, various structures are required for temperature detection, and even if they are provided outside the module, a corresponding space is required.
[0123]
However, when a composite transistor is used, the number of temperature detection diodes can be reduced, so that the configuration in the module can be further simplified.
[0124]
FIG. 10 shows a planar layout in the package of the semiconductor device module 300 in which the temperature detection diode is mounted on the composite transistor.
[0125]
In FIG. 10, conductor patterns P3 and P4 having a rectangular shape in plan view are arranged in parallel on a rectangular circuit board BS4. Then, conductor patterns P31, P32, P33 and P34 are arranged in this order along one long side of the conductor pattern P3 on the outer periphery of the conductor pattern P3.
[0126]
In addition, conductor patterns P41, P42, P43, and P44 are sequentially arranged along one long side of the conductor pattern P4 on the outer periphery of the conductor pattern P4.
[0127]
A composite transistor CT5 is disposed above the conductor pattern P3, and a temperature detection diode X10 is disposed on the upper main surface of the composite transistor CT5.
[0128]
The composite transistor CT5 has a rectangular shape in plan view, and a gate pad GP is provided at an end edge on one long side of the upper main surface thereof.
[0129]
Note that the composite transistor CT5 is disposed such that the gate pad GP is positioned close to the conductor pattern P33.
[0130]
A composite transistor CT6 is disposed on the conductor pattern P4, and a temperature detection diode X20 is disposed on the upper main surface of the composite transistor CT6. The compound transistor CT6 has a rectangular shape in plan view, and a gate pad GP is provided at an edge of one upper side of the upper main surface.
[0131]
The composite transistor CT6 is disposed such that the gate pad GP is positioned close to the conductor pattern P43.
[0132]
A collector terminal C1 and an emitter terminal E2 are disposed outside one side parallel to the short sides of the conductor patterns P3 and P4 of the circuit board BS4.
The collector terminal C1 is disposed so as to correspond to the region where the conductor pattern P3 is disposed, and the emitter terminal E2 is disposed so as to correspond to the region where the conductor pattern P4 is disposed.
[0133]
Also, the circuit board BS4 Conductor pattern An output terminal OT is disposed outside the other side parallel to the short sides of P3 and P4. The output terminal OT is disposed along one side so as to correspond to the region where the conductor patterns P3 and P4 are disposed.
[0134]
Further, an output terminal OT is disposed outside one side of the circuit board BS4 opposite to the side where the collector terminal C1 and the emitter terminal E2 are disposed. The output terminal OT is arranged along the side so as to correspond to the arrangement region of the conductor patterns P3 and P4.
[0135]
The composite transistor CT5 may be referred to as a P-side arm transistor, and the composite transistor CT6 may be referred to as an N-side arm transistor.
[0136]
The output terminal OT is also an emitter terminal for the P-side arm composite transistor and a collector terminal for the N-side arm composite transistor.
[0137]
In addition, a cathode terminal K1, an anode terminal A1, a gate terminal G1, and a control emitter terminal CE1 are arranged in order from the collector terminal C1 side on the outer side of the long side of the conductor pattern P3 of the circuit board BS4. .
[0138]
Also, a cathode terminal K2, an anode terminal A2, a gate terminal G2, and a control emitter terminal CE2 are arranged in this order from the emitter terminal E2 side on the outer side of the long side of the conductor pattern P4 of the circuit board BS4. .
[0139]
The collector terminal C1 is electrically connected to the conductor pattern P3 by a wire line WR such as aluminum. The emitter of the composite transistor CT5 is electrically connected to the output terminal OT by the wire line WR, and the gate of the composite transistor CT5 is electrically connected to the conductor pattern P33 via the wire line WR. It is configured to be electrically connected to the gate terminal G1 via the via. The emitter of the composite transistor CT5 is also electrically connected to the control emitter terminal CE1 via the conductor pattern P34.
[0140]
Further, the cathode and the anode of the temperature detection diode X10 on the composite transistor CT5 are electrically connected to the cathode terminal K1 and the anode terminal A1 via the conductor patterns P31 and P32, respectively.
[0141]
The output terminal OT is electrically connected to the conductor pattern P4 by a wire line WR such as aluminum. The emitter of the composite transistor CT6 is electrically connected to the emitter terminal E2 by the wire line WR, and the gate of the composite transistor CT6 is electrically connected to the conductor pattern P43 via the wire line WR. It is configured to be electrically connected to the gate terminal G2 via the via. The emitter of the composite transistor CT6 is also electrically connected to the control emitter terminal CE2 via the conductor pattern P44.
[0142]
Further, the cathode and anode of the temperature detection diode X20 on the composite transistor CT6 are electrically connected to the cathode terminal K3 and the anode terminal A3 via conductor patterns P41 and P42, respectively.
[0143]
As described above, by using the composite transistors CT3 and CT4, a temperature detection diode for detecting the temperature of the freewheel diode becomes unnecessary, and therefore, the number of wire lines WR, the number of terminals, and the number of conductor patterns can be reduced. The configuration in the module can be further simplified.
[0144]
Here, the arrangement state of the temperature detection diode will be described with reference to FIG. 11 by taking X10 arranged on the composite transistor CT5 as an example.
[0145]
FIG. 11 is a side view of the composite transistor CT5 shown in FIG. 10, and is placed on the conductor pattern P3 so that the collector electrode CD (first main electrode) faces, and the emitter electrode ED (second electrode). The temperature detection diode X10 is disposed on the main electrode) via an insulator ZL. The wire wire connected to the temperature detection diode X10 may be a gold wire wire that can be formed thinner than the aluminum wire wire WR.
[0146]
The portion where the gate pad GP is provided is shown by omitting a part of the emitter electrode ED, and schematically showing a state in which the gate pad GP extends through the emitter electrode ED into the chip. ing. Needless to say, the gate pad GP is electrically insulated from the emitter electrode ED.
[0147]
<5. Other examples of compound transistors>
In the composite transistor CT described with reference to FIGS. 3 and 4, the free wheel diode structure and the IGBT structure are different from each other, and the entire chip alternately performs the IGBT operation and the diode operation. However, as shown in FIG. 12, for example, the IGBT region IG and the diode region FW may be alternately arranged in a matrix like a chess board. Thereby, it is possible to prevent an uneven temperature distribution on the circuit board.
[0148]
【The invention's effect】
According to the semiconductor device of the first aspect of the present invention, the transistor and the diode are separately provided by using a plurality of composite transistors having a structure of the transistor and the diode that are electrically in antiparallel relation. As in the case, it is possible to prevent the temperature distribution from being biased due to the difference in the power loss ratio between the transistor and the diode. Therefore, it is not necessary to arrange a plurality of transistors alternately on the circuit board, and the wiring inductance between the first main electrode and the collector terminal and between the second main electrode and the emitter terminal are eliminated. A plurality of composite transistors can be arranged so that the wiring inductances of the two are the same. As a result, main current unbalance does not occur, and considerations such as lowering the rating in anticipation of unbalance are not required, and the design of the semiconductor layer can be simplified.
[0149]
According to the semiconductor device of the second aspect of the present invention, the plurality of composite transistors are composite transistors of the same arm that operate with a common potential as a reference, and are electrically connected in parallel. It is possible to prevent the main current from being unbalanced among the elements.
[0150]
According to the semiconductor device of the third aspect of the present invention, the layout of the collector terminal and the emitter terminal of each of the first arm composite transistor and the second arm composite transistor is rotation Symmetrical position Since the first arm composite transistor and the second arm composite transistor are arranged in such a relationship, it is possible to prevent the wiring inductance from becoming non-uniform, and the first arm composite transistor and the second arm composite. In the transistor, the main current is not unbalanced, and even when a short circuit between the phases occurs in the inverter circuit, it is possible to prevent the current from being concentrated on a specific transistor and causing a malfunction.
[0151]
According to the semiconductor device of the fourth aspect of the present invention, since the plurality of composite transistors are arranged so that the respective gate pads are arranged in a line, for example, the gate pads are electrically connected to the gate pads. It is easy to make the distance to the conductor pattern uniform, and the wiring inductance can be easily made uniform.
[0152]
According to the semiconductor device of the fifth aspect of the present invention, In the first arm composite transistor and the second arm composite transistor, Each gate pad line Since a plurality of composite transistors are arranged so as to have a symmetrical positional relationship, for example, the arrangement of the conductor pattern electrically connected to the gate pad can be easily determined, and the wiring inductance can be easily uniformized. it can.
[0153]
According to the semiconductor device of the sixth aspect of the present invention, since the diode for detecting the temperature is further provided on the second main electrode of the plurality of composite transistors, the temperature of the composite transistor can be detected. Compared to the case where transistors and diodes are provided separately, the number of diodes for temperature detection can be reduced, and the number of wires, terminals, and conductor patterns can be reduced to further improve the configuration of the semiconductor device. It can be simplified.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a circuit configuration of a semiconductor device module according to an embodiment of the present invention.
FIG. 2 is a diagram showing a planar layout in the package of the semiconductor device module according to the embodiment of the present invention;
FIG. 3 is a diagram showing a cross-sectional configuration of a composite transistor incorporating a freewheel diode.
FIG. 4 is a diagram showing a planar configuration of a composite transistor incorporating a freewheel diode.
FIG. 5 is a diagram illustrating a circuit configuration of the semiconductor device module according to the embodiment of the present invention.
FIG. 6 is a diagram showing a planar layout in the package of the semiconductor device module according to the embodiment of the present invention;
FIG. 7 is a diagram showing a circuit configuration of a semiconductor device module having a half-bridge circuit.
FIG. 8 is a diagram showing a planar layout in a package of a semiconductor device module having a half-bridge circuit.
FIG. 9 is a block diagram illustrating a configuration of a temperature detection unit.
FIG. 10 is a diagram showing a planar layout in a package of a semiconductor device module in which a temperature detection diode is mounted on a composite transistor.
FIG. 11 is a diagram illustrating a state in which a temperature detection diode is mounted on a composite transistor.
FIG. 12 is a diagram showing a modification of the composite transistor.
FIG. 13 is a diagram illustrating a circuit configuration of a conventional semiconductor device module.
FIG. 14 is a diagram showing a planar layout in a package of a conventional semiconductor device module.
FIG. 15 is a diagram illustrating an example of a simulation result of power loss between an IGBT and a free wheel diode.
FIG. 16 is a diagram schematically showing the wiring inductance of each chip.
FIG. 17 is a diagram illustrating the characteristics of collector current that flows during switching of two transistors having non-uniform wiring inductance.
[Explanation of symbols]
CT1-CT6, CT10-CT30 Composite transistor, BS1, BS2, BS4 Circuit board, P3, P4, P9, P11, P12 Conductor pattern, X10, X20 Temperature detection diode.

Claims (6)

A circuit board having a conductor pattern;
A plurality of composite transistors disposed on the main surface of the conductor pattern and having a structure of transistors and diodes in an electrically antiparallel relationship;
A collector terminal disposed around the circuit board;
An emitter terminal disposed around the circuit board,
The plurality of composite transistors are:
A first main electrode corresponding to a collector of the transistor and a cathode of the diode provided on one main surface thereof;
A second main electrode corresponding to an emitter of the transistor and an anode of the diode provided on the other main surface opposite to the one main surface, wherein the first main electrode is the conductor pattern. Arranged to face the main surface of
The conductor pattern and the collector terminal, and the second main electrode and the emitter terminal are respectively electrically connected by wire lines,
The plurality of composite transistors are arranged such that the wiring inductance between the first main electrode and the collector terminal and the wiring inductance between the second main electrode and the emitter terminal are the same. A semiconductor device is provided.   The semiconductor device according to claim 1, wherein the plurality of composite transistors are composite transistors of the same arm that operate with a common potential as a reference, and are electrically connected in parallel. The plurality of composite transistors are:
A first arm composite transistor operating with a first potential as a reference;
A second-arm composite transistor operating with a second potential lower than the first potential as a reference,
An inverter circuit is configured by series connection of the composite transistor of the first arm and the composite transistor of the second arm,
The composite transistor of the first arm and the composite transistor of the second arm are arranged so that layouts of the collector terminals and the emitter terminals are in a positional relationship to be rotated . Semiconductor device. Each of the plurality of composite transistors is
A gate pad electrically insulated from the second main electrode at an edge of the second main electrode;
The semiconductor device according to claim 1, wherein the plurality of composite transistors are arranged so that the gate pads are arranged in a line. The plurality of composite transistors are:
A first arm composite transistor operating with a first potential as a reference;
A second arm composite transistor that operates with a second potential lower than the first potential as a reference;
5. The semiconductor device according to claim 4, wherein the gate pads of the first arm composite transistor and the second arm composite transistor are arranged so as to have a line- symmetrical positional relationship. 6. The plurality of composite transistors are:
The semiconductor device according to claim 1, further comprising a diode for temperature detection disposed on the second main electrode.

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