JP3914328B2 - Trench gate semiconductor device with current detection cell and power conversion device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device applied to an inverter or the like of various electric products such as electric locomotives and home appliances, and more particularly to improvement of a current detection function of the semiconductor device.
[0002]
[Prior art]
Along with energy saving of inverters and the like, the loss of insulated gate bipolar transistors (hereinafter referred to as IGBTs) which are switching elements of inverters is being reduced. Particularly in recent years, so-called trench gate IGBTs in which a gate electrode is embedded in a silicon substrate have been actively developed.
[0003]
The trench gate IGBT can increase the integration density of the unit cells as compared with the conventional planar gate IGBT. For this reason, a voltage drop generated in the element when current is applied, that is, a so-called on-voltage is smaller than that of the planar gate IGBT, and loss can be reduced. However, since the cell density is high, the saturation current increases, and an excessive current flows when an accident such as a load short-circuit occurs, resulting in a problem that the cell becomes more fragile than the planar gate IGBT.
[0004]
In order to solve this problem, an overcurrent protection circuit that detects an overcurrent and protects the IGBT when an accident occurs may be provided, but this circuit requires a highly accurate current detection mechanism. In particular, in the case of a trench gate IGBT, the current increase rate at turn-on is large, and a large current flows and breaks instantaneously. Therefore, an accurate and high-speed overcurrent detection mechanism is required.
[0005]
FIG. 3 shows an equivalent circuit of an IGBT having an overcurrent detection mechanism. The IGBT with an overcurrent detection mechanism is separated from the main IGBT 300 and the sense IGBT 301 for current detection, the collector electrode 121 common to the main IGBT and the sense IGBT, the gate electrode 106, and the emitter electrode 122 of the main IGBT 300. It is composed of a sense IGBT emitter electrode 120 (hereinafter referred to as a sense electrode).
[0006]
Generally, the number of cells of the sense IGBT is designed to be about 1/1000 of the number of cells of the main IGBT, and a current about 1/1000 of the current flowing through the main IGBT can be taken out. By monitoring this minute sense current, it is possible to monitor a main current having a large energization amount. However, in practice, the ratio of the current of the main IGBT (main current) to the current of the sense IGBT (sense current) is not necessarily the same as the ratio of the number of cells, and varies depending on the collector voltage, temperature, and the like. In the planar gate IGBT, many structures for improving these have been proposed, for example, “Current Sensing IGBT for Future Intelligent Power Module” (M, Kudoh et al, Proceedings ISPSD, pp. 303-306, 1996).
[0007]
FIG. 4 shows an example of the layout of the sense IGBT cell of the planar gate IGBT. In this example, the detection accuracy is improved by arranging the sense IGBT cells 401 as shown in FIG. 4 or providing the blocking layer 402 between the main IGBT cell 400 and the sense IGBT cell 401.
[0008]
[Problems to be solved by the invention]
However, according to the study of the present inventor, there is a problem that a desired detection sensitivity cannot be obtained even if the sense IGBT cell array in the conventional planar gate IGBT is applied to the trench gate IGBT.
[0009]
Further, in the element formation process, the shape of the trench gate of the main IGBT and the shape of the trench gate of the sense IGBT are different, which causes a problem that the detection accuracy is lowered. Furthermore, there is a problem that the detection sensitivity of the sense IGBT is lowered due to the interaction between the main IGBT cell and the sense IGBT cell.
[0010]
The present invention has been made in consideration of the above-described problems, and provides a trench gate semiconductor device capable of improving current detection accuracy.
[0011]
[Means for Solving the Problems]
In the semiconductor device according to the present invention, a main cell having a trench gate and energizing a main current and a current detecting cell having a trench gate and energizing a detection current are formed on the same semiconductor substrate. Whether the crystal plane orientation of the trench sidewall in which the channel of the trench gate of the main cell is formed and the crystal plane orientation of the trench sidewall in which the channel of the trench gate of the current detection cell is formed are the same or substantially the same. Or equivalent or substantially equivalent.
[0012]
According to the above structure, the crystal plane orientation of the trench sidewall where the channel of the trench gate of the main cell is formed and the crystal plane orientation of the trench sidewall where the channel of the trench gate of the current detection cell is formed are the same or substantially the same. In other words, the ratio between the current flowing through the main cell and the current flowing through the current detection cell can be accurately set.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
1 and 2 are a plan view and a sectional view of a first embodiment according to the present invention, respectively. FIG. 2 shows an A-B cross section in FIG. In the following description, “crystal plane orientation” is simply referred to as “plane orientation”.
[0014]
1 and 2, 100 is a collector layer, 101 is a buffer layer adjacent to the collector layer 100, 102 is a drift layer adjacent to the buffer layer and having a lower impurity concentration than the buffer layer, and 103 is in the drift layer of the sense IGBT region. The formed sense base layer, 104 is a sense contact layer formed in the sense base layer, 105 is a sense emitter layer formed in the sense base layer, and 106 is formed to reach the drift layer in the silicon substrate. The trench gate electrode, 107 is a gate insulating film for insulating and isolating the silicon substrate and the gate electrode, 108 is an interlayer insulating film for insulating and isolating the electrode and the silicon substrate, and 109 is a sense base layer at the end of the sense IGBT region Sense WELL layer 110 formed in contact with the gate electrode is formed in the drift layer of the main IGBT region. Main base layer 111 is a main contact layer formed in the main base layer, 112 is a main emitter layer formed in the main base layer, and 113 is formed in contact with the main IGBT base layer at the end of the main IGBT region. Main WELL layer, 120 is a sense electrode formed in contact with the sense contact layer and the sense emitter layer, 121 is a collector electrode formed in contact with the collector layer, and 122 is formed in contact with the main contact layer and the main emitter layer. The emitter electrode 130 is a channel formation region formed along the side wall of the trench gate in the main base layer and the sense base layer. Of the two rectangles indicated by dotted lines in FIG. 1, the inner rectangle indicates the boundary of the sense base layer 103, and the inner region is the sense base layer 103. Further, an outer rectangle indicated by a dotted line in FIG. 1 indicates a boundary of the main base layer 110, and the main base layer 110 is formed in the outer region. For convenience of drawing, the channel formation region is drawn only in the sense IGBT cell and a part of the main IGBT cell in FIG. 1, but in reality, it is formed in all the cells of the main IGBT cell.
[0015]
The feature of this embodiment is that the trench gates of the main IGBT cell and the sense IGBT cell are formed in parallel, and the surface orientation of the surface of the semiconductor layer in the trench sidewall where the channel of the trench gate of the main IGBT is formed (hereinafter simply referred to as “trench sidewall”). The surface orientation of the trench side wall in which the channel of the trench gate of the sense IGBT is formed is the same.
[0016]
An important factor that determines the characteristics of the IGBT is the mobility of electrons in the channel region. The mobility greatly depends on the crystal plane orientation of the region where the channel is formed. For example, the mobility on the (111) plane is about half that of the (100) plane, and the mobility varies greatly depending on the crystal plane orientation. For this reason, when the plane orientation of the gate sidewall of the region where the channel of the main IGBT cell is formed differs from the plane orientation of the gate sidewall of the region where the channel of the sense IGBT cell is formed, the main IGBT and the sense The current flow of the IGBT is different and deviates from a desired current ratio.
[0017]
In addition, when the surface orientation of the gate sidewall of the region where the channel of the main IGBT cell is formed and the surface orientation of the gate sidewall of the region where the channel of the sense IGBT cell is formed are different, Are different, and the detection accuracy is reduced.
[0018]
Therefore, if the trench gates of the main IGBT cell and the sense IGBT cell are formed in parallel as shown in the present embodiment, the surface orientation of the trench gate side wall in which the channel region is formed can be made the same. And the sense IGBT current ratio can be set to a desired value. In addition, the plane orientation and sense of the trench sidewall of the main IGBT
The same effect is obtained when the angle formed by the surface orientation of the trench sidewall of the IGBT is substantially parallel within 5 °, that is, when both surface orientations are substantially the same.
[0019]
In forming this structure, it is preferable to simultaneously form the trench gate of the main IGBT cell and the trench gate of the sense IGBT. This is because if formed in different process steps, the trench sidewall state may be different between the main IGBT cell and the sense IGBT cell due to differences in process conditions such as the etching rate.
[0020]
Another feature of the present embodiment is that the trench gate of the main IGBT and the trench of the sense IGBT gate are separated. As shown in FIG. 1, this configuration is obtained by providing a region where no trench is formed between the main IGBT region and the sense IGBT region, and discontinuity between the trench of the gate of the main IGBT and the trench of the gate of the sense IGBT. It is done.
[0021]
In the on state of the IGBT, a storage layer is formed on the surface of the trench gate. This accumulation layer often has a lower resistance than the drift layer. Therefore, a leakage current flows between the main IGBT and the sense IGBT through this accumulation layer, resulting in a decrease in detection sensitivity. As shown in the present embodiment, if a region where no trench is formed is provided and the trench of the gate of the main IGBT and the trench of the gate of the sense IGBT are separated, the formation of the accumulation layer can be prevented and the detection sensitivity is reduced. Can be suppressed.
[0022]
Furthermore, since the trench gate of the main IGBT and the trench gate of the sense IGBT are separated from each other in this embodiment, there is an effect that the main IGBT and the sense IGBT can be individually controlled. For example, control such as delaying the operation by connecting a resistor only to the gate electrode of the sense IGBT becomes possible. In addition, there is an effect that the degree of freedom of layout of the sense IGBT cell can be increased.
[0023]
Another feature of this embodiment is that the sense IGBT cell is double-wrapped by the sense well layer 109 and the main well layer 113 which are deeper than the trench gate. Further, the trench gate of the main IGBT and the trench gate of the sense IGBT terminate in the main well layer and the sense well layer, respectively. With such a configuration, it is possible to prevent the breakdown voltage degradation at the divided trench gate termination and improve the reliability of the element. In addition, since the well layers are doubled through the drift layer therebetween, mutual interference between the sense IGBT and the main IGBT can be prevented, and the accuracy of current detection can be improved.
[0024]
Further, this embodiment has the following features. In other words, the trench formed across both the double well layers formed surrounding the sense IGBT is eliminated. This will be described in detail with reference to FIG. As shown by the alternate long and short dash line as a trench gate in the case where the sense IGBT region is penetrated in FIG. 1, the trench gate of the main IGBT penetrates the empty region where the gate trench of the sense IGBT in the sense IGBT region is not formed. In the case where the IGBT is on, a leakage current flows between the main IGBT and the sense IGBT due to the low-resistance accumulation layer formed on the surface of the trench gate in the on state of the IGBT, and the detection sensitivity is lowered. Therefore, the number of trenches in the gate of the main IGBT that crosses the sense IGBT region is preferably as small as possible, and it is preferable that the trench does not cross at all as shown in FIG. By adopting such a configuration, it is possible to prevent a decrease in sense sensitivity due to mutual interference between the main IGBT and the sense IGBT.
[0025]
The present embodiment does not require a special process for manufacturing, and can be formed by the same manufacturing process as that of the conventional trench gate IGBT.
[0026]
As described above, according to the present embodiment, a trench gate IGBT with a current detection cell can be realized at low cost and with high accuracy.
[0027]
The configuration in which the trench gate terminates in the well layer as described above is not limited to the present embodiment, but can be applied to other trench gate IGBT with current detection cell and trench gate MOSFET.
[0028]
(Example 2)
FIG. 5 shows a plan structural view of a second embodiment according to the present invention. In FIG. 5, the same components as those in FIGS. 1 and 4 are denoted by the same reference numerals.
[0029]
The feature of this embodiment is that the trench gates of the sense IGBT and the trench gate of the main IGBT are arranged so as to be orthogonal to each other. Considering a wafer having a crystal plane orientation of (100) as an example, if the plane orientation of the trench sidewall in which the channel of the trench gate of the main IGBT is formed is the (110) plane, the trench is oriented in a direction perpendicular to this. When the gate is formed, a crystal plane having a plane orientation crystallographically equivalent to the (110) plane appears on the side wall of the trench gate. By arranging the sense IGBTs as in this embodiment, the plane orientation of the trench gate side wall where the channel of the main IGBT cell is formed and the plane direction of the trench gate side wall where the channel of the sense IGBT cell is formed can be equivalent. Thereby, the same effect as Example 1 can be acquired.
[0030]
If the surface orientation of the trench sidewall of the sense IGBT is shifted within 5 ° in angle with respect to the surface orientation equivalent to the surface orientation of the trench sidewall of the main IGBT, that is, if the both surface orientation is substantially equivalent. Have the same effect.
[0031]
Further, even if a sense IGBT is configured by combining 90 ° orthogonal cells as shown in FIG. 8, all the plane orientations of the trench gate sidewalls where these channels are formed can be (110) planes. An effect can be obtained.
[0032]
As described above, the wafer having the crystal plane orientation of (100) is taken as an example. However, the same effect can be obtained by using this embodiment even if other crystal plane orientation wafers are used.
[0033]
(Example 3)
FIG. 9 and FIG. 10 show a plan structural view and a sectional structural view of a third embodiment according to the present invention, respectively. FIG. 10 shows an A-B cross section in FIG. 9 and 10, the same reference numerals are given to the same components as those in FIGS. 1, 2, 5, and 8. 9 and 10 are different from FIGS. 1, 2, 5, and 8 in a thick oxide film 1000 formed on the sense well layer 109 and a sense pad 900 on the thick oxide film 1000.
[0034]
A feature of this embodiment is that a sense pad 900 for bonding wire connection is provided in a region above the sense well layer 109. A wire connected to a circuit outside the chip by bonding is connected to the sense pad 900, but a large impact is applied to the pad during bonding, and the oxide film under the pad may be destroyed, and the emitter electrode and the silicon substrate may be short-circuited. There is. If the well layer of the main IGBT is formed on the silicon substrate under the pad, the sense electrode and the emitter electrode of the main IGBT are electrically connected through the well layer, and an accurate sense potential can be obtained. Disappear. Further, when nothing is formed on the silicon substrate under the pad and the drift layer is exposed, the sense electrode and the drift layer are electrically connected to each other, which causes a defect that the main breakdown voltage is reduced. . According to this embodiment, even if the oxide film under the sense pad is destroyed due to an impact during wire bonding or the like and the sense electrode is short-circuited to the silicon substrate, the sense well layer has the same potential as the sense electrode. Problems such as a decrease in sense sensitivity and a decrease in main breakdown voltage can be solved.
[0035]
The sense pad 900 is formed on the sense well layer so that the trench gate does not cross under the pad. Specifically, as shown in FIG. 9, it is preferably provided in a region without a sense IGBT cell in the sense IGBT region. This is because if there is a trench gate under the sense pad 900, a defect may occur in the trench due to an impact during bonding, which may cause a breakdown voltage failure.
[0036]
Example 4
FIG. 11 is a sectional structural view of a fourth embodiment according to the present invention. In FIG. 11, the same reference numerals are given to components common to those in FIGS. 1, 2, 5, 8, and 10.
[0037]
11 differs from FIG. 1, FIG. 2, FIG. 5, FIG. 8 and FIG. 10 in that a dummy trench gate 1100 formed between the main IGBT region and the sense IGBT region, a dummy trench gate and a drift layer are provided. A dummy trench gate insulating film 1101 to be insulated and isolated, and a dummy base layer 1102 formed adjacent to the dummy trench gate. In this embodiment, the main well layer and the sense well layer are not formed.
[0038]
The feature of this embodiment is that a dummy cell that does not perform the IGBT operation is arranged between the main IGBT cell and the sense IGBT cell.
[0039]
If the main IGBT cell and the sense IGBT cell are formed adjacent to each other in order to minimize the increase in area due to the formation of the sense IGBT, there is a problem that the current detection sensitivity of the sense IGBT is lowered. This is because the potential of the base layer 110 of the main IGBT affects the potential of the base layer 103 of the sense IGBT.
[0040]
According to the present embodiment, this problem can be solved by providing a dummy trench cell between the main IGBT region and the sense IGBT region. This dummy cell includes a dummy trench gate 1100 and a dummy base layer 1102 sandwiched therebetween. The dummy base layer 1102 is formed separately from the base layer 110 of the main IGBT and the base layer 103 of the sense IGBT, and is electrically insulated. Accordingly, the potential of the dummy base layer is in a floating state, and the potential varies under the influence of the surrounding potential. Since the dummy base layer 1102 absorbs a potential difference between the main IGBT cell and the sense IGBT cell, mutual interference can be prevented. At this time, as the number of dummy cells increases, the mutual interference can be reduced. However, if the number of dummy cells is too large, the main current conduction region decreases. Therefore, the minimum number is required to prevent mutual interference between the main IGBT and the sense IGBT. Is preferred. The trench gate of the dummy cell may be continuous or discontinuous with the trench gate of the main IGBT, but is preferably separated from the trench gates of the main IGBT and the sense IGBT to be in a floating state.
[0041]
The configuration in which the dummy trench gate as described above is provided is not limited to the present embodiment, and can be applied to other trench gate IGBT with current cell and trench gate MOSFET.
[0042]
(Example 5)
FIG. 15 is a sectional structural view of a fifth embodiment according to the present invention. In FIG. 15, the same reference numerals are given to the same components as those in FIGS. 1, 2, 5, 8, 10, and 11.
[0043]
15 differs from FIG. 1, FIG. 2, FIG. 5, FIG. 8, FIG. 10 and FIG. 11 in that it is formed wider than the trench gates of the main IGBT cell and the sense IGBT cell between the main IGBT region and the sense IGBT region. This is an isolation trench gate 1500. In this embodiment, the main well layer and the sense well layer are not formed.
[0044]
The feature of the present embodiment is that the main IGBT region and the sense IGBT region are separated by the isolation trench gate 1500 having a groove width wider than the trench gates of the main IGBT cell and the sense IGBT cell.
[0045]
In order to obtain sufficient detection accuracy of the sense IGBT, it is important to electrically separate the main IGBT and the sense IGBT. In particular, in the case of a trench gate IGBT, since the unit cell size is small, if the main IGBT cell and the sense IGBT cell are arranged adjacent to each other like the planar gate IGBT, sufficient insulation cannot be obtained and the detection sensitivity decreases due to mutual interference. Resulting in.
[0046]
According to the present embodiment, since the trench gate having a wide groove width is formed between the main IGBT region and the sense IGBT region, the interaction between the main IGBT region and the sense IGBT region can be reduced, and the detection sensitivity can be improved.
[0047]
At this time, it is preferable that the isolation trench 1500 is electrically insulated from the trench gate of the main IGBT and the trench gate electrode 106 of the sense IGBT. In the operation state of the IGBT, a storage layer is induced at the bottom of the isolation trench gate 1500 by the drive voltage applied to the trench gate electrode 106, and mutual interference occurs through the storage layer. By electrically separating the isolation trench gate from the trench gate electrode 106, the formation of the accumulation layer can be prevented and the occurrence of mutual interference can be suppressed. As in the method described in the first embodiment, the isolation trench is separated from the isolation trench from the main IGBT and the sense IGBT trench in a discontinuous manner, or part of the trench is electrically filled with an insulator. There are methods such as isolation, or isolation by increasing the gate threshold voltage by partially thickening a part of the gate insulating film of the trench.
[0048]
Note that the configuration in which the isolation trench gate as described above is provided is not limited to the present embodiment, and can be applied to other trench gate IGBT with current cell and trench gate MOSFET.
[0049]
(Example 6)
FIGS. 12, 13, and 16 show an equivalent circuit diagram, a sectional structure diagram, and a plan structure diagram of a sixth embodiment according to the present invention, respectively. 13 is a cross-sectional structure diagram when FIG. 12 is formed in the same semiconductor substrate, and FIG. 16 shows the planar structure. 12, 13, and 16, the same reference numerals are given to the same components as those in FIGS. 1, 2, 5, 8, 11, and 15.
[0050]
12, 13, and 16 are different from FIGS. 1, 2, 5, 8, 11, and 15 in that a collector electrode terminal 1200 that is a main electrode and an IGBT control signal are input. Gate electrode terminal 1201, emitter electrode terminal 1202, gate resistor 1203 connected to the gate of the IGBT, diode 1204 whose anode is connected to the gate of the IGBT to prevent energization at the time of reverse bias of the gate, Is connected to the emitter of the sense IGBT, the drain is connected to the cathode of the diode 1204, the source is connected to the emitter electrode 1202, the MOSFET 1205, and the sense resistor 1206 for current detection connected between the emitter and the emitter electrode of the sense IGBT. Cutoff well layer formed in drift layer between main IGBT and sense IGBT region and protection circuit region 1210, a MOSFET base layer 1211 formed in the drift layer of the protection circuit region, a protection circuit region excluding the drain layer 1212 and source layer 1213 formed in the MOSFET base layer 1211, the MOSFET contact layer 1214, and the MOSFET 1205 formation region. The formed oxide film 1220, the interlayer insulating film 1221 for insulating and isolating the gate of the MOSFET, the gate insulating film 1222, the anode electrode 1230 of the gate reverse bias blocking diode formed on the oxide film, the cathode electrode 1231, the source of the MOSFET 1205 MOSFET source electrode 1232 formed in contact with layer 1213, sense resistor electrodes 1233 and 1234 formed on the oxide film, anode reverse bias blocking diode anode layer 1240 and cathode layer 1241 formed on the oxide film, and polycrystalline Silicon 1242, sense IGBT area And a protection circuit region 1600 formed adjacent to the main IGBT region, a breakdown voltage holding region 1601 provided around the chip for holding a breakdown voltage, a sense IGBT region 1602 provided adjacent to the protection circuit and beside the gate pad, and a gate A gate pad 1603 for wire extraction, 1604 for emitter wire extraction, and a main IGBT region. FIG. 13 shows an A-B cross section in FIG.
[0051]
This embodiment is characterized in that the overcurrent protection circuit and the trench gate IGBT with current detection cell are formed in the same semiconductor substrate. As described above, the trench gate IGBT has a large current change rate at the time of switching. Therefore, when an accident such as a load circuit short-circuit occurs, a large current is instantaneously applied and is destroyed.
[0052]
According to the present embodiment, by forming the overcurrent protection circuit on the same semiconductor substrate as the trench gate IGBT, the time until the protection circuit operation can be greatly shortened, and the performance of the trench gate IGBT can be sufficiently exhibited. I can do it. These built-in circuits may be a simple circuit as shown in FIG. 12, and operate quickly when an overcurrent is energized to cut off or reduce the current. In the case of limiting the current, it is more preferable to limit the current value so that the IGBT does not break for about several μs to several tens of μs and to stop the operation by control such as soft switching by an external circuit.
[0053]
Although FIG. 13 shows an example in which a protection circuit is formed using a planar MOSFET, a structure in which the gate electrode of the MOSFET is also a trench gate is better in consideration of process step consistency.
[0054]
Although the present invention has been described with respect to a trench IGBT having a so-called stripe gate structure in which trench gate cells are formed in a stripe shape, the present invention is not limited to this, and the same effect can be obtained with an IGBT having a trench gate. For example, a trench IGBT having a mesh gate structure in which a trench gate is formed in a mesh shape can be used to obtain the same effect by adopting the configuration of the present invention.
[0055]
Moreover, although the case where the present invention is applied to the IGBT has been described in the above-described embodiments, the same effect can be obtained as long as the element has an insulated gate structure. FIG. 17 shows an embodiment in which the present invention is applied to a MOSFET. In FIG. 17, 1701 is a drain layer adjacent to the drain electrode, 1702 is a drift layer adjacent to the drain layer and having a lower impurity concentration than the drain layer, 1703 is a sense base layer formed in the drift layer of the sense MOSFET region, and 1704 is A sense contact layer formed in the sense base layer; 1705, a sense emitter layer formed in the sense base layer;
1706 is a trench gate electrode formed so as to reach the drift layer in the silicon substrate, 1707 is a gate insulating film for insulating and separating the silicon substrate and the gate electrode, and 1708 is for insulating and separating the electrode and the silicon substrate. Interlayer insulating film, 1709 is a sense WELL layer formed continuously to the sense base layer at the end of the sense MOSFET region, 1710 is a main base layer formed in the drift layer of the main MOSFET region, and 1711 is in the main base layer The formed main contact layer, 1712 is a main emitter layer formed in the main base layer, 1713 is a main WELL layer formed continuously to the main MOSFET base layer at the end of the main MOSFET region, and 1720 is a sense contact layer. A sense electrode 1721 formed in contact with the sense emitter layer, a drain electrode 1721 formed in contact with the drain layer and entirely formed; Reference numeral 722 denotes an emitter electrode formed in contact with the main contact layer and the main emitter layer, and reference numeral 1730 denotes a channel formation region formed along the side wall of the trench gate in the main base layer and the sense base layer.
[0056]
Unlike an IGBT, a MOSFET is a unipolar device that allows current to flow by electrons injected from a MOS gate. For this reason, all the energization currents are composed of electronic currents, and are different from IGBTs in this respect. The embodiment of FIG. 1 suppresses the mutual interference between the main IGBT and the sense IGBT, which mainly suppresses the leakage current of the electron current flowing between the main IGBT and the sense IGBT. Therefore, in a MOSFET that is a unipolar device, the effect of the present invention may be greater than when applied to an IGBT.
[0057]
(Example 7)
FIG. 14 shows an equivalent circuit diagram of a seventh embodiment according to the present invention.
[0058]
In FIG. 14, 1400 and 1401 are DC input terminals connected to a DC power source, 1405 is a trench gate semiconductor device with a current detection function to which the present invention is applied, two connected in series between the DC input terminals, 1402 to 1404 An AC output terminal connected to an interconnection point of two trench gate semiconductor devices with a current detection function to which the present invention is applied, connected in series, 1406 is a trench gate semiconductor switching device 1405 with a current detection function to which the present invention is applied. Each is a freewheeling diode connected in antiparallel.
[0059]
A feature of this embodiment is that a trench gate semiconductor switching device with a current detection function is applied to an inverter system. When an overcurrent is detected in the trench gate semiconductor switching device 1405, the control device (not shown) turns off the trench gate semiconductor switching device 1405 to protect the system.
[0060]
When the present invention is applied to an inverter system, since it has a high-precision overcurrent detection cell, high-precision current detection can be performed without a current detection device such as a current probe for current detection. Cost reduction can be achieved.
[0061]
Of course, this is not limited to the inverter system, and it is obvious that the same effect can be obtained by applying it to a current and voltage conversion circuit such as a converter system that maintains the same configuration or a chopper system. is there.
[0062]
As described above, the example in which the present invention is applied to the trench gate IGBT having the stripe cell structure has been described. However, the present invention is not limited to this, and the present invention can be similarly applied to the trench gate IGBT having the mesh cell structure. 6 and 7 are a plan view and a cross-sectional view when the present invention is applied to a trench gate IGBT having a mesh cell structure. FIG. 7 shows an A-B cross section in FIG. Constituent elements common to those in FIG. As shown in FIG. 6, the same effect can be obtained by arranging the meshes of the main IGBT cell and the sense IGBT cell in the same direction.
[0063]
Further, the present invention is not limited to the IGBT, and it is obvious that the same effect can be obtained if the device has a trench gate such as a trench gate MOSFET.
[0064]
【The invention's effect】
As described above, according to the present invention, current detection can be improved in a trench gate semiconductor device with a current detection cell.
[Brief description of the drawings]
FIG. 1 is a plan structural view of a first embodiment of the present invention.
FIG. 2 is a sectional structural view of a first embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of an IGBT with a sense terminal.
FIG. 4 is a plan structural view of a sense IGBT cell of a planar gate IGBT.
FIG. 5 is a plan structural view of a second embodiment of the present invention.
FIG. 6 is a plan view showing an embodiment having a mesh cell structure of the present invention.
7 is a cross-sectional structure diagram of FIG. 6;
FIG. 8 is a plan structural view showing a modification of the second embodiment of the present invention.
FIG. 9 is a plan structural view of a third embodiment of the present invention.
10 is a cross-sectional structure diagram of FIG. 9;
FIG. 11 is a sectional structural view of a fourth embodiment of the present invention.
FIG. 12 is an equivalent circuit diagram of a sixth embodiment of the present invention.
13 is a sectional structural view of FIG. 12. FIG.
FIG. 14 is an equivalent circuit diagram of a seventh embodiment of the present invention.
FIG. 15 is a sectional structural view of a fifth embodiment of the present invention.
FIG. 16 is a plan structural view of a sixth embodiment of the present invention.
FIG. 17 shows an embodiment in which the present invention is applied to a MOSFET.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Collector layer, 101 ... Buffer layer, 102 ... Drift layer, 103 ... Sense base layer, 104 ... Sense contact layer, 105 ... Sense emitter layer, 106 ... Trench gate electrode, 107 ... Gate insulating film, 108 ... Interlayer insulating film 109 ... sense well layer, 110 ... main base layer, 111 ... main contact layer, 112 ... main emitter layer, 113 ... main well layer, 120 ... sense electrode, 121 ... collector electrode, 122 ... emitter electrode, 130 ... channel formation Region 131, sense base layer boundary, 132, main IGBT base layer boundary, 300, main IGBT, 301 ... sense IGBT, 400 ... main IGBT cell, 401 ... sense IGBT cell, 402 ... blocking region, 600 ... main IGBT trench gate Electrode, 601... Sense IGBT trench gate electrode, 900 Sense pad, 1000 ... thick oxide film, 1100 ... dummy trench gate, 1101 ... dummy trench gate insulating film, 1102 ... dummy base layer, 1200 ... collector electrode terminal, 1201 ... gate electrode terminal, 1201 ... gate electrode terminal, 1202 ... emitter Electrode terminal, 1203... Gate resistance, 1204... Gate reverse bias blocking diode, 1205... MOSFET, 1206... Sense resistor, 1210. Contact layer, 1220 ... thick insulating film, 1221 ... interlayer insulating film, 1222 ... gate insulating film, 1230 ... anode electrode of gate reverse bias blocking diode, 1231 ... cathode electrode of gate reverse bias blocking diode, 1232 ... MOSFET source electrode, 1233 , 234 ... sense resistance electrode, 1240 ... anode layer of gate reverse bias blocking diode, 1241 ... cathode layer of gate reverse bias blocking diode, 1242 ... polycrystalline silicon film, 1400, 1401 ... DC input terminal, 1402-1404 ... AC output terminal 1405... Trench gate IGBT with current detection function to which the present invention is applied, 1406.

Claims (10)

A main cell having a trench gate and energizing a main current;
Has a trench gate, the semiconductor device and the current detection Dese Le energizing is formed on the same semiconductor substrate detection current,
The surface orientation of the trench sidewall in which the channel of the trench gate of the main cell is formed and the surface orientation of the trench sidewall in which the channel of the trench gate of the current detection cell is formed are the same or substantially the same,
The trench of the trench gate of the main cell and the trench gate of the current detection cell are discontinuous ,
A trench gate semiconductor device with a current detection cell , comprising: a first well layer surrounding the current detection cell; and a second well layer surrounding the first well layer .   2. The trench gate semiconductor device with a current detection cell according to claim 1, wherein an angle formed by a surface orientation of the trench sidewall of the main cell and a surface orientation of the trench sidewall of the current detection cell is within 5 °. A trench gate semiconductor device with a current detection cell. A main cell having a trench gate and energizing a main current;
Has a trench gate, the semiconductor device and the current detection Dese Le energizing is formed on the same semiconductor substrate detection current,
The plane orientation of the trench sidewall where the channel of the trench gate of the main cell is formed and the plane orientation of the trench sidewall where the channel of the trench gate of the current detection cell is formed are equivalent or substantially equivalent ,
The trench of the trench gate of the main cell and the trench gate of the current detection cell are discontinuous,
A trench gate semiconductor device with a current detection cell , comprising: a first well layer surrounding the current detection cell; and a second well layer surrounding the first well layer .   4. The trench gate semiconductor device with a current detection cell according to claim 3, wherein a surface orientation of a trench side wall of the current detection cell is an angle formed with respect to a surface orientation equivalent to a surface orientation of the trench side wall of the main cell. Is within 5 °, a trench gate semiconductor device with a current detection cell. Wherein the first well layer, and the second well layer, a current detection cell according to any one of claims 1 to 4, characterized in that deeper than the trench gate of the main cell and current sensing cell Trench gate semiconductor device.   A current detection pad electrically connected to the emitter electrode of the current detection cell; and a pad well layer electrically connected to the emitter electrode of the current detection cell and formed in a semiconductor substrate. 5. The trench gate semiconductor device with a current detection cell according to claim 1, wherein the current detection pad is formed on a layer. 6. A pair of DC terminals;
AC terminals of the same number as the number of phases of AC output,
Connected between the pair of DC terminals, each having a configuration in which two parallel circuits of diode switching elements and diodes of opposite polarity are connected in series, and the output points of AC outputs connected to different AC terminals at different interconnection points. In the power conversion device comprising the same number of inverter units as the number of phases,
The semiconductor switching element is
Has a trench gate, a main cell for supplying a main current, having a trench gate, a current sense Dese Le energizing the detected current is being formed on the same semiconductor substrate,
The plane orientation of the trench sidewall in which the channel of the trench gate of the main cell is formed and the plane orientation of the trench sidewall in which the channel of the trench gate of the current detection cell is formed are the same or substantially the same, The trench of the cell trench gate and the trench of the current detection cell trench gate are discontinuous ,
A power conversion device comprising a trench gate semiconductor device with a current detection cell , wherein a first well layer surrounding the current detection cell and a second well layer surrounding the first well layer are arranged . A pair of DC terminals;
AC terminals of the same number as the number of phases of AC output,
Connected between the pair of DC terminals, each having a configuration in which two parallel circuits of diode switching elements and diodes of opposite polarity are connected in series, and the output points of AC outputs connected to different AC terminals at different interconnection points. In the power conversion device comprising the same number of inverter units as the number of phases,
The semiconductor switching element is
A main cell having a trench gate and energizing a main current;
Has a trench gate, a current sense Dese Le energizing the detected current is being formed on the same semiconductor substrate,
The plane orientation of the trench sidewall in which the channel of the trench gate of the main cell is formed and the plane orientation of the trench sidewall in which the channel of the trench gate of the current detection cell is formed are equivalent or substantially equivalent ,
The trench of the trench gate of the main cell and the trench gate of the current detection cell are discontinuous,
A power conversion device comprising: a trench gate semiconductor device with a current detection cell , comprising: a first well layer surrounding the current detection cell; and a second well layer surrounding the first well layer . Power converter, wherein the power converter according to claim 7 or claim 8, an IGBT said current sensing cell with a trench-gate semiconductor device formed on a silicon substrate. Power converter, wherein the power converter according to claim 7 or claim 8, a MOSFET in which the current sensing cell with a trench-gate semiconductor device formed on a silicon substrate.

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