JP4167294B2 - Semiconductor elements and electrical equipment - Google Patents

Semiconductor elements and electrical equipment Download PDF

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Publication number
JP4167294B2
JP4167294B2 JP2007528443A JP2007528443A JP4167294B2 JP 4167294 B2 JP4167294 B2 JP 4167294B2 JP 2007528443 A JP2007528443 A JP 2007528443A JP 2007528443 A JP2007528443 A JP 2007528443A JP 4167294 B2 JP4167294 B2 JP 4167294B2
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Prior art keywords
schottky
region
electrode
diode
semiconductor
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JPWO2007013377A1 (en
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真 北畠
修 楠本
正雄 内田
賢哉 山下
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Abstract

In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Description

本発明は、半導体素子、特に、インバータ回路などを制御する半導体パワースイッチング素子に関する。   The present invention relates to a semiconductor element, and more particularly to a semiconductor power switching element that controls an inverter circuit and the like.

通常の半導体パワースイッチング素子としては、例えば、IGBT(Insulated Gate Bipolar Transistor)などが挙げられる。そして、半導体パワースイッチング素子の応用例としては、パワーエレクトロニクス制御に用いられる制御回路があり、例えば、三相モータを制御するインバータ回路が挙げられる。   Examples of normal semiconductor power switching elements include IGBTs (Insulated Gate Bipolar Transistors). As an application example of the semiconductor power switching element, there is a control circuit used for power electronics control, for example, an inverter circuit for controlling a three-phase motor.

図9は、この従来のインバータ回路の概要を示す回路図である。図9に示すように、従来のインバータ回路(ここでは3相用)は、スイッチ機能部分(以下、上アームという)23Hとスイッチ機能部分(以下、下アームという)23Lとが直列に接続されてなる回路(以下、相スイッチング回路という)23を相数分(ここでは3つ)備え、上アーム23H及び下アーム23Lの各々は、互いに並列に接続されたスイッチング素子21とダイオード22とで構成されている。スイッチング素子21は、例えば、シリコンを用いたIGBTで構成されている。そして、上アーム23Hが高電位配線25に接続され、下アーム23Lがアース電位配線24に接続されている。各アーム23の中点26は負荷である3相交流モータの入力端子(以下、モータ入力端子という)27に接続されている。そして、上アーム23Hと下アーム23Lとのオン、オフのタイミングを調整することによって、中点26の電位を制御することができる。すなわち、中点26ひいては入力端子27の電位は、下アーム23Lをオンにし、上アーム23Hをオフにした場合にはアース電位24と等しくなる。一方、中点26ひいては入力端子27の電位は、上アーム23Hをオンにし、下アーム23Lをオフにした場合には高電位25と等しくなる。このように、モータ入力端子27の電位をアース電位24と高電位25とに切り替えることにより、三相モータ28を制御することができる。   FIG. 9 is a circuit diagram showing an outline of this conventional inverter circuit. As shown in FIG. 9, a conventional inverter circuit (here, for three phases) has a switch function part (hereinafter referred to as an upper arm) 23H and a switch function part (hereinafter referred to as a lower arm) 23L connected in series. Circuit (hereinafter referred to as phase switching circuit) 23 corresponding to the number of phases (here, three), each of the upper arm 23H and the lower arm 23L includes a switching element 21 and a diode 22 connected in parallel to each other. ing. The switching element 21 is composed of, for example, an IGBT using silicon. The upper arm 23H is connected to the high potential wiring 25, and the lower arm 23L is connected to the ground potential wiring 24. A midpoint 26 of each arm 23 is connected to an input terminal (hereinafter referred to as a motor input terminal) 27 of a three-phase AC motor that is a load. The potential at the midpoint 26 can be controlled by adjusting the on / off timing of the upper arm 23H and the lower arm 23L. That is, the potential of the midpoint 26 and hence the input terminal 27 is equal to the ground potential 24 when the lower arm 23L is turned on and the upper arm 23H is turned off. On the other hand, the potential of the midpoint 26 and hence the input terminal 27 becomes equal to the high potential 25 when the upper arm 23H is turned on and the lower arm 23L is turned off. Thus, the three-phase motor 28 can be controlled by switching the potential of the motor input terminal 27 between the ground potential 24 and the high potential 25.

しかし、スイッチング素子21やダイオード22の応答速度が有限であるため、スイッチング素子21やダイオード22に対してオン状態からオフ状態に切り替える信号を与えても、すぐにはオフ状態とならない。このため、上アーム23Hと下アーム23Lとのオン、オフの切り替えを同時に行うと、上アーム23Hと下アーム23Lとが共にオン状態となり得る。このような状態は、高電位25とアース電位24とがショートした状態であり、インバータ回路に大電流が流れてしまう。また、この電流は損失電流となるため、スイッチング損失が増加し、電力利用効率を低下させる。そして、インバータ回路においては高速のスイッチングによる高効率インバータ制御を行うため、一回のスイッチング損失がスイッチング回数分積算されて、全体のスイッチング損失が大きくなる。そこで、従来においては、スイッチング素子21やダイオード22の応答速度を考慮してスイッチングのタイミングを決めている。換言すると、スイッチング素子21やダイオード22の応答速度の制約により、インバータ制御の周波数が決められている。しかし、さらに高速なスイッチングにより高効率インバータ制御をしようとする場合には、スイッチング素子21及びダイオード22のスイッチングをさらに高速化することが求められる。   However, since the response speed of the switching element 21 and the diode 22 is finite, even if a signal for switching the ON state from the ON state to the switching element 21 or the diode 22 is given, the switching element 21 and the diode 22 are not immediately turned off. For this reason, if the upper arm 23H and the lower arm 23L are switched on and off at the same time, both the upper arm 23H and the lower arm 23L can be turned on. Such a state is a state in which the high potential 25 and the ground potential 24 are short-circuited, and a large current flows through the inverter circuit. Further, since this current becomes a loss current, the switching loss increases and the power use efficiency is lowered. Since the inverter circuit performs high-efficiency inverter control by high-speed switching, one switching loss is integrated for the number of times of switching, and the entire switching loss increases. Therefore, conventionally, the switching timing is determined in consideration of the response speed of the switching element 21 and the diode 22. In other words, the frequency of inverter control is determined by the restriction on the response speed of the switching element 21 and the diode 22. However, when high-efficiency inverter control is to be performed by faster switching, it is required to further speed up switching of the switching element 21 and the diode 22.

しかし、スイッチング素子としてIGBTを用いた場合、このIGBTはバイポーラデバイスであるため、マイノリティーキャリアのライフタイムが長く、逆回復に要する時間がかかるため、オンからオフへのスイッチングが高速に行われない。そこで、ユニポーラデバイスであるMOSFET(金属−酸化物−半導体−電界効果トランジスタ)をスイッチング素子として用いることが考えられる。ユニポーラデバイスは、マイノリティーキャリアの影響を受けないので、オンからオフへのスイッチングを高速に行うことができる。しかし、シリコンにより構成されたMOSFETは、単位面積当たりのオン抵抗Ron(Ωcm)が大きく、発熱による導通損失が増加する。 However, when an IGBT is used as a switching element, since this IGBT is a bipolar device, the minority carrier has a long lifetime and takes a long time for reverse recovery, so switching from on to off is not performed at high speed. Therefore, it is conceivable to use a MOSFET (metal-oxide-semiconductor-field effect transistor) which is a unipolar device as a switching element. Since the unipolar device is not affected by the minority carrier, switching from on to off can be performed at high speed. However, MOSFETs made of silicon have a large on-resistance Ron (Ωcm 2 ) per unit area and increase conduction loss due to heat generation.

一方、ダイオードのスイッチングを高速化したものには、キャリアのライフタイム制御を施したファーストリカバリーダイオードがある。しかし、ファーストリカバリーダイオードは、数10kHz以上の高周波での動作が困難である。また、ファーストリカバリーダイオードはバイポーラデバイスであるため、マイノリティーキャリアの拡散によってオン抵抗は小さくなるが、マイノリティーキャリアのライフタイムが長いため、オンからオフへのスイッチングに時間がかかる。また、ダイオードのスイッチングをさらに高速化したものに、ショットキー電極を半導体にショットキー接合を形成するように設けたショットキーダイオードがある。ショットキーダイオードはユニポーラデバイスであり、マイノリティーキャリアの影響を受けないため、オンからオフへのスイッチングを高速に行うことができる。しかし、シリコンにより構成されたショットキーダイオードの場合には、100V程度の耐圧しかなく、600V以上の耐圧を必要とするパワーエレクトロニクス分野では利用できなかった。   On the other hand, there is a fast recovery diode in which the lifetime of the carrier is controlled as a diode whose switching speed is increased. However, the fast recovery diode is difficult to operate at a high frequency of several tens of kHz or more. Further, since the first recovery diode is a bipolar device, the on-resistance is reduced by the diffusion of minority carriers, but it takes time to switch from on to off because the lifetime of the minority carriers is long. In addition, there is a Schottky diode in which a Schottky electrode is provided so as to form a Schottky junction in a semiconductor as a diode whose switching speed is further increased. Since the Schottky diode is a unipolar device and is not affected by minority carriers, switching from on to off can be performed at high speed. However, a Schottky diode made of silicon has only a withstand voltage of about 100 V, and cannot be used in the power electronics field that requires a withstand voltage of 600 V or more.

また、シリコンにより構成されたIGBTやダイオードは、キャリアのライフタイム制御が施されているため、ワンチップとして集積することができなかった。   Further, since IGBTs and diodes made of silicon are subjected to carrier lifetime control, they cannot be integrated as a single chip.

そこで、インバータ回路などに用いられるスイッチング素子及びダイオードをワイドバンドギャップ半導体により構成することが提案されている。   Therefore, it has been proposed that switching elements and diodes used in inverter circuits and the like are formed of wide band gap semiconductors.

例えば、ダイオードに関しては、ワイドバンドギャップ半導体により構成されるショットキーダイオードは、耐圧が600V以上もあり、オン抵抗もシリコンにより構成された場合に比べて十分に小さく、かつ、オンからオフへのスイッチングを高速に行うことができる。   For example, with regard to diodes, Schottky diodes composed of wide bandgap semiconductors have a withstand voltage of 600 V or higher, on-resistance is sufficiently smaller than that composed of silicon, and switching from on to off Can be performed at high speed.

一方、スイッチング素子に関しては、ワイドバンドギャップ半導体により構成されるMOSFETは、シリコンにより構成されるIGBTに比べて単位面積当たりのオン抵抗が十分に小さく、耐圧を確保することができ、かつ、オンからオフへのスイッチングを高速に行うことができる。   On the other hand, with regard to switching elements, MOSFETs composed of wide bandgap semiconductors have sufficiently low on-resistance per unit area compared to IGBTs composed of silicon, and can withstand withstand voltage, and from the on-state. Switching to off can be performed at high speed.

しかしながら、SiC−MISFETであっても半導体装置内のp型領域とn型領域のPN接合から構成される寄生ダイオードにより、逆バイアス時の寄生ダイオードのオン状態からSiC−MISFETのオフへの切り替えにおける逆回復時間の遅れを伴う可能性がある。   However, even in the SiC-MISFET, in the switching from the ON state of the parasitic diode at the time of reverse bias to the OFF state of the SiC-MISFET due to the parasitic diode composed of the PN junction of the p-type region and the n-type region in the semiconductor device. There may be a delay in reverse recovery time.

例えば、スイッチング素子のターンオフ時にインダクタンス負荷により発生する逆起電力としてのプラス電圧が、ソース電極に印加された場合には、寄生ダイオードを介して少数キャリアとしての正孔がn型領域に注入され、ダイオード動作の逆回復時間の遅れをきたすことになる。   For example, when a positive voltage as a back electromotive force generated by an inductance load when the switching element is turned off is applied to the source electrode, holes as minority carriers are injected into the n-type region via the parasitic diode, The reverse recovery time of the diode operation will be delayed.

一方、MOSFETをワイドバンドギャップ半導体により構成し、この縦型MOSFETのドリフト領域にショットキー接合するようにショットキー電極を配設することによって、ショットキーダイオードとスイッチング素子たるMOSFETとをワンチップとして集積することができるようになる(特許文献1参照)。
特開2002−203967号公報
On the other hand, the MOSFET is composed of a wide band gap semiconductor, and the Schottky diode and the switching element MOSFET are integrated as a single chip by disposing the Schottky electrode so as to form a Schottky junction in the drift region of this vertical MOSFET. (See Patent Document 1).
JP 2002-203967 A

ところで、上記従来の半導体素子を、具体的なインバータ電源回路(例えば、エアコンディショナーコンプレッサ等の3相モータ用のインバータ電源回路)を構成するスイッチング素子として使用する場合、こうしたスイッチング素子の実用化に向けて以下のような課題が顕在化してきた。   By the way, when the conventional semiconductor element is used as a switching element constituting a specific inverter power supply circuit (for example, an inverter power supply circuit for a three-phase motor such as an air conditioner compressor), the practical use of such a switching element is aimed at. The following issues have become apparent.

ショットキー接合の金属電極(ショットキー電極)の配置面積は、半導体素子の高速スイッチング動作に大きな障害をもたらしはしない。しかし、MOSFET内に存在する寄生ダイオード及びショットキーダイオードに順方向電圧が印加され、両者に電流を流すような状況を勘案すれば、ショットキー電極の配置面積は、適切な通電能力確保の観点から重要な考慮すべき内容となる。   The arrangement area of the metal electrode (Schottky electrode) of the Schottky junction does not cause a great obstacle to the high-speed switching operation of the semiconductor element. However, considering the situation where a forward voltage is applied to the parasitic diode and the Schottky diode existing in the MOSFET and current flows through both, the layout area of the Schottky electrode is from the viewpoint of securing an appropriate current-carrying capacity. This is an important consideration.

実際に、3相モータ用のインバータ電源回路に特許文献1に記載された技術を適用したところ、スイッチング素子ターンオフ時におけるインダクタンス負荷に基づく逆起電力をトリガーにして、ショットキー電極に集中する電流に起因した素子の破壊に至る可能性が発見された。   Actually, when the technique described in Patent Document 1 is applied to an inverter power supply circuit for a three-phase motor, the current concentrated on the Schottky electrode is triggered by the counter electromotive force based on the inductance load when the switching element is turned off. The possibility of the destruction of the resulting element was discovered.

また、特許文献1の図2に示されたショットキー電極は、平面視において電界効果トランジスタ領域を囲むよう細配線に結ばれた直交格子状に配置されている。このため、半導体素子の製造途中において細配線の断線が誘発され易く、これが半導体素子の製造歩留まりを低下させる要因となり得る。   Further, the Schottky electrodes shown in FIG. 2 of Patent Document 1 are arranged in an orthogonal lattice shape connected to fine wirings so as to surround the field effect transistor region in plan view. For this reason, the disconnection of the fine wiring is likely to be induced during the manufacturing of the semiconductor element, and this may be a factor of reducing the manufacturing yield of the semiconductor element.

本発明は、このような事情に鑑みてなされたものであり、高速スイッチング動作とエネルギー損失低減との両立が図れ、かつ電気機器のインダクタンス負荷等による逆起電力に基づく電流集中耐性に優れ、かつワイヤボンディング時における電界効果トランジスタの絶縁膜の劣化を抑制可能な半導体素子及び電気機器を提供することを目的とする。   The present invention has been made in view of such circumstances, and it is possible to achieve both high-speed switching operation and energy loss reduction, and is excellent in current concentration resistance based on counter electromotive force due to inductance load of an electrical device, and the like. It is an object of the present invention to provide a semiconductor element and an electric device capable of suppressing deterioration of an insulating film of a field effect transistor during wire bonding.

本件発明者らは、上記課題を解決するために鋭意検討した結果、特許文献1の構成ではショットキー電極の配設された領域の面積が半導体素子全体の面積に対して占める割合が小さいため、ショットキー電極に電流が集中して半導体素子が破壊されることを突き止めた。   As a result of intensive studies to solve the above problems, the inventors of the present invention have a small proportion of the area of the area where the Schottky electrode is arranged in the configuration of Patent Document 1 to the total area of the semiconductor element. It was found that the current was concentrated on the Schottky electrode and the semiconductor element was destroyed.

また、高電圧で大電流をスイッチングする半導体素子をボンディングする場合、大電流に耐えられるようにするため、0.3mm径以上の太いワイヤをワイヤボンドして電極端子などと結線する。この場合、超音波を印加しながらワイヤを半導体素子上に配置されたボンディングパッドに押し付けてワイヤボンドするが、ボンディングパッドの下に電界効果トランジスタが配置されていると超音波の印加によって電界効果トランジスタが破壊されるおそれがある。そして、本件発明者らは、超音波を印加することにより電界効果トランジスタにおける絶縁膜が耐圧劣化することを発見した。   When bonding a semiconductor element that switches a large current at a high voltage, a thick wire having a diameter of 0.3 mm or more is wire-bonded and connected to an electrode terminal or the like in order to withstand the large current. In this case, a wire is bonded by pressing a wire against a bonding pad disposed on a semiconductor element while applying an ultrasonic wave. If a field effect transistor is disposed under the bonding pad, the field effect transistor is applied by applying an ultrasonic wave. May be destroyed. The inventors of the present invention have found that the insulation film in the field effect transistor deteriorates withstand voltage by applying ultrasonic waves.

そこで、本発明の半導体素子は、半導体層と、該半導体層に該半導体層の上面を含むように形成された第1導電型の第1のソース/ドレイン領域と、前記半導体層に前記上面及び前記第1のソース/ドレイン領域を含むように形成された第2導電型領域と、前記半導体層に前記上面及び前記第2導電型領域を含むように形成された第1導電型のドリフト領域と、少なくとも前記第1のソース/ドレイン領域の前記上面に接するように設けられた第1のソース/ドレイン電極と、ゲート絶縁膜を介して少なくとも前記第2導電型領域の前記上面に対向するように設けられたゲート電極と、前記ドリフト領域にオーミックに接続された第2のソース/ドレイン電極と、を有する電界効果トランジスタと、前記ドリフト領域の前記上面に該上面とショットキー接合を形成するように設けられたショットキー電極と、前記第1のソース/ドレイン電極、ゲート電極、及びショットキー電極が設けられた前記半導体層の上面を覆う層間絶縁膜と、前記層間絶縁膜の上に配設され、前記第1のソース/ドレイン電極、ゲート電極、及びショットキー電極の少なくともいずれかと電気的に接続された複数のボンディングパッドと、を備える。そして、前記半導体層は、平面視において仮想の境界線により複数のセルに分割され、前記複数のセルに延在するように前記ドリフト領域及び第2のソース/ドレイン電極が形成され、前記複数のセルは、その中に前記電界効果トランジスタが形成されたトランジスタセルと、その中に前記ショットキー電極が形成されたダイオードセルとで構成されている。また、平面視において、複数の前記トランジスタセルの間に1以上の前記ダイオードセルが島状に配置され、この島状に配置された1以上の前記ダイオードセルの前記ショットキー電極の上方に前記ボンディングパッドが位置している。 Accordingly, the semiconductor element of the present invention includes a semiconductor layer, a first source / drain region of a first conductivity type formed in the semiconductor layer so as to include the upper surface of the semiconductor layer, the upper surface and A second conductivity type region formed to include the first source / drain region; a first conductivity type drift region formed to include the upper surface and the second conductivity type region in the semiconductor layer; A first source / drain electrode provided so as to be in contact with at least the upper surface of the first source / drain region, and at least the upper surface of the second conductivity type region through a gate insulating film. A field effect transistor having a provided gate electrode and a second source / drain electrode ohmically connected to the drift region; and an upper surface and a shim on the upper surface of the drift region. A Schottky electrode provided to form a utkey junction; an interlayer insulating film covering an upper surface of the semiconductor layer provided with the first source / drain electrode, the gate electrode, and the Schottky electrode; and the interlayer insulation disposed on the film, said first source / drain electrode, and a plurality of bonding pads electrically connected to at least one of the gate electrode, and the Schottky electrode, Ru comprising a. The semiconductor layer is divided into a plurality of cells by a virtual boundary line in plan view, and the drift region and the second source / drain electrode are formed so as to extend to the plurality of cells. The cell is composed of a transistor cell in which the field effect transistor is formed and a diode cell in which the Schottky electrode is formed . In plan view, one or more diode cells are arranged in an island shape between the plurality of transistor cells, and the bonding is performed above the Schottky electrode of the one or more diode cells arranged in the island shape. The pad is located.

このような構成とすると、ボンディングパッドにワイヤをボンディングする際に、超音波を印加しながらワイヤをボンディングパッドに押し付けてワイヤボンドしても、ボンディングパッドの下方にはショットキー電極が配設されたダイオードセルが配置されているので、トランジスタセルに形成された電界効果トランジスタの破壊やゲート絶縁膜の耐圧劣化を低減することができる。また、電界効果トランジスタに存在するp/n障壁に比べて小さいエネルギー障壁を有するショットキー接合が半導体素子中に存在するので、半導体素子にサージ電圧が印加された場合に、ショットキー接合部分に優先的にリーク電流が流れ、それにより、サージ電圧が緩和され、半導体素子の破壊が抑制される。また、電界効果トランジスタの寄生ダイオードをオンからオフへとスイッチングした場合に、電界効果トランジスタの寄生ダイオードに由来する少数キャリアがショットキー電極により吸収され、高速のスイッチングが行えるようになる。   With such a configuration, when a wire is bonded to the bonding pad, a Schottky electrode is disposed below the bonding pad even if wire bonding is performed by pressing the wire against the bonding pad while applying an ultrasonic wave. Since the diode cell is arranged, it is possible to reduce the breakdown of the field effect transistor formed in the transistor cell and the breakdown voltage deterioration of the gate insulating film. In addition, since a Schottky junction having an energy barrier smaller than that of the p / n barrier existing in the field effect transistor exists in the semiconductor element, when a surge voltage is applied to the semiconductor element, priority is given to the Schottky junction portion. Thus, a leakage current flows, whereby the surge voltage is reduced and the destruction of the semiconductor element is suppressed. Further, when the parasitic diode of the field effect transistor is switched from on to off, minority carriers derived from the parasitic diode of the field effect transistor are absorbed by the Schottky electrode, and high-speed switching can be performed.

このような構成とすると、ショットキー電極を配設する領域の面積を十分広く取ることができるようになるため、ショットキー電極への電流の集中が防止され、半導体素子の破壊が抑制される。   With such a configuration, the area of the region where the Schottky electrode is provided can be made sufficiently large, so that current concentration on the Schottky electrode is prevented, and destruction of the semiconductor element is suppressed.

前記第1のソース/ドレイン電極が、前記第1のソース/ドレイン領域及び第2導電型領域の前記上面に接するように設けられていてもよい。   The first source / drain electrode may be provided in contact with the upper surface of the first source / drain region and the second conductivity type region.

前記第1導電型がn型であり、前記第2導電型がp型であってもよい。   The first conductivity type may be n-type and the second conductivity type may be p-type.

前記半導体層がワイドバンドギャップ半導体で構成されていてもよい。   The semiconductor layer may be composed of a wide band gap semiconductor.

前記複数のボンディングパッドは、ワイヤによって互いに接続されていてもよい。   The plurality of bonding pads may be connected to each other by wires.

前記ボンディングパッドは辺の長さが0.3mm以上である四角形の形状を有していてもよい。   The bonding pad may have a quadrangular shape with a side length of 0.3 mm or more.

前記半導体素子の平面視における面積に対する全ての前記トランジスタセルの平面視における面積の割合が50%以上でかつ99%以下であることが好ましい。   The ratio of the area of all the transistor cells in plan view to the area of the semiconductor element in plan view is preferably 50% or more and 99% or less.

前記半導体素子の平面視における面積に対する前記ショットキー電極の面積の割合が1%以上でかつ50%以下であることが好ましい。   The ratio of the area of the Schottky electrode to the area of the semiconductor element in plan view is preferably 1% or more and 50% or less.

前記ダイオードセルにおける前記ショットキー電極の面積が前記トランジスタセルにおける前記第2導電型領域の平面視における面積より大きいことが好ましい。   It is preferable that an area of the Schottky electrode in the diode cell is larger than an area in a plan view of the second conductivity type region in the transistor cell.

また、本発明は、交流駆動装置のインバータ電源回路を構成する半導体素子として用いることができ、例えば、前記半導体素子がアームモジュールとして組み込まれている電気機器に適用することができる。   In addition, the present invention can be used as a semiconductor element that constitutes an inverter power supply circuit of an AC drive device. For example, the present invention can be applied to an electric device in which the semiconductor element is incorporated as an arm module.

このような電気機器によれば、半導体素子の導通損失は電流に電圧を乗じた値(電流×電圧)に対応することから、従来のPN接合ダイオードの順方向電圧に比べてショットキーダイオードの順方向電圧を低く保つことができる。したがって、電気機器のインバータ電源回路においてアームモジュールとして組み込まれている半導体素子の導通損失が、PN接合ダイオードを採用した既存のものに比較して改善する。   According to such an electrical device, the conduction loss of the semiconductor element corresponds to the value obtained by multiplying the current by the voltage (current × voltage), so that the forward voltage of the Schottky diode is higher than the forward voltage of the conventional PN junction diode. The directional voltage can be kept low. Therefore, the conduction loss of the semiconductor element incorporated as an arm module in the inverter power supply circuit of the electric device is improved as compared with the existing one employing the PN junction diode.

さらに、電気機器のインバータ電源回路においてアームモジュールとして組み込まれている半導体素子のオン状態からオフ状態への切り替え速度が速くなり、スイッチング損失が低減される。   Furthermore, the switching speed from the ON state to the OFF state of the semiconductor element incorporated as an arm module in the inverter power supply circuit of the electric equipment is increased, and the switching loss is reduced.

前記交流駆動装置内のインダクタンス負荷によって発生する逆起電力に基づいて、前記電界効果トランジスタの寄生ダイオード及び前記ドリフト領域と該ドリフト領域の上面とショットキー接合を形成するショットキー電極とによって構成されたショットキーダイオードに印加される電圧は、前記ショットキーダイオードの順方向の立ち上がり電圧よりも大きく、かつ前記寄生ダイオードの順方向の立ち上がり電圧より小さくして構成されても良い。   Based on the back electromotive force generated by the inductance load in the AC drive device, the parasitic diode of the field effect transistor and the drift region, and the Schottky electrode that forms the Schottky junction with the upper surface of the drift region The voltage applied to the Schottky diode may be configured to be larger than the forward rising voltage of the Schottky diode and smaller than the forward rising voltage of the parasitic diode.

前記交流駆動装置の一例は、前記インバータ電源回路により駆動される交流モータであり、この交流モータにより、例えばエアコンディショナーのコンプレッサが駆動される。   An example of the AC drive device is an AC motor driven by the inverter power supply circuit, and, for example, a compressor of an air conditioner is driven by the AC motor.

本発明の上記目的、他の目的、特徴、及び利点は、添付図面参照の下、以下の好適な実施態様の詳細な説明から明らかにされる。   The above object, other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

本発明によれば、高速スイッチング動作とエネルギー損失低減の両立が図れ、かつ電気機器のインダクタンス負荷等による逆起電力に基づく電流集中耐性に優れ、かつワイヤボンディング時における電界効果トランジスタの絶縁膜の劣化を抑制可能な半導体素子及び電気機器が得られる。   According to the present invention, both high-speed switching operation and energy loss reduction can be achieved, the current concentration resistance based on the counter electromotive force due to the inductance load etc. of electrical equipment is excellent, and the insulating film of the field effect transistor is deteriorated during wire bonding. A semiconductor element and an electric device that can suppress the above are obtained.

以下、本発明の実施形態を、図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

(第1実施形態)
図1及び図2は、本発明の第1実施形態の半導体素子の構成を示す平面図である。図3は、図1の半導体素子の構成の一部を拡大した部分平面図である。図4は、図1の半導体素子の断面視における構造を示す部分断面図であって、図3に示すIV−IV線に沿って切断した断面図である。
(First embodiment)
1 and 2 are plan views showing the configuration of the semiconductor element according to the first embodiment of the present invention. FIG. 3 is an enlarged partial plan view of a part of the configuration of the semiconductor element of FIG. 4 is a partial cross-sectional view showing the structure of the semiconductor element of FIG. 1 in a cross-sectional view, and is a cross-sectional view taken along line IV-IV shown in FIG.

本実施形態の半導体素子は、電界効果トランジスタ(以下、MOSFETという場合もある)とショットキーダイオードとが並列に接続された回路として機能し、そのような回路を構成する複数の電界効果トランジスタと複数のショットキーダイオードとが集積化された1つのICチップで構成されている。そして、本実施形態の半導体素子は、例えば、三相モータ駆動用のインバータ回路(図6参照)において相スイッチング回路23として用いられる。電界効果トランジスタの集積化される数は所望の電流容量により決定される。   The semiconductor element of this embodiment functions as a circuit in which a field effect transistor (hereinafter also referred to as a MOSFET) and a Schottky diode are connected in parallel, and a plurality of field effect transistors and a plurality of the circuit elements constituting such a circuit. The Schottky diode is integrated into one IC chip. And the semiconductor element of this embodiment is used as the phase switching circuit 23 in the inverter circuit (refer FIG. 6) for a three-phase motor drive, for example. The number of integrated field effect transistors is determined by the desired current capacity.

図1及び図2に示すように、本実施形態の半導体素子20は、トランジスタ形成領域10を有している。このトランジスタ形成領域10は、ここでは、平面視において正方形である。なお、セル形成領域201は、平面視において正方形である場合に限られない。このトランジスタ形成領域10は、平面視において格子状の仮想の境界線50で区切られた複数のセル200、言い換えれば、行列状に区画された領域からなる複数のセル200に分割されている。各セル200は、ここでは正方形である。この複数のセル200は、後述する電界効果トランジスタ90が形成されたトランジスタセル100と、ショットキー電極9aが配設されショットキーダイオード70が形成されたダイオードセル80とで構成される。そして、本実施形態の半導体素子20においては、トランジスタ形成領域10において、1以上のダイオードセル80が配設された領域(以下、ダイオード形成領域という。)9が島状に形成され、この島状のダイオード形成領域9の間を埋めるようにトランジスタセル100が形成されている。本実施形態では、ダイオード形成領域9は、トランジスタ形成領域10に計9箇所配設されているが、ダイオード形成領域9の数はこれに限定されない。また、本実施形態では、1つのダイオード形成領域9は、縦3×横3の計9つのダイオードセル80が集まって構成されているが、ダイオードセル80の数もその配置もこれには限定されない。   As shown in FIGS. 1 and 2, the semiconductor element 20 of this embodiment has a transistor formation region 10. Here, the transistor formation region 10 is square in plan view. The cell formation region 201 is not limited to a square shape in plan view. The transistor formation region 10 is divided into a plurality of cells 200 partitioned by a lattice-like virtual boundary line 50 in plan view, in other words, a plurality of cells 200 composed of regions partitioned in a matrix. Each cell 200 is square here. The plurality of cells 200 includes a transistor cell 100 in which a field effect transistor 90 described later is formed, and a diode cell 80 in which a Schottky electrode 9a is provided and a Schottky diode 70 is formed. In the semiconductor element 20 of this embodiment, a region (hereinafter referred to as a diode formation region) 9 in which one or more diode cells 80 are disposed is formed in an island shape in the transistor formation region 10. Transistor cells 100 are formed so as to fill the gaps between the diode formation regions 9. In the present embodiment, a total of nine diode forming regions 9 are disposed in the transistor forming region 10, but the number of diode forming regions 9 is not limited to this. In the present embodiment, one diode formation region 9 is configured by a total of nine diode cells 80 of 3 × 3 in length, but the number and arrangement of the diode cells 80 are not limited to this. .

トランジスタ形成領域10の外側には後述する半導体層3の表面にトランジスタ形成領域10を囲むようにガードリング11が形成されている。そして、ダイオード形成領域9を覆うようにしてボンディングパッド(ソース・ショットキー用パッド)12Sが配設されている。なお、ソース・ショットキー用パッド12Sの面積は、ダイオード形成領域9の面積よりも小さくしてもよい。そして、このソース・ショットキー用パッド12S同士がワイヤ13Sで架橋されるようにして接続されている。また、トランジスタ形成領域10の外周の端部には、ボンディングパッド(ゲート用パッド)12Gが配設され、このゲート用パッド12Gがワイヤ13Gで接続されている。   A guard ring 11 is formed outside the transistor formation region 10 so as to surround the transistor formation region 10 on the surface of a semiconductor layer 3 described later. Then, a bonding pad (source / Schottky pad) 12S is disposed so as to cover the diode forming region 9. The area of the source / Schottky pad 12S may be smaller than the area of the diode formation region 9. The source / Schottky pads 12S are connected so as to be bridged by wires 13S. A bonding pad (gate pad) 12G is disposed at an outer peripheral end of the transistor formation region 10, and the gate pad 12G is connected by a wire 13G.

次に、仮想の境界線50について説明する。図10は、仮想の境界線を説明するための概略図であって、(a)は仮想の境界線を特定する第1の手法を示す図、(b)は仮想の境界線を特定する第2の手法を示す図、(c)は仮想の境界線を特定する第3の手法を示す図、(d)は仮想の境界線を特定する第4の手法を示す図である。   Next, the virtual boundary line 50 will be described. 10A and 10B are schematic diagrams for explaining a virtual boundary line, where FIG. 10A is a diagram illustrating a first method for specifying a virtual boundary line, and FIG. 10B is a first diagram for specifying a virtual boundary line. FIG. 2C is a diagram showing a third technique for specifying a virtual boundary line, and FIG. 4D is a diagram showing a fourth technique for specifying a virtual boundary line.

図1乃至図3において、2点鎖線で示した仮想の境界線50は、請求の範囲や明細書の内容を説明しやすくするものであって、本発明を具現化した製品に実在するものではない。仮想の境界線50は、トランジスタセル100同士が隣接する場合には、トランジスタセル100の各々の中心から等距離に縦方向又は横方向に延びる仮想線であり、ダイオードセル80同士が隣接する場合にはダイオードセル80の各々の中心から等距離に縦方向又は横方向に延びる仮想線であり、トランジスタセル100とダイオードセル80とが隣接する場合にはトランジスタセル100の中心とダイオードセル80の中心とから等距離に縦方向又は横方向に延びる仮想線である。仮想の境界線50は、電界効果トランジスタ90及びショットキーダイオード70の形状により、適宜、変更される。   In FIG. 1 to FIG. 3, a virtual boundary line 50 indicated by a two-dot chain line is intended to facilitate the explanation of the scope of the claims and the description, and does not actually exist in a product embodying the present invention. Absent. When the transistor cells 100 are adjacent to each other, the virtual boundary line 50 is a virtual line extending in the vertical direction or the horizontal direction at the same distance from the center of each of the transistor cells 100, and when the diode cells 80 are adjacent to each other. Is a virtual line extending in the vertical or horizontal direction at equal distances from the center of each of the diode cells 80. When the transistor cell 100 and the diode cell 80 are adjacent to each other, the center of the transistor cell 100 and the center of the diode cell 80 are Is a virtual line extending in the vertical direction or the horizontal direction at equal distances. The virtual boundary line 50 is appropriately changed depending on the shapes of the field effect transistor 90 and the Schottky diode 70.

ここで、電界効果トランジスタ90及びショットキーダイオード70の実際の配列として、図10に示すように、各種の配置パターンが想定される。このため、各配置パターンに対応する仮想の境界線50を特定する手法を、図10を参照しながら説明する。なお、以下においては、仮想の境界線50を、横境界ライン50a,50cと、縦境界ライン50b,50dとに分けて説明する。説明を簡略化する目的で、図10では、電界効果トランジスタ90を素子「T」と略記し、ショットキーダイオード70を素子「S」と略記する。また、説明の便宜上、横境界ライン50a,50cの延びる方向を「X方向」、縦境界ライン50b,50dの延びる方向を「Y方向」とする。さらに、X方向に並んだ素子S及び素子Tの配列を行方向配列とし、Y方向に並んだ素子S及び素子Tの配列を列方向配列とする。   Here, as an actual arrangement of the field effect transistor 90 and the Schottky diode 70, various arrangement patterns are assumed as shown in FIG. For this reason, a method of specifying the virtual boundary line 50 corresponding to each arrangement pattern will be described with reference to FIG. In the following description, the virtual boundary line 50 is divided into horizontal boundary lines 50a and 50c and vertical boundary lines 50b and 50d. For the purpose of simplifying the description, in FIG. 10, the field effect transistor 90 is abbreviated as an element “T”, and the Schottky diode 70 is abbreviated as an element “S”. For convenience of explanation, the direction in which the horizontal boundary lines 50a and 50c extend is referred to as “X direction”, and the direction in which the vertical boundary lines 50b and 50d extend is referred to as “Y direction”. Further, the arrangement of the elements S and T arranged in the X direction is a row arrangement, and the arrangement of the elements S and T arranged in the Y direction is a column arrangement.

まず、仮想の境界線50を特定する第1の手法について、図10(a)を参照しながら説明する。   First, a first method for specifying the virtual boundary line 50 will be described with reference to FIG.

図10(a)は、3行及び3列のマトリクス状に配置された素子T及び素子Sを例示する。素子Tは、素子Sが配置された領域を囲むようにして配置されている。図10(a)においては、素子T及び素子Sが正方形状に形成された例が示されている。このように、ショットキー電極9aの形状については、説明を容易にするため、正方形状に簡略化して記載している。   FIG. 10A illustrates elements T and S arranged in a matrix of 3 rows and 3 columns. The element T is disposed so as to surround a region where the element S is disposed. FIG. 10A shows an example in which the element T and the element S are formed in a square shape. As described above, the shape of the Schottky electrode 9a is simplified in a square shape for easy explanation.

しかし、このような素子T及び素子Sの形状や配列は、あくまで、仮想の境界線50の特定の手法を説明するためのものである。したがって、例えば、素子T及び素子Sの具体的な形状は、必ずしも正方形である必要はなく、その中心が適切に定まれば、円形、三角形、又は五角形以上の多角形であってもよい。   However, such shapes and arrangements of the elements T and S are merely for explaining a specific method of the virtual boundary line 50. Therefore, for example, the specific shapes of the element T and the element S are not necessarily square, and may be a circle, a triangle, or a pentagon or more polygon as long as the center is appropriately determined.

ただし、素子Tを正方形状にし、素子Sを三角形状にする場合のように、素子Tと素子Sとの形状が大幅に異なる場合には、半導体素子20全体の面積に対するトランジスタセル100又はダイオードセル80の面積割合を求める際に、適宜の補正係数に基づく修正が必要な場合がある。   However, when the shapes of the element T and the element S are significantly different, as in the case where the element T is square and the element S is triangular, the transistor cell 100 or the diode cell with respect to the total area of the semiconductor element 20 When the area ratio of 80 is obtained, correction based on an appropriate correction coefficient may be necessary.

図10(a)に示すように、3行及び3列からなる各部位に存在する素子T及び素子Sは正方形状であることから、これらの素子の中心Pij(i=1〜3,j=1〜3)は、正方形の対角線の交点として一意に定まる。 As shown in FIG. 10 (a), the element T and the element S existing in each part of 3 rows and 3 columns are square, and therefore, the centers P ij (i = 1 to 3, j) of these elements. = 1 to 3) is uniquely determined as an intersection of square diagonal lines.

ここで、横境界ライン50aは、互いに列方向に隣接する一対の素子Tの各々の中心(P11とP21)から等距離に、かつ、互いに列方向に隣接する素子T及び素子Sの各々の中心(例えば、P12とP22)から等距離になるようにして形成されている。また、横境界ライン50cは、互いに列方向に隣接する一対の素子Tの各々の中心(P21とP31)から等距離に、かつ、互いに列方向に隣接する一対の素子Sの各々の中心(例えば、P22とP32)から等距離になるようにして形成されている。 Here, the horizontal boundary line 50a from each of the centers of the pair of elements T adjacent to each other in the column direction (P 11 and P 21) equidistant from each other, and each of the elements T and the element S are adjacent to each other in the column direction Are formed so as to be equidistant from the center (for example, P 12 and P 22 ). The horizontal boundary line 50c, from the respective centers of the pair of elements T adjacent to each other in the column direction (P 21 and P 31) equidistant from each other, and the center of each of the pair of elements S adjacent to each other in the column direction It is formed so as to be equidistant from (for example, P 22 and P 32 ).

縦境界ライン50bは、互いに行方向に隣接する一対の素子Tの各々の中心(P11とP12)から等距離に、かつ、互いに行方向に隣接する素子T及び素子Sの各々の中心(例えば、P21とP22)から等距離になるようにして形成されている。また、縦境界ライン50dは、互いに行方向に隣接する一対の素子Tの各々の中心(P12とP13)から等距離に、かつ、互いに行方向に隣接する一対の素子Sの各々の中心(例えば、P22とP23)から等距離になるようにして形成されている。 Vertical boundary line 50b is equidistant from each of the centers of the pair of elements T (P 11 and P 12) adjacent to each other in the row direction, and, in each of the elements T and the element S adjacent to each other in the row direction center ( For example, it is formed so as to be equidistant from P 21 and P 22 ). The vertical border line 50d is equidistant from each of the centers of the pair of elements T (P 12 and P 13) adjacent to each other in the row direction, and the center of each of the pair of elements S adjacent to each other in the row direction It is formed so as to be equidistant from (for example, P 22 and P 23 ).

次に、仮想の境界線50を特定する第2の手法について、図10(b)を参照しながら説明する。   Next, a second method for specifying the virtual boundary line 50 will be described with reference to FIG.

図10(b)は、正方形の素子T及び正方形の素子Sが千鳥状(ジグザグアライメント)に配置されたものを例示する。素子Tは、素子Sが配置された領域を囲むようにして形成されている。2行目の配列を構成する素子T及び素子Sは、1行目及び3行目の配列を構成する素子T及び素子Sに対し、1行目及び3行目の配列を構成する素子T及び素子Sのピッチの半分だけX方向にずれている。したがって、素子T及び素子Sの配置パターンは、3行及び6列になる。これにより、3行及び6列からなる各部位のうちの一部(例えば、2行×3列の部位)には、素子T及び素子Sが配置されていない。   FIG. 10B illustrates an example in which square elements T and square elements S are arranged in a zigzag pattern (zigzag alignment). The element T is formed so as to surround a region where the element S is disposed. The elements T and S constituting the second row array are the elements T and S constituting the first row and the third row, and the elements T and S constituting the first row and the third row. It is displaced in the X direction by half the pitch of the element S. Therefore, the arrangement pattern of the elements T and S is 3 rows and 6 columns. Thereby, the element T and the element S are not arranged in a part (for example, a part of 2 rows × 3 columns) of each part composed of 3 rows and 6 columns.

3行及び6列からなる各部位の適所に存在する素子T及び素子Sは正方形であることから、素子T及び素子Sの中心Pij(i=1〜3,j=1〜6、ただし、P12,P14,P16,P21,P23,P25,P32,P34,P36は除く)は、この正方形の対角線の交点として一意に定まる。 Since the element T and the element S present at appropriate positions in each part of 3 rows and 6 columns are square, the centers P ij (i = 1 to 3, j = 1 to 6 of the elements T and S, where P 12 , P 14 , P 16 , P 21 , P 23 , P 25 , P 32 , P 34 , and P 36 are uniquely determined as the intersections of the diagonal lines of this square.

横境界ライン50a(図10(b)では、細い二点鎖線で図示)は、互いに斜め方向に隣接する1行目×1列目の素子Tの中心P11及び2行目×2列目の素子Tの中心P22を結ぶジグザグライン51上の中点(図10(b)に示す黒丸:以下同じ)と、互いに斜め方向に隣接する2行目×2列目の素子Tの中心P22及び1行目×3列目の素子Tの中心P13を結ぶジグザグライン51上の中点と、互いに斜め方向に隣接する1行目×3列目の素子Tの中心P13及び2行目×4列目の素子Sの中心P24を結ぶジグザグライン51上の中点と、互いに斜め方向に隣接する2行目×4列目の素子Sの中心P24及び1行目×5列目の素子Tの中心P15を結ぶジグザグライン51上の中点と、互いに斜め方向に隣接する1行目×5列目の素子Tの中心P15及び2行目×6列目の素子Sの中心P26を結ぶジグザグライン51上の中点と、を通るようにしてX方向に延びる仮想線である。 (In FIG. 10 (b), in the illustrated thin two-dot chain line) next to the boundary line 50a is the first row × 1 column of elements T adjacent each other in the diagonal direction center P 11 and second row × 2 column of midpoint on the zigzag line 51 connecting the centers P 22 of element T (black circles shown in FIG. 10 (b): hereinafter the same) center P 22 of the second row × 2 column of elements T adjacent each other in the diagonal direction and the first line and the midpoint on the zigzag line 51 connecting the centers P 13 of × 3 column of elements T, the center P 13 and the second row of the first row × 3 column of elements T adjacent each other in the diagonal direction the midpoint on the zigzag line 51 connecting the centers P 24 of × 4 column of elements S, the center P 24 and 1 row × 5 column of the second row × 4 column of elements S adjacent each other in the diagonal direction midpoint and the first line × 5 column of diagonally adjacent to each other on the zigzag line 51 connecting the centers P 15 of element T of the Is a virtual line extending in the X direction so as to pass through the midpoint on the zigzag line 51 connecting the centers P 26 of the center P 15 and second row × 6 column of elements S child T, the.

縦境界ライン50b(図10(b)では、太い二点鎖線で図示)は、互いに行方向に隣接する一対の素子Tの各々の中心(P11とP13)から等距離になるようにY方向に延びるY部分仮想線50Yと、互いに行方向に隣接する素子Tの中心P22と素子Sの中心P24とからから等距離になるようにY方向に延びるY部分仮想線50Yと、互いに行方向に隣接する素子Tの中心P31と素子Sの中心P33とから等距離になるようにY方向に延びるY部分仮想線50Yと、これらの3つのY部分仮想線50Yの端同士をつないでX方向に延びる2つのX部分仮想線50Xとからなる仮想線である。 (In FIG. 10 (b), shown by a thick chain double-dashed line) vertical boundary line 50b, as will become equidistant from the center of each of the pair of elements T adjacent to each other in the row direction (P 11 and P 13) Y Y partial virtual line 50Y extending in the direction, Y partial virtual line 50Y extending in the Y direction so as to be equidistant from the center P 22 of element T and the center P 24 of element S adjacent to each other in the row direction, and Y portion virtual line 50Y extending in the Y direction so as to be equidistant from the center P 33 Metropolitan center P 31 and the element S of the element T that is adjacent to the row direction, the ends together of these three Y portion virtual line 50Y The virtual line is composed of two X partial virtual lines 50X extending in the X direction.

次に、仮想の境界線50を特定する第3の手法について、図10(c)を参照しながら説明する。   Next, a third method for specifying the virtual boundary line 50 will be described with reference to FIG.

図10(c)は、X方向に3個配置された長方形の素子Tと、このうちの一対の素子T間(3列目)に配置された1個の長方形の素子Sと、を例示する。素子T及び素子Sは、Y方向に切れ目なく連なるストライプ状に形成されている。   FIG. 10C illustrates three rectangular elements T arranged in the X direction and one rectangular element S arranged between the pair of elements T (third row). . The elements T and S are formed in stripes that are continuous in the Y direction.

素子T及び素子Sは長方形であることから、これらの素子の中心Pij(i=1,j=1〜4)は、当該長方形の対角線の交点として一意に定まる。 Since the element T and the element S are rectangular, the center P ij (i = 1, j = 1 to 4) of these elements is uniquely determined as an intersection of the diagonal lines of the rectangle.

縦境界ライン50bは、互いに行方向に隣接する素子Tの各々の中心P11,P12から等距離になるようにY方向に延びる仮想線である。また、縦境界ライン50dは、互いに行方向に隣接する素子Tの中心P12と素子Sの中心P13とから等距離になるようにY方向に延びる仮想線である。 The vertical boundary line 50b is a virtual line extending in the Y direction so as to be equidistant from the centers P 11 and P 12 of the elements T adjacent to each other in the row direction. The vertical border line 50d is a virtual line extending in the Y direction so as to be equidistant from the center P 13 Metropolitan center P 12 and the element S element T adjacent to each other in the row direction.

図10(c)では、互いに列方向に隣接する素子T及び素子Sは存在しない。このため、横境界ライン50aとして、行方向に隣接して並んだ4個の各素子の中心からY方向に等距離になるような一対の仮想線が選ばれる。ここでは、この仮想線の例として、素子T及び素子Sの両端面を通る一対の横境界ライン50aが示されている。   In FIG. 10C, the element T and the element S adjacent to each other in the column direction do not exist. For this reason, a pair of virtual lines that are equidistant in the Y direction from the centers of the four elements arranged adjacent to each other in the row direction are selected as the horizontal boundary lines 50a. Here, as an example of this imaginary line, a pair of horizontal boundary lines 50a passing through both end faces of the element T and the element S are shown.

次に、仮想の境界線50を特定する第4の手法について、図10(d)を参照しながら説明する。   Next, a fourth method for specifying the virtual boundary line 50 will be described with reference to FIG.

図10(d)は、マトリクス状に配置された正方形の素子Tと、この素子Tが配置された領域に囲まれた素子Sと、を例示する。1つの素子Sが、4つのセル200からなる略正方形に形成されている。図10(d)に示した素子T及び素子Sの配置パターンは、素子Sが複数のセル200に延在するようにして横境界ライン50c及び縦境界ライン50dと交差して形成されている点を除き、図10(a)に示した素子T及び素子Sの配置と同様である。したがって、ここでは、素子Sと交差する横境界ラインc及び縦境界ライン50d以外の仮想の境界線50の説明を省略する。   FIG. 10D illustrates a square element T arranged in a matrix and an element S surrounded by a region where the element T is arranged. One element S is formed in a substantially square shape composed of four cells 200. The arrangement pattern of the element T and the element S shown in FIG. 10D is formed so as to intersect the horizontal boundary line 50c and the vertical boundary line 50d so that the element S extends to the plurality of cells 200. Except for, the arrangement of the elements T and S shown in FIG. Therefore, the description of the virtual boundary line 50 other than the horizontal boundary line c and the vertical boundary line 50d intersecting the element S is omitted here.

図10(d)に示すように、素子Sと交差する横境界ライン50cは、互いに列方向に隣接する素子Tの各々の中心(P21,P31)から等距離になるようにして行方向に延びる仮想線の延長線である。また、素子Sと交差する縦境界ライン50dは、互いに行方向に隣接する素子Tの各々の中心(P12,P13)から等距離になるようにして列方向に延びる仮想線の延長線である。 As shown in FIG. 10 (d), the horizontal boundary line 50c intersecting with the element S is equidistant from the centers (P 21 , P 31 ) of the elements T adjacent to each other in the column direction. It is an extension line of an imaginary line extending to The vertical boundary line 50d intersecting with the element S is an extension line of a virtual line extending in the column direction so as to be equidistant from the centers (P 12 , P 13 ) of the elements T adjacent to each other in the row direction. is there.

次に、プレーナ型を採用した半導体素子20の構造を詳しく説明する。   Next, the structure of the semiconductor element 20 adopting the planar type will be described in detail.

図4に示すように、半導体素子20は半導体基板2を有している。この半導体基板2はSiCで構成され、n型(高不純物濃度のn型)にドープされている。半導体基板2の下面には全面に渡ってドレイン電極(第2のソース/ドレイン電極)1が形成されている。ドレイン電極1は、導電性の材料、例えば、Ni、Al、Ti、Moなどの金属で構成されている。また、半導体基板2の上面には全面に渡って半導体層3が形成されている。半導体基板2及び半導体層3は、このように、炭化珪素(SiC)で構成されているが、他のワイドバンドギャップ半導体で構成されてもよい。具体的には、GaNやAlNなどのIII族窒化物、ダイヤモンドなどを用いることができる。ここで、ワイドバンドギャップ半導体とは、伝導帯の下端と荷電子帯の上端とのエネルギー差であるエネルギーバンドギャップが2.0eV以上である半導体をいう。この半導体層3と半導体基板2とが半導体素子20の半導体を構成し、この半導体が上述の複数のセル200に分割されている。 As shown in FIG. 4, the semiconductor element 20 has a semiconductor substrate 2. The semiconductor substrate 2 is made of SiC and is doped n + type (high impurity concentration n-type). A drain electrode (second source / drain electrode) 1 is formed on the entire lower surface of the semiconductor substrate 2. The drain electrode 1 is made of a conductive material, for example, a metal such as Ni, Al, Ti, or Mo. A semiconductor layer 3 is formed over the entire top surface of the semiconductor substrate 2. The semiconductor substrate 2 and the semiconductor layer 3 are thus made of silicon carbide (SiC), but may be made of other wide band gap semiconductors. Specifically, a group III nitride such as GaN or AlN, diamond, or the like can be used. Here, the wide band gap semiconductor refers to a semiconductor having an energy band gap of 2.0 eV or more, which is an energy difference between the lower end of the conduction band and the upper end of the valence band. The semiconductor layer 3 and the semiconductor substrate 2 constitute a semiconductor of the semiconductor element 20, and the semiconductor is divided into the plurality of cells 200 described above.

半導体層3のトランジスタセル100には、その上面を含むようにn型のソース領域(第1のソース/ドレイン領域)5が形成されている。ソース領域5は、平面視において矩形の環状に形成され、かつ、その中心がトランジスタセル100の中心と略一致するように形成されている。そして、半導体層3に、その上面を含みかつソース領域5を含むようにp型半導体領域(第2導電型領域)4が形成されている。具体的には、p型半導体領域4は、半導体層3に、その上面の、ソース領域5の内側部分とソース領域5を囲む矩形の環状部分とを含み、かつソース領域5の下端より深い位置に渡るように形成されている。そして、半導体層3のソース領域5及びp型半導体領域4以外の領域がn型(低不純物濃度のn型)のドリフト領域3aで構成されている。従って、ドレイン電極1はn型の半導体基板2を介してドリフト領域3aにオーミックに接続されている。そして、トランジスタセル100において、半導体層3の上面のソース領域5の中程からトランジスタセル100の外周に渡る部分を覆うようにゲート絶縁膜7が形成されている。換言すれば、ゲート絶縁膜7は、ソース領域5の外周部と、p型半導体領域4のソース領域5とドリフト領域3aとの間の部分(以下、p型半導体領域外周部という。)4aと、ドリフト領域3aのp型半導体領域外周部4aの近傍に位置する部分との上に形成されている。ゲート絶縁膜7は、酸化膜(SiO)で構成される。そして、ゲート絶縁膜7に丁度重なるように該ゲート絶縁膜7の上にゲート電極8が形成されている。従って、p型半導体領域外周部4aがチャネル領域を形成している。ゲート電極8は、導電性の材料、例えば、Ni、Ti、Al、Moなどの金属、ポリシリコンなどで構成されている。そして、トランジスタセル100において、半導体層3の上面のソース領域5の中程から内側に位置する部分の上にソース電極(第1のソース/ドレイン電極)6が形成されている。換言すれば、ソース電極6は、ソース領域5の内周部とp型半導体領域4のソース領域5の内側に位置する部分(以下、p型半導体領域中央部という。)4bの上に形成されている。ソース電極6はn型のソース領域5及びp型半導体領域4を介して半導体層3にオーミックに接続されている。ソース電極6は、導電性の材料、例えば、Ni、Ti、Al、Moなどの金属で構成されている。 In the transistor cell 100 of the semiconductor layer 3, an n + -type source region (first source / drain region) 5 is formed so as to include the upper surface thereof. The source region 5 is formed in a rectangular ring shape in plan view, and is formed so that the center thereof substantially coincides with the center of the transistor cell 100. A p-type semiconductor region (second conductivity type region) 4 is formed in the semiconductor layer 3 so as to include the upper surface and the source region 5. Specifically, the p-type semiconductor region 4 includes, on the semiconductor layer 3, a position on the upper surface of the semiconductor layer 3 that is deeper than the lower end of the source region 5 and includes an inner portion of the source region 5 and a rectangular annular portion surrounding the source region 5. It is formed to cross over. A region other than the source region 5 and the p-type semiconductor region 4 of the semiconductor layer 3 is formed of an n -type (low impurity concentration n-type) drift region 3a. Accordingly, the drain electrode 1 is ohmically connected to the drift region 3 a via the n + type semiconductor substrate 2. In the transistor cell 100, the gate insulating film 7 is formed so as to cover a portion extending from the middle of the source region 5 on the upper surface of the semiconductor layer 3 to the outer periphery of the transistor cell 100. In other words, the gate insulating film 7 includes an outer peripheral portion of the source region 5 and a portion between the source region 5 and the drift region 3a of the p-type semiconductor region 4 (hereinafter referred to as a p-type semiconductor region outer peripheral portion) 4a. The drift region 3a is formed on a portion located in the vicinity of the p-type semiconductor region outer peripheral portion 4a. The gate insulating film 7 is composed of an oxide film (SiO 2 ). A gate electrode 8 is formed on the gate insulating film 7 so as to overlap the gate insulating film 7. Therefore, the p-type semiconductor region outer peripheral portion 4a forms a channel region. The gate electrode 8 is made of a conductive material, for example, a metal such as Ni, Ti, Al, or Mo, polysilicon, or the like. In the transistor cell 100, a source electrode (first source / drain electrode) 6 is formed on a portion of the upper surface of the semiconductor layer 3 located in the middle to the inside of the source region 5. In other words, the source electrode 6 is formed on the inner peripheral portion of the source region 5 and a portion (hereinafter referred to as a p-type semiconductor region central portion) 4b located inside the source region 5 of the p-type semiconductor region 4. ing. The source electrode 6 is ohmically connected to the semiconductor layer 3 through the n + -type source region 5 and the p-type semiconductor region 4. The source electrode 6 is made of a conductive material, for example, a metal such as Ni, Ti, Al, or Mo.

一方、半導体層3のダイオードセル80においては、ダイオードセル80の外周との間に若干の隙間を有するようにして、その上面の略全面に渡ってショットキー電極9aが形成されている。ダイオードセル80においては、半導体層3の全領域がn型のドリフト領域3aで構成されているので、ショットキー電極9aは半導体層3とショットキー接合している。ショットキー電極9aは、電界の集中による破壊を防止するため、図2及び図3に示すように、角部を丸みが帯びた形状にすることが好ましい。ショットキー電極9aは、導電性の材料、例えば、Ni、Ti、Al、Moなどの金属で構成されている。 On the other hand, in the diode cell 80 of the semiconductor layer 3, the Schottky electrode 9 a is formed over substantially the entire upper surface of the diode cell 80 so as to have a slight gap with the outer periphery of the diode cell 80. In the diode cell 80, since the entire region of the semiconductor layer 3 is composed of the n type drift region 3 a, the Schottky electrode 9 a is in Schottky junction with the semiconductor layer 3. The Schottky electrode 9a preferably has a rounded corner as shown in FIGS. 2 and 3 in order to prevent breakdown due to electric field concentration. The Schottky electrode 9a is made of a conductive material, for example, a metal such as Ni, Ti, Al, or Mo.

ここで、ショットキー電極9aの面積は、p型半導体領域4の平面視における面積より大きいことが好ましい。これは、ショットキー電極9aとドリフト領域3aとの間のショットキー障壁はp型半導体領域4とドリフト領域3aとの間のp/n接合の障壁より小さいことから、半導体素子20にサージ電圧が印加された場合に、ショットキー電極9aによってそのサージ電圧が緩和されるので、そのような構成とすると、この効果がより大きくなるからである。   Here, the area of the Schottky electrode 9a is preferably larger than the area of the p-type semiconductor region 4 in plan view. This is because the Schottky barrier between the Schottky electrode 9a and the drift region 3a is smaller than the barrier of the p / n junction between the p-type semiconductor region 4 and the drift region 3a. This is because, when applied, the surge voltage is relaxed by the Schottky electrode 9a, and this effect becomes even greater with such a configuration.

以上の構成により、トランジスタセル100には1つのnチャネル型の縦型電界効果トランジスタ90が形成され、ダイオードセル80には1つのショットキーダイオード70が形成されている。また、ドリフト領域3a、半導体基板2、及びドレイン電極1は全てのセル200に渡るように設けられている。また、ゲート絶縁層7及びゲート電極8は隣接するトランジスタセル100の間では連続するように形成されており、かつ多数のトランジスタセル100の間に島状にダイオードセル80が形成されているので、半導体層3の全体の表面に格子状のゲート絶縁層7及びゲート電極8がそれぞれ1つ存在し、その格子状のゲート絶縁層7の開口内にソース電極6又はショットキー電極9aが存在している。   With the above configuration, one n-channel vertical field effect transistor 90 is formed in the transistor cell 100, and one Schottky diode 70 is formed in the diode cell 80. Further, the drift region 3 a, the semiconductor substrate 2, and the drain electrode 1 are provided so as to extend over all the cells 200. In addition, the gate insulating layer 7 and the gate electrode 8 are formed so as to be continuous between adjacent transistor cells 100, and the diode cells 80 are formed in an island shape between the many transistor cells 100. One lattice-like gate insulating layer 7 and one gate electrode 8 are present on the entire surface of the semiconductor layer 3, and the source electrode 6 or the Schottky electrode 9 a is present in the opening of the lattice-like gate insulating layer 7. Yes.

図1及び図2に示すように、半導体層3の上面には、さらにガードリング11が形成されている。ガードリング11は、トランジスタ形成領域10を半導体層3の端(チップの端)14との間に、平面視において矩形の環状に2重に形成されている。ここで、ガードリング11は、平面視において矩形の環状に形成されることに限定されず、セル形成領域201の外周を囲んでいればよい。また、ガードリング11は、2重に形成されることに限定されず、1重、3重など、何重に形成されていてもよい。ガードリング11は、ドリフト領域3aと反対の導電型のp型半導体領域で構成されている。   As shown in FIGS. 1 and 2, a guard ring 11 is further formed on the upper surface of the semiconductor layer 3. The guard ring 11 is formed in a rectangular ring shape in a plan view in a double manner between the transistor formation region 10 and the end (chip end) 14 of the semiconductor layer 3. Here, the guard ring 11 is not limited to being formed in a rectangular ring shape in a plan view, and may only surround the outer periphery of the cell formation region 201. Moreover, the guard ring 11 is not limited to being formed in double, and may be formed in multiple, such as single or triple. The guard ring 11 is composed of a p-type semiconductor region having a conductivity type opposite to that of the drift region 3a.

そして、ソース電極6、ゲート電極8、及びショットキー電極9aが形成された半導体層3の表面を覆うように、層間絶縁膜40が設けられている。この層間絶縁膜40の上面には、ダイオード形成領域9の上方に位置するように、ソース・ショットキー用パッド12Sが配設されている。ソース・ショットキー用パッド12Sは、Alなどの金属により構成される。ソース・ショットキー用パッド12Sは、ここでは、辺の長さが0.6mm以上の正方形の形状を有している。なお、ソース・ショットキー用パッド12Sの形状は、正方形に限定されない。ソース・ショットキー用パッド12Sは、平面視におけるトランジスタ形成領域10に、縦3×横3の合計9個配設されている。ソース・ショットキー用パッド12Sは、ソース電極6及びショットキー電極9aに電気的に接続されている。また、平面視におけるトランジスタ形成領域10の外周の端部には、ゲート電極8に電気的に接続されたゲート用パッド12Gが1個配設されている。層間絶縁膜40には、これを貫通してゲート電極8、ソース電極6、及びショットキー電極9aにそれぞれ接続するように複数の導電体からなるプラグ(図示せず)が設けられている。また、層間絶縁膜40の上面には、各プラグとその対応するボンディングパッドとを接続する配線(図示せず)が配設されている。従って、ソース・ショットキー用パッド12Sとソース電極6とはその対応するプラグ及び配線(ソース配線)により接続され、ソース・ショットキー用パッド12Sとショットキー電極9aとはその対応するプラグ及び配線(ショットキー配線)により接続され、ゲート用パッド12Gとゲート電極8とはその対応するプラグ及び配線(ゲート配線)により接続されている。本実施形態の半導体素子20では、ソース・ショットキー用パッド12Sが9個配設されているが、ソース・ショットキー用パッド12Sの個数はこれに限定されない。ソース・ショットキー用パッド12Sの全体には、電界効果トランジスタ90がトランジスタセル100の数だけ並列に接続され、ショットキー電極9aがダイオードセル80の数だけ並列に接続されている。また、本実施形態の半導体素子20では、ゲート用パッド12Gが1個配設されているが、ゲート用パッド12Gの個数はこれに限定されない。すなわち、複数個のゲート用パッド12Gを配設することもできる。この場合においては、上記ソース・ショットキー用パッド12Sの場合と同様に、複数個のゲート用パッド12Gを架橋するようにワイヤ13Gで接続してもよい。   An interlayer insulating film 40 is provided so as to cover the surface of the semiconductor layer 3 on which the source electrode 6, the gate electrode 8, and the Schottky electrode 9a are formed. On the upper surface of the interlayer insulating film 40, a source / Schottky pad 12S is disposed so as to be positioned above the diode formation region 9. The source / Schottky pad 12S is made of a metal such as Al. Here, the source / schottky pad 12S has a square shape with a side length of 0.6 mm or more. The shape of the source / Schottky pad 12S is not limited to a square. A total of nine source / Schottky pads 12S, 3 × 3 in the vertical direction, are arranged in the transistor formation region 10 in plan view. The source / Schottky pad 12S is electrically connected to the source electrode 6 and the Schottky electrode 9a. Further, one gate pad 12G electrically connected to the gate electrode 8 is disposed at the outer peripheral end of the transistor formation region 10 in plan view. The interlayer insulating film 40 is provided with plugs (not shown) made of a plurality of conductors so as to penetrate through the interlayer insulating film 40 and connect to the gate electrode 8, the source electrode 6, and the Schottky electrode 9a. In addition, on the upper surface of the interlayer insulating film 40, wirings (not shown) for connecting each plug and its corresponding bonding pad are disposed. Accordingly, the source / Schottky pad 12S and the source electrode 6 are connected by the corresponding plug and wiring (source wiring), and the source / Schottky pad 12S and the Schottky electrode 9a are connected by the corresponding plug and wiring (source wiring). The gate pad 12G and the gate electrode 8 are connected by a corresponding plug and wiring (gate wiring). In the semiconductor element 20 of the present embodiment, nine source / Schottky pads 12S are provided, but the number of source / Schottky pads 12S is not limited to this. Field effect transistors 90 are connected in parallel by the number of transistor cells 100 and Schottky electrodes 9a are connected in parallel by the number of diode cells 80 over the entire source / Schottky pad 12S. In the semiconductor device 20 of the present embodiment, one gate pad 12G is provided, but the number of gate pads 12G is not limited to this. That is, a plurality of gate pads 12G can be provided. In this case, as in the case of the source / Schottky pad 12S, a plurality of gate pads 12G may be connected by wires 13G so as to be bridged.

そして、一方向に並ぶ3個のソース・ショットキー用パッド12Sがワイヤ13Sによって架橋されるように接続されている。ワイヤ13Sは、AlやAuなどの金属により構成される。ソース・ショットキー用パッド12Sとワイヤ13Sとは、超音波を印加しながらワイヤ13Sをソース・ショットキー用パッド12Sに押し付けることによって接続されている。本実施形態の半導体素子20では、ワイヤ13Sとして0.3mm径のものを用いたが、大電流に耐えられるようにするため、それ以上の径のものを用いることが好ましい。本実施形態の半導体素子20では三本のワイヤ13Sを用いたが、ワイヤ13Sの本数はこれに限定されない。   Three source / Schottky pads 12S arranged in one direction are connected so as to be bridged by wires 13S. The wire 13S is made of a metal such as Al or Au. The source Schottky pad 12S and the wire 13S are connected by pressing the wire 13S against the source Schottky pad 12S while applying ultrasonic waves. In the semiconductor element 20 of the present embodiment, a wire having a diameter of 0.3 mm is used as the wire 13S. However, it is preferable to use a wire having a diameter larger than that in order to withstand a large current. In the semiconductor element 20 of the present embodiment, the three wires 13S are used, but the number of the wires 13S is not limited to this.

また、ソース・ショットキー用パッド12Sの一辺の長さは、ボンディングをするためには、ワイヤ13Sの径以上にすることが好ましい。本実施形態ではワイヤ13Sとして0.3mm径のものを用いたので、ソース・ショットキー用パッド12Sの一辺の長さを0.3mm以上にすればよい。ここで、ボンディングを容易にするためには、本実施形態のようにソース・ショットキー用パッド12Sの一辺の長さを0.6mm以上にすることが好ましい。なお、さらにボンディングを容易にするためには、ソース・ショットキー用パッド12Sの一辺の長さを0.9mm以上にすることがより好ましい。   The length of one side of the source / Schottky pad 12S is preferably equal to or larger than the diameter of the wire 13S for bonding. In this embodiment, since the wire 13S having a diameter of 0.3 mm is used, the length of one side of the source / Schottky pad 12S may be 0.3 mm or more. Here, in order to facilitate bonding, the length of one side of the source / Schottky pad 12S is preferably 0.6 mm or more as in the present embodiment. In order to further facilitate the bonding, the length of one side of the source / Schottky pad 12S is more preferably 0.9 mm or more.

一方、ゲート用パッド12Gは、ワイヤ13Gにより接続されている。ここで、ワイヤ13Gは、AlやAuなどの金属により構成される。ゲート用パッド12Gとワイヤ13Gとは、超音波を印加しながらワイヤ13Gをゲート用パッド12Gに押し付けることによって接続されている。本実施形態の半導体素子20では、ソース・ショットキー用パッド12Sを接続するワイヤ13Sとして0.3mm径のものを用いたが、ゲート電極8にはそれほど大きな電流を流さないため、ゲート用パッド12Gを接続するワイヤ13Gとしては、より細い径のものを用いることが好ましい。   On the other hand, the gate pad 12G is connected by a wire 13G. Here, the wire 13G is made of a metal such as Al or Au. The gate pad 12G and the wire 13G are connected by pressing the wire 13G against the gate pad 12G while applying ultrasonic waves. In the semiconductor element 20 of the present embodiment, a wire 13S having a diameter of 0.3 mm is used as the wire 13S for connecting the source / Schottky pad 12S. However, since a large current does not flow through the gate electrode 8, the gate pad 12G It is preferable to use a wire having a smaller diameter as the wire 13G for connecting the wires.

次に、以上のように構成された半導体素子20の製造方法を、図1乃至図4を参照して説明する。なお、製造法自体は周知のプロセスで構成されるので、簡単に説明する。   Next, a method for manufacturing the semiconductor element 20 configured as described above will be described with reference to FIGS. The manufacturing method itself is a well-known process and will be described briefly.

但し、ここでは各製造工程途中の図示を省く。このため、本製造方法の説明に際しては、製造工程途中の各構成部分の参照符号の説明を便宜上、図1乃至図4に示した完成品の符号により代用する。   However, illustration in the middle of each manufacturing process is omitted here. For this reason, in the description of the present manufacturing method, the reference numerals of the components in the course of the manufacturing process are substituted with the reference numerals of the finished products shown in FIGS.

まず、窒素濃度が3×1018cm−3となるように窒素がドープされたn型の4H−SiC(0001)Si面の[11−20]方向8度オフカット面を有する半導体基板2が用意される。 First, the semiconductor substrate 2 having an [11-20] direction 8 degree off-cut surface of an n + type 4H—SiC (0001) Si surface doped with nitrogen so that the nitrogen concentration becomes 3 × 10 18 cm −3. Is prepared.

次いで、この半導体基板2が洗浄された後に、上記オフカット面に、1.3×1016cm−3濃度に調整された窒素ドープのn型のエピタキシャル成長層としてのSiC層(半導体層)3が、CVD法により厚み10μmに調整して成膜される。 Next, after the semiconductor substrate 2 is cleaned, a SiC layer (semiconductor layer) 3 as a nitrogen-doped n type epitaxial growth layer adjusted to a concentration of 1.3 × 10 16 cm −3 on the off-cut surface. However, the film is formed by adjusting the thickness to 10 μm by the CVD method.

そして、SiC層3の表面の適所を開口するマスク(図示せず)を配置して、SiC層3の表面に向けて30〜700keVの範囲の内の多段のイオンエネルギーを適宜選択して、2×1014cm−2濃度のドーズ量でアルミニウムイオンが、開口を介して注入される。このイオン注入より、SiC層3の表層に、深さ0.8μm程度のp型半導体領域4が島状に形成される。また、ガードリング11も同時に形成される。 Then, a mask (not shown) that opens an appropriate position on the surface of the SiC layer 3 is arranged, and multistage ion energy within a range of 30 to 700 keV is appropriately selected toward the surface of the SiC layer 3, and 2 Aluminum ions are implanted through the opening at a dose of × 10 14 cm -2 concentration. By this ion implantation, a p-type semiconductor region 4 having a depth of about 0.8 μm is formed in an island shape on the surface layer of the SiC layer 3. A guard ring 11 is also formed at the same time.

その後、p型半導体領域4の表面の適所を開口する別のマスク(図示せず)を用いて、p型半導体領域4に対して30〜180keVのエネルギーであって、1.4×1015cm−2濃度のドーズ量で窒素イオンが注入され、n型のソース領域5が形成される。 Then, using another mask (not shown) that opens an appropriate position on the surface of the p-type semiconductor region 4, the energy is 30 to 180 keV with respect to the p-type semiconductor region 4 and is 1.4 × 10 15 cm. Nitrogen ions are implanted at a dose of −2 concentration, and an n + -type source region 5 is formed.

続いて、この半導体基板2は、Ar雰囲気に曝して1700℃の温度に保って熱処理を約1時間に亘って施され、上記イオン注入領域が活性化される。   Subsequently, the semiconductor substrate 2 is exposed to an Ar atmosphere and kept at a temperature of 1700 ° C. and subjected to heat treatment for about 1 hour, and the ion implantation region is activated.

次に、この半導体基板2は、酸化処理炉内において1100℃の温度に保って、3時間に亘ってウェット酸化される。この酸化処理により、SiC層3の表面全域には、厚み40nmのシリコン酸化膜が形成される。   Next, the semiconductor substrate 2 is wet-oxidized for 3 hours while maintaining a temperature of 1100 ° C. in an oxidation treatment furnace. By this oxidation treatment, a silicon oxide film having a thickness of 40 nm is formed on the entire surface of the SiC layer 3.

このシリコン酸化膜に、フォトリソグラフィー技術及びエッチング技術を用いてソース電極用の第1の開口とショットキー電極用の第2の開口とがパターニングして形成される。これにより、このシリコン酸化膜がゲート絶縁膜7となる。   In this silicon oxide film, the first opening for the source electrode and the second opening for the Schottky electrode are formed by patterning using the photolithography technique and the etching technique. As a result, this silicon oxide film becomes the gate insulating film 7.

そして、第1の開口内に露出するSiC層3の表面にNiからなる電極が選択的に形成され、この第1の開口内に形成された電極がソース電極6となる。   An electrode made of Ni is selectively formed on the surface of the SiC layer 3 exposed in the first opening, and the electrode formed in the first opening becomes the source electrode 6.

次いで、半導体基板2の裏面に、Niからなるドレイン電極1が設けられる。   Next, a drain electrode 1 made of Ni is provided on the back surface of the semiconductor substrate 2.

そして、これらのNiの層を堆積した後、適宜の熱処理が施され、上記電極6,1と半導体との間がオーミックに接続される。   Then, after depositing these Ni layers, an appropriate heat treatment is performed to establish ohmic connection between the electrodes 6 and 1 and the semiconductor.

さらに、上記第2の開口内に露出するSiC層3の表面にNiからなる電極が選択的に形成され、この第2の開口内に形成された電極がショットキー電極9aとなる。   Further, an electrode made of Ni is selectively formed on the surface of the SiC layer 3 exposed in the second opening, and the electrode formed in the second opening becomes the Schottky electrode 9a.

その後、ゲート絶縁膜7の表面に、Alからなるゲート電極8が形成される。   Thereafter, a gate electrode 8 made of Al is formed on the surface of the gate insulating film 7.

その後、ソース電極6、ゲート電極8、及びショットキー電極9aの表面に層間絶縁膜40が形成され、この層間絶縁膜40に対して、適宜、プラグ、配線、ボンディングパッド12S、12Gが形成される。   Thereafter, an interlayer insulating film 40 is formed on the surfaces of the source electrode 6, the gate electrode 8, and the Schottky electrode 9a, and plugs, wirings, and bonding pads 12S and 12G are appropriately formed on the interlayer insulating film 40. .

次いで、ボンディングパッド12S、12Gがワイヤ13S、13Gにより適宜接続される。   Next, the bonding pads 12S and 12G are appropriately connected by the wires 13S and 13G.

このようにして、本実施形態の半導体素子20が得られる。   In this way, the semiconductor element 20 of this embodiment is obtained.

次に、半導体素子20における電界効果トランジスタ90をトレンチ型で形成した場合と、プレーナ型で形成した場合との比較について説明する。   Next, a comparison between the case where the field effect transistor 90 in the semiconductor element 20 is formed in a trench type and the case where it is formed in a planar type will be described.

電界効果トランジスタの構造として、半導体層上に平面状にp層とn層とを形成したプレーナ型と、細くて深い溝を作りゲート電極とゲート絶縁膜とを埋め込んだトレンチ型とがある。本実施形態の半導体素子20における電界効果トランジスタ90は、以下に述べるショットキーダイオード70との関連性等の各種の理由を考慮して、プレーナ型を採用している。   As a structure of a field effect transistor, there are a planar type in which a p layer and an n layer are formed in a planar shape on a semiconductor layer, and a trench type in which a thin and deep groove is formed and a gate electrode and a gate insulating film are embedded. The field effect transistor 90 in the semiconductor element 20 of the present embodiment adopts a planar type in consideration of various reasons such as relevance to the Schottky diode 70 described below.

例えば、特表2005−501408号公報(以下、先行例という)では、トレンチタイプのMOSFETに対して、ショットキーダイオードを一体化する構造が開示されている。この先行例においては、トレンチ(掘られた溝または穴)の底面に、半導体と金属とのショットキー接合部分を形成して、ショットキーダイオードを構成する。上記先行例のトレンチ部分は、本来、トランジスタ単位素子部分の間隙を構成する部分であり、トランジスタ単位素子(本実施形態のように、仮想の境界線50に基づいて区画された四角形の複数のセル200)とは異なる。   For example, Japanese translations of PCT publication No. 2005-501408 (hereinafter referred to as the preceding example) discloses a structure in which a Schottky diode is integrated with a trench type MOSFET. In this prior example, a Schottky junction portion between a semiconductor and a metal is formed on the bottom surface of a trench (excavated groove or hole) to constitute a Schottky diode. The trench portion of the preceding example is originally a portion that constitutes a gap between the transistor unit element portions, and is a transistor unit element (a plurality of rectangular cells partitioned based on the virtual boundary line 50 as in the present embodiment). 200).

これに対し、本実施形態のショットキーダイオード70が形成された部分は、仮想の境界線50に基づいて区画された四角形の複数のセル200のうちの一部のセル200の略全域を占めている。したがって、本実施形態のショットキーダイオード70が形成された部分は、上記先行例の間隙(のトレンチ部分)にショットキー電極を埋め込む構造とは全く異なる。   On the other hand, the portion where the Schottky diode 70 according to the present embodiment is formed occupies substantially the entire area of a part of the plurality of rectangular cells 200 partitioned based on the virtual boundary line 50. Yes. Therefore, the portion where the Schottky diode 70 of this embodiment is formed is completely different from the structure in which the Schottky electrode is embedded in the gap (trench portion) of the preceding example.

本実施形態の半導体素子20のように、プレーナ型のMOSFET90とショットキーダイオード70との組み合わせは、仮想の境界線50に基づいて区画された四角形の複数のセル200に、MOSFET90を設置するかショットキーダイオード70を設置するかを任意に選択できる構造的な自由度を有し、先行例のようにトレンチ型のMOSFETを採用した場合と比較して優位性がある。この構造的な自由度により、MOSFET90及びショットキーダイオード70が配置された部分の半導体素子20全体に対する面積比を任意に設定できるという本発明の特徴のうちのひとつが、はじめて具体化される。   As in the semiconductor device 20 of the present embodiment, the combination of the planar MOSFET 90 and the Schottky diode 70 can be realized by installing the MOSFET 90 in a plurality of rectangular cells 200 partitioned based on the virtual boundary line 50 or by shot. It has a structural degree of freedom in which it is possible to arbitrarily select whether to install the key diode 70, and is superior to the case where a trench type MOSFET is employed as in the previous example. With this structural freedom, one of the features of the present invention that the area ratio of the portion where the MOSFET 90 and the Schottky diode 70 are disposed to the entire semiconductor element 20 can be arbitrarily set is realized for the first time.

また、先行例においては、トレンチの壁面にゲート絶縁膜を介してゲート電極を形成し、さらに層間絶縁膜で絶縁を確保し、その上にショットキー電極を形成する必要がある。このように、トレンチ壁面に多層の絶縁膜と電極とを形成した場合、多層の絶縁膜の部分によって覆われてしまうトレンチの底面部分には、大面積のショットキー電極が形成できない。よって、トレンチの底面の一部しかショットキーダイオードとして機能しない。このため、ショットキーダイオードの形成面積が小さくなるよう制限される。本実施形態の半導体素子20のように、MOSFET90をプレーナ型にする場合においては、上記の面積的な制限はない。   In the prior example, it is necessary to form a gate electrode on the wall surface of the trench via a gate insulating film, further to ensure insulation with an interlayer insulating film, and to form a Schottky electrode thereon. Thus, when a multilayer insulating film and an electrode are formed on the trench wall surface, a large-area Schottky electrode cannot be formed on the bottom portion of the trench that is covered by the multilayer insulating film portion. Therefore, only a part of the bottom surface of the trench functions as a Schottky diode. For this reason, the formation area of the Schottky diode is limited to be small. In the case where the MOSFET 90 is a planar type like the semiconductor element 20 of the present embodiment, there is no area limitation described above.

さらに、先行例のようにトレンチ底面にショットキー電極を形成すると、裏面のドレイン電極に近い位置にショットキー電極が存在する構造となり、ショットキー電極に電界集中が起こって、耐圧性に不安が残る。一方、プレーナ型のMOSFETを採用する場合には、ショットキー電極9aは、半導体層3の表面に形成されると共に、ショットキー電極9aと隣接するMOSFET90のP型半導体領域4は深く形成されているため、ショットキー電極9aに電界集中が起こらず、耐圧性が確保される。   Further, when the Schottky electrode is formed on the bottom surface of the trench as in the previous example, the Schottky electrode is present at a position close to the drain electrode on the back surface, electric field concentration occurs in the Schottky electrode, and there is anxiety about pressure resistance. . On the other hand, when a planar MOSFET is employed, the Schottky electrode 9a is formed on the surface of the semiconductor layer 3, and the P-type semiconductor region 4 of the MOSFET 90 adjacent to the Schottky electrode 9a is formed deep. Therefore, electric field concentration does not occur in the Schottky electrode 9a, and the pressure resistance is ensured.

以上に述べたとおり、本実施形態の半導体素子20のようにプレーナ型のMOSFET90を採用する場合には、MOSFET90及びショットキーダイオード70の半導体素子20全体に対する面積比が任意に設定可能になる。また、プレーナ型のMOSFET90は、耐圧性も確保でき、形成プロセスも単純であるため、先行例に示されたトレンチ型のMOSFETを採用した場合と比較して効果が大きい。   As described above, when the planar type MOSFET 90 is employed as in the semiconductor element 20 of the present embodiment, the area ratio of the MOSFET 90 and the Schottky diode 70 to the entire semiconductor element 20 can be arbitrarily set. Further, the planar type MOSFET 90 can secure a withstand voltage and has a simple formation process, and therefore has a greater effect than the case where the trench type MOSFET shown in the preceding example is adopted.

なお、上記においては、ショットキー電極9aの材料にニッケル(Ni)を用いた例を説明したが、ショットキー電極9aの材料はこれに限られず、前述のように、チタン(Ti)、アルミニウム(Al)、モリブデン(Mo)などを用いた場合も同様である。   In the above description, the example in which nickel (Ni) is used as the material of the Schottky electrode 9a has been described. However, the material of the Schottky electrode 9a is not limited to this, and as described above, titanium (Ti), aluminum ( The same applies when Al), molybdenum (Mo), or the like is used.

次に、以上のように構成された半導体素子20の作用効果について説明する。   Next, the function and effect of the semiconductor element 20 configured as described above will be described.

本実施形態の半導体素子20は、600Vの耐圧を有するパワーデバイス(3mm角(3mm×3mmの四角形)、定格電流値が20A)として機能する。そして、本実施形態の半導体素子20では、ソース・ショットキー用パッド12Sがショットキー電極9aの上方に位置するように配設されているので、ソース・ショットキー用パッド12Sにワイヤ13Sをボンディングする際に、超音波を印加しながらワイヤ13Sをソース・ショットキー用パッド12Sに押し付けてワイヤボンドしても、ソース・ショットキー用パッド12Sの下方にはショットキー電極9aが配設されたダイオードセル80が配置されているので、トランジスタセル100に形成された電界効果トランジスタ90の破壊やゲート絶縁膜7の耐圧劣化を防止することができる。   The semiconductor element 20 of this embodiment functions as a power device (3 mm square (3 mm × 3 mm square) having a rated current value of 20 A) having a withstand voltage of 600V. In the semiconductor element 20 of the present embodiment, the source / Schottky pad 12S is disposed above the Schottky electrode 9a, and therefore the wire 13S is bonded to the source / Schottky pad 12S. At this time, even if the wire 13S is pressed against the source / Schottky pad 12S while applying an ultrasonic wave and wire-bonded, the diode cell in which the Schottky electrode 9a is disposed below the source / Schottky pad 12S. Since 80 is disposed, it is possible to prevent the field effect transistor 90 formed in the transistor cell 100 from being broken and the breakdown voltage of the gate insulating film 7 from being deteriorated.

また、本実施形態の半導体素子20では、ソース電極6がp型半導体領域中央部4bと接触し、p型半導体領域4の下方のn型のドリフト領域3aがドレイン電極1に半導体基板2を介して接続されているため、ソース電極6とドレイン電極1との間にドリフト領域3aとp型半導体領域4とから構成される寄生ダイオードが存在する。また、本実施形態の半導体素子20では、ソース電極6がドリフト領域3aとショットキー接合を形成するように設けられているため、ソース電極6とドレイン電極1との間にショットキー電極9aとドリフト領域3aとから構成されるショットキーダイオード70が存在する。 Further, in the semiconductor element 20 of the present embodiment, the source electrode 6 is in contact with the central portion 4 b of the p-type semiconductor region, and the n -type drift region 3 a below the p-type semiconductor region 4 is connected to the drain electrode 1 and the semiconductor substrate 2. Therefore, a parasitic diode composed of the drift region 3 a and the p-type semiconductor region 4 exists between the source electrode 6 and the drain electrode 1. Further, in the semiconductor element 20 of the present embodiment, since the source electrode 6 is provided so as to form a Schottky junction with the drift region 3 a, the Schottky electrode 9 a and the drift are formed between the source electrode 6 and the drain electrode 1. There is a Schottky diode 70 composed of the region 3a.

そして、本実施形態の半導体素子20は、使用時においてソース電極6とドレイン電極1との間にソース電極6に対しドレイン電極1の方が高電位となる電圧が印加される。そして、この状態で、ゲート電極8に閾値以上の電圧(ソース電極6に対する電圧)が印加されると、ゲート電極8の下方に位置するp型半導体領域4の上層部にnチャネルが形成される。そして、ソース電極6からソース領域、nチャネル、ドリフト領域3a、及び半導体基板2を経てドレイン電極1へと電子が移動し、それにより、ドレイン電極1からソース電極6へと電流が流れる。   In the semiconductor element 20 of this embodiment, a voltage at which the drain electrode 1 has a higher potential than the source electrode 6 is applied between the source electrode 6 and the drain electrode 1 in use. In this state, when a voltage equal to or higher than the threshold value (voltage with respect to the source electrode 6) is applied to the gate electrode 8, an n channel is formed in the upper layer portion of the p-type semiconductor region 4 located below the gate electrode 8. . Then, electrons move from the source electrode 6 to the drain electrode 1 through the source region, the n-channel, the drift region 3 a, and the semiconductor substrate 2, whereby a current flows from the drain electrode 1 to the source electrode 6.

一方、負荷が誘導性である場合には、負荷のインダクタンスにより、電界効果トランジスタ90をオンからオフへとスイッチングした場合に、ソース電極6とドレイン電極1との間にドレイン電極1に対しソース電極6の方が高電位となる電圧が一時的に印加される。それにより、ダイオードセル80におけるショットキーダイオード70がオンし、ソース電極6からドレイン電極1へと電流が流れる。また、ソース電極6における正の電圧がさらに上がると、電界効果トランジスタ90の寄生ダイオードがオンし、ドリフト領域3aに少数キャリア(正孔)が注入される。しかし、ショットキー電極9aの面積を十分広く設計することにより、ショットキーダイオード70のオン抵抗を寄生ダイオードのオン抵抗より小さくすることができ、それにより、この場合にショットキーダイオード70に優先的に電流が流れる。その結果、ドリフト領域3aに注入される少数キャリアの数が低減される。また、この注入された少数キャリアは、その後、ソース電極6とドレイン電極1との間に印加される電圧がドレイン電極1に対しソース電極6の方が低電位となる電圧となると、瞬時にショットキー電極9aに吸収される。従って、半導体素子20は、従来例に比べて、オンからオフへのスイッチングが高速に行える。また、ショットキー電極9aを配設する領域の面積を十分広くすることができるため、ショットキー電極9aへの電流の集中が防止され、半導体素子20の破壊が抑制される。   On the other hand, when the load is inductive, the source electrode with respect to the drain electrode 1 is interposed between the source electrode 6 and the drain electrode 1 when the field effect transistor 90 is switched from on to off due to the inductance of the load. 6 is temporarily applied with a higher voltage. Thereby, the Schottky diode 70 in the diode cell 80 is turned on, and a current flows from the source electrode 6 to the drain electrode 1. When the positive voltage at the source electrode 6 further rises, the parasitic diode of the field effect transistor 90 is turned on, and minority carriers (holes) are injected into the drift region 3a. However, by designing the area of the Schottky electrode 9a to be sufficiently wide, the on-resistance of the Schottky diode 70 can be made smaller than the on-resistance of the parasitic diode. Current flows. As a result, the number of minority carriers injected into the drift region 3a is reduced. Further, the injected minority carriers are instantaneously shot when the voltage applied between the source electrode 6 and the drain electrode 1 becomes a voltage at which the source electrode 6 has a lower potential than the drain electrode 1. Absorbed by the key electrode 9a. Therefore, the semiconductor element 20 can be switched from on to off at a higher speed than the conventional example. In addition, since the area of the region where the Schottky electrode 9a is disposed can be sufficiently widened, current concentration on the Schottky electrode 9a is prevented, and destruction of the semiconductor element 20 is suppressed.

また、本実施形態の半導体素子20では、トランジスタ形成領域10の内部にダイオード形成領域9を配設したため、電界効果トランジスタ90に存在するp/n障壁に比べて小さいエネルギー障壁を有するショットキー接合が半導体素子20中に存在することとなり、半導体素子20にサージ電圧が印加された場合に、ショットキー接合部分に優先的にリーク電流が流れ、それにより、サージ電圧が緩和され、半導体素子20の破壊が抑制される。   Further, in the semiconductor element 20 of the present embodiment, since the diode formation region 9 is disposed inside the transistor formation region 10, a Schottky junction having an energy barrier smaller than the p / n barrier existing in the field effect transistor 90 is formed. When a surge voltage is applied to the semiconductor element 20, the leakage current preferentially flows through the Schottky junction, thereby reducing the surge voltage and destroying the semiconductor element 20. Is suppressed.

さらに、サージ電流に関しては、ショットキーダイオード70と寄生ダイオード(PN接合ダイオード)とが並列に接続された構造となっているため、ある程度の電流値(順方向電圧Vfの低い領域に対応する電流値)まではショットキーダイオード70が高速で電流を流し、さらに大きな電流値(順方向電圧Vfの高い領域に対応する電流値)になると寄生ダイオードが電流を流すことになる。したがって、ショットキーダイオード70への電流集中による破壊も防止される。   Further, regarding the surge current, since the Schottky diode 70 and the parasitic diode (PN junction diode) are connected in parallel, a certain current value (a current value corresponding to a region where the forward voltage Vf is low). ) Until the Schottky diode 70 passes a current at a high speed, and when the current value becomes larger (a current value corresponding to a region where the forward voltage Vf is high), the parasitic diode passes a current. Therefore, destruction due to current concentration on the Schottky diode 70 is also prevented.

したがって、本発明の半導体素子20は、サージ電圧及びサージ電流に対して高い耐性を有する。   Therefore, the semiconductor element 20 of the present invention has high resistance to surge voltage and surge current.

また、寄生ダイオードがオンのときに、マイノリティーキャリアがp型半導体領域4、ソース領域5にそれぞれ注入されても、逆バイアスが印加されると、ショットキー電極9aにマイノリティーキャリアが吸い込まれて、速やかに寄生ダイオードをオフ状態とすることができる。これにより、本発明の半導体素子20では、従来のPN接合ダイオードのみを有する半導体素子において懸念される、すばやくオフ状態とすることができない、いわゆるラッチアップの状態になることが抑制される。   Further, even when the minority carriers are injected into the p-type semiconductor region 4 and the source region 5 when the parasitic diode is on, when the reverse bias is applied, the minority carriers are sucked into the Schottky electrode 9a and quickly. The parasitic diode can be turned off. Thereby, in the semiconductor element 20 of the present invention, a so-called latch-up state that cannot be quickly turned off, which is a concern in a conventional semiconductor element having only a PN junction diode, is suppressed.

また、本実施形態の半導体素子20を構成するショットキーダイオード70は、Niからなるショットキー電極9aをアノードとして用い、ワイドバンドギャップ半導体(本実施形態では、SiC)をカソード(半導体層3)として用いている。このショットキーダイオード70は、通常使用の通電動作によっては半導体層3とショットキー電極9aとの界面にシリサイド層が形成されにくいため、高電流耐性及び高電圧耐性の観点から好適である。   Further, the Schottky diode 70 constituting the semiconductor element 20 of the present embodiment uses a Schottky electrode 9a made of Ni as an anode, and a wide band gap semiconductor (SiC in the present embodiment) as a cathode (semiconductor layer 3). Used. The Schottky diode 70 is suitable from the viewpoint of high current resistance and high voltage resistance because a silicide layer is hardly formed at the interface between the semiconductor layer 3 and the Schottky electrode 9a depending on a normal energization operation.

仮に、アノード(ショットキー電極9a)としてNiを用い、カソード(半導体層3)としてSi(シリコン)を用いてショットキーダイオードを構成した場合には、このショットキーダイオードに大電流を流すことが困難になる。すなわち、カソードとしてSiを用いたショットキーダイオードでは、SiとNiとの界面にシリサイド層が形成されやすく、その結果、SiとNiとがオーミックに接続され、ダイオードとしての機能を果たさなくなる場合がある。そうすると、優先的にショットキーダイオード70にサージ電圧によるリーク電流を流すことにより、半導体素子20の絶縁破壊を防止するという本発明の課題解決原理に反する可能性がある。   If a Schottky diode is configured using Ni as the anode (Schottky electrode 9a) and Si (silicon) as the cathode (semiconductor layer 3), it is difficult to flow a large current through the Schottky diode. become. That is, in a Schottky diode using Si as the cathode, a silicide layer is easily formed at the interface between Si and Ni, and as a result, the Si and Ni are ohmicly connected, and the function as a diode may not be achieved. . If so, there is a possibility that the current problem principle of the present invention, which prevents the dielectric breakdown of the semiconductor element 20, is preferentially caused by causing a leakage current due to a surge voltage to flow through the Schottky diode 70.

したがって、本実施形態においては、カソードの構成の差異(半導体層3をSiCで構成するか、Siで構成するかの差異)は、当業者による単なる設計事項の類ではなく、上記課題解決原理に直結する事項である。   Therefore, in this embodiment, the difference in the configuration of the cathode (the difference in whether the semiconductor layer 3 is made of SiC or Si) is not just a kind of design matter by those skilled in the art, but is based on the above problem solving principle. It is a directly connected matter.

さらに、カソード(半導体層3)としてワイドバンドギャップ半導体であるSiCを用いたショットキーダイオード70は、カソード(半導体層3)としてSiを用いたショットキーダイオードと比較して、サージ電圧が印加された場合の耐圧特性に優れる。   Furthermore, the Schottky diode 70 using SiC, which is a wide band gap semiconductor, as the cathode (semiconductor layer 3) was applied with a surge voltage as compared with the Schottky diode using Si as the cathode (semiconductor layer 3). Excellent withstand voltage characteristics.

なお、PN接合ダイオードは、一般的に、高電流耐性及び高電圧耐性に優れているが、ワイドバンドギャップ半導体たるSiCを用いてPN接合ダイオードを構成すると、順方向電圧Vfの上昇分に起因する導通損失が生じてしまう。   In general, the PN junction diode is excellent in high current resistance and high voltage resistance. However, when the PN junction diode is formed using SiC as a wide band gap semiconductor, it is caused by an increase in the forward voltage Vf. Conduction loss will occur.

以上の事項を総括すると、本実施形態の半導体素子20では、半導体層3にワイドバンドギャップ半導体(SiC)を用いてショットキーダイオード70を構成することが好適である。   Summarizing the above matters, in the semiconductor element 20 of the present embodiment, it is preferable to form the Schottky diode 70 using a wide band gap semiconductor (SiC) for the semiconductor layer 3.

次に、本実施形態における実施例を説明する。   Next, examples in the present embodiment will be described.

[実施例]
本実施例として、本実施形態の半導体素子20を複数個作製し、ゲート絶縁膜7におけるリーク電流を測定したところ、5%の半導体素子20で1μAのリーク電流が確認され、歩留まりは95%であった。一方、比較例として、ダイオード形成領域9を配設せず、電界効果トランジスタ90の表面に直接ソース・ショットキー用パッド12Sを被覆してワイヤボンドした半導体素子を複数個作製し、ゲート絶縁膜7におけるリーク電流を測定したところ、30%の半導体素子で1μAのリーク電流が確認され、歩留まりは70%であった。すなわち、本実施形態の半導体素子20では、ダイオード形成領域9の表面を被覆するようにしてソース・ショットキー用パッド12Sが配設されており、ダイオード形成領域9にはゲート絶縁膜7が形成されていない。また、ソース・ショットキー用パッド12Sの下方に位置するショットキーダイオード70は、電界効果トランジスタ90よりも超音波に対する強度が大きい。このため、超音波を印加しながらワイヤ13Sをソース・ショットキー用パッド12Sに押し付けてボンディングしても、それによるゲート絶縁膜7の損傷が低減され、かつ電界効果トランジスタ90が破壊されることが抑制される。
[Example]
As this example, a plurality of semiconductor elements 20 of the present embodiment were fabricated and the leakage current in the gate insulating film 7 was measured. As a result, a leakage current of 1 μA was confirmed in 5% of the semiconductor elements 20, and the yield was 95%. there were. On the other hand, as a comparative example, a plurality of semiconductor elements in which the diode-forming region 9 is not provided and the surface of the field effect transistor 90 is directly covered with the source / Schottky pad 12S to be wire-bonded are manufactured. As a result, the leakage current of 1 μA was confirmed in 30% of the semiconductor elements, and the yield was 70%. That is, in the semiconductor element 20 of the present embodiment, the source / Schottky pad 12S is disposed so as to cover the surface of the diode forming region 9, and the gate insulating film 7 is formed in the diode forming region 9. Not. Further, the Schottky diode 70 located below the source / Schottky pad 12 </ b> S has a higher strength against ultrasonic waves than the field effect transistor 90. For this reason, even if the wire 13S is pressed against the source / Schottky pad 12S while being applied with ultrasonic waves and bonded, damage to the gate insulating film 7 due to the bonding can be reduced and the field effect transistor 90 can be destroyed. It is suppressed.

(第2実施形態)
本発明の第2実施形態は、第1実施形態の半導体素子20を用いたアームモジュール(半導体装置)を組み込んだインバータ回路を例示したものである。
(Second Embodiment)
The second embodiment of the present invention exemplifies an inverter circuit incorporating an arm module (semiconductor device) using the semiconductor element 20 of the first embodiment.

[アームモジュール]
図5は本発明の第2実施形態に係る半導体装置としてのアームモジュールの構成を模式的に示す平面図である。図5において図1乃至図4と同一又は相当する部分には同一の符号を付してその説明を省略する。
[Arm module]
FIG. 5 is a plan view schematically showing a configuration of an arm module as a semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same or corresponding parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof is omitted.

本実施形態のアームモジュールは、図5に示すように、第1実施形態の半導体素子20と、ドレイン電極端子15、ソース電極端子16、及びゲート電極端子17を有するパッケージとを備えている。   As shown in FIG. 5, the arm module of the present embodiment includes the semiconductor element 20 of the first embodiment and a package having the drain electrode terminal 15, the source electrode terminal 16, and the gate electrode terminal 17.

半導体素子20は、その下面のドレイン電極1がドレイン電極端子15の上面に接続されるようにして、ドレイン電極端子1の上に配設されている。そして、半導体素子20のソース・ショットキー用パッド12Sがワイヤ13Sによってソース電極端子16に接続され、半導体素子20のゲート用パッド12Gがワイヤ13Gによってゲート電極端子17に接続されている。半導体素子20のドレイン電極1とドレイン電極端子15とは、ダイボンディングによって接続されている。また、ワイヤ13S、13Gの端部と、ソース電極端子16又はゲート電極端子17とは、ボンディングにより接続されている。   The semiconductor element 20 is disposed on the drain electrode terminal 1 so that the drain electrode 1 on the lower surface thereof is connected to the upper surface of the drain electrode terminal 15. The source / Schottky pad 12S of the semiconductor element 20 is connected to the source electrode terminal 16 by the wire 13S, and the gate pad 12G of the semiconductor element 20 is connected to the gate electrode terminal 17 by the wire 13G. The drain electrode 1 and the drain electrode terminal 15 of the semiconductor element 20 are connected by die bonding. The ends of the wires 13S and 13G and the source electrode terminal 16 or the gate electrode terminal 17 are connected by bonding.

そして、このように相互に接続された半導体素子20及び各電極端子15、16、17が封止樹脂18によって封止(モールド)されている。ここで、上記封止樹脂18としては、汎用のものを用いることができる。   The semiconductor element 20 and the electrode terminals 15, 16, and 17 connected to each other in this way are sealed (molded) with a sealing resin 18. Here, a general-purpose resin can be used as the sealing resin 18.

[インバータ回路]
図6は本発明の第2実施形態に係るインバータ回路の構成を示す回路図である。図6において図9と同一又は相当する部分には同一の符号を付してその説明を省略する。
[Inverter circuit]
FIG. 6 is a circuit diagram showing a configuration of an inverter circuit according to the second embodiment of the present invention. 6, parts that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and descriptions thereof are omitted.

本実施形態のインバータ回路は、三相交流モータ駆動用であり、上アーム23Hと下アーム23Lとが直列に接続されてなる相スイッチング回路23を相数分(ここでは3つ)備え、上アーム23H及び下アーム23Lの各々は、互いに並列に接続されたスイッチング素子21とダイオード22とで構成されている。そして、上アーム23H及び下アーム23Lがそれぞれ本実施形態のアームモジュールで構成されている。また、各アーム23H,23Lのスイッチング素子21は、第1実施形態の半導体素子20のうちの電界効果トランジスタ90で構成されている。一方、ダイオード22は、スイッチング素子21と並列に接続された帰還ダイオードであって、第1実施形態の半導体素子20のうちのショットキーダイオード70で構成されている。それ以外の点については、背景技術の欄でも説明したので、その説明を省略する。   The inverter circuit according to the present embodiment is for driving a three-phase AC motor, and includes phase switching circuits 23 (three in this case) having the upper arm 23H and the lower arm 23L connected in series. Each of the 23H and the lower arm 23L includes a switching element 21 and a diode 22 connected in parallel to each other. And the upper arm 23H and the lower arm 23L are each comprised by the arm module of this embodiment. Moreover, the switching element 21 of each arm 23H and 23L is comprised by the field effect transistor 90 of the semiconductor elements 20 of 1st Embodiment. On the other hand, the diode 22 is a feedback diode connected in parallel with the switching element 21 and is composed of the Schottky diode 70 in the semiconductor element 20 of the first embodiment. Since other points have been described in the background art section, the description thereof will be omitted.

本実施形態では、このインバータ回路を用いて第1実施形態の半導体素子20の構成を検討した。   In the present embodiment, the configuration of the semiconductor element 20 of the first embodiment was examined using this inverter circuit.

図2乃至図4を参照して、半導体素子20においては、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合が1%以上でかつ50%以下であることが好ましい。さらに、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合が10%以上でかつ50%以下であることがより好ましい。   2 to 4, in the semiconductor element 20, the ratio of the area of the Schottky electrode 9 a to the area of the semiconductor element 20 in plan view is preferably 1% or more and 50% or less. Further, the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is more preferably 10% or more and 50% or less.

まず、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を1%にした場合について説明する。このような半導体素子20を、本実施形態のアームモジュールとして用いた場合のスイッチング損失を測定したところ、2%のスイッチング損失の低減が実現できる。ここで、半導体素子20について、ダイオード形成領域9の単位面積換算のオン抵抗は1mΩcm程度となる。そして、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を1%にした場合、ショットキーダイオード70の順方向に電流を流す際の順方向電圧Vfが、ショットキー障壁による順方向の立ち上がり電圧(1V)を加えて3V程度(抵抗分電流による順方向電圧Vf上昇は2V)であれば、素子全体の電流密度換算で20A/cm(半導体素子については2A)程度の電流を流すことができる。ここで、順方向電圧が3Vというのは、本発明の半導体素子20に存在する寄生ダイオードに順方向の電流を流す際の最低の順方向電圧である。これは、半導体材料としてSiCを用いたことに起因する。従って、ショットキー電極9aに順方向の電流を流した場合に、順方向電圧Vfを3V以下に保つことができれば、ショットキー電極9aを配設しない従来の半導体素子に比べてスイッチング損失を低減することができる。 First, a case where the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is 1% will be described. When such a semiconductor element 20 is used as an arm module of this embodiment and the switching loss is measured, a reduction in switching loss of 2% can be realized. Here, for the semiconductor element 20, the on-resistance in terms of unit area of the diode formation region 9 is about 1 mΩcm 2 . When the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is 1%, the forward voltage Vf when the current flows in the forward direction of the Schottky diode 70 is the forward voltage due to the Schottky barrier. Current of about 20 A / cm 2 ( 2 A for semiconductor elements) in terms of the current density of the entire device if the rising voltage (1 V) in the direction is added and the voltage is about 3 V (the forward voltage Vf rise due to the resistance current is 2 V) Can flow. Here, the forward voltage of 3 V is the lowest forward voltage when a forward current flows through the parasitic diode existing in the semiconductor element 20 of the present invention. This is due to the use of SiC as the semiconductor material. Therefore, when a forward current flows through the Schottky electrode 9a, if the forward voltage Vf can be maintained at 3V or less, switching loss is reduced as compared with a conventional semiconductor element in which the Schottky electrode 9a is not provided. be able to.

このとき、トランジスタ形成領域10の平均化した単位面積換算のオン抵抗は、ダイオード形成領域9の単位面積換算のオン抵抗よりも約一桁大きい値となる。具体的には、トランジスタ形成領域10の平均化した単位面積換算のオン抵抗は、10mΩcmとなる。したがって、電界効果トランジスタ90がオンしたときの電流密度(以下、オン電流密度という)は、順方向電圧Vf上昇を2Vとして、200A/cmと見積もれる。なお、電界効果トランジスタ90がオンしたときの電流(以下、オン電流という)は、ショットキーダイオード70を流れる電流の流れと逆方向である。 At this time, the averaged on-resistance in terms of unit area of the transistor formation region 10 is about one digit larger than the on-resistance in terms of unit area of the diode formation region 9. Specifically, the averaged on-resistance of the transistor formation region 10 in terms of unit area is 10 mΩcm 2 . Therefore, the current density when the field-effect transistor 90 is turned on (hereinafter referred to as on-current density) is estimated to be 200 A / cm 2 where the forward voltage Vf increase is 2 V. A current when the field effect transistor 90 is turned on (hereinafter referred to as an on-current) is in a direction opposite to the current flowing through the Schottky diode 70.

よって、電界効果トランジスタ90のオン電流密度の約10分の1の電流密度となる電流値をオン電流と逆方向にショットキーダイオード70に流す場合には、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を1%にすることが好適である。   Therefore, when a current value having a current density that is approximately one-tenth of the on-current density of the field effect transistor 90 is passed through the Schottky diode 70 in the direction opposite to the on-current, the shot with respect to the area of the semiconductor element 20 in plan view The area ratio of the key electrode 9a is preferably 1%.

一方、上アーム23H及び下アーム23Lの連続動作試験中に、上アーム23H及び下アーム23Lは、発熱により動作が安定しない場合があった。これは、ショットキーダイオード70を流れる電流値が、上記許容電流値(20A/cm)を超えてしまったためと推定される。したがって、許容電流値がショットキーダイオード70を流れる電流値よりも高くなるよう、ショットキー電極9aの面積の割合を設計することが好ましい。 On the other hand, during the continuous operation test of the upper arm 23H and the lower arm 23L, the operation of the upper arm 23H and the lower arm 23L may not be stabilized due to heat generation. This is presumably because the value of the current flowing through the Schottky diode 70 has exceeded the allowable current value (20 A / cm 2 ). Therefore, it is preferable to design the ratio of the area of the Schottky electrode 9a so that the allowable current value is higher than the current value flowing through the Schottky diode 70.

次に、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を10%にした半導体素子20を作製し、この半導体素子20をアームモジュールとして用いた場合には、5%のスイッチング損失の低減が実現できる。また、この場合において、ショットキーダイオード70を流れる電流の許容値は、素子全体の電流密度換算で200A/cm(半導体素子については20A)である。ここで、許容電流値が200A/cmというのは十分に高い電流値であるため、ショットキーダイオード70を流れる電流値が許容電流値を超えず、上アーム23H及び下アーム23Lが安定動作する。 Next, the semiconductor element 20 is manufactured in which the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is 10%. When the semiconductor element 20 is used as an arm module, the switching is 5%. Loss can be reduced. In this case, the allowable value of the current flowing through the Schottky diode 70 is 200 A / cm 2 (20 A for a semiconductor element) in terms of the current density of the entire element. Here, since the allowable current value of 200 A / cm 2 is a sufficiently high current value, the current value flowing through the Schottky diode 70 does not exceed the allowable current value, and the upper arm 23H and the lower arm 23L operate stably. .

前述のように、トランジスタ形成領域10の平均化した単位面積換算のオン抵抗は、10mΩcmであるので、電界効果トランジスタ90のオン電流密度と同じ電流密度となる電流値を、オン電流と逆方向にショットキーダイオード70に流す場合には、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を10%にすることが好適である。 As described above, the averaged on-resistance in unit area of the transistor formation region 10 is 10 mΩcm 2 , so that the current value having the same current density as the on-current density of the field effect transistor 90 is set in the direction opposite to the on-current. When the current flows through the Schottky diode 70, the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is preferably 10%.

また、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を50%にした半導体素子20を作製し、この半導体素子20をアームモジュールとして用いた場合には、1%のスイッチング損失の低減が実現できる。   Further, when the semiconductor element 20 is manufactured in which the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is 50% and this semiconductor element 20 is used as an arm module, the switching loss is 1%. Can be reduced.

前述のように、トランジスタ形成領域10の平均化した単位面積換算のオン抵抗は、10mΩcmであるが、将来、チャネル抵抗の低減等により、トランジスタ形成領域10の単位面積換算のオン抵抗を低減させることができると考えられる。その結果、トランジスタ形成領域10の単位面積換算のオン抵抗が、ダイオード形成領域9の単位面積換算のオン抵抗(1mΩcm)に近づく。ここで、トランジスタ形成領域10のオン抵抗は、ショットキーダイオード形成領域9のオン抵抗よりも小さくなりえないが、両者のオン抵抗が同程度の値となる場合がある。この場合において、電界効果トランジスタ90に流れるオン電流の電流密度と、ショットキーダイオード70に流れるオン電流の電流密度とが同じであるとすると、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を50%にすることが好適である。 As described above, the averaged on-resistance in unit area of the transistor formation region 10 is 10 mΩcm 2 , but in the future, the on-resistance in unit area conversion of the transistor formation region 10 will be reduced by reducing the channel resistance or the like. It is considered possible. As a result, the on-resistance in terms of unit area of the transistor formation region 10 approaches the on-resistance in terms of unit area of the diode formation region 9 (1 mΩcm 2 ). Here, the on-resistance of the transistor formation region 10 cannot be smaller than the on-resistance of the Schottky diode formation region 9, but the on-resistances of both may be approximately the same. In this case, assuming that the current density of the on-current flowing through the field effect transistor 90 is the same as the current density of the on-current flowing through the Schottky diode 70, the Schottky electrode 9a has an area relative to the area of the semiconductor element 20 in plan view. It is preferable that the area ratio is 50%.

ここで、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を10%以上にした場合には、半導体素子20の発熱も抑制され、インバータ回路が安定動作した。   Here, when the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view was 10% or more, the heat generation of the semiconductor element 20 was suppressed and the inverter circuit operated stably.

しかし、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合が50%を超えるようにした場合には、トランジスタセル100の半導体素子20全体に占める割合が低下するため、電界効果トランジスタ90のオン抵抗が増大し、スイッチング損失も増加した。   However, when the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view exceeds 50%, the ratio of the transistor cell 100 to the entire semiconductor element 20 is reduced, so that the field effect transistor The on-resistance of 90 increased and the switching loss also increased.

また、ショットキーダイオード70を流れる電流が素子全体の電流密度換算で200〜600A/cmであれば、半導体素子20の安定動作が期待されるため、半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合が10%以上でかつ30%以下であることが、より好ましい。 Further, if the current flowing through the Schottky diode 70 is 200 to 600 A / cm 2 in terms of the current density of the entire device, stable operation of the semiconductor device 20 is expected, so that the Schottky with respect to the area of the semiconductor device 20 in plan view is expected. The area ratio of the electrode 9a is more preferably 10% or more and 30% or less.

以上に述べたとおり、ショットキーダイオード70に流れる電流値と、電界効果トランジスタ90に流れる電流値とが同じ(ただし、流れる方向は逆)であるとすると、ダイオード形成領域9のオン抵抗がトランジスタ形成領域10のオン抵抗の10分の1である場合には半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を10%にすればよい。また、ダイオード形成領域9のオン抵抗がトランジスタ形成領域10のオン抵抗の3分の1である場合には半導体素子20の平面視における面積に対するショットキー電極9aの面積の割合を約30%にすればよい。   As described above, if the current value flowing through the Schottky diode 70 and the current value flowing through the field effect transistor 90 are the same (however, the flow direction is opposite), the on-resistance of the diode formation region 9 is the transistor formation. When the on-resistance of the region 10 is 1/10, the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view may be 10%. When the on-resistance of the diode formation region 9 is one third of the on-resistance of the transistor formation region 10, the ratio of the area of the Schottky electrode 9a to the area of the semiconductor element 20 in plan view is reduced to about 30%. That's fine.

以上の検討結果を総括すると、第1実施形態の半導体素子20においては、本来のスイッチング素子としての機能を十分に果たすようにするため、半導体素子20の平面視における面積に対する全てのトランジスタセル100の平面視における面積の割合が50%以上でかつ99%以下であることが好ましい。さらに、半導体素子20の安定動作のためには、半導体素子20の平面視における面積に対する全てのトランジスタセル100の平面視における面積の割合が70%以上でかつ90%以下であることが、より好ましい。   Summarizing the above examination results, in the semiconductor element 20 of the first embodiment, in order to sufficiently perform the function as the original switching element, all the transistor cells 100 with respect to the area of the semiconductor element 20 in a plan view are described. The area ratio in plan view is preferably 50% or more and 99% or less. Furthermore, for the stable operation of the semiconductor element 20, it is more preferable that the ratio of the area of all the transistor cells 100 in the plan view to the area of the semiconductor element 20 in the plan view is 70% or more and 90% or less. .

(第3実施形態)
図7は、本発明の第3実施形態の半導体素子の構成を示す平面図である。図8は、図7の半導体素子の構成の一部を拡大した部分平面図である。図7及び図8において図1乃至図3と同一又は相当する部分には同一の符号を付してその説明を省略する。
(Third embodiment)
FIG. 7 is a plan view showing a configuration of a semiconductor device according to the third embodiment of the present invention. FIG. 8 is a partial plan view in which a part of the configuration of the semiconductor element of FIG. 7 is enlarged. 7 and 8, the same or corresponding parts as in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.

図7及び図8に示すように、本実施形態の半導体素子20では、ダイオード形成領域9は、平面視において格子状の仮想の境界線50で区切られたセル200のうちの複数のダイオードセル80の上面を覆うようなショットキー電極9bを、トランジスタ形成領域10の内部に島状に配設することによって構成されている。その他の点は、第1実施形態と同様である。   As shown in FIGS. 7 and 8, in the semiconductor element 20 of the present embodiment, the diode formation region 9 includes a plurality of diode cells 80 out of the cells 200 that are partitioned by the lattice-like virtual boundary line 50 in plan view. The Schottky electrode 9b that covers the upper surface of the transistor is arranged in an island shape inside the transistor formation region 10. Other points are the same as in the first embodiment.

ショットキー電極9bは、トランジスタ形成領域10の内部に計9箇所配設されている。なお、ショットキー電極9bの配設される数はこれに限定されない。すなわち、ショットキー電極9bを複数個のセル200に渡って配設したり、ショットキー電極9bの全体又は一部を一体化して形成したりして、その個数が変更されてもかまわない。このような構成としても、上記の第1実施形態と同様の効果を奏する。また、このような構成とすると、構成部品点数が少なくなり、半導体素子20の製造が容易になり、歩留まりが向上する。   A total of nine Schottky electrodes 9b are arranged inside the transistor formation region 10. Note that the number of the Schottky electrodes 9b is not limited to this. That is, the number of Schottky electrodes 9b may be changed by arranging the Schottky electrodes 9b over a plurality of cells 200 or by forming all or part of the Schottky electrodes 9b integrally. Even with such a configuration, the same effects as those of the first embodiment can be obtained. Further, with such a configuration, the number of component parts is reduced, the manufacture of the semiconductor element 20 is facilitated, and the yield is improved.

本実施形態における半導体素子20においても、電界の集中による破壊を防止するため、図7及び図8に示すように、ショットキー電極9bの角部を丸みが帯びた形状にすることが好ましい。   Also in the semiconductor element 20 according to the present embodiment, in order to prevent the breakdown due to the concentration of the electric field, it is preferable that the corner of the Schottky electrode 9b is rounded as shown in FIGS.

なお、本実施形態の半導体素子20も第1実施形態の半導体素子20と同様に第2実施形態のアームモジュール及びインバータ回路に用いることができ、第1実施形態の半導体素子20を用いた場合と同様の効果を得ることができる。また、本実施形態の半導体素子20の平面視における面積に対する全てのトランジスタセル100の平面視における面積の割合も50%以上でかつ99%以下であることが好ましい。   The semiconductor element 20 of the present embodiment can be used for the arm module and the inverter circuit of the second embodiment, similarly to the semiconductor element 20 of the first embodiment, and when the semiconductor element 20 of the first embodiment is used. Similar effects can be obtained. The ratio of the area of all the transistor cells 100 in plan view to the area of the semiconductor element 20 in plan view in the plan view is preferably 50% or more and 99% or less.

なお、第1乃至第3実施形態では、電界効果トランジスタ90がnチャネル型である場合を説明したが、本発明は電界効果トランジスタ90がpチャネル型である場合にも同様に適用できる。但し、この場合には、各半導体領域の導電型が逆になり、ソース領域及びソース電極とドレイン領域及びドレイン電極とが逆になる。   In the first to third embodiments, the case where the field effect transistor 90 is an n-channel type has been described. However, the present invention can be similarly applied to a case where the field effect transistor 90 is a p-channel type. However, in this case, the conductivity type of each semiconductor region is reversed, and the source region, the source electrode, and the drain region and the drain electrode are reversed.

上記説明から、当業者にとっては、本発明の多くの改良や他の実施形態が明らかである。従って、上記説明は、例示としてのみ解釈されるべきであり、本発明を実行する最良の態様を当業者に教示する目的で提供されたものである。本発明の精神を逸脱することなく、その構造及び/又は機能の詳細を実質的に変更できる。   From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

本発明による半導体素子は、高速スイッチング動作とエネルギー損失低減の両立が図れ、かつ電気機器のインダクタンス負荷等による逆起電力に基づく電流集中耐性に優れると共に、ワイヤボンディング時における電界効果トランジスタの絶縁膜の劣化を抑制可能であり、例えば、電気機器の高速インバータ電源回路の用途に適用可能である。   The semiconductor device according to the present invention can achieve both high-speed switching operation and energy loss reduction, and is excellent in current concentration resistance based on counter electromotive force due to inductance load of an electric device, etc. Degradation can be suppressed, and can be applied to, for example, the use of a high-speed inverter power supply circuit for electrical equipment.

図1は、本発明の第1実施形態の半導体素子の構成を示す平面図である。FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention. 図2は、本発明の第1実施形態の半導体素子の構成を示す平面図である。FIG. 2 is a plan view showing the configuration of the semiconductor element according to the first embodiment of the present invention. 図3は、図1の半導体素子の構成の一部を拡大した部分平面図である。FIG. 3 is an enlarged partial plan view of a part of the configuration of the semiconductor element of FIG. 図4は、図1の半導体素子の断面視における構造を示す部分断面図であって、図3に示すIV−IV線に沿って切断した断面図である。4 is a partial cross-sectional view showing the structure of the semiconductor element of FIG. 1 in a cross-sectional view, and is a cross-sectional view taken along line IV-IV shown in FIG. 図5は、本発明の第2実施形態に係る半導体装置としてのアームモジュールの構成を模式的に示す平面図である。FIG. 5 is a plan view schematically showing a configuration of an arm module as a semiconductor device according to the second embodiment of the present invention. 図6は、本発明の第2実施形態に係るインバータ回路の構成を示す回路図である。FIG. 6 is a circuit diagram showing a configuration of an inverter circuit according to the second embodiment of the present invention. 図7は、本発明の第3実施形態の半導体素子の構成を示す平面図である。FIG. 7 is a plan view showing a configuration of a semiconductor device according to the third embodiment of the present invention. 図8は、図7の半導体素子の構成の一部を拡大した部分平面図である。FIG. 8 is a partial plan view in which a part of the configuration of the semiconductor element of FIG. 7 is enlarged. 図9は、従来の半導体素子の応用例である三相モータ駆動用のインバータ回路の概要を示す回路図である。FIG. 9 is a circuit diagram showing an outline of an inverter circuit for driving a three-phase motor, which is an application example of a conventional semiconductor element. 図10は、仮想の境界線を説明するための概略図であって、(a)は仮想の境界線を特定する第1の手法を示す図、(b)は仮想の境界線を特定する第2の手法を示す図、(c)は仮想の境界線を特定する第3の手法を示す図、(d)は仮想の境界線を特定する第4の手法を示す図である。10A and 10B are schematic diagrams for explaining a virtual boundary line, where FIG. 10A is a diagram illustrating a first method for specifying a virtual boundary line, and FIG. 10B is a first diagram for specifying a virtual boundary line. FIG. 2C is a diagram showing a third technique for specifying a virtual boundary line, and FIG. 4D is a diagram showing a fourth technique for specifying a virtual boundary line.

符号の説明Explanation of symbols

1 ドレイン電極
2 半導体基板
3 半導体層(SiC層)
3a ドリフト領域
4 p型半導体領域(第2導電型領域)
4a p型半導体領域外周部
4b p型半導体領域中央部
5 ソース領域
6 ソース電極
7 ゲート絶縁膜
8 ゲート電極
9 ダイオード形成領域
9a,9b ショットキー電極
10 トランジスタ形成領域
11 ガードリング(耐圧部材)
12S ソース・ショットキー用パッド
12G ゲート用パッド
13S、13G ワイヤ
14 半導体素子端部
15 ドレイン電極端子
16 ソース電極端子
17 ゲート電極端子
18 封止樹脂
20 半導体素子
21 スイッチング素子
22 ダイオード
23 相スイッチング回路
23H 上アーム
23L 下アーム
24 アース電位配線(アース電位)
25 高電位配線(高電位)
26 アームの中点
27 モータ入力端子
28 三相モータ
40 層間絶縁膜
50 仮想の境界線
50a,50c 横境界ライン
50b,50d 縦境界ライン
50X X部分仮想線
50Y Y部分仮想線
51 ジグザグライン
70 ショットキーダイオード
80 ダイオードセル
90 電界効果トランジスタ(MOSFET)
100 トランジスタセル
200 セル
DESCRIPTION OF SYMBOLS 1 Drain electrode 2 Semiconductor substrate 3 Semiconductor layer (SiC layer)
3a drift region 4 p-type semiconductor region (second conductivity type region)
4a p-type semiconductor region outer peripheral part 4b p-type semiconductor region central part 5 source region 6 source electrode 7 gate insulating film 8 gate electrode 9 diode forming region 9a, 9b Schottky electrode 10 transistor forming region 11 guard ring (withstand voltage member)
12S pad for source schottky 12G pad for gate
13S, 13G wire 14 semiconductor element end 15 drain electrode terminal 16 source electrode terminal 17 gate electrode terminal 18 sealing resin 20 semiconductor element 21 switching element 22 diode 23 phase switching circuit 23H upper arm 23L lower arm 24 ground potential wiring (ground potential) )
25 High potential wiring (high potential)
26 Arm midpoint 27 Motor input terminal 28 Three-phase motor 40 Interlayer insulating film 50 Virtual boundary lines 50a, 50c Horizontal boundary lines 50b, 50d Vertical boundary lines 50X X partial virtual lines 50Y Y partial virtual lines 51 Zigzag lines 70 Schottky Diode 80 Diode cell 90 Field effect transistor (MOSFET)
100 transistor cells 200 cells

Claims (12)

半導体層と、該半導体層に該半導体層の上面を含むように形成された第1導電型の第1のソース/ドレイン領域と、前記半導体層に前記上面及び前記第1のソース/ドレイン領域を含むように形成された第2導電型領域と、前記半導体層に前記上面及び前記第2導電型領域を含むように形成された第1導電型のドリフト領域と、少なくとも前記第1のソース/ドレイン領域の前記上面に接するように設けられた第1のソース/ドレイン電極と、ゲート絶縁膜を介して少なくとも前記第2導電型領域の前記上面に対向するように設けられたゲート電極と、前記ドリフト領域にオーミックに接続された第2のソース/ドレイン電極と、を有する電界効果トランジスタと、
前記ドリフト領域の前記上面に該上面とショットキー接合を形成するように設けられたショットキー電極と、
前記第1のソース/ドレイン電極、ゲート電極、及びショットキー電極が設けられた前記半導体層の上面を覆う層間絶縁膜と、
前記層間絶縁膜の上に配設され、前記第1のソース/ドレイン電極、ゲート電極、及びショットキー電極の少なくともいずれかと電気的に接続された複数のボンディングパッドと、を備え、
前記半導体層は、平面視において仮想の境界線により複数のセルに分割され、
前記複数のセルに延在するように前記ドリフト領域及び第2のソース/ドレイン電極が形成され、
前記複数のセルは、その中に前記電界効果トランジスタが形成されたトランジスタセルと、その中に前記ショットキー電極が形成されたダイオードセルとで構成され、
平面視において、複数の前記トランジスタセルの間に1以上の前記ダイオードセルが島状に配置され、この島状に配置された1以上の前記ダイオードセルの前記ショットキー電極の上方に前記ボンディングパッドが位置している、半導体素子。
A semiconductor layer; a first source / drain region of a first conductivity type formed in the semiconductor layer so as to include the upper surface of the semiconductor layer; and the upper surface and the first source / drain region in the semiconductor layer. A second conductivity type region formed to include the first conductivity type drift region formed to include the upper surface and the second conductivity type region in the semiconductor layer, and at least the first source / drain A first source / drain electrode provided so as to be in contact with the upper surface of the region; a gate electrode provided so as to face at least the upper surface of the second conductivity type region via a gate insulating film; and the drift A field effect transistor having a second source / drain electrode ohmically connected to the region;
A Schottky electrode provided on the upper surface of the drift region so as to form a Schottky junction with the upper surface;
An interlayer insulating film covering an upper surface of the semiconductor layer provided with the first source / drain electrode, the gate electrode, and the Schottky electrode;
A plurality of bonding pads disposed on the interlayer insulating film and electrically connected to at least one of the first source / drain electrode, the gate electrode, and the Schottky electrode;
The semiconductor layer is divided into a plurality of cells by virtual boundary lines in plan view,
The drift region and the second source / drain electrode are formed to extend to the plurality of cells;
The plurality of cells includes a transistor cell in which the field effect transistor is formed, and a diode cell in which the Schottky electrode is formed.
In plan view, one or more of the diode cells are arranged in an island shape between the plurality of transistor cells, and the bonding pad is disposed above the Schottky electrode of the one or more of the diode cells arranged in the island shape. A semiconductor element located.
前記第1のソース/ドレイン電極が、前記第1のソース/ドレイン領域及び第2導電型領域の前記上面に接するように設けられている、請求項1に記載の半導体素子。  2. The semiconductor device according to claim 1, wherein the first source / drain electrode is provided in contact with the upper surface of the first source / drain region and the second conductivity type region. 前記第1導電型がn型であり、前記第2導電型がp型である、請求項1に記載の半導体素子。  The semiconductor element according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. 前記半導体層がワイドバンドギャップ半導体で構成されている、請求項1に記載の半導体素子。  The semiconductor element according to claim 1, wherein the semiconductor layer is formed of a wide band gap semiconductor. 前記複数のボンディングパッドは、ワイヤによって互いに接続されている、請求項1に記載の半導体素子。  The semiconductor device according to claim 1, wherein the plurality of bonding pads are connected to each other by wires. 前記ボンディングパッドは辺の長さが0.3mm以上である四角形の形状を有している、請求項1に記載の半導体素子。  The semiconductor element according to claim 1, wherein the bonding pad has a quadrangular shape with a side length of 0.3 mm or more. 前記半導体素子の平面視における面積に対する全ての前記トランジスタセルの平面視における面積の割合が50%以上でかつ99%以下である、請求項1に記載の半導体素子。  2. The semiconductor element according to claim 1, wherein a ratio of an area of each of the transistor cells in a plan view to an area of the semiconductor element in a plan view is 50% or more and 99% or less. 前記半導体素子の平面視における面積に対する前記ショットキー電極の面積の割合が1%以上でかつ50%以下である、請求項1に記載の半導体素子。  The semiconductor element according to claim 1, wherein a ratio of an area of the Schottky electrode to an area of the semiconductor element in plan view is 1% or more and 50% or less. 前記ダイオードセルにおける前記ショットキー電極の面積が前記トランジスタセルにおける前記第2導電型領域の平面視における面積より大きい、請求項1に記載の半導体素子。  2. The semiconductor device according to claim 1, wherein an area of the Schottky electrode in the diode cell is larger than an area in a plan view of the second conductivity type region in the transistor cell. 交流駆動装置と、該交流駆動装置のインバータ電源回路を構成する請求項1乃至の何れかに記載の半導体素子と、を備え、
前記半導体素子がアームモジュールとして組み込まれている、電気機器。
An AC drive device and the semiconductor element according to any one of claims 1 to 9 constituting an inverter power supply circuit of the AC drive device,
An electric device in which the semiconductor element is incorporated as an arm module.
前記交流駆動装置内のインダクタンス負荷によって発生する逆起電力に基づいて前記電界効果トランジスタの寄生ダイオード及び前記ドリフト領域と該ドリフト領域の上面とショットキー接合を形成するショットキー電極とによって構成されたショットキーダイオードに印加される電圧は、前記ショットキーダイオードの順方向の立ち上がり電圧より大きく、かつ前記寄生ダイオードの順方向の立ち上がり電圧より小さくして構成される、請求項1記載の電気機器。A shot composed of a parasitic diode of the field effect transistor and a drift region and a Schottky electrode forming a Schottky junction with the upper surface of the drift region based on a back electromotive force generated by an inductance load in the AC drive device voltage applied to the key diodes, forward larger than the rising voltage and is configured to be smaller than a forward rising voltage of the parasitic diode of claim 1, 0 electrical apparatus according of the Schottky diode. 前記交流駆動装置は、前記インバータ電源回路により駆動される交流モータである、請求項1記載の電気機器。The AC drive, the an AC motor driven by an inverter power source circuit, according to claim 1 0 electrical apparatus according.
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