JP2019096631A - Semiconductor device and power converter - Google Patents

Abstract

To provide a trench gate type semiconductor device in which gate electrodes 304 are arranged in a stripe shape and in which a protective diffusion layer 306 and a source electrode 5 can be reliably connected to suppress a decrease in the switching speed.SOLUTION: A semiconductor device includes a plurality of active stripe regions 3 separated by a plurality of stripe trenches 307 and a protective diffusion layer ground region 4 where a source electrode 5 is connected to a protective diffusion layer 306 through an opening 402 provided in a semiconductor layer 2 between adjacent stripe trenches 307, and a plurality of first active stripe regions 3a including protective diffusion layer ground region 4 and a plurality of second active stripe regions 3b not including the protective diffusion layer ground region 4 and provided so as to be sandwiched between the active stripe regions 3 exist in the plurality of active stripe regions 3.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a trench gate type semiconductor device.

  In power electronics devices, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements for controlling power supply to loads such as motors. There is. A trench gate type semiconductor device in which a gate electrode is embedded in a semiconductor layer is present as one of such insulating gate type semiconductor devices.

  As an index representing the loss of the switching element, an on-resistance representing the electrical resistance between the main electrodes when the semiconductor device is on is known. Since the trench gate type semiconductor device can increase the channel width density as compared with a normal planar type semiconductor device, the on-resistance per unit area can be reduced.

  Furthermore, MOSFETs and IGBTs using wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) based materials and diamond are attracting attention as next-generation switching elements, and hexagonal systems such as SiC In the case of using the materials of the above, the current path of the trench gate type semiconductor device coincides with the direction of the a axis of high carrier mobility, and therefore, a significant reduction of the on resistance is expected.

  By the way, when a trench gate type semiconductor device is used for a power electronic device which requires a withstand voltage of several hundred volts to several thousand volts, there is a problem that the electric field is concentrated at the bottom of the trench and the gate insulating film is easily broken. Therefore, in order to reduce the electric field concentration at the bottom of the trench, there is widely known a technique in which a protective diffusion layer having a conductivity type opposite to that of the drift layer is provided in the drift layer at the bottom of the trench (see, for example, Patent Document 1). Patent Document 1 discloses a technique for reducing the electric field applied to the insulating film at the bottom of the trench by spreading the depletion layer from the protective diffusion layer of the second conductivity type provided at the bottom of the trench to the drift layer of the first conductivity type. It is shown.

  Furthermore, when the protective diffusion layer is at a floating potential, the response speed of the depletion layer during switching is slowed and the switching speed is slow. Therefore, when the protective diffusion layer is provided, a technique for connecting the protective diffusion layer and the source electrode is known. (See, for example, Patent Document 2). In Patent Document 2, one central cell is used as a protective contact region to which a protective diffusion layer and a source electrode are connected for every nine cells in a matrix shape separated by lattice-like gate electrodes.

JP, 2005-142243, A WO 2012-077617

  The depletion layer extending from the protective diffusion layer has a certain spread not only when blocking a high voltage between the drain and source but also when the drain and source are in a conductive state. Because of this spread, the on current path in the drift layer is narrowed, and a resistance component called a JFET (Junction FET) resistance becomes large. The ON current path is narrowed particularly between the protective diffusion layers adjacent to each other, which may contribute to an increase in ON resistance.

  When the protective diffusion layer is provided at the bottom of the gate electrode in a planar arrangement as in the patent document 2 described above, the ON current path is narrowed from four directions, and the influence of the increase in JFET resistance is particularly problematic. On the other hand, as a planar arrangement of gate electrodes, a stripe-like planar arrangement in which a plurality of gate electrodes extending in one direction are arranged in parallel is also known. When the gate electrodes are arranged in the form of stripes, the on current path is narrowed in only two directions except at the end, so that the increase in JFET resistance can be suppressed as compared with the lattice arrangement. .

  However, in the trench gate type semiconductor device in which the gate electrodes are arranged in a stripe, how to connect the protective diffusion layer and the source electrode when the protective diffusion layer is provided at the bottom of the gate electrode is conventionally known. It has not been proposed at all. For example, in the semiconductor device described in Patent Document 2 in which the protective diffusion layer and the source electrode are connected using a central cell of nine cells, part of the protection is achieved if the planar arrangement of the gate electrode is made as it is. The diffusion layer (the protective diffusion layer below the gate electrode 304 in the second, fifth, and eighth rows from the top in FIG. 22) is not connected to the source electrode, and the response at the time of switching is partially deteriorated. Could lead to problems such as

  According to the present invention, in order to solve the problems as described above, in a trench gate type semiconductor device in which gate electrodes are arranged in a stripe, a protective diffusion layer and a source electrode are securely connected to suppress a decrease in switching speed. It is an object of the present invention to provide a semiconductor device that can

  A semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, a base region of a second conductivity type provided above the semiconductor layer, a source region provided above the base region, and a base in the semiconductor layer. A gate insulating film provided in a stripe trench formed in a plurality of stripes extending up to a deeper position than the region and a gate having a side surface facing the base region provided in the stripe trench via the gate insulating film A plurality of active stripe regions separated by a plurality of stripe trenches, comprising: an electrode, a protective diffusion layer of a second conductivity type provided below the stripe trench, and a source electrode connected to the source region and the base region; Protection in which the source electrode is connected to the protective diffusion layer through the opening provided in the semiconductor layer between adjacent stripe trenches And a plurality of first active stripe regions including a protective diffusion layer ground region and a plurality of active stripe regions not including the protective diffusion layer ground region and being sandwiched by the first active stripe regions. And the provided second active stripe region is present.

  According to the semiconductor device of the present invention, the second active stripe region not including the protective diffusion layer ground region is provided sandwiched between the first active stripe region including the protective diffusion layer ground region. It is possible to connect the layer and the source electrode more reliably, and it is possible to suppress a decrease in switching speed.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is an enlarged plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. It is a top view which shows the semiconductor device concerning Embodiment 2 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 2 of this invention. It is a top view which shows the semiconductor device concerning Embodiment 3 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. It is a top view showing a semiconductor device concerning a comparative example of the present invention. It is a top view showing a semiconductor device concerning a comparative example of the present invention. It is a circuit block diagram which shows the power converter device concerning Embodiment 4 of this invention.

Embodiment 1
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a plan view showing a semiconductor device 100 according to the first embodiment, and FIG. 2 is a partial cross-sectional view of the semiconductor device 100 according to the first embodiment. It is. In this embodiment, an n-type MOSFET using silicon carbide will be described as an example.

  In FIG. 1, a semiconductor device 100 is a trench gate type MOSFET provided with gate electrodes 304 arranged in a stripe shape, and has an active stripe region 3 and a protective diffusion layer ground region 4. In FIG. 1, the gate electrodes 304 extend in one direction (left and right direction in FIG. 1), and a plurality of gate electrodes 304 are arranged in parallel at regular intervals while being spaced apart. Among the sections divided by the gate electrode 304, the minimum unit of the section in which the on current path is formed is the active stripe cell 30.

  On the other hand, active stripe regions 3 are stripe-shaped regions divided by gate electrodes 304 arranged in a stripe, and indicate rows arranged in the vertical direction in FIG. In this specification, one active stripe region 3 is a region (one row) sandwiched by adjacent stripe-shaped gate electrodes 304, and includes gate electrodes 304 on both sides. That is, the gate electrode 304 sandwiched between the adjacent active stripe regions 3 is shared by the respective active stripe regions 3. The protective diffusion layer ground region 4 is a region connecting the source electrode 5 described later and the protective diffusion layer 306. In the active stripe region 3, a region (row) including the protective diffusion layer ground region 4 is referred to as a first active stripe region 3a, and a region (row) not including the protective diffusion layer ground region 4 is referred to as a second activity. It is called stripe area 3b.

  FIG. 2 is a partial cross-sectional view including both the active stripe region 3 and the protective diffusion layer ground region 4. As shown in FIG. 2, the semiconductor device 100 includes the SiC substrate 1, the epitaxial layer 2, the ohmic electrode 301a, the source region 302, the base region 303, the gate electrode 304, the gate insulating film 305, the protective diffusion layer 306, the ohmic electrode 401a, And the drain electrode 7. The SiC substrate 1 (semiconductor substrate) is an n-type semiconductor substrate formed of silicon carbide, and the epitaxial layer 2 (semiconductor layer) is an n-type semiconductor layer grown on the SiC substrate 1. On the other hand, drain electrode 7 is formed on the back surface of SiC substrate 1.

  In the active stripe region 3, a p-type base region 303 is formed above the epitaxial layer 2, and the region of the epitaxial layer 2 excluding the base region 303 is the n-type drift layer 2 a. An n-type source region 302 is formed in part of the upper portion of the base region 303. A stripe trench 307 which penetrates the source region 302 and the base region 303 and reaches the drift layer 2 a is formed on both sides of the active stripe region 3, and a gate electrode 304 and a gate insulating film 305 are provided in the stripe trench 307. There is. The gate insulating film 305 is provided on the side surface and the bottom surface of the gate electrode 304, and the side surface of the gate electrode 304 is opposed to the base region 303 and the source region 302 via the gate insulating film 305.

  The film thickness of the gate insulating film 305 at a position corresponding to the bottom surface of the gate electrode 304 may be thicker than the film thickness at a position corresponding to the side surface of the gate electrode 304. Although the gate insulating film 305 shown in FIG. 2 has the same thickness on both the side and the bottom, only the side actually functions as a gate insulating film, and the bottom does not contribute to the operation as a MOSFET. In addition, as described above, the electric field is likely to be concentrated at the bottom of the trench, and the dielectric breakdown is likely to occur. Therefore, by selectively thickening only the gate insulating film 305 on the bottom surface of the gate electrode 304, the electric field applied to the gate insulating film 305 can be further alleviated.

  In order to ease the electric field at the bottom of the stripe trench 307, a p-type protective diffusion layer 306 is formed on the bottom of the gate electrode 304 (at the bottom of the stripe trench 307) with the gate insulating film 305 interposed therebetween. Further, an interlayer insulating film 6 having contact holes 301 and 401 is provided above the gate electrode 304.

  In the active stripe region 3, the source electrode 5 is connected (ohmic contact) to the source region 302 and the base region 303 through the contact hole 301 of the interlayer insulating film 6. More specifically, the ohmic electrode 301a is formed in the contact hole 301, and the source electrode 5 forms an ohmic contact with the source region 302 and the base region 303 via the ohmic electrode 301a.

  On the other hand, in the protective diffusion layer ground region 4, an opening penetrating the base region 303 and the source region 302 not only in the stripe trench 307 in which the gate electrodes 304 on both sides are disposed but also in the whole between the gate electrodes 304 on both sides. The part 402 is formed. That is, in the protective diffusion layer ground region 4, the stripe trench 307 in which the gate electrodes 304 on both sides are disposed and the opening 402 therebetween are integrated and provided as one opening. The protective diffusion layer 306 is formed in the protective diffusion layer ground region 4 from the bottom of one gate electrode 304 to the bottom of the other gate electrode 304 over the entire lower portion of the stripe trench 307 and the opening 402. Source electrode 5 extends from above epitaxial layer 2 to the bottom of opening 402 in protective diffusion layer ground region 4, and source electrode 5 passes through contact hole 401 of interlayer insulating film 6 at the bottom of opening 402. It is connected to the protective diffusion layer 306.

  More specifically, interlayer insulating film 6 is provided to cover the upper surface and the side surface of gate electrode 304 in opening 402 of protective diffusion layer ground region 4, and protective diffusion layer ground region 4 is formed in interlayer insulating film 6. The contact hole 401 is formed in the. An ohmic electrode 401 a is formed in the contact hole 401, and the source electrode 5 forms an ohmic contact with the protective diffusion layer 306 via the ohmic electrode 401 a. The interlayer insulating film 6 covering the side surface of the gate electrode 304 is integrally formed with the interlayer insulating film 6 covering the upper surface of the gate electrode 304, but the upper surface of the interlayer insulating film 6 covering the side surface of the gate electrode 304 and the gate electrode 304 It may be provided separately from the covering interlayer insulating film 6. The thickness of the interlayer insulating film 6 covering the side surface of the gate electrode 304 may be set appropriately, but the thickness is made larger than that of the gate insulating film 305 in order to reduce the parasitic capacitance between the gate and the source. Is desirable.

  Returning to FIG. 1, the layout of the active stripe region 3 and the protective diffusion layer ground region 4 will be described. 1 is a plan view of the surface of the epitaxial layer 2 of the semiconductor device 100 shown in FIG. 2 in order to improve the visibility, and the illustration of the source electrode 5 and the interlayer insulating film 6 on the epitaxial layer 2 is omitted. It is a plan view.

  As shown in FIG. 1, a plurality of gate electrodes 304 are provided in the form of stripes in the left-right direction of FIG. 1, and regions divided by the adjacent gate electrodes 304 are defined as active stripe regions 3. The gate electrodes 304 are spaced apart and parallel to each other in the lateral direction (vertical direction in FIG. 1) of the gate electrode 304. Further, it is desirable that the distance between the gate electrodes 304 be constant, that is, it be desirable that the length of the short side of each active stripe region 3 be constant. If active stripe regions 3 having different short side lengths coexist, the current may be concentrated on the long active stripe regions 3 on the short side. Therefore, by making the length of the short side of active stripe region 3 constant, current concentration in a part of active stripe region 3 can be suppressed.

  In FIG. 1, a part of active stripe region 3 of active stripe region 3 includes protective diffusion layer ground region 4, and as described above, active stripe region 3 including protective diffusion layer ground region 4 is Active stripe region 3 which is referred to as active stripe region 3a of 1 and which does not include protective diffusion layer ground region 4 is referred to as second active stripe region 3b.

  The first active stripe region 3a has a plurality of protective diffusion layer ground regions 4 provided spaced apart. Then, in the first active stripe region 3 a, a section divided by the two gate electrodes 304 adjacent to the protective diffusion layer ground region 4 becomes an active stripe cell 30. Active stripe cell 30 is a rectangular section whose periphery is divided by gate electrode 304 (including gate electrode 304 in protective diffusion layer ground region 4), and an active cell in which on current flows according to the potential of gate electrode 304. It is.

  FIG. 3 shows an enlarged plan view of the semiconductor device 100 according to the present embodiment around the boundary between the active stripe cell 30 and the protective diffusion layer ground region 4. As shown in FIG. 3, in the protective diffusion layer ground region 4, the gate electrode 304 and the gate insulating film 305 are formed along the short side of the active stripe cell 30. Gate electrodes 304 formed along the short sides of the active stripe cells 30 connect the gate electrodes 304 formed in adjacent stripe trenches. Therefore, protective diffusion layer ground region 4 is formed along the short side of active stripe cell 30 with gate electrode 304 (gate electrode 304 extending in the lateral direction in FIG. 3) formed in stripe trench 307. This region is divided by 304 (gate electrodes 304 extending in the vertical direction in FIG. 3).

  Since the outline of the active stripe cell 30 is rectangular as shown in FIG. 1 and FIG. 3, the narrowing of the on current path by the depletion layer extending from the protective diffusion layer 306 is Only in two directions. Therefore, the increase in JFET resistance can be suppressed as compared with the case where the gate electrode 304 is formed in a lattice type. On the other hand, in the case of such a stripe-type cell layout, the channel resistance is increased because the channel width density is reduced. Therefore, the on-resistance can be reduced as compared to the lattice layout by determining the outline of the active stripe cell 30 so that the reduction in JFET resistance relative to the lattice cell layout exceeds the increase in channel resistance. it can. Specifically, the long side of the active stripe cell 30 is preferably 1.5 or more, and more preferably 2.0 or more with respect to the short side.

  On the other hand, since the second active stripe region 3 b does not include the protective diffusion layer ground region 4, the entire second active stripe region 3 b becomes one active stripe cell 30. In the present embodiment, as shown in FIG. 1, the first active stripe regions 3 a and the second active stripe regions 3 b are alternately arranged in the short side direction of the active stripe region 3.

  As shown in FIG. 1, it is desirable that the protective diffusion layer ground regions 4 be arranged at regular intervals. In the present embodiment, the general shape of protective diffusion layer ground region 4 is substantially square, but may be any shape such as another polygon, and the length of each side is also the short side of active stripe region 3. It does not have to be equal to the length. However, in order to make the short side of active stripe region 3 the same in all active stripe regions 3, it is preferable that one side of protective diffusion layer ground region 4 be an integral multiple of the short side of active stripe region 3.

  Next, the operation of the semiconductor device 100 will be described. The semiconductor device 100 switches between the on state and the off state by a voltage applied to the gate electrode 304. When a voltage (for example, a voltage of 20 V or more) is applied to the gate electrode 304 with the source electrode 5 as a reference potential, a channel region is formed in the base region 303 opposite to the side surface of the gate electrode 304. As a result, the drain electrode 7 and the source electrode 5 are electrically connected to each other through the channel region to be turned on. On the other hand, when a voltage (for example, a voltage of 0 V) less than the threshold voltage is applied to the gate electrode 304 with the source electrode 5 as a reference potential, a channel region is formed in the base region 303 facing the side surface of the gate electrode 304 Thus, the space between the drain electrode 7 and the source electrode 5 is cut off. As a result, the semiconductor device 100 is turned off.

  The semiconductor device 100 switches between the on state and the off state described above according to the voltage applied to the gate electrode 304, and implements the switching operation. By the way, in the semiconductor device 100, a parasitic capacitance called depletion capacitance exists between the protective diffusion layer 306 and the drift layer 2a. Then, at the time of switching between the on state and the off state of the semiconductor device 100, the parasitic capacitance between the protective diffusion layer 306 and the drift layer 2a is charged and discharged. It will affect 100 switching characteristics (speed, loss, etc.). In the semiconductor device 100, since the protective diffusion layer 306 provided under the stripe trench 307 is connected to the source electrode 5 through at least one of the protective diffusion layer ground regions 4, the source electrode is connected through the protective diffusion layer ground region 4 A charge / discharge current of parasitic capacitance flows between the point 5 and the protective diffusion layer 306.

  Subsequently, a method of manufacturing the semiconductor device 100 will be described. 4 to 10 are cross-sectional views showing steps of the method of manufacturing the semiconductor device 100. First, as shown in FIG. In the following description, materials, dimensions, and the like of each component are merely examples, and the present invention is not limited thereto.

In FIG. 4, epitaxial layer 2 (semiconductor layer) is formed on SiC substrate 1. Here, an n-type low-resistance SiC substrate 1 having a polytype of 4H is prepared, and an n-type epitaxial layer 2 is epitaxially grown thereon by a chemical vapor deposition (CVD) method. The epitaxial layer 2 has an n-type impurity concentration of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ and a thickness of 5 to 200 μm. The surface of the SiC substrate 1 is a surface having an angle (off angle) of 4 ° to the (0001) plane which is the c-plane of the SiC crystal.

  Next, in FIG. 4, a base region 303 and a source region 302 are formed by ion implantation of a predetermined dopant on the surface of the epitaxial layer 2.

The base region 303 is formed by ion implantation of aluminum (Al) which is a p-type impurity. The depth of the ion implantation of Al is about 0.5 to 3.0 μm within the range not exceeding the thickness of the epitaxial layer 2. The impurity concentration of Al to be implanted is made higher than the n-type impurity concentration of the epitaxial layer 2. Specifically, the p-type impurity concentration of the base region 303 is in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . At this time, the region of the epitaxial layer 2 deeper than the implantation depth of Al becomes the n-type drift layer 2a. The base region 303 may be formed by p-type epitaxial growth. Also in such a case, the impurity concentration and thickness of the base region 303 are made equal to those formed by ion implantation.

The source region 302 is formed by ion implantation of nitrogen (N), which is an n-type impurity, in a part of the surface of the base region 303. The planar pattern of the source region 302 is formed in a pattern corresponding to the layout of the gate electrode 304 formed in the process described later. Specifically, when the gate electrode 304 is formed, the planar arrangement of the source region 302 is determined so that the source region 302 is disposed on both sides of the gate electrode 304. The ion implantation depth of N is shallower than the thickness of the base region 303. The impurity concentration of N to be implanted is higher than the p-type impurity concentration of the base region 303 and in the range of 1 × 10 ²¹ cm ⁻³ or lower. The order of ion implantation may not be as described above if the structure of the semiconductor device 100 shown in FIG. 2 is finally obtained, and boron (B) may be used as a p-type impurity and phosphorus as an n-type impurity. (P) may be used (the same applies to the following injection steps).

  Further, a depletion suppression layer (not shown) having a higher n-type impurity concentration than the drift layer 2a may be provided under the base region 303. In the structure shown in FIG. 2, the current path is narrowed by the depletion layer extending from both the base region 303 and the protective diffusion layer 306, and a so-called JFET resistance is generated therebetween. When the depletion suppression layer is provided as described above, extension of the depletion layer from the base region 303 can be suppressed when the semiconductor device 100 is turned on, so that the JFET resistance can be reduced.

The depletion suppression layer is formed by ion implantation of nitrogen (N) or phosphorus (P) which is an n-type impurity. The depth of the depletion suppression layer is preferably in the range of about 0.5 to 3 μm within the range that is deeper than the base region 303 and does not exceed the thickness of the epitaxial layer 2. The impurity concentration of N to be implanted is preferably higher than the n-type impurity concentration of the epitaxial layer 2 and is 1 × 10 ¹⁷ cm ⁻³ or more. The depletion suppression layer may be formed by n-type epitaxial growth. In such a case, the impurity concentration and thickness of the depletion suppression layer are equal to those formed by ion implantation. In addition, the depletion suppression layer may be a planar pattern in which only the central portion of the active stripe cell 30 is removed.

  In FIG. 5, a silicon oxide film 8 is deposited on the surface of the epitaxial layer 2 to a thickness of about 1 to 2 μm, and an etching mask 9 made of a resist material is formed on the silicon oxide film 8. The etching mask 9 is formed in a pattern opened corresponding to the formation region of the trench by photolithography. Then, the silicon oxide film 8 is patterned by reactive ion etching (RIE) processing using the etching mask 9 as a mask. Thereby, the pattern of the etching mask 9 is transferred to the silicon oxide film 8. The patterned silicon oxide film 8 serves as an etching mask in the next step.

  In FIG. 6, a stripe trench 307 and an opening 402 are formed in the epitaxial layer 2 through the source region 302 and the base region 303 by RIE using the patterned silicon oxide film 8 as a mask. The depth of the trench is equal to or greater than the depth of the base region 303, and is about 1.0 to 6.0 μm. Also, the planar pattern of the trench corresponds to the planar pattern of the combination of the gate electrode 304 and the gate insulating film 305 in FIG. More specifically, a plurality of stripe trenches 307 provided in the form of stripes are provided so as to define active stripe region 3, and between adjacent stripe trenches 307 only in the region corresponding to protective diffusion layer ground region 4. An opening 402 is formed, and the entire protective diffusion layer ground region 4 is etched. In the present specification, the stripe trench 307 defining the active stripe region 3 and the opening 402 formed in the protective diffusion layer ground region 4 are collectively referred to as a trench.

  In addition, it is desirable that stripe trench 307 (active stripe region 3) be disposed parallel to the step flow of epitaxial layer 2 formed by the off angle of SiC substrate 1. In the active region where the on current path is formed, a portion adjacent to the gate electrode 304 in the active stripe region 3 functions as a MOSFET. When the stripe trench 307 is disposed parallel to the off angle of the SiC substrate 1, no atomic layer step occurs at the interface between the gate insulating film 305 and SiC (epitaxial layer 2), but is disposed vertically An atomic layer step occurs at the interface. The presence of the atomic layer step affects the number of interface states, and by arranging the stripe trench 307 in parallel to the step flow of the epitaxial layer 2, the gate breakdown voltage can be increased.

In FIG. 7, a pattern having an opening at a portion of the trench, that is, an implantation mask 10 having the same pattern as the etching mask 9 is formed, and ion implantation is performed using the implantation mask 10 as a mask. Form Here, Al is used as a p-type impurity. The impurity concentration of Al to be implanted is preferably in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ and the thickness is in the range of 0.1 to 2.0 μm. The Al impurity concentration of the protective diffusion layer 306 is determined from the electric field applied to the gate insulating film 305 when a working breakdown voltage is applied between the drain and source of the MOSFET. Instead of the implantation mask 10, a (patterned) silicon oxide film 8 may be used, which is an etching mask for trench formation. Thereby, simplification of the manufacturing process and cost reduction can be achieved. When silicon oxide film 8 is used instead of implantation mask 10, it is necessary to adjust the thickness and etching conditions of silicon oxide film 8 so that silicon oxide film 8 having a sufficient thickness remains after forming the trench. There is.

  After the implantation mask 10 is removed, annealing is performed using a heat treatment apparatus to activate the impurity implanted in the above step. The annealing treatment is performed in an inert gas atmosphere such as argon (Ar) gas or in vacuum under the conditions of 1300 to 1900 ° C. for 30 seconds to 1 hour.

  In FIG. 8, a silicon oxide film 11 is formed on the entire surface of the epitaxial layer 2 including the inside of the trench, and then a polysilicon film 12 is deposited by a low pressure CVD method. Then, in FIG. 9, the gate insulating film 305 and the gate electrode 304 are formed in the stripe trench 307 by patterning or etching back the silicon oxide film 11 and the polysilicon film 12. The silicon oxide film 11 to be the gate insulating film 305 may be formed by thermally oxidizing the surface of the epitaxial layer 2 or may be formed by deposition on the epitaxial layer 2.

  In FIG. 10, the interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 2 by the low pressure CVD method, and the gate electrode 304 is covered with the interlayer insulating film 6. By patterning interlayer insulating film 6, contact hole 301 reaching source region 302 and base region 303 is formed in active stripe region 3, and contact hole 401 reaching protective diffusion layer 306 in protective diffusion layer ground region 4 is formed. Form. Then, ohmic electrodes 301 a and 401 a are formed on the surface of epitaxial layer 2 exposed at the bottom of contact holes 301 and 401. As a method of forming the ohmic electrodes 301a and 401a, for example, a metal film containing Ni as a main component is formed on the entire surface of the epitaxial layer 2 including the inside of each contact hole, and reacted with silicon carbide by heat treatment at 600-1100.degree. A silicide film to be an ohmic electrode is formed.

  Thereafter, an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 5 on the interlayer insulating film 6 and in the contact holes 301 and 401 (not shown). Finally, an electrode material such as an Al alloy is deposited on the lower surface of the SiC substrate 1 to form the drain electrode 7 (not shown). Through the above steps, the semiconductor device 100 shown in FIG. 2 is obtained.

  Next, the effects of the semiconductor device 100 according to the present embodiment will be described. 21 and 22 show comparative examples of the semiconductor device 100 according to the present embodiment. FIG. 21 shows a semiconductor device 200 in which a protective diffusion layer ground region 4 is provided in the center of nine sections in a grid type layout in which gate electrodes 304 are arranged in a grid as shown in Patent Document 2. It shows. FIG. 22 shows a semiconductor device 300 in which the gate electrode 304 is replaced with a stripe-like layout in the semiconductor device 200 shown in FIG.

  In the semiconductor device 200 shown in FIG. 21, the active cells divided by the grid-like gate electrodes 304 are surrounded by the gate electrodes 304 in four directions, and thus extend from the protective diffusion layer 306 provided at the bottom of each gate electrode 304. Due to the influence of the depletion layer, the on current path is narrowed in four directions, which may cause an increase in on resistance. Therefore, when the layout of the gate electrode 304 is changed from the lattice type to the stripe type in order to suppress such an increase in on-resistance, the semiconductor device 300 shown in FIG. 22 is obtained. In the semiconductor device 300, since the narrowing of the on current path is from only two directions except near the short side of the active stripe cell 30, the on current path can be broadened, and the on resistance can be reduced.

  However, in the semiconductor device 300 shown in FIG. 22, there is a region in which the second active stripe regions 3b not including the protective diffusion layer ground region 4 are aligned, and stripe trenches 307 between the adjacent second active stripe regions 3b. More specifically, stripe trenches 307 in the second, fifth, and eighth rows from the top in FIG. 22 are not in contact with protective diffusion layer ground region 4. Therefore, the protective diffusion layer 306 provided under the stripe trench 307 is not connected to the protective diffusion layer ground region 4 either. Then, the potential of the protective diffusion layer 306 not in contact with the protective diffusion layer ground region 4 is floating, and the response speed of the depletion layer is delayed compared to other protective diffusion layers 306 at the time of transient response. As a result, there is a possibility that an increase in switching loss, a characteristic variation in the semiconductor device 300, and a breakdown of the gate insulating film due to current concentration at high speed operation may result.

  In the semiconductor device 100 according to the present embodiment, the first active stripe region 3 a including the protective diffusion layer ground region 4 and the second active stripe region 3 b not including the protective diffusion layer ground region 4 correspond to the active stripe region 3. The second active stripe regions 3 b not including the protective diffusion layer ground region 4 are sandwiched between the first active stripe regions 3 a including the protective diffusion layer ground region 4 because they are alternately arranged in the short direction of Thus, all the stripe trenches 307 are connected to the protective diffusion layer ground region 4. As a result, there is no place where the protective diffusion layer 306 provided in the lower part of the stripe trench 307 becomes floating, and the increase in switching loss, the characteristic variation in the semiconductor device 300, and the current concentration at high speed operation The problem of destruction can be suppressed.

  Therefore, in the semiconductor device 100 according to the present embodiment, the layout of the gate electrodes 304 is in the form of stripes to widen the on current path and reduce the on resistance, and part of the protective diffusion layer 306 is in a floating state. It is possible to suppress the problem of an increase in switching loss, a variation in characteristics in the semiconductor device 100, and a breakdown of the gate insulating film 305 due to current concentration at high speed operation.

  Further, since the distance in which the depletion layer extends increases with the temperature rise, in the trench gate type semiconductor device provided with the protective diffusion layer 306, the JFET resistance increases with the temperature rise. In the semiconductor device 100 according to the present embodiment, by forming the gate electrodes 304 in a stripe layout, the current path is wider than in the grid layout, and therefore, the increase in JFET resistance with temperature rise is moderate. And temperature characteristics of the on-resistance (variations associated with temperature change) can be improved.

  Further, in the semiconductor device 100 according to the present embodiment, the source electrode 5 and the protective diffusion layer 306 are connected in the protective diffusion layer ground region 4. Unlike the semiconductor device 100 according to the present embodiment, an opening may be partially provided between the gate electrodes 304 on both sides in the protective diffusion layer ground region 4, but the protective diffusion layer may be grounded as in the present embodiment. By providing an opening between the gate electrodes 304 on both sides in the region 4 and connecting the source electrode 5 and the protective diffusion layer 306 in the opening 402, the contact area is expanded, and the source electrode 5 and the protective diffusion layer It is possible to reduce the contact resistance with 306.

  Furthermore, in the protective diffusion layer ground region 4, the position in the depth direction where the source electrode 5 and the protective diffusion layer 306 are in contact may be changed as appropriate, but as in the semiconductor device 100 according to the present embodiment, It is desirable that the source electrode 5 extend to the bottom of the opening 402 deeper than the base region 303 in the opening 402 of the protective diffusion layer ground region 4 and be connected to the protective diffusion layer 306 at the bottom of the opening 402 . When connecting the source electrode 5 and the protective diffusion layer 306 in the protective diffusion layer ground region 4, the protective diffusion layer 306 can be formed on the surface of the epitaxial layer 2 and connected to the source electrode 5, etc. The source electrode 5 having a resistivity lower than that of the diffusion layer 306 is extended to the bottom of the opening 402, and the source electrode 5 and the protective diffusion layer 306 are connected, so that the space between the protective diffusion layer 306 and the source electrode 5 is The resistance can be reduced and the switching loss can be reduced.

  Further, in the semiconductor device 100 according to the present embodiment, the interlayer insulating film 6 covering the side surface of the gate electrode 304 is thicker than the gate insulating film 305 in the opening 402 of the protective diffusion layer ground region 4. The parasitic capacitance between the gate and the source can be reduced, and the switching characteristics (loss, time, etc.) can be improved.

  The semiconductor device 100 according to the present embodiment can be appropriately modified or changed without departing from the spirit of the present invention. Therefore, a modified example of the semiconductor device 100 according to the present embodiment is shown using FIGS. 11 to 13 are plan views showing modified examples of the semiconductor device 100 according to the present embodiment. Hereinafter, only differences from the semiconductor device 100 according to the present embodiment will be described.

  In the semiconductor device 101 shown in FIG. 11, the base region 303 exposed in the contact hole 301 in the active stripe region 3 is divided into a plurality of regions in comparison with the semiconductor device 100 according to the present embodiment. The only difference is that it has been changed to In the semiconductor device 100 shown in FIG. 1, the base region 303 exposed in the contact hole 301 is made into a single rectangular shape corresponding to the shape of the active stripe cell 30 which is rectangular. On the other hand, in the semiconductor device 101 shown in FIG. 11, in the active stripe cell 30 having a rectangular shape, the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is made of a plurality of square regions, It is spaced apart and provided.

  When the gate electrodes 304 have a stripe-like layout as in the semiconductor device 100 shown in FIG. 1, the reduction in channel width density can be suppressed by reducing the pitch in the short side direction of the active stripe region 3. However, reducing the distance between the contact hole 301 and the gate electrode 304 may increase the gate-source leakage rate, so a certain distance between the contact hole 301 and the gate electrode 304 is secured. There is a need. Therefore, to reduce the pitch on the short side of active stripe region 3, it is necessary to reduce the size of contact hole 301, but reducing the size of the contact hole leads to an increase in contact resistance. Although the channel resistance can be reduced, the contact resistance is increased.

  Therefore, by reducing the occupied area of the base region 303 in the contact hole 301 and increasing the source region 302, the contact area between the source region 302 and the source electrode 5 can be increased, and the contact resistance can be reduced. In semiconductor device 101 shown in FIG. 11, base region 303 exposed on the surface of epitaxial layer 2 in contact hole 301 is divided into a plurality of regions, and source region 302 is separated between the plurality of divided base regions 303. Is exposed. Therefore, compared to the semiconductor device 100 shown in FIG. 1, the area of the source region 302 in the contact hole 301 can be increased, and the contact resistance between the source region 302 and the source electrode 5 can be reduced. However, if there is a concern that the response of the base region 303 during switching may be delayed if the area of the base region 303 is too small, the occupied area of the base region 303 in the contact hole 301 is desirably 20% or more.

  Note that, in manufacturing the semiconductor device 101 shown in FIG. 11, the layout of the mask for transferring the pattern at the time of forming the base region 303 or the source region 302 may be simply changed, and the number of steps is not increased.

  In the semiconductor device 102 shown in FIG. 12, the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is formed of a plurality of rectangular regions and provided at predetermined intervals. Each of the exposed base regions 303 extends from one of the adjacent stripe trenches 307 to the other in the direction of the short side of the active stripe region 3.

  When the pitch in the short side direction of active stripe region 3 is reduced, if contact hole 301 is displaced in the short side direction of active stripe region 3, the change in the occupied area of source region 302 in contact hole 301 becomes remarkable. As a result, there is a concern that the variation in the on-resistance of each active stripe cell 30 may increase. In the semiconductor device 102 shown in FIG. 12, since each of the base regions 303 exposed on the surface is uniformly provided in the short side direction of the active stripe region 3 between the stripe trenches 307, the short of the active stripe region 3 is Even when the position of the contact hole 301 is shifted in the side direction, the area of the source region 302 occupied in the contact hole 301 does not change. Therefore, the pitch in the short side direction of the active stripe region 3 can be further reduced, and the on-resistance can be reduced.

  In the semiconductor device 103 shown in FIG. 13, the composition ratio of the first active stripe region 3a to the second active stripe region 3b is 2: 1. More specifically, in the direction of the short side of active stripe region 3, two first active stripe regions 3a are arranged, and second active stripe region 3b is arranged one by three, with the three active stripe regions 3 as a minimum unit, and repeatedly arranged. It is. Further, the width of the protective diffusion layer ground region 4 in the direction of the short side of the active stripe region 3 is twice the width of the short side of the active stripe region 3, relative to the two adjacent first active stripe regions 3 a. A common protective diffusion layer ground region 4 is provided. The composition ratio of the first active stripe region 3a to the second active stripe region 3b is not limited to 2: 1 and can be set as appropriate. At this time, the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 corresponds to the composition ratio of the first active stripe region 3a and the second active stripe region 3b. If the width of the short side of the active stripe region 3 is an integral multiple of the width of the short side of the active stripe region 3, the short sides of the active stripe region 3 can be equally disposed.

  In the semiconductor device 100 shown in FIG. 1, the first active stripe region 3a including the protective diffusion layer ground region 4 and the second active stripe region 3b not including the protective diffusion layer ground region 4 are alternately arranged. The arrangement of the first active stripe region 3a and the second active stripe region 3b is not limited to this. As shown in FIG. 13, one second active stripe area 3b may be provided for each of the plurality of first active stripe areas 3a. At this time, as shown in FIG. 22, when the second active stripe regions 3b are adjacent to each other, the protective diffusion layer 306 provided under the stripe trench 307 between the second active stripe regions 3b is floated. There is a risk of Therefore, as shown in FIG. 13, the first active stripe area 3a is adjacent to both sides of each second active stripe area 3b, and the second active stripe area 3b is sandwiched by the first active stripe area 3a. Arrange as. Accordingly, floating of some of the protective diffusion layers 306 can be suppressed.

  According to the present embodiment, the second active stripe region 3 b not including the protective diffusion layer ground region 4 is disposed so as to be sandwiched by the first active stripe region 3 a including the protective diffusion layer ground region 4. Floating of some protective diffusion layers 306 can be suppressed, and deterioration of switching characteristics can be suppressed.

Second Embodiment
FIG. 14 is a plan view showing a semiconductor device 110 according to the second embodiment of the present invention. Hereinafter, in the present embodiment, parts different from the first embodiment will be described, and the description of the same or corresponding parts will be omitted. In FIG. 14, the same reference numerals as in FIG. 1 indicate the same or corresponding configurations. The present embodiment is different from the first embodiment in that a crossing trench 308 intersecting the stripe trench 307 is provided.

  In the first embodiment, the first active stripe region 3 a including the protective diffusion layer ground region 4 is disposed adjacent to both sides of the second active stripe region 3 b not including the protective diffusion layer ground region 4. The second active stripe regions 3 b are adjacent to each other, and the protective diffusion layer 306 provided under the stripe trench 307 between the second active stripe regions 3 b is prevented from floating. On the other hand, as in the semiconductor device 300 shown in FIG. 22, even in the structure in which the second active stripe regions 3b are adjacent to each other, the second active stripe region is provided by providing the crossing trenches 308 crossing the stripe trenches 307. The protective diffusion layer 306 provided in the lower part of the stripe trench 307 between 3 b can be connected to the source electrode 5.

  In the present embodiment, as shown in FIG. 14, an intersecting trench 308 intersecting the stripe trench 307 in a direction perpendicular to the longitudinal direction of the stripe trench 307 is provided. Like the other trenches, the gate electrode 304 and the gate insulating film 305 are disposed in the intersection trench, and the protective diffusion layer 306 is provided also in the lower part of the intersection trench. Cross trenches are respectively provided between adjacent two protective diffusion layer ground regions 4 and extend toward the short side of active stripe region 3. More specifically, cross trench 308 is provided between adjacent protective diffusion layer ground regions 4 so as to connect two protective diffusion layer ground regions 4 adjacent in the direction of the short side of active stripe region 3. Between the protective diffusion layer ground region 4 and the stripe trench 307 sandwiched by the second active stripe region 3 b.

  In the semiconductor device 300 shown in FIG. 22, the protective diffusion layer 306 provided under the stripe trench 307 sandwiched by the second active stripe region 3b is in a floating state, but in the semiconductor device 110 according to the present embodiment. The protective diffusion layer 306 in the lower portion of the stripe trench sandwiched by the second active stripe region 3 b is also connected to the protective diffusion layer ground region 4 through the protective diffusion layer 306 provided in the lower portion of the intersection trench 308. Become. Therefore, the protective diffusion layer 306 can be more reliably connected to the source electrode 5, and therefore, the increase in switching loss, the characteristic variation in the semiconductor device 300, and the breakdown of the gate insulating film due to the current concentration at high speed operation It can be suppressed.

  Further, in the semiconductor device 110 according to the present embodiment, the channel is formed also on the side surface of the crossing trench 308 by providing the crossing trench 308 in which the gate electrode 304 is disposed, so the channel width density is improved. And the on-resistance can be reduced. On the other hand, providing the crossing trench 308 narrows the length of the long side of the active stripe cell 30, and may increase the JFET resistance due to the depletion layer extending from the protective diffusion layer 306. The active stripe cell 30 is set to at least a stripe shape (rectangular shape). Preferably, the length of the long side of the active stripe cell 30 is 1.5 times or more of the length of the short side, more preferably 2. It is set to be 0 times or more.

  In the semiconductor device 200 shown in FIG. 21, since the gate electrode of the lattice type is disposed, if at least one protective diffusion layer ground region 4 is provided, all the protective diffusion layers 306 provided under the gate electrode 304. Is inevitably connected to the source electrode 5, but the depletion layer from the protective diffusion layer 306 extends from four directions in each active cell, increasing the resistance of the JFET and leading to the increase of the on-resistance. On the other hand, in order to suppress such an increase in on-resistance, as shown in FIG. 22, when gate electrode 304 is directly changed to a stripe-like layout in the structure of semiconductor device 200 of FIG. As described above, it becomes floating and causes deterioration of switching characteristics and the like.

  In the present embodiment, the protective diffusion layers 306 provided under the stripe trench 307 are connected to each other through the protective diffusion layer 306 provided under the intersection trench 308, whereby some of the protective diffusion layers 306 are formed. By setting the distance between the crossing trenches 308 so that the active stripe cells 30 maintain the stripe shape while suppressing the floating, the increase in the JFET resistance can be suppressed, and the on-resistance can be reduced.

  Further, the configuration in which the cross trench 308 is provided is not limited to the structure in which the second active stripe regions 3b are adjacent to each other as in the present embodiment, and, for example, as in the first embodiment In the layout in which the stripe regions 3a and the second active stripe regions 3b are alternately arranged, the crossing trench 308 may be provided.

  FIG. 15 shows a semiconductor device 111 according to a modification of the present embodiment. In FIG. 15, similarly to the first embodiment, the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short side direction, and the second active stripe region 3b is In the present embodiment, crossing trenches 308 are provided at regular intervals in the long side direction of the active stripe region 3. Further, in FIG. 15, a cross trench 308 is provided for each protective diffusion layer ground region 4, and one end of each cross trench 308 is connected to the protective diffusion layer ground region 4. Even in the configuration in which the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short direction, the cross trench 308 is provided to improve the channel width density and increase the on resistance. It can be reduced.

  According to the present embodiment, the deterioration of the switching characteristics can be suppressed by connecting the stripe trench 307 that can be floating and the protective diffusion layer ground region 4 by the crossing trench 308. Further, by providing the cross trench 308, it is possible to form a channel region on the side surface of the cross trench 308, so it is possible to improve the channel width density and reduce the on resistance.

Third Embodiment
FIG. 16 is a plan view showing a semiconductor device 120 according to the third embodiment of the present invention. Hereinafter, in the present embodiment, parts different from the first embodiment will be described, and description of the same or corresponding parts will be omitted. In FIG. 16, ones given the same reference numerals as in FIG. 1 indicate the same or corresponding configurations. The present embodiment is different from the first embodiment in that protective diffusion layer ground regions 4 are provided in all active stripe regions 3.

  In FIG. 16, the protective diffusion layer ground region 4 is provided in each of the plurality of active stripe regions 3, that is, only the first active stripe region 3 a including the protective diffusion layer ground region 4 is formed. The protective diffusion layer ground region 4 of each active stripe region 3 is continuously formed in the short side direction of the active stripe region 3. In other words, the protective diffusion layer ground region 4 in the present embodiment is formed by one stripe-shaped opening extending in the direction of the short side of the active stripe region 3 (vertical direction in FIG. 16). A plurality of stripe-shaped protective diffusion layer ground regions 4 are provided at regular intervals in the longitudinal direction of the active stripe region 3.

  Gate electrodes 304 are provided (not shown) on both side surfaces of the stripe-shaped opening (protective diffusion layer ground region 4) extending in the vertical direction in FIG. Therefore, a plurality of gate electrodes 304 provided in stripe trench 307 extending in the lateral direction of FIG. 16 and defining active stripe cell 30 are connected to each other by gate electrodes 304 provided in protective diffusion layer ground region 4. It will be Along with this, the protective diffusion layers 306 provided under the stripe trench 307 (gate electrode 304) are connected to each other by the protective diffusion layer 306 provided under the opening 402 in the protective diffusion layer ground region 4; It is connected to the source electrode 5 in the protective diffusion layer ground region 4.

  In the semiconductor device 120 according to the present embodiment, since the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, a part of the protective diffusion layer 306 is floated to suppress deterioration of the switching characteristics. be able to. Further, in the case of the present embodiment, the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, but the ratio of the protective diffusion layer ground region 4 is relatively increased as compared to the first embodiment. There is a risk of Since no on current path is formed in the protective diffusion layer ground region 4, if the protective diffusion layer ground region 4 is made dense, the on current path may be narrowed and the on resistance may increase. Therefore, it is desirable to make the distance between the protective diffusion layer ground regions 4 larger than that in the first embodiment, and set the ratio of the area occupied by the protective diffusion layer ground region 4 to such a degree that there is no problem with the on resistance. It is desirable to do.

  On the other hand, in the semiconductor device 120 according to the present embodiment, the gate electrode 304 in the stripe trench 307 is divided independently in the lateral direction by the striped protective diffusion layer ground region 4 extending in the vertical direction in FIG. Therefore, the gate resistance may be increased. Therefore, in order to reduce the gate resistance, it is preferable that the protective diffusion layer ground regions 4 included in each active stripe region 3 are not formed adjacent to each other. FIG. 17 is a plan view of a semiconductor device 121 according to a modification of the present embodiment. In the semiconductor device 121 shown in FIG. 17, the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, and the protective diffusion layer ground region 4 included in each active stripe region 3 is provided to reduce gate resistance. They are spaced apart at regular intervals. A gate electrode 304 is disposed along each side of the square protective diffusion layer ground region 4. As a result, the gate electrode 304 is not divided by the protective diffusion layer ground region 4, and therefore, an increase in gate resistance can be suppressed.

  Further, in the present embodiment, the protective diffusion layer ground region 4 of each adjacent active stripe region 3 is formed continuously and formed by one stripe-shaped opening, but the protective diffusion layer ground region 4 May be divided into a plurality of sections. FIG. 18 shows a modification in which the protective diffusion layer ground region 4 is divided into a plurality of sections in the semiconductor device 120 according to the present embodiment. In the semiconductor device 122 shown in FIG. 18, the protective diffusion layer ground region 4 is formed of a plurality of spaced square sections, and a plurality of rows in which the protective diffusion layer ground regions 4 are arranged in a row are provided. . The active stripe cells 30 are formed between the columns of the protective diffusion layer ground region 4.

  In FIG. 18, square-shaped active cells 31 are provided between the plurality of sections constituting the protective diffusion layer ground region 4. The side in the short side direction of the active stripe region 3 in the active cell 31 is formed of two crossing trenches 308 crossing the stripe trench 307, and the gate electrode 304 and the gate insulating film 305 are disposed inside the crossing trench 308. A protective diffusion layer 306 is provided in the lower part of the crossing trench 308. In addition, a trench extending in the longitudinal direction of the active stripe region 3 is provided at the boundary between the active cell 31 and the protective diffusion layer ground region 4, and a gate electrode 304 is provided inside the trench. As described above, by providing the active cell 31 having a planar shape different from that of the active stripe cell 30 in a part of the region where the protective diffusion layer ground region 4 is formed, the on current path is increased, and the channel width density is also increased. The on-resistance can be reduced to improve.

  In the present specification, the active stripe cell 30 is also referred to as a first active cell, and the active cell 31 is also referred to as a second active cell. If it is intended to constitute only a single-shaped active cell and a protective diffusion layer ground region, it may be difficult to sufficiently adjust the proportion of the active cell in the entire semiconductor device. Therefore, in the semiconductor device 122 shown in FIG. 18, the first active cell (30) in a stripe shape and the second active cell (31) in a square shape different in planar shape from the first active cell are provided. The on-resistance can be reduced because the space in the planar direction can be fully utilized and the area that can be utilized as the on-current path can be increased.

  Further, in the semiconductor device 122 shown in FIG. 18, the boundary between the protective diffusion layer ground region 4 and the active cell 31 is a half cycle of the pitch in the short side direction of the active stripe cell 30 with respect to the boundary between the active stripe cells 30. The protective diffusion layer ground region 4 is provided so as to be shifted by an amount. Although each active stripe region 3 includes a partial (half) region of the protective diffusion layer ground region 4, the protective diffusion layer ground region 4 is referred to as “active stripe region 3” in this specification. The configuration “included” also includes one in which the active stripe region 3 includes a part of the protective diffusion layer ground region 4 as described above. Also in the semiconductor device 122 shown in FIG. 18, the gate electrode 304 is integrally formed without being divided, so that an increase in gate resistance can be suppressed.

  Further, in any of the configurations described above, the protective diffusion layer ground region 4 has a square shape, but is not limited to this. FIG. 19 shows a semiconductor device 123 in which the planar shape of the protective diffusion layer ground region 4 in the semiconductor device 122 shown in FIG. 18 is rectangular. As shown in FIG. 19, the protective diffusion layer ground region 4 may be rectangular. In FIG. 19, the protective diffusion layer ground region 4 has the same shape as the active stripe cell 30, and accordingly, the active cell 31 provided between the protective diffusion layer ground regions 4 also has a rectangular shape similar to the active stripe cell 30. It becomes a state.

  Furthermore, the protective diffusion layer ground region 4 and the active stripe cell 30 are not limited to the square shape, and may be configured in a polygonal shape such as a hexagon. FIG. 20 shows a semiconductor device 124 in which the planar shapes of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 in the semiconductor device 122 shown in FIG. 18 are hexagonal. As shown in FIG. 20, the protective diffusion layer ground region 4 and the active cell 31 are formed in a regular hexagonal shape, and the active stripe cell 30 has a regular hexagonal shape extending in one direction along the stripe trench 307. In addition, as shown in FIG. 20, protective diffusion layer ground region 4, active stripe cell 30 and active cell 31 are separated by a cross trench 308 crossing stripe trench 307. Furthermore, in FIG. 20, the plane orientation of the side wall of epitaxial layer 2 formed by crossing trench 308 having an obtuse angle with respect to stripe trench 307 is constituted by a plane equivalent to the (10-10) plane. This makes it possible to reduce the influence of the off angle and to suppress the decrease in gate breakdown voltage.

  When the active stripe cell 30 having a shape different from a rectangle, such as a hexagonal shape shown in FIG. 20, is arranged, the ratio of the long side to the short side of the active stripe cell 30 is the distance between the long sides of the active stripe cell 30 It can be considered as a short side and calculated. And, even if the shape of the active stripe cell 30 changes, the ratio of the long side to the short side is preferably 1.5 or more, more preferably 2.0 or more.

  As shown in FIG. 20, the crossing trench 308 provided in the second embodiment does not necessarily need to be orthogonal to the stripe trench 307, and the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31. Accordingly, it may be provided.

  In the present embodiment, the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, so that a part of the protective diffusion layer 306 is prevented from floating to suppress the deterioration of the switching characteristics and the like. be able to.

  In the description of the first to third embodiments described above, although the MOSFET having a structure in which the drift layer 2a and the SiC substrate 1 (buffer layer) have the same conductivity type is described, the conductivity type in which the drift layer 2a and the SiC substrate 1 are different is described. The present invention is also applicable to an IGBT having a structure having For example, when the SiC substrate 1 is a p-type substrate in the semiconductor device 100 shown in FIG. In that case, the source region 302 and the source electrode 5 of the MOSFET correspond to the emitter region and the emitter electrode of the IGBT, respectively, and the drain electrode 7 of the MOSFET corresponds to the collector electrode of the IGBT. The source region and the source electrode in the present specification include an emitter region and an emitter electrode, and the drain electrode also includes a collector electrode. In the case of forming an IGBT, the n-type SiC substrate to be the substrate may be deleted and a p-type region formed by ion implantation in the epitaxial layer 2 may be used as the p-type substrate.

  In the first to third embodiments, a semiconductor device formed using SiC, which is one of wide band gap semiconductors, has been described. However, other wide band gap semiconductors such as gallium nitride (GaN) based material, diamond, etc. The present invention can also be applied to semiconductor devices using a semiconductor device or semiconductor devices using a silicon semiconductor. Furthermore, although the n-type insulated gate semiconductor device is described as an example in the above embodiment, the present invention may be applied to a p-type insulated gate semiconductor device. Note that in this specification, a wide band gap semiconductor is a semiconductor having a wider band gap than at least a silicon semiconductor.

Fourth Embodiment
The present embodiment is an application of the semiconductor device according to the above-described first to third embodiments to a power conversion device. Although the present invention is not limited to a specific power converter, the case where the present invention is applied to a three-phase inverter will be described below as a fourth embodiment.

  FIG. 23 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

  The power conversion system shown in FIG. 23 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply, and supplies DC power to the power conversion device 2000. The power supply 1000 can be configured by various things, and can be configured by, for example, a DC system, a solar cell, or a storage battery, or as a rectifier circuit or an AC / DC converter connected to an AC system. It is also good. Further, the power supply 1000 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.

  Power converter 2000 is a three-phase inverter connected between power supply 1000 and load 3000, converts DC power supplied from power supply 1000 into AC power, and supplies AC power to load 3000. Power converter 2000, as shown in FIG. 23, includes a main conversion circuit 2001 that converts DC power into AC power and outputs the same, and a drive circuit 2002 that outputs driving signals to drive each switching element of main conversion circuit 2001. And a control circuit 2003 for outputting a control signal for controlling the main conversion circuit 2001 to the drive circuit 2002.

  The load 3000 is a three-phase motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, and is a motor mounted on various electric devices, and is used as, for example, a hybrid car, an electric car, a rail car, an elevator, or a motor for an air conditioner.

  Hereinafter, details of the power conversion device 2000 will be described. The main conversion circuit 2001 includes a switching element and a free wheeling diode (not shown), converts the DC power supplied from the power source 1000 into AC power by switching the switching element, and supplies the AC power to the load 3000. Although there are various specific circuit configurations of the main conversion circuit 2001, the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and respective switching elements. It can be composed of six anti-parallel freewheeling diodes. The semiconductor device according to any one of the first to third embodiments described above is applied to each switching element of the main conversion circuit 2001. Six switching elements are connected in series for every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, ie, the three output terminals of the main conversion circuit 2001, are connected to the load 3000.

  The drive circuit 2002 generates a drive signal for driving the switching element of the main conversion circuit 2001, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001. Specifically, in accordance with a control signal from a control circuit 2003 described later, a drive signal to turn on the switching element and a drive signal to turn off the switching element are output to the control electrodes of the switching elements. When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is voltage lower than the threshold voltage of the switching element It becomes a signal (off signal).

  The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that a desired power is supplied to the load 3000. Specifically, based on the power to be supplied to the load 3000, the time (on-time) in which each switching element of the main conversion circuit 2001 should be turned on is calculated. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the on time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 2002 so that the on signal is output to the switching element to be turned on at each time point and the off signal is output to the switching element to be turned off. The drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

  In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to third embodiments is applied as a switching element of the main conversion circuit 2001. It is possible to realize high-frequency operation and reduction of switching loss, and to provide a highly efficient power converter.

  In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this, and can be applied to various power conversion devices. In this embodiment, a two-level power converter is used, but a three-level or multi-level power converter may be used. When supplying power to a single-phase load, the present invention is applied to a single-phase inverter. You may apply it. Further, when power is supplied to a DC load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

  Moreover, the power conversion device to which the present invention is applied is not limited to the case where the load described above is a motor, and, for example, a power supply of an electric discharge machine or a laser machine, or an induction heating cooker or a noncontact machine power supply system It can also be used as a device, and can also be used as a power conditioner of a solar power generation system, a storage system, or the like.

  In the present invention, within the scope of the invention, it is possible to freely combine each embodiment and its modification, and to appropriately modify or omit each embodiment. For example, the configuration in which a plurality of base regions 303 are exposed in a single contact hole 301 shown in FIG. 11 as a modification of the first embodiment can be applied to the configurations of the second and third embodiments. The modifications of each embodiment can be appropriately applied to the other embodiments.

  Reference Signs List 1 SiC substrate, 2 epitaxial layer (semiconductor layer), 3 active stripe region, 30 active stripe cell, 31 active cell, 301 contact hole, 301a ohmic electrode, 302 source region, 303 base region, 304 gate electrode, 305 gate insulating film , 306 protective diffusion layer, 307 stripe trench, 308 intersection trench, 4 protective diffusion layer ground region, 401 contact hole, 401a ohmic electrode, 402 opening, 5 source electrode, 6 interlayer insulating film, 7 drain electrode, 8 silicon oxide film , 9 etching masks, 10 implantation masks, 100 semiconductor devices.

Claims (16)

A semiconductor layer of a first conductivity type,
A base region of a second conductivity type provided on top of the semiconductor layer;
A source region provided above the base region;
A gate insulating film provided in a plurality of stripe trenches formed in a plurality of stripes extending up to a position deeper than the base region in the semiconductor layer;
A gate electrode provided in the stripe trench and having a side surface facing the base region through the gate insulating film;
A protective diffusion layer of the second conductivity type provided below the stripe trench;
A source electrode connected to the source region and the base region;
Equipped with
A plurality of active stripe regions separated by a plurality of the stripe trenches;
A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches;
Have
A plurality of first active stripe regions including the protective diffusion layer ground region and the protective diffusion layer ground region are not included in the plurality of active stripe regions and provided between the first active stripe regions. There are two active stripe areas,
Semiconductor device. A semiconductor layer of a first conductivity type,
A base region of a second conductivity type provided on top of the semiconductor layer;
A source region provided above the base region;
A gate insulating film provided in a plurality of stripe trenches formed in a plurality of stripes extending up to a position deeper than the base region in the semiconductor layer;
A gate electrode provided in the stripe trench and having a side surface facing the base region through the gate insulating film;
A protective diffusion layer of the second conductivity type provided below the stripe trench;
A source electrode connected to the source region and the base region;
Equipped with
A plurality of active stripe regions separated by a plurality of the stripe trenches;
A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches;
Have
The protective diffusion layer is also provided at a lower portion of a crossing trench crossing the stripe trench,
The protective diffusion layer provided under the at least one of the plurality of stripe trenches is connected to the source electrode in the protective diffusion layer ground region via the protective diffusion layer provided under the intersection trench. Connecting,
Semiconductor device. A semiconductor layer of a first conductivity type,
A base region of a second conductivity type provided on top of the semiconductor layer;
A source region provided above the base region;
A gate insulating film provided in a plurality of stripe trenches formed in a plurality of stripes extending up to a position deeper than the base region in the semiconductor layer;
A gate electrode provided in the stripe trench and having a side surface facing the base region through the gate insulating film;
A protective diffusion layer of the second conductivity type provided below the stripe trench;
A source electrode connected to the source region and the base region;
Equipped with
A plurality of active stripe regions separated by a plurality of the stripe trenches;
A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches;
Have
The protective diffusion layer ground region is included in each of a plurality of active stripe regions separated by a plurality of the stripe trenches,
Semiconductor device. A plurality of protective diffusion layer grounding regions are provided,
A plurality of the protective diffusion layer ground regions are provided at regular intervals along the longitudinal direction of the stripe trench.
The semiconductor device according to any one of claims 1 to 3, characterized in that: A plurality of protective diffusion layer grounding regions are provided,
The semiconductor device according to any one of claims 1 to 4, wherein the plurality of protective diffusion layer ground regions are provided at regular intervals along a direction perpendicular to the longitudinal direction of the stripe trench. The opening is formed entirely between the adjacent stripe trenches in the protective diffusion layer ground region,
In the opening, the gate electrode and the source electrode are provided so as to be insulated from each other.
The semiconductor device according to any one of claims 1 to 5, characterized in that: And an interlayer insulating film provided between the gate electrode and the source electrode in the opening and having a thickness greater than that of the gate insulating film.
7. The semiconductor device according to claim 6, wherein The protective diffusion layer is also provided under the opening of the protective diffusion layer ground region,
The source electrode is connected to the protective diffusion layer provided below the opening.
The semiconductor device according to any one of claims 1 to 6, characterized in that: And an interlayer insulating film which covers the gate electrode and insulates the gate electrode from the source electrode.
The source electrode is connected to the source region and the base region through the contact hole,
A plurality of the base regions are exposed apart from each other on the surface of the semiconductor layer exposed in the contact hole.
The semiconductor device according to any one of claims 1 to 8, characterized in that: The active stripe region includes a stripe-shaped first active cell separated by the gate electrode,
The length of the long side of the first active cell is 1.5 times or more the length of the short side of the first active cell in plan view.
The semiconductor device according to any one of claims 1 to 9, characterized in that: In the active stripe area. A stripe-shaped first active cell divided by the gate electrode, and a second active cell having a shape different from that of the first active cell in plan view and having a longer side than the first active cell It is included,
The semiconductor device according to any one of claims 1 to 10, characterized in that: The width of the protective diffusion layer ground region in the direction of the short side of the active stripe region is an integral multiple of the short side of the active stripe region.
The semiconductor device according to any one of claims 1 to 11, characterized in that: A depletion suppression layer having a first conductive type impurity concentration higher than that of the semiconductor layer is provided below the base region.
The semiconductor device according to any one of claims 1 to 12, characterized in that: The semiconductor device has an off angle,
The longitudinal direction of the stripe trench coincides with the direction of the step flow formed by the off angle,
The semiconductor device according to any one of claims 1 to 13, characterized in that: The semiconductor layer is a wide band gap semiconductor.
The semiconductor device according to any one of claims 1 to 14, characterized in that: A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 15, converting input power and outputting the power.
A drive circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device;
A control circuit for outputting a control signal for controlling the main conversion circuit to the drive circuit;
Power converter equipped with.

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