CN118248736B - Wide SOA shielding grid MOSFET device and preparation method - Google Patents
Wide SOA shielding grid MOSFET device and preparation method Download PDFInfo
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- CN118248736B CN118248736B CN202410643740.0A CN202410643740A CN118248736B CN 118248736 B CN118248736 B CN 118248736B CN 202410643740 A CN202410643740 A CN 202410643740A CN 118248736 B CN118248736 B CN 118248736B
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000001259 photo etching Methods 0.000 abstract description 10
- 230000017525 heat dissipation Effects 0.000 abstract description 5
- 230000003111 delayed effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 155
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a wide SOA shielded gate MOSFET device, which forms different layout layouts of groove width and contact hole width by interval dislocation or parallel arrangement in an active area of the device, wherein the layout forms different widths of the groove and the contact hole by interval dislocation or parallel arrangement in the active area of the device in a photoetching mode, so that the area has a narrower distance from the groove to the contact hole, thereby forming different concentration gradients of the area and other areas after the contact hole is injected, realizing that the other areas are preferentially started and the areas are delayed to be started when the device is conducted, and finally being used as a heat dissipation field plate to promote the whole SOA of the device under the condition that the other areas are preferentially started. The invention also provides a preparation method of the device, which is compatible with the manufacturing process of the common power device, and can be applied to power devices such as plane type, groove type, shielded gate type MOSFET, super junction MOSFET, IGBT and the like.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a wide SOA (service oriented architecture) shielded gate MOSFET device and a preparation method thereof.
Background
Power MOSFETs are commonly used power devices in switching converters, and the magnitude of the losses have a direct impact on the performance and efficiency of the switching converter. The loss of the power MOSFET mainly consists of two parts, namely conduction loss and switching loss, and a general device generally adopts a power MOSFET device with the characteristics of low on-resistance, high withstand voltage value, high gain, low switching loss, low gate threshold voltage and the like. However, for devices that need to operate in linear mode, such as active loads, the power MOSFET devices described above are not satisfactory. Because if the gain (Gm) of the power MOSFET is too high, it is difficult to keep the drain current constant without applying a negative feedback link in view of its negative temperature coefficient of gate threshold voltage (VGS (th)), and it may even cause the power MOSFET to be permanently damaged by thermal breakdown.
Disclosure of Invention
The first aspect of the present invention provides a wide SOA shielded gate MOSFET device, in which different layout layouts of trench widths and contact hole widths are formed by offset or parallel arrangement in the active region of the device, the layouts are formed by offset or parallel arrangement in the active region of the device in a photolithography manner, so that the region has a narrower trench-to-contact hole distance, and thus a concentration gradient different from that of other regions is formed after the contact hole is implanted, so that when the device is turned on, the other regions are turned on preferentially and turned on with a delay (about 1V delay) and finally, when the other regions are turned on preferentially, the region can serve as a heat dissipation field plate to promote the SOA of the whole device. The reconstruction of the temperature relation between Vgs and Id current of the power device is realized by changing the device, namely, the ZTC position (zero temperature coefficient point) of the device is reduced, namely, the position of the crossover point of the transfer characteristic curve of the device at normal temperature (such as 25 ℃) and high temperature (such as 150 ℃) is indicated, the ID of the device is continuously increased along with the increase of the temperature and is displayed as positive feedback and is a positive temperature coefficient, and the ID of the device is also reduced along with the increase of the temperature and is displayed as negative feedback and is a negative temperature coefficient when the ID of the device is arranged above the crossover point, so that the area above the position is wider, thereby enhancing the forward bias safe operating area (FBSOA: forward Biased Safe Operating Area) of the device, and solving the problems existing in the prior art.
The second aspect of the present invention also provides a method for manufacturing the device, which is compatible with a general power device manufacturing process, and can be applied to power devices such as planar, trench-type and shielded gate-type MOSFETs, superjunction MOSFETs, IGBTs, and the like.
The technical scheme provided by the invention is as follows:
the invention provides a wide SOA shielded gate MOSFET device, comprising:
The epitaxial device comprises a substrate, wherein an epitaxial layer grows on the surface of the substrate, a plurality of parallel grooves which are arranged at equal intervals are etched in the epitaxial layer along a first direction, and groove gates are arranged in the grooves;
The surface of the epitaxial layer is sequentially provided with an N+ heavily doped source electrode layer and a P-type well region layer from top to bottom, an insulating medium layer is deposited on the epitaxial layer, and a source electrode metal layer is arranged on the surface of the insulating medium layer;
the surface of the epitaxial layer is provided with a contact hole along the direction parallel to the groove, the top of the contact hole penetrates through the insulating medium layer to be abutted against the source metal layer, the bottom of the contact hole penetrates through the N+ heavily doped source layer to extend into the P-type well region layer, the bottom of the contact hole is provided with an injection layer, the injection layer is positioned in the P-type well region layer, and the contact holes are distributed at the middle positions of the adjacent grooves;
the distance between any position on the contact hole and the grooves on two adjacent sides is D1 and D2, or the distance between the contact Kong Renyi position and the groove on one side is D1 and the distance between the contact Kong Renyi position and the groove on the other side is D2, and D1 is larger than D2.
Further, the groove includes a first portion and a second portion, the second portion having a width greater than a width of the first portion;
Two ends of second parts of different grooves along a second direction are flush, the distance between the second parts and adjacent contact holes is D2, and the distance between the first parts and adjacent contact holes is D1;
the second direction is perpendicular to the first direction.
Further, the groove includes a first portion and a second portion, the second portion having a width greater than a width of the first portion;
The second parts of the adjacent grooves are staggered, the second parts of the grooves in the nth row are flush with the two ends of the second parts of the grooves in the n-2 th row along the second direction, the number of columns of the grooves is greater than or equal to n, and the distances between the second parts of the grooves and the adjacent contact holes are D1 and D2 respectively;
the second direction is perpendicular to the first direction.
Further, the contact hole includes a third portion and a fourth portion, the fourth portion having a width greater than a width of the third portion;
two ends of a fourth part of the different contact holes along the second direction are flush, the distance between the fourth part and the adjacent groove is D2, and the distance between the third part and the adjacent groove is D1;
the second direction is perpendicular to the first direction.
Further, the contact hole includes a third portion and a fourth portion, the fourth portion having a width greater than a width of the third portion;
the fourth parts of the adjacent contact holes are staggered, the fourth parts of the contact holes in the nth row are flush with the two ends of the fourth parts of the contact holes in the n-2 th row along the second direction, the number of the contact holes is greater than or equal to n, and the distances between the fourth parts of the contact holes and the adjacent grooves are D1 and D2 respectively;
the second direction is perpendicular to the first direction.
Further, the trench gate comprises a source polycrystalline silicon layer and a gate polycrystalline silicon layer which are filled in the trench from bottom to top;
An oxide layer is further grown between the source polycrystalline silicon layer and the side wall of the groove, and a gate oxide layer is grown between the gate polycrystalline silicon layer and the side wall of the groove and between the source polycrystalline silicon layer.
Further, the bottom of the P-type well region layer does not exceed the bottom of the groove;
The back of the substrate is provided with a drain electrode metal layer;
and a metal filling layer is arranged in the contact hole.
Further, the material of the metal filling layer is Ti/TiN and tungsten;
the insulating dielectric layer is formed by silicon dioxide and BPSG.
Meanwhile, the invention also provides a preparation method of the wide SOA shielding gate MOSFET device, which is used for preparing the wide SOA shielding gate MOSFET device and comprises the following steps:
S100, providing a substrate, growing an epitaxial layer on the surface of the substrate, depositing an etching barrier layer on the surface of the epitaxial layer, determining the position of a groove, and forming grooves distributed along a first direction through the etching barrier layer;
S200, removing the etching barrier layer, and forming a trench gate in all the trenches;
s300, sequentially forming a P-type well region layer and an N+ heavily doped source electrode layer on the surface of the epitaxial layer in an ion implantation mode, wherein the junction depth of the P-type well region layer is larger than that of the N+ heavily doped source electrode layer;
S400, depositing an insulating medium layer on the surface of the epitaxial layer to serve as a device isolation layer, defining a contact hole area to be etched, removing the insulating medium layer in the contact hole area to form a contact hole, and enabling the contact hole to penetrate through the N+ heavily doped source electrode layer and extend into the P-type well region layer;
S500, injecting elements into the contact holes to activate and form injection layers, depositing and forming metal filling layers in the contact holes, depositing and forming source electrode metal layers on the surfaces of the insulating medium layers, and forming back drain electrode metal layers on the back surfaces of the substrates.
Further, in step S200, the forming a trench gate in all the trenches includes the following steps:
growing an oxide layer on the inner wall of the groove;
forming a source polycrystalline silicon layer in the groove, and grinding the surface of the source polycrystalline silicon layer to be flush with the surface of the epitaxial layer;
etching the source polycrystalline silicon layer to a first depth to form a polycrystalline silicon etching region;
Removing the oxide layer in the polysilicon etching region, growing a gate oxide layer on the side wall and the bottom of the polysilicon etching region, and depositing a gate polysilicon layer in the polysilicon etching region.
Compared with the prior art, the invention has the beneficial effects that:
The application forms different layout layouts of groove width and contact hole width by interval dislocation or parallel arrangement in the active area of the device, the layout forms different widths of the groove and the contact hole by interval dislocation or parallel arrangement in the active area of the device in a photoetching mode, so that the area has narrower groove-to-contact hole distance, thereby forming different concentration gradients of the area and other areas after the contact hole injection, realizing that the other areas are preferentially opened and the area is delayed to be opened (delay of about 1V) when the device is conducted, and finally the area can be used as a heat dissipation field plate to promote the SOA of the whole device under the condition that the other areas are preferentially opened. Therefore, the application realizes the reconstruction of the temperature relation between Vgs and Id current of the power device, namely, the ZTC (zero temperature coefficient point) position of the reduced device refers to the crossing point position of the transfer characteristic curve of the device at normal temperature (such as 25C) and high temperature (such as 150C), the ID of the device is continuously increased along with the increase of temperature and is displayed as positive feedback and is a positive temperature coefficient, and the ID of the device is also reduced along with the increase of temperature and is displayed as negative feedback and is a negative temperature coefficient when the ID of the device is displayed in the area above the crossing point, so that the area above the position is wider, thereby enhancing the forward bias safety operating area (FBSOA: forward Biased Safe Operating Area) of the device. Meanwhile, the manufacturing process method of the device is simple, and the device is compatible with the manufacturing process of the traditional shielded gate MOSFET device.
Drawings
FIG. 1 is a schematic diagram of a trench layout in embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a trench layout in embodiment 2 of the present invention;
FIG. 3 is a schematic diagram of a trench layout in embodiment 3 of the present invention;
FIG. 4 is a schematic diagram of a trench layout in embodiment 4 of the present invention;
FIG. 5 is a schematic cross-sectional view of step 1 in example 5 of the present invention;
FIG. 6 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 2 of example 5 of the present invention;
FIG. 7 is a schematic cross-sectional view taken along Ay2 in FIG. 1 in example 5 of the present invention;
FIG. 8 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 3 of example 5 of the present invention;
FIG. 9 is a schematic cross-sectional view taken along Ay2 in FIG. 1, step 3 of example 5 of the present invention;
FIG. 10 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 4 of example 5 of the present invention;
FIG. 11 is a schematic cross-sectional view taken along Ay2 in FIG. 1 in example 5 of the present invention;
FIG. 12 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 5 of example 5 of the present invention;
FIG. 13 is a schematic cross-sectional view taken along Ay2 in FIG. 1 in step 5 of example 5 of the present invention;
FIG. 14 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in example 5 of the present invention;
FIG. 15 is a schematic cross-sectional view taken along Ay2 in FIG. 1, step 6 of example 5 of the present invention;
FIG. 16 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 7 of example 5 of the present invention;
FIG. 17 is a schematic cross-sectional view taken along Ay2 in FIG. 1, step 7 of example 5 of the present invention;
FIG. 18 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 8 of example 5 of the present invention;
FIG. 19 is a schematic cross-sectional view taken along Ay2 in FIG. 1, step 8 of example 5 of the present invention;
FIG. 20 is a schematic cross-sectional view taken along Ay1 in FIG. 1 in step 9 of example 5 of the present invention;
FIG. 21 is a schematic cross-sectional view taken along Ay2 in FIG. 1 in step 9 of example 5 of the present invention;
FIG. 22 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 2 of example 6 of the present invention;
FIG. 23 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 2 of example 6 of the present invention;
FIG. 24 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 3 of example 6 of the present invention;
FIG. 25 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 3 of example 6 of the present invention;
FIG. 26 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 4 of example 6 of the present invention;
FIG. 27 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 4 of example 6 of the present invention;
FIG. 28 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 5 of example 6 of the present invention;
FIG. 29 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 5 of example 6 of the present invention;
FIG. 30 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 6 of example 6 of the present invention;
FIG. 31 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 6 of example 6 of the present invention;
FIG. 32 is a cross-sectional view taken along the direction By1 in FIG. 2, taken at step 7 in example 6 of the present invention;
FIG. 33 is a cross-sectional view taken along the direction By2 in FIG. 2, taken at step 7 in example 6 of the present invention;
FIG. 34 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 8 of example 6 of the present invention;
FIG. 35 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 8 of example 6 of the present invention;
FIG. 36 is a cross-sectional view taken along the direction By1 in FIG. 2, taken in step 9 of example 6 of the present invention;
FIG. 37 is a cross-sectional view taken along the direction By2 in FIG. 2, taken in step 9 of example 6 of the present invention;
FIG. 38 is a cross-sectional view taken along the direction Ay1 in FIG. 3 of the device prepared in example 7 of the present invention;
FIG. 39 is a cross-sectional view taken along the direction Ay2 in FIG. 3 of the device prepared in example 7 of the present invention;
FIG. 40 is a cross-sectional view taken along the direction By1 in FIG. 4 of the device prepared in example 8 of the present invention;
fig. 41 is a cross-sectional view of the device prepared in example 8 of the present invention taken along the direction By2 in fig. 4.
The reference numerals are as follows:
1-substrate, 2-epitaxial layer, 3-etching barrier layer, 4-trench, 41-first portion, 42-second portion, 5-oxide layer, 6-source polysilicon layer, 7-polysilicon etched region, 8-gate oxide layer, 9-gate polysilicon layer, 10-P-type well region layer, 11-N+ heavily doped source layer, 12-insulating dielectric layer, 13-contact hole, 131-third portion, 132-fourth portion, 14-implanted layer, 15-metal filling layer, 16-source metal layer, 17-drain metal layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the embodiments described below are some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Accordingly, the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, is intended to represent only selected embodiments of the application, and not to limit the scope of the application as claimed. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments of the present application, are within the scope of the present application.
It should be understood that in the description of embodiments of the invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first," "second," etc. may explicitly or implicitly include one or more of the described features.
In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific circumstances.
The invention provides a wide SOA shielded gate MOSFET device, comprising:
The substrate 1, the surface growth of substrate 1 has one deck epitaxial layer 2, and epitaxial layer 2 is etched along the first direction has a plurality of parallel and equidistant slot 4 that set up, is provided with the trench gate in the slot 4.
The surface of the epitaxial layer 2 is sequentially provided with an N+ heavily doped source electrode layer 11 and a P-type well region layer 10 from top to bottom, an insulating medium layer 12 is deposited on the epitaxial layer 2, and a source electrode metal layer 16 is arranged on the surface of the insulating medium layer 12.
The epitaxial layer 2 surface is provided with contact hole 13 along parallel slot 4 direction, and insulating medium layer 12 butt source metal layer 16 is run through at contact hole 13's top, and N+ heavily doped source layer 11 is run through at contact hole 13's bottom and is extended into P type well region layer 10, and contact hole 13's bottom is provided with injection layer 14, and injection layer 14 is located P type well region layer 10, and contact hole 13 distributes in adjacent slot 4 intermediate position.
The distance between any position of the contact hole 13 and the adjacent grooves 4 on two sides is D1 and D2, or the distance between any position of the contact hole 13 and one groove 4 is D1 and the distance between the other groove 4 is D2, and D1 is larger than D2.
It should be noted that, in the wide SOA shielded gate MOSFET device provided by the present application, the trenches 4 are arranged in parallel with the contact holes 13, the trenches 4 are arranged at equal intervals, and the contact holes 13 are arranged at the middle position of every two adjacent trenches 4. The layout distribution of the grooves 4 and the contact holes 13 is strip-shaped, and the device is different from the traditional device in that the distance between the contact holes 13 and the grooves 4 is not consistent all the time, and for any one contact hole 13, from left to right, the distance between the contact hole 13 and the grooves 4 on two sides is near or far from the layout, for example, the distance of a far point is D1, the distance of a near point is D2, and the narrower distance from the grooves 4 on different positions in the active region to the contact holes 13 is realized. To achieve this, the application is implemented by arranging different widths of trenches 4 in the device active region at intervals or in parallel, or by arranging different widths of contact holes 13 in the device active region at intervals or in parallel. Therefore, for any one of the different positions of the contact hole 13, there are only three cases where the widths from the adjacent two side grooves 4 are D1, D2, or where any one position of the contact hole 13 is located at a distance D1 from one side groove 4 and a distance D2 from the other side groove 4.
Optionally, the trench gate includes a source polysilicon layer 6 and a gate polysilicon layer 9 filled inside the trench 4 from bottom to top.
An oxide layer 5 is also grown between the source polysilicon layer 6 and the side wall of the trench 4, and a gate oxide layer 8 is grown between the gate polysilicon layer 9 and the side wall of the trench 4 and between the source polysilicon layer 6.
Optionally, the bottom of the P-type well region layer 10 does not exceed the bottom of the trench 4.
The back side of the substrate 1 is provided with a drain metal layer 17.
A metal filling layer 15 is provided in the contact hole 13.
Optionally, the material of the metal filling layer 15 is Ti/TiN and tungsten.
The insulating dielectric layer 12 is formed of silicon dioxide and BPSG.
The application forms different layout layouts of groove width and contact hole width by interval dislocation or parallel arrangement in the active area of the device, the layout forms different widths of the groove 4 and the contact hole 13 by interval dislocation or parallel arrangement in the active area of the device in a photoetching mode, so that the area has a narrower distance from the groove 4 to the contact hole 13, thereby forming different concentration gradients of the area and other areas after the contact hole is injected, realizing that the other areas are preferentially opened and the area is delayed to be opened (delay of about 1V) when the device is conducted, and finally, the area can be used as a heat dissipation field plate to promote the SOA of the whole device under the condition that the other areas are preferentially opened. Therefore, the application realizes the reconstruction of the temperature relation between Vgs and Id current of the power device, namely, the ZTC (zero temperature coefficient point) position of the reduced device refers to the crossing point position of the transfer characteristic curve of the device at normal temperature (such as 25C) and high temperature (such as 150C), the ID of the device is continuously increased along with the increase of temperature and is displayed as positive feedback and is a positive temperature coefficient, and the ID of the device is also reduced along with the increase of temperature and is displayed as negative feedback and is a negative temperature coefficient when the ID of the device is displayed in the area above the crossing point, so that the area above the position is wider, thereby enhancing the forward bias safety operating area (FBSOA: forward Biased Safe Operating Area) of the device. Meanwhile, the manufacturing process method of the device is simple, and the device is compatible with the manufacturing process of the traditional shielded gate MOSFET device.
Example 1
As shown in fig. 1, the device provided in this embodiment achieves a narrower distance from the trenches 4 to the contact holes 13 at different positions in the active region by arranging different widths of the trenches 4 in parallel in the active region.
The groove 4 comprises a first portion 41 and a second portion 42, the width of the second portion 42 being greater than the width of the first portion 41, as shown in fig. 1, the first portion 41 and the second portion 42 of the groove 4 being symmetrical up and down in fig. 1, where up and down refer to up and down in the figure rather than up and down in the actual structure. The shape of the second portion 42 may be diamond or other shape as desired. In this embodiment, the second portion 42 is diamond-shaped.
The second portions 42 of the different trenches 4 in the second direction are flush at both ends, the second portions 42 are spaced apart from the adjacent contact holes 13 by a distance D2, and the first portions 41 are spaced apart from the adjacent contact holes 13 by a distance D1.
The second direction is perpendicular to the first direction, which is defined as the direction from left to right in fig. 1, and the second direction is the direction from top to bottom in fig. 1.
The contact hole 13 is in a smooth strip-shaped structure in this embodiment.
Example 2
As shown in fig. 2, in the device provided in this embodiment, by arranging different widths of the trenches 4 at intervals and in a staggered manner in the active area, a narrower distance from the trenches 4 at different positions in the active area to the contact hole 13 is realized.
The groove 4 comprises a first portion 41 and a second portion 42, the width of the second portion 42 being greater than the width of the first portion 41.
The second portions 42 of the adjacent grooves 4 are staggered, the second portions 42 of the grooves 4 in the nth row are flush with the two ends of the second portions 42 of the grooves 4 in the n-2 th row along the second direction, the number of columns of the grooves 4 is greater than or equal to n, and the distances between the second portions 42 of the grooves 4 and the adjacent contact holes 13 are respectively D1 and D2. For example, the second portions 42 of the 1 st row of grooves 4 are aligned with the second portions 42 of the 3 rd row of grooves 4, the second portions 42 of the 2 nd row of grooves 4 are aligned with the second portions 42 of the 4 th row of grooves 4, the second portions 42 of the 1 st row of grooves 4 are offset from the second portions 42 of the 2 nd row of grooves 4, and so on.
The difference between this embodiment and embodiment 1 is that the second portions 42 are arranged in parallel in embodiment 1, but the second portions 42 are arranged in a staggered manner in this embodiment, and the shape of the second portions 42 is unchanged. The contact hole 13 is also in a smooth strip-shaped structure in this embodiment.
Example 3
As shown in fig. 3, the device provided in this embodiment realizes a narrower distance from the trench 4 to the contact hole 13 at different positions in the active region by arranging different widths of the contact hole 13 in parallel in the active region. The arrangement of the contact holes 13 in this embodiment is similar to that of the trenches 4 in embodiment 1, and the principle is to achieve a narrower distance from the trenches 4 to the contact holes 13 at different positions in the active region.
The contact hole 13 includes a third portion 131 and a fourth portion 132, and the fourth portion 132 has a width greater than that of the third portion 131. The fourth portion 132 is also diamond-shaped in shape.
The fourth portions 132 of the different contact holes 13 are flush along the second direction, the fourth portions 132 are spaced apart from the adjacent trenches 4 by a distance D2, and the third portions 131 are spaced apart from the adjacent trenches 4 by a distance D1.
The grooves 4 are in this embodiment smooth strip-shaped structures.
Example 4
As shown in fig. 4, in the device provided in this embodiment, by arranging different widths of the contact holes 13 at intervals and in a staggered manner in the active region, narrower distances from the trenches 4 to the contact holes 13 at different positions in the active region are realized.
The contact hole 13 includes a third portion 131 and a fourth portion 132, and the fourth portion 132 has a width greater than that of the third portion 131.
The fourth portions 132 of the adjacent contact holes 13 are staggered, and the fourth portions 132 of the contact holes 13 in the nth row are flush with the two ends of the fourth portions 132 of the contact holes 13 in the n-2 th row along the second direction, the number of columns of the contact holes 13 is greater than or equal to n, and the distances between the fourth portions 132 of the contact holes 13 and the adjacent grooves 4 are respectively D1 and D2.
The grooves 4 in this embodiment are also smooth bar-shaped structures.
The invention also provides a preparation method for preparing the wide SOA shielding gate MOSFET device, which comprises the following steps:
S100, providing a substrate 1, growing an epitaxial layer 2 on the surface of the substrate 1, depositing an etching barrier layer 3 on the surface of the epitaxial layer 2, determining the positions of the grooves 4, and forming the grooves 4 distributed along the first direction through the etching barrier layer 3.
And S200, removing the etching barrier layer 3, and forming a trench gate in all the trenches 4.
S300, sequentially forming a P-type well region layer 10 and an N+ heavily doped source layer 11 on the surface of the epitaxial layer 2 in an ion implantation mode, wherein the junction depth of the P-type well region layer 10 is larger than that of the N+ heavily doped source layer 11.
S400, depositing an insulating medium layer 12 on the surface of the epitaxial layer 2 to serve as a device isolation layer, defining a contact hole 13 area to be etched, removing the insulating medium layer 12 in the contact hole 13 area to form a contact hole 13, and enabling the contact hole 13 to penetrate through the N+ heavily doped source layer 11 and extend into the P-type well region layer 10.
S500, injecting elements into the contact holes 13 to activate and form an injection layer 14, depositing and form a metal filling layer 15 in the contact holes 13, depositing and forming a source metal layer 16 on the surface of the insulating dielectric layer 12, and forming a back drain metal layer 17 on the back of the substrate 1.
Optionally, in step S200, a trench gate is formed in all trenches 4, including the following steps:
an oxide layer 5 is grown on the inner wall of the trench 4.
A source polysilicon layer 6 is formed in the trench 4 and the surface of the source polysilicon layer 6 is polished to be flush with the surface of the epitaxial layer 2.
The source polysilicon layer 6 is etched to a first depth to form a polysilicon etched region 7.
The oxide layer 5 in the polysilicon etching region 7 is removed, a gate oxide layer 8 is grown on the side wall and the bottom of the polysilicon etching region 7, and a gate polysilicon layer 9 is deposited in the polysilicon etching region 7.
The above preparation method is further illustrated by the following specific examples.
Example 5
The present embodiment provides a method for manufacturing a device in embodiment 1, where different distances from the trench 4 to the contact hole 13 are realized by parallel arrangement of trenches, and the specific manufacturing method is as follows:
1. An Oxide (silicon dioxide hard mask) is deposited on the surface of the substrate 1 and the epitaxial layer 2 as a trench etching barrier layer 3, as shown in fig. 5.
2. And determining the position of the groove 4 through photoresist and a photoetching mask plate, etching the exposed hard mask plate, removing the photoresist, and forming the groove 4 by taking the hard mask plate as a blocking etching silicon, wherein the sectional views along the Ay1 and Ay2 directions in FIG. 1 are respectively shown in FIG. 6 and FIG. 7.
3. The hard mask layer is removed by wet method, and then an oxide layer 5 is grown by thermal oxidation, and the sectional views taken along the Ay1 and Ay2 directions in FIG. 1 are shown in FIG. 8 and FIG. 9, respectively.
4. An N-type heavily doped polysilicon (Poly) is deposited as the source polysilicon layer 6 of the device, and the source polysilicon layer 6 is polished and etched by CMP (chemical polishing) and dry etching back, and the cross-sectional views taken along the directions Ay1 and Ay2 in fig. 1 are shown in fig. 10 and 11, respectively.
5. The source polysilicon layer 6 with a certain depth is etched in the device active region by a photoetching method to form an N-type heavily doped polysilicon etching region 7 (depending on the specific technological parameter requirements), and the sectional views along the Ay1 and Ay2 directions in FIG. 1 are shown in FIG. 12 and FIG. 13 respectively.
6. Removing the oxide layer 5 at the positions of the table top of the active region and the side wall of the groove by utilizing a photoresist and a photoetching mask plate through a wet method, growing a layer of high-quality gate oxide layer 8 through a thermal oxidation process after removing the photoresist, depositing a layer of N-type heavily doped gate polysilicon layer 9 through a deposition process, and etching gate poly to the surface of the gate oxide layer 8 through CMP (chemical polishing) and dry etching back. Sectional views taken along the Ay1 and Ay2 directions in FIG. 1 are shown in FIGS. 14 and 15, respectively.
7. Defining a body imp region to be implanted through a photoetching process, implanting P-type doping elements through ions, removing photoresist, and pushing the body imp to a required junction depth (the junction depth is positioned above the bottom of the grid polysilicon) through a hot push well mode to form a P-type well region layer 10; defining an SN imp region to be implanted through a photoetching process, implanting an N-type heavily doped element through ions, removing photoresist, pushing the SN imp to a required junction depth through a hot push well mode to form an N+ heavily doped source layer 11, and respectively obtaining sectional views along Ay1 and Ay2 in the directions shown in fig. 1 as shown in fig. 16 and 17.
8. An insulating dielectric layer 12 is formed by depositing a layer of silicon dioxide (BPSG) as a device isolation layer. Then defining CT (contact hole) region to be etched by photoetching process, removing surface silicon dioxide by dry etching mode, removing photoresist, removing silicon by dry etching process, and making its depth must penetrate SN IMP (source electrode) to form contact hole 13, and the sectional views along Ay1 and Ay2 directions in figure 1 are respectively shown in figure 18 and figure 19.
9. The P-type doping element is implanted by ions, and then the implanted element is activated by high temperature to form an implanted layer 14; a Ti/TiN layer is deposited, then a good ohmic contact is formed on the surface of the contact hole by a suitable high temperature process, a tungsten layer is deposited, and the metal filling layer 15 is formed by removing the metal tungsten on the surface layer of BPSG by a back etching process. A metal layer is deposited, and then a source metal layer 16 is formed through a photoetching process; then, the back of the wafer is thinned to a required thickness by adopting a back thinning process, and a metal layer is evaporated on the back to form a device back drain metal layer 17, and sectional views taken along the Ay1 and Ay2 directions in FIG. 1 are respectively shown in FIG. 20 and FIG. 21.
The device trench layout prepared by this embodiment is shown in fig. 1, in which the second portions 42 of the trenches 4 are aligned in parallel. The contact holes 13 of the device are bar-shaped contact holes.
Example 6
The present embodiment provides a method for manufacturing a device in embodiment 2, where different distances from the trench 4 to the contact hole 13 are realized by the staggered arrangement of the trenches, and the method for manufacturing a device in this embodiment is substantially the same as that in embodiment 5, except that the positions of the first portion 41 and the second portion 42 of the trench 4 determined in step 2 are different, and in this embodiment, the second portion 42 of the trench 4 is aligned in parallel in the staggered arrangement of the trenches.
The device trench layout prepared by this example is shown in fig. 2.
Fig. 22 and 23 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 2; FIGS. 24 and 25 are sectional views taken along the directions By1 and By2 in FIG. 2, respectively, taken in step 3; fig. 26 and 27 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 4; fig. 28 and 29 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 5; FIGS. 30 and 31 are sectional views taken along the directions By1 and By2 in FIG. 2, respectively, taken in step 6; fig. 32 and 33 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 7; fig. 34 and 35 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 8; fig. 36 and 37 are sectional views taken along the directions By1 and By2 in fig. 2, respectively, taken in step 9.
Example 7
The present embodiment provides a method for manufacturing a device in embodiment 3, which implements different distances from the trench 4 to the contact hole 13 by arranging the contact holes 13 in parallel, and the method for manufacturing a device in this embodiment is substantially the same as that in embodiment 5, except that the trench 4 determined in step 2 is a stripe-shaped trench including only the first portion 41, the contact hole 13 formed in step 8 includes a third portion 131 and a fourth portion 132, and the fourth portion 132 is aligned in parallel.
The device trench layout prepared by this example is shown in fig. 3, and fig. 38 and 39 are cross-sectional views of the device prepared by this method taken along the directions Ay1 and Ay2 in fig. 3.
Example 8
The present embodiment provides a method for manufacturing a device in embodiment 4, which implements different distances from the trench 4 to the contact hole 13 by using a staggered arrangement of the contact holes 13, and the method for manufacturing a device in this embodiment is substantially the same as that in embodiment 5, except that the trench 4 determined in step 2 is a stripe-shaped trench including only the first portion 41, the contact hole 13 formed in step 8 includes a third portion 131 and a fourth portion 132, and the fourth portion 132 is aligned in parallel.
The device trench layout prepared By this example is shown in fig. 4, and fig. 40 and 41 are cross-sectional views of the device prepared By this method taken along the directions By1 and By2 in fig. 4.
According to the device provided by the application, the area from the groove 4 to the contact hole 13 at a narrower distance is influenced by the injection of the contact hole, so that a certain concentration gradient exists between the area and the Meas (mesa) of the accessory area; the opening voltage from the trench 4 to the contact hole 13 in the active region is higher than that from the nearby trench 4 to the contact hole 13 in the wider distance region by about 1V, and when the device is normally opened, the wider distance region is preferentially opened, and the narrower distance region can be used as a heat dissipation plate to release heat generated by the conduction of the device until the device is completely conducted; from the above description, the staggered or parallel grooves 4 and the contact holes 13 in the active region of the device are arranged in different widths to form two different concentration gradients in the two regions, so that the reconstruction of the Vgs and Id current temperature relationship of the power device is realized, and the forward bias safe operating area (FBSOA: forward Biased Safe Operating Area) of the device is enhanced. The preparation method provided by the application is compatible with the traditional power device manufacturing process, can be applied to power devices such as plane type, groove type, shielded gate type MOSFET, super junction MOSFET and IGBT, and the like, and has simple operation and wide prospect.
The foregoing description is merely illustrative of the preferred embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present application should be covered. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (6)
1. A wide SOA shielded gate MOSFET device comprising:
the epitaxial device comprises a substrate, wherein an epitaxial layer grows on the surface of the substrate, a plurality of parallel grooves are etched in the epitaxial layer along a first direction, and groove gates are arranged in the grooves;
The surface of the epitaxial layer is sequentially provided with an N+ heavily doped source electrode layer and a P-type well region layer from top to bottom, an insulating medium layer is deposited on the epitaxial layer, and a source electrode metal layer is arranged on the surface of the insulating medium layer;
the surface of the epitaxial layer is provided with a contact hole along the direction parallel to the groove, the top of the contact hole penetrates through the insulating medium layer to be abutted against the source metal layer, the bottom of the contact hole penetrates through the N+ heavily doped source layer to extend into the P-type well region layer, the bottom of the contact hole is provided with an injection layer, the injection layer is positioned in the P-type well region layer, and the contact holes are distributed at the middle positions of the adjacent grooves;
the groove comprises a first part and a second part, the width of the second part is larger than that of the first part, and the contact hole is of a smooth strip-shaped structure;
Two ends of second parts of different grooves along a second direction are flush, the distance between the second parts and adjacent contact holes is D2, and the distance between the first parts and adjacent contact holes is D1; or the second parts of the adjacent grooves are staggered, the second parts of the grooves in the nth row are flush with the two ends of the second parts of the grooves in the n-2 th row along the second direction, the number of columns of the grooves is more than 2, the distance between the second parts and the adjacent contact holes is D2, and the distance between the first parts and the adjacent contact holes is D1;
the second direction is perpendicular to the first direction.
2. The wide SOA shield gate MOSFET device of claim 1, wherein:
the trench gate comprises a source polycrystalline silicon layer and a gate polycrystalline silicon layer which are filled in the trench from bottom to top;
An oxide layer is further grown between the source polycrystalline silicon layer and the side wall of the groove, and a gate oxide layer is grown between the gate polycrystalline silicon layer and the side wall of the groove and between the source polycrystalline silicon layer.
3. The wide SOA shield gate MOSFET device of claim 2, wherein:
The bottom of the P-type well region layer does not exceed the bottom of the groove;
The back of the substrate is provided with a drain electrode metal layer;
and a metal filling layer is arranged in the contact hole.
4. A wide SOA shield gate MOSFET device according to claim 3, characterized in that:
the metal filling layer is made of Ti, tiN and tungsten;
the insulating dielectric layer is formed by silicon dioxide and BPSG.
5. A method for preparing a wide SOA shield gate MOSFET device according to any of claims 1-4, comprising the steps of:
S100, providing a substrate, growing an epitaxial layer on the surface of the substrate, depositing an etching barrier layer on the surface of the epitaxial layer, determining the position of a groove, and forming grooves distributed along a first direction through the etching barrier layer;
S200, removing the etching barrier layer, and forming a trench gate in all the trenches;
s300, sequentially forming a P-type well region layer and an N+ heavily doped source electrode layer on the surface of the epitaxial layer in an ion implantation mode, wherein the junction depth of the P-type well region layer is larger than that of the N+ heavily doped source electrode layer;
S400, depositing an insulating medium layer on the surface of the epitaxial layer to serve as a device isolation layer, defining a contact hole area to be etched, removing the insulating medium layer in the contact hole area to form a contact hole, and enabling the contact hole to penetrate through the N+ heavily doped source electrode layer and extend into the P-type well region layer;
S500, injecting elements into the contact holes to activate and form injection layers, depositing and forming metal filling layers in the contact holes, depositing and forming source electrode metal layers on the surfaces of the insulating medium layers, and forming back drain electrode metal layers on the back surfaces of the substrates.
6. The method for manufacturing a wide SOA shield gate MOSFET device according to claim 5, wherein in step S200, the trench gate is formed in all the trenches, comprising the steps of:
growing an oxide layer on the inner wall of the groove;
forming a source polycrystalline silicon layer in the groove, and grinding the surface of the source polycrystalline silicon layer to be flush with the surface of the epitaxial layer;
etching the source polycrystalline silicon layer to a first depth to form a polycrystalline silicon etching region;
Removing the oxide layer in the polysilicon etching region, growing a gate oxide layer on the side wall and the bottom of the polysilicon etching region, and depositing a gate polysilicon layer in the polysilicon etching region.
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