WO2017175460A1 - Semiconductor device and power conversion device - Google Patents

Semiconductor device and power conversion device Download PDF

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Publication number
WO2017175460A1
WO2017175460A1 PCT/JP2017/003434 JP2017003434W WO2017175460A1 WO 2017175460 A1 WO2017175460 A1 WO 2017175460A1 JP 2017003434 W JP2017003434 W JP 2017003434W WO 2017175460 A1 WO2017175460 A1 WO 2017175460A1
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Prior art keywords
stripe
region
diffusion layer
semiconductor device
protective diffusion
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PCT/JP2017/003434
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French (fr)
Japanese (ja)
Inventor
勝俊 菅原
梨菜 田中
裕 福井
亘平 足立
和也 小西
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三菱電機株式会社
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Publication of WO2017175460A1 publication Critical patent/WO2017175460A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a trench gate type semiconductor device.
  • insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements for controlling power supply to loads such as motors. Yes.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • a trench gate type semiconductor device in which a gate electrode is embedded in a semiconductor layer.
  • an on-resistance representing the electrical resistance between the main electrodes when the semiconductor device is on is known. Since a trench gate type semiconductor device can have a higher channel width density than an ordinary planar type semiconductor device, an on-resistance per unit area can be reduced.
  • next-generation switching elements silicon carbide (SiC), gallium nitride (GaN) -based materials, MOSFETs and IGBTs using wide band gap semiconductors such as diamond, etc. are attracting attention, and hexagonal systems such as SiC.
  • SiC silicon carbide
  • GaN gallium nitride
  • MOSFETs and IGBTs using wide band gap semiconductors such as diamond, etc. are attracting attention, and hexagonal systems such as SiC.
  • the current path of the trench gate type semiconductor device coincides with the a-axis direction having a high carrier mobility, so that a significant reduction in on-resistance is expected.
  • Patent Document 1 discloses a technique for reducing the electric field applied to the insulating film at the bottom of the trench by spreading a depletion layer from the second conductive type protective diffusion layer provided at the bottom of the trench into the drift layer of the first conductivity type. It is shown.
  • Patent Document 2 For each of the nine cells in a matrix shape partitioned by a lattice-like gate electrode, one central cell is used as a protective contact region where the protective diffusion layer and the source electrode are connected.
  • the depletion layer extending from the protective diffusion layer has a certain spread not only when the high voltage is cut off between the drain and source, but also when the drain and source are conductive. Due to this spreading, the on-current path in the drift layer is narrowed, and a resistance component called a JFET (Junction FET) resistance increases. Especially when the protective diffusion layers are adjacent to each other, the on-current path becomes narrow, which can contribute to an increase in on-resistance.
  • JFET Joint FET
  • the present invention reliably connects a protective diffusion layer and a source electrode in a trench gate type semiconductor device in which gate electrodes are arranged in a stripe pattern, and suppresses a decrease in switching speed.
  • An object of the present invention is to provide a semiconductor device that can be used.
  • a semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type base region provided above the semiconductor layer, a source region provided above the base region, and a base in the semiconductor layer.
  • a gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the region, and a gate having a side surface that is provided in the stripe trench and faces the base region through the gate insulating film
  • a plurality of active stripe regions each including an electrode, a protective diffusion layer of a second conductivity type provided at a lower portion of the stripe trench, and a source electrode connected to the source region and the base region;
  • a source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches.
  • a plurality of active stripe regions, and a plurality of first active stripe regions including a protective diffusion layer ground region and a first active stripe region not including a protective diffusion layer ground region.
  • the second active stripe region not including the protective diffusion layer ground region is provided between the first active stripe region including the protective diffusion layer ground region. It becomes possible to connect the layer and the source electrode more reliably, and a decrease in switching speed can be suppressed.
  • 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is an enlarged plan view showing a semiconductor device according to a first embodiment of the present invention;
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • FIG. 1 is a plan view showing the semiconductor device 100 according to the first embodiment.
  • FIG. 2 is a partial cross-sectional view of the semiconductor device 100 according to the first embodiment, and is a partial cross-sectional view taken along line AA in FIG. It is.
  • an n-type MOSFET using silicon carbide will be described as an example.
  • a semiconductor device 100 is a trench gate type MOSFET having gate electrodes 304 arranged in a stripe shape, and has an active stripe region 3 and a protective diffusion layer ground region 4.
  • the gate electrode 304 extends in one direction (the left-right direction in FIG. 1), and a plurality of gate electrodes 304 are arranged in parallel at a predetermined interval.
  • the minimum unit of the section where the on-current path is formed is the active stripe cell 30.
  • the active stripe region 3 is each stripe-shaped region partitioned by the gate electrodes 304 arranged in a stripe shape, and indicates each row arranged in the vertical direction in FIG.
  • one active stripe region 3 is a region (one row) sandwiched between adjacent stripe-shaped gate electrodes 304 and includes gate electrodes 304 on both sides. That is, it is assumed that the gate electrode 304 sandwiched between adjacent active stripe regions 3 is shared by each active stripe region 3.
  • the protective diffusion layer ground region 4 is a region for connecting a source electrode 5 and a protective diffusion layer 306 described later.
  • a region (row) including the protective diffusion layer ground region 4 is referred to as a first active stripe region 3a, and a region (row) not including the protective diffusion layer ground region 4 is a second active stripe region 3a. This is referred to as a stripe region 3b.
  • FIG. 2 is a partial cross-sectional view including both the active stripe region 3 and the protective diffusion layer ground region 4.
  • the semiconductor device 100 includes a SiC substrate 1, an epitaxial layer 2, an ohmic electrode 301a, a source region 302, a base region 303, a gate electrode 304, a gate insulating film 305, a protective diffusion layer 306, an ohmic electrode 401a, And a drain electrode 7.
  • SiC substrate 1 semiconductor substrate
  • epitaxial layer 2 semiconductor layer
  • a drain electrode 7 is formed on the back surface of the SiC substrate 1.
  • a p-type base region 303 is formed on the epitaxial layer 2, and a region of the epitaxial layer 2 excluding the base region 303 becomes an n-type drift layer 2a.
  • An n-type source region 302 is formed in part of the upper portion of the base region 303.
  • a stripe trench 307 that penetrates the source region 302 and the base region 303 and reaches the drift layer 2 a is formed on both sides of the active stripe region 3, and a gate electrode 304 and a gate insulating film 305 are provided in the stripe trench 307. Yes.
  • the gate insulating film 305 is provided on the side surface and the bottom surface of the gate electrode 304, and the side surface of the gate electrode 304 faces the base region 303 and the source region 302 with the gate insulating film 305 interposed therebetween.
  • the film thickness of the gate insulating film 305 at the position corresponding to the bottom surface of the gate electrode 304 may be larger than the film thickness at the position corresponding to the side surface of the gate electrode 304.
  • the gate insulating film 305 shown in FIG. 2 has the same thickness at the side and bottom, only the side actually operates as the gate insulating film, and the bottom does not contribute to the operation as the MOSFET.
  • the electric field tends to concentrate on the bottom of the trench, and the insulating film is easily broken. Therefore, by selectively thickening only the gate insulating film 305 on the bottom surface of the gate electrode 304, the electric field applied to the gate insulating film 305 can be further reduced.
  • a p-type protective diffusion layer 306 is formed on the bottom of the gate electrode 304 (below the stripe trench 307) via the gate insulating film 305.
  • An interlayer insulating film 6 having contact holes 301 and 401 is provided on the gate electrode 304.
  • the source electrode 5 is connected (ohmic contact) to the source region 302 and the base region 303 through the contact hole 301 of the interlayer insulating film 6. More specifically, an ohmic electrode 301a is formed in the contact hole 301, and the source electrode 5 forms an ohmic contact with the source region 302 and the base region 303 via the ohmic electrode 301a.
  • the protective diffusion layer grounding region 4 not only the stripe trenches 307 in which the gate electrodes 304 on both sides are disposed, but also the opening between the base region 303 and the source region 302 not only in the gate electrodes 304 on both sides. A portion 402 is formed. That is, in the protective diffusion layer ground region 4, the stripe trench 307 in which the gate electrodes 304 on both sides are disposed and the opening 402 therebetween are integrated and provided as one opening. In the protective diffusion layer ground region 4, the protective diffusion layer 306 is formed from the bottom of one gate electrode 304 to the bottom of the other gate electrode 304 over the entire lower part of the stripe trench 307 and the opening 402.
  • the source electrode 5 extends from above the epitaxial layer 2 to the bottom of the opening 402 in the protective diffusion layer ground region 4, and the source electrode 5 passes through the contact hole 401 of the interlayer insulating film 6 at the bottom of the opening 402. Connected to the protective diffusion layer 306.
  • an interlayer insulating film 6 is provided in the opening 402 of the protective diffusion layer grounding region 4 so as to cover the upper surface and side surfaces of the gate electrode 304, and the protective diffusion layer grounding region 4 is provided on the interlayer insulating film 6.
  • a contact hole 401 is formed in FIG.
  • An ohmic electrode 401a is formed in the contact hole 401, and the source electrode 5 forms an ohmic contact with the protective diffusion layer 306 via the ohmic electrode 401a.
  • the interlayer insulating film 6 that covers the side surface of the gate electrode 304 is formed integrally with the interlayer insulating film 6 that covers the upper surface of the gate electrode 304, but the upper surface of the interlayer insulating film 6 and the gate electrode 304 that covers the side surface of the gate electrode 304 is formed. It is good also as providing separately with the interlayer insulation film 6 to cover.
  • the thickness of the interlayer insulating film 6 covering the side surface of the gate electrode 304 may be set as appropriate, but the thickness is made larger than that of the gate insulating film 305 in order to reduce the gate-source parasitic capacitance. Is desirable.
  • FIG. 1 is a plan view of the surface of the epitaxial layer 2 of the semiconductor device 100 shown in FIG. 2 in order to improve visibility, and the source electrode 5 and the interlayer insulating film 6 on the epitaxial layer 2 are not shown. It is a plan view.
  • a plurality of gate electrodes 304 are provided in a stripe shape in the left-right direction of FIG. 1, and a region partitioned by adjacent gate electrodes 304 is defined as an active stripe region 3.
  • Each of the gate electrodes 304 is provided in parallel and spaced apart in the short direction of the gate electrode 304 (up and down direction in FIG. 1). Further, it is desirable that the interval between the gate electrodes 304 be constant, that is, the length of the short side of each active stripe region 3 is desirably constant. If active stripe regions 3 having different short sides are mixed, current may concentrate on the active stripe regions 3 having long short sides. Therefore, by concentrating the length of the short side of the active stripe region 3, current concentration in a part of the active stripe regions 3 can be suppressed.
  • a part of the active stripe regions 3 in the active stripe region 3 includes the protective diffusion layer ground region 4.
  • the active stripe region 3 including the protective diffusion layer ground region 4 is changed to the first active stripe region 3.
  • One active stripe region 3a is referred to as an active stripe region 3 that does not include the protective diffusion layer ground region 4 and is referred to as a second active stripe region 3b.
  • the first active stripe region 3a has a plurality of protective diffusion layer ground regions 4 that are spaced apart from each other.
  • a section defined by the two gate electrodes 304 adjacent to the protective diffusion layer ground region 4 becomes the active stripe cell 30.
  • the active stripe cell 30 is a rectangular section whose periphery is partitioned by a gate electrode 304 (including the gate electrode 304 in the protective diffusion layer ground region 4), and an active cell in which an on-current flows according to the potential of the gate electrode 304. It is.
  • FIG. 3 is an enlarged plan view of the semiconductor device 100 according to the present embodiment around the boundary between the active stripe cell 30 and the protective diffusion layer grounding region 4.
  • the gate electrode 304 and the gate insulating film 305 are formed along the short side of the active stripe cell 30 in the protective diffusion layer ground region 4.
  • the gate electrodes 304 formed along the short sides of the active stripe cell 30 connect the gate electrodes 304 formed in adjacent stripe trenches. Therefore, the protective diffusion layer ground region 4 includes a gate electrode 304 formed in the stripe trench 307 (a gate electrode 304 extending in the horizontal direction in FIG. 3) and a gate electrode formed along the short side of the active stripe cell 30.
  • the region is divided by 304 (the gate electrode 304 extending in the vertical direction in FIG. 3).
  • the ON current path is narrowed by the depletion layer extending from the protective diffusion layer 306 except for the vicinity of the short side of the active stripe cell 30. There are only two directions. Therefore, an increase in JFET resistance can be suppressed as compared with the case where the gate electrode 304 is a lattice type. On the other hand, in such a stripe-type cell layout, the channel resistance increases because the channel width density decreases.
  • the on-resistance can be reduced as compared with the lattice-type layout. it can. Specifically, it is desirable that the long side of the active stripe cell 30 is 1.5 or more, more preferably 2.0 or more with respect to the short side.
  • the second active stripe region 3b does not include the protective diffusion layer ground region 4, the entire second active stripe region 3b becomes one active stripe cell 30.
  • the first active stripe region 3 a and the second active stripe region 3 b are alternately arranged in the short side direction of the active stripe region 3.
  • the protective diffusion layer grounding regions 4 are arranged at regular intervals.
  • the protective diffusion layer grounding region 4 is roughly square in shape, but may be any shape such as other polygons, and the length of each side is the short side of the active stripe region 3. It is not necessarily equal to the length. However, in order to make the short side of the active stripe region 3 the same in all the active stripe regions 3, it is desirable that one side of the protective diffusion layer ground region 4 is an integral multiple of the short side of the active stripe region 3.
  • the semiconductor device 100 operates by switching between an on state and an off state according to a voltage applied to the gate electrode 304.
  • a voltage equal to or higher than a threshold voltage for example, a voltage of 20 V
  • a threshold voltage for example, a voltage of 20 V
  • a voltage lower than the threshold voltage for example, a voltage of 0 V
  • a voltage lower than the threshold voltage for example, a voltage of 0 V
  • the semiconductor device 100 switches between the above-described on-state and off-state according to the voltage applied to the gate electrode 304, thereby realizing a switching operation.
  • a parasitic capacitance called a depletion capacitance exists between the protective diffusion layer 306 and the drift layer 2a.
  • the protective diffusion layer 306 provided under the stripe trench 307 is connected to the source electrode 5 through at least one of the protective diffusion layer ground regions 4.
  • a charge / discharge current of parasitic capacitance flows between the protective layer 5 and the protective diffusion layer 306.
  • 4 to 10 are cross-sectional views showing the steps of the method for manufacturing the semiconductor device 100.
  • the material, dimensions, and the like of each component are merely examples, and the present invention is not limited thereto.
  • epitaxial layer 2 (semiconductor layer) is formed on SiC substrate 1.
  • an n-type low-resistance SiC substrate 1 having a 4H polytype was prepared, and an n-type epitaxial layer 2 was epitaxially grown thereon by a chemical vapor deposition (CVD) method.
  • the epitaxial layer 2 has an n-type impurity concentration of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 and a thickness of 5 to 200 ⁇ m.
  • the surface of the SiC substrate 1 is an angle of 4 ° (off angle) with respect to the (0001) plane which is the c-plane of the SiC crystal.
  • a base region 303 and a source region 302 are formed by ion-implanting a predetermined dopant into the surface of the epitaxial layer 2.
  • the base region 303 is formed by ion implantation of aluminum (Al) which is a p-type impurity.
  • Al aluminum
  • the depth of Al ion implantation is about 0.5 to 3.0 ⁇ m within a range not exceeding the thickness of the epitaxial layer 2.
  • the impurity concentration of Al to be implanted is set higher than the n-type impurity concentration of the epitaxial layer 2.
  • the p-type impurity concentration of the base region 303 is set to a range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the region of the epitaxial layer 2 deeper than the Al implantation depth becomes the n-type drift layer 2a.
  • the base region 303 may be formed by p-type epitaxial growth. Even in such a case, the impurity concentration and thickness of the base region 303 are the same as those formed by ion implantation.
  • the source region 302 is formed by ion-implanting nitrogen (N) that is an n-type impurity into part of the surface of the base region 303.
  • the planar pattern of the source region 302 is formed with a pattern corresponding to the layout of the gate electrode 304 formed in a process described later. Specifically, the planar arrangement of the source region 302 is determined so that the source region 302 is disposed on both sides of the gate electrode 304 when the gate electrode 304 is formed.
  • the N ion implantation depth is made shallower than the thickness of the base region 303.
  • the impurity concentration of N to be implanted is not less than the p-type impurity concentration of the base region 303 and not more than 1 ⁇ 10 21 cm ⁇ 3 .
  • a depletion suppression layer (not shown) having an n-type impurity concentration higher than that of the drift layer 2a may be provided below the base region 303.
  • a current path is narrowed by a depletion layer extending from both the base region 303 and the protective diffusion layer 306, and a so-called JFET resistance is generated between them.
  • the depletion suppression layer is provided as described above, since the extension of the depletion layer from the base region 303 can be suppressed when the semiconductor device 100 is turned on, the JFET resistance can be reduced.
  • the depletion suppression layer is formed by ion implantation of nitrogen (N) or phosphorus (P) which are n-type impurities.
  • the depth of the depletion suppressing layer is preferably deeper than the base region 303 and within the range not exceeding the thickness of the epitaxial layer 2, and the thickness is preferably about 0.5 to 3 ⁇ m.
  • the impurity concentration of N to be implanted is preferably higher than the n-type impurity concentration of the epitaxial layer 2 and 1 ⁇ 10 17 cm ⁇ 3 or more.
  • the depletion suppression layer may be formed by n-type epitaxial growth. In such a case, the impurity concentration and thickness of the depletion suppression layer are the same as those formed by ion implantation.
  • the depletion suppression layer may be a planar pattern in which only the central portion of the active stripe cell 30 is removed.
  • a silicon oxide film 8 is deposited on the surface of the epitaxial layer 2 by about 1 to 2 ⁇ m, and an etching mask 9 made of a resist material is formed on the silicon oxide film 8.
  • the etching mask 9 is formed in a pattern opened corresponding to a trench formation region by a photolithography technique. Then, the silicon oxide film 8 is patterned by a reactive ion etching (RIE) process using the etching mask 9 as a mask. Thereby, the pattern of the etching mask 9 is transferred to the silicon oxide film 8.
  • the patterned silicon oxide film 8 becomes an etching mask for the next step.
  • RIE reactive ion etching
  • a stripe trench 307 and an opening 402 that penetrate the source region 302 and the base region 303 are formed in the epitaxial layer 2 by RIE using the patterned silicon oxide film 8 as a mask.
  • the depth of the trench is not less than the depth of the base region 303 and is about 1.0 to 6.0 ⁇ m.
  • the planar pattern of the trench corresponds to the planar pattern in which the gate electrode 304 and the gate insulating film 305 in FIG. 1 are combined. More specifically, a plurality of stripe trenches 307 are provided in a stripe shape so as to define the active stripe region 3, and only the region corresponding to the protective diffusion layer ground region 4 is also formed between adjacent stripe trenches 307.
  • An opening 402 is formed, and the entire protective diffusion layer grounding region 4 is etched.
  • the stripe trench 307 defining the active stripe region 3 and the opening 402 formed in the protective diffusion layer ground region 4 are collectively referred to as a trench.
  • the stripe trench 307 (active stripe region 3) is arranged in parallel to the step flow of the epitaxial layer 2 formed by the off angle of the SiC substrate 1.
  • a portion adjacent to the gate electrode 304 in the active stripe region 3 functions as a MOSFET.
  • an implantation mask 10 having the same pattern as the etching mask 9 is formed by opening a trench portion, and ion implantation using the implantation mask 10 as a mask is performed to form a p-type protective diffusion layer 306 at the bottom of the trench.
  • Al is used as a p-type impurity.
  • the impurity concentration of Al to be implanted is preferably in the range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 and the thickness is preferably in the range of 0.1 to 2.0 ⁇ m.
  • the Al impurity concentration of the protective diffusion layer 306 is determined from the electric field applied to the gate insulating film 305 when a working breakdown voltage is applied between the drain and source of the MOSFET.
  • a (patterned) silicon oxide film 8 that is an etching mask for forming a trench may be used instead of the implantation mask 10. Thereby, simplification of the manufacturing process and cost reduction can be achieved.
  • the silicon oxide film 8 is used instead of the implantation mask 10, it is necessary to adjust the thickness and etching conditions of the silicon oxide film 8 so that the silicon oxide film 8 having a sufficient thickness remains after the trench is formed. There is.
  • annealing is performed using a heat treatment apparatus, thereby activating the impurities implanted by the above process.
  • the annealing treatment is performed in an inert gas atmosphere such as argon (Ar) gas or in vacuum under conditions of 1300 to 1900 ° C. and 30 seconds to 1 hour.
  • a polysilicon film 12 is deposited by a low pressure CVD method.
  • the gate insulating film 305 and the gate electrode 304 are formed in the stripe trench 307 by patterning or etching back the silicon oxide film 11 and the polysilicon film 12.
  • the silicon oxide film 11 to be the gate insulating film 305 may be formed by thermally oxidizing the surface of the epitaxial layer 2 or may be formed by being deposited on the epitaxial layer 2.
  • the interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 2 by low pressure CVD, and the gate electrode 304 is covered with the interlayer insulating film 6. Further, by patterning the interlayer insulating film 6, a contact hole 301 reaching the source region 302 and the base region 303 is formed in the active stripe region 3, and a contact hole 401 reaching the protective diffusion layer 306 is formed in the protective diffusion layer ground region 4. Form. Then, ohmic electrodes 301 a and 401 a are formed on the surface of the epitaxial layer 2 exposed at the bottoms of the contact holes 301 and 401.
  • a metal film containing Ni as a main component is formed on the entire surface of the epitaxial layer 2 including the inside of each contact hole, and reacted with silicon carbide by heat treatment at 600 to 1100 ° C.
  • a silicide film to be an ohmic electrode is formed.
  • an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 5 on the interlayer insulating film 6 and in the contact holes 301 and 401 (not shown).
  • an electrode material such as an Al alloy is deposited on the lower surface of the SiC substrate 1 to form the drain electrode 7 (not shown).
  • FIG. 21 and 22 show a comparative example of the semiconductor device 100 according to the present embodiment.
  • FIG. 21 shows a semiconductor device 200 in which a protective diffusion layer grounding region 4 is provided in a central section of nine sections in a lattice layout in which gate electrodes 304 are arranged in a lattice form as shown in Patent Document 2.
  • FIG. 22 shows a semiconductor device 300 in which the gate electrode 304 is replaced with a stripe layout in the semiconductor device 200 shown in FIG.
  • the active cells divided by the lattice-like gate electrodes 304 are surrounded by the gate electrodes 304 in four directions, they extend from the protective diffusion layer 306 provided at the bottom of each gate electrode 304. Due to the influence of the depletion layer, the on-current path is narrowed from four directions, which may increase the on-resistance. Therefore, when the layout of the gate electrode 304 is changed from the lattice type to the stripe type in order to suppress such an increase in on-resistance, the semiconductor device 300 shown in FIG. 22 is obtained. In the semiconductor device 300, the on-current path is narrowed only in two directions except for the vicinity of the short side of the active stripe cell 30, so that the on-current path can be widened and the on-resistance can be reduced.
  • the semiconductor device 300 shown in FIG. 22 there is a region where the second active stripe regions 3b are arranged without including the protective diffusion layer ground region 4, and the stripe trench 307 between the adjacent second active stripe regions 3b.
  • the stripe trenches 307 in the second, fifth, and eighth rows from the top in FIG. 22 do not contact the protective diffusion layer ground region 4. Therefore, the protective diffusion layer 306 provided below the stripe trenches 307 is not connected to the protective diffusion layer ground region 4.
  • the potential of the protective diffusion layer 306 that is not in contact with the protective diffusion layer ground region 4 becomes floating, and the response speed of the depletion layer is delayed as compared with the other protective diffusion layers 306 during the transient response.
  • the gate insulating film may be destroyed due to an increase in switching loss, characteristic variations in the semiconductor device 300, and eventually current concentration during high-speed operation.
  • the active stripe region 3 includes the first active stripe region 3 a including the protective diffusion layer ground region 4 and the second active stripe region 3 b not including the protective diffusion layer ground region 4. Since the second active stripe regions 3b that do not include the protective diffusion layer ground region 4 are sandwiched between the first active stripe regions 3a that include the protective diffusion layer ground region 4, Thus, all the stripe trenches 307 are connected to the protective diffusion layer ground region 4. As a result, there is no place where the protective diffusion layer 306 provided below the stripe trench 307 is in a floating state, and an increase in switching loss, variation in characteristics within the semiconductor device 300, and further current concentration during high-speed operation, Problems such as destruction can be suppressed.
  • the layout of the gate electrode 304 is striped to widen the on-current path and reduce the on-resistance, and part of the protective diffusion layer 306 is in a floating state. Therefore, problems such as an increase in switching loss, characteristic variations in the semiconductor device 100, and breakdown of the gate insulating film 305 due to current concentration during high-speed operation can be suppressed.
  • the gate electrode 304 has a stripe layout, so that the current path becomes wider compared to the lattice layout, so that the increase in JFET resistance with a rise in temperature becomes moderate.
  • the temperature characteristics of on-resistance can be improved.
  • the source electrode 5 and the protective diffusion layer 306 are connected in the protective diffusion layer ground region 4.
  • an opening may be partially provided between the gate electrodes 304 on both sides in the protective diffusion layer ground region 4, but the protective diffusion layer ground is provided as in the present embodiment.
  • an opening is provided between the gate electrodes 304 on both sides, and the source electrode 5 and the protective diffusion layer 306 are connected within the opening 402, thereby expanding the contact area, and the source electrode 5 and the protective diffusion layer. The contact resistance with 306 can be reduced.
  • the position in the depth direction where the source electrode 5 and the protective diffusion layer 306 are in contact with each other may be appropriately changed, but as in the semiconductor device 100 according to the present embodiment,
  • the source electrode 5 preferably extends to the bottom of the opening 402 deeper than the base region 303 and is connected to the protective diffusion layer 306 at the bottom of the opening 402. .
  • the protective diffusion layer 306 can be formed up to the surface of the epitaxial layer 2 and connected to the source electrode 5.
  • the source electrode 5 having a resistivity lower than that of the diffusion layer 306 is extended to the bottom of the opening 402 and the source electrode 5 and the protective diffusion layer 306 are connected to each other, so that the gap between the protective diffusion layer 306 and the source electrode 5 is reached. Resistance can be reduced and switching loss can be reduced.
  • the interlayer insulating film 6 that covers the side surface of the gate electrode 304 is thicker than the gate insulating film 305 in the opening 402 of the protective diffusion layer ground region 4.
  • the parasitic capacitance between the gate and the source can be reduced, and the switching characteristics (loss, time, etc.) can be improved.
  • FIGS. 11 to 13 are plan views showing modifications of the semiconductor device 100 according to the present embodiment.
  • FIGS. 11 to 13 are plan views showing modifications of the semiconductor device 100 according to the present embodiment.
  • the base region 303 exposed in the contact hole 301 in the active stripe region 3 is divided into a plurality of regions as compared with the semiconductor device 100 according to the present embodiment. The only difference is that it has been changed.
  • the base region 303 exposed in the contact hole 301 has a single rectangular shape corresponding to the shape of the rectangular active stripe cell 30.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of square regions, and has a constant interval. Are provided apart from each other.
  • the reduction in channel width density can be suppressed by reducing the pitch in the short side direction of the active stripe region 3.
  • reducing the distance between the contact hole 301 and the gate electrode 304 may increase the gate-source leakage rate, a certain distance is ensured between the contact hole 301 and the gate electrode 304.
  • reducing the size of the contact hole leads to an increase in contact resistance. Although the channel resistance can be reduced, the contact resistance increases.
  • the contact area between the source region 302 and the source electrode 5 can be increased, and the contact resistance can be reduced.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is divided into a plurality of regions, and the source region 302 is interposed between the plurality of divided base regions 303. Is exposed. Therefore, compared with the semiconductor device 100 shown in FIG. 1, the area of the source region 302 in the contact hole 301 can be increased, and the contact resistance between the source region 302 and the source electrode 5 can be reduced.
  • the occupied area of the base region 303 in the contact hole 301 is desirably 20% or more.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of rectangular regions and is provided at regular intervals. Each of the base regions 303 exposed on the surface extends from one of the adjacent stripe trenches 307 to the other in the short side direction of the active stripe region 3.
  • each of the base regions 303 exposed on the surface is uniformly provided in the short side direction of the active stripe region 3 between the stripe trenches 307. Even when the position of the contact hole 301 is shifted in the side direction, the area of the source region 302 in the contact hole 301 does not change. Therefore, the pitch in the short side direction of the active stripe region 3 can be further reduced, and the on-resistance can be reduced.
  • the composition ratio of the first active stripe region 3a and the second active stripe region 3b is 2: 1. More specifically, in the short side direction of the active stripe region 3, two first active stripe regions 3a and two second active stripe regions 3b are arranged as a minimum unit, and this is repeatedly arranged. It is out. Further, the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 is twice the short side of the active stripe region 3, and the two adjacent first active stripe regions 3a are adjacent to each other. A common protective diffusion layer ground region 4 is provided.
  • the configuration ratio of the first active stripe region 3a and the second active stripe region 3b is not limited to 2: 1 and can be set as appropriate.
  • the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 corresponds to the composition ratio of the first active stripe region 3a and the second active stripe region 3b. If the width is an integral multiple of the width of the short side, the short sides of the active stripe region 3 can be arranged equally.
  • the first active stripe region 3a including the protective diffusion layer ground region 4 and the second active stripe region 3b not including the protective diffusion layer ground region 4 are alternately arranged.
  • the arrangement of the first active stripe region 3a and the second active stripe region 3b is not limited to this.
  • one second active stripe region 3b may be provided for each of the plurality of first active stripe regions 3a.
  • the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is floated. There is a fear. Therefore, as shown in FIG.
  • the first active stripe region 3a is adjacent to both sides of each second active stripe region 3b, and the second active stripe region 3b is sandwiched between the first active stripe regions 3a. Arrange so that. Thereby, it is possible to prevent a part of the protective diffusion layer 306 from floating.
  • the second active stripe region 3b that does not include the protective diffusion layer ground region 4 is disposed so as to be sandwiched between the first active stripe region 3a that includes the protective diffusion layer ground region 4, Some of the protective diffusion layers 306 can be prevented from floating, and deterioration of switching characteristics can be suppressed.
  • FIG. FIG. 14 is a plan view showing the semiconductor device 110 according to the second embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that an intersection trench 308 that intersects with the stripe trench 307 is provided.
  • the first active stripe region 3a including the protective diffusion layer ground region 4 is disposed adjacent to both sides of the second active stripe region 3b not including the protective diffusion layer ground region 4.
  • the second active stripe regions 3b are adjacent to each other, and the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is prevented from floating.
  • the second active stripe region can be obtained by providing the intersecting trench 308 intersecting the stripe trench 307.
  • a protective diffusion layer 306 provided below the stripe trench 307 between 3 b can be connected to the source electrode 5.
  • an intersection trench 308 that intersects with the stripe trench 307 in a direction perpendicular to the longitudinal direction of the stripe trench 307 is provided.
  • a gate electrode 304 and a gate insulating film 305 are disposed in the intersection trench, and a protective diffusion layer 306 is also provided under the intersection trench.
  • the intersecting trenches are respectively provided between two adjacent protective diffusion layer ground regions 4 and extend in the short side direction of the active stripe region 3. More specifically, the intersecting trench 308 is provided between the adjacent protective diffusion layer ground regions 4 so as to connect the two adjacent protective diffusion layer ground regions 4 in the short side direction of the active stripe region 3. Between the protective diffusion layer ground regions 4 to be crossed, the stripes 307 perpendicularly intersect with the second active stripe regions 3b.
  • the protective diffusion layer 306 provided below the stripe trench 307 sandwiched between the second active stripe regions 3b is floating, but in the semiconductor device 110 according to the present embodiment, The protective diffusion layer 306 below the stripe trench sandwiched between the second active stripe regions 3b is also connected to the protective diffusion layer ground region 4 via the protective diffusion layer 306 provided below the intersecting trench 308. Become. Accordingly, since the protective diffusion layer 306 can be connected to the source electrode 5 more reliably, an increase in switching loss, a variation in characteristics within the semiconductor device 300, and a breakdown of the gate insulating film due to current concentration during high-speed operation can be prevented. Can be suppressed.
  • the semiconductor device 110 by providing the intersecting trench 308 in which the gate electrode 304 is provided, a channel is also formed on the side surface of the intersecting trench 308, so that the channel width density is improved. Thus, the on-resistance can be reduced.
  • the intersection trench 308 by providing the intersection trench 308, the length of the long side of the active stripe cell 30 is narrowed, and the JFET resistance due to the depletion layer extending from the protective diffusion layer 306 may increase.
  • the active stripe cells 30 are set to have at least a stripe shape (rectangular shape), preferably the length of the long side of the active stripe cell 30 is 1.5 times the length of the short side, more preferably 2. It is set to be 0 times or more.
  • the semiconductor device 200 shown in FIG. 21 has a lattice-type gate electrode arrangement, if at least one protective diffusion layer ground region 4 is provided, all the protective diffusion layers 306 provided below the gate electrode 304 are provided. Inevitably is connected to the source electrode 5, but the depletion layer from the protective diffusion layer 306 extends from the four directions in each active cell, increasing the JFET resistance and increasing the on-resistance.
  • the gate electrode 304 is changed to a striped layout as it is in the structure of the semiconductor device 200 of FIG. As described above, becomes floating and causes deterioration of switching characteristics.
  • a part of the protective diffusion layers 306 is formed by connecting the protective diffusion layers 306 provided below the stripe trenches 307 via the protective diffusion layers 306 provided below the intersection trenches 308.
  • intersection trench 308 is not limited to the structure in which the second active stripe regions 3b are adjacent to each other as in the present embodiment.
  • the first active stripe region 3b is provided.
  • the intersection trench 308 may be provided.
  • FIG. 15 shows a semiconductor device 111 according to a modification of the present embodiment.
  • the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short side direction, and the second active stripe region 3b Are provided with intersecting trenches 308 at regular intervals in the long side direction of the active stripe region 3.
  • an intersection trench 308 is provided for each protective diffusion layer ground region 4, and one end of each intersection trench 308 is connected to the protection diffusion layer ground region 4.
  • the channel width density is improved and the on-resistance is increased. Can be reduced.
  • the deterioration of the switching characteristics can be suppressed by connecting the stripe trench 307 that can be floated by the intersection trench 308 and the protective diffusion layer grounding region 4.
  • the cross trench 308 since the cross trench 308 is provided, a channel region can be formed on the side surface of the cross trench 308, so that the channel width density can be improved and the on-resistance can be reduced.
  • FIG. 16 is a plan view showing a semiconductor device 120 according to the third embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding components.
  • the present embodiment is different from the first embodiment in that the protective diffusion layer ground region 4 is provided in all the active stripe regions 3.
  • each of the plurality of active stripe regions 3 is provided with a protective diffusion layer ground region 4, that is, only the first active stripe region 3 a including the protective diffusion layer ground region 4.
  • the protective diffusion layer ground region 4 of each active stripe region 3 is continuously formed in the short side direction of the active stripe region 3.
  • the protective diffusion layer ground region 4 in the present embodiment is formed by one stripe-shaped opening extending in the short side direction (vertical direction in FIG. 16) of the active stripe region 3.
  • a plurality of stripe-shaped protective diffusion layer ground regions 4 are provided at regular intervals in the longitudinal direction of the active stripe region 3.
  • a gate electrode 304 is provided on both side surfaces of a striped opening (protective diffusion layer grounding region 4) extending in the vertical direction in FIG. 16 (not shown). Therefore, the plurality of gate electrodes 304 provided in the stripe trenches 307 extending in the left-right direction in FIG. 16 and defining the active stripe cell 30 are connected to each other by the gate electrodes 304 provided in the protective diffusion layer ground region 4. Will be. Accordingly, the protective diffusion layer 306 provided below the stripe trench 307 (gate electrode 304) is connected to each other by the protective diffusion layer 306 provided below the opening 402 in the protective diffusion layer ground region 4, and The protective diffusion layer ground region 4 is connected to the source electrode 5.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is prevented that a part of the protective diffusion layer 306 is floated and the switching characteristics are deteriorated. be able to.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, but the ratio of the protective diffusion layer ground region 4 is relatively increased as compared with the first embodiment. There is a risk. Since the on-current path is not formed in the protective diffusion layer ground region 4, if the protective diffusion layer ground region 4 is made dense, the on-current path may be narrowed and the on-resistance may be increased. Therefore, it is desirable that the interval between the protective diffusion layer grounding regions 4 is larger than that in the first embodiment, and the exclusive area of the protective diffusion layer grounding region 4 is set to a ratio that does not hinder the on-resistance. It is desirable to do.
  • FIG. 17 shows a plan view of a semiconductor device 121 according to a modification of the present embodiment.
  • the protective diffusion layer ground region 4 is provided in each active stripe region 3, and the protective diffusion layer ground region 4 included in each active stripe region 3 is provided in order to reduce the gate resistance. They are provided at regular intervals.
  • a gate electrode 304 is disposed along each side of the square-shaped protective diffusion layer grounding region 4. Thereby, since the gate electrode 304 is not divided by the protective diffusion layer grounding region 4, an increase in gate resistance can be suppressed.
  • the protective diffusion layer ground region 4 of each adjacent active stripe region 3 is formed continuously and formed by one stripe-shaped opening, but the protective diffusion layer ground region 4 is formed. May be divided into a plurality of sections.
  • FIG. 18 shows a modification in which the protective diffusion layer ground region 4 is divided into a plurality of sections in the semiconductor device 120 according to the present embodiment.
  • the protective diffusion layer grounding region 4 is composed of a plurality of spaced square sections, and a plurality of columns in which the protective diffusion layer grounding regions 4 are arranged in a plurality of spaced apart are provided. .
  • Active stripe cells 30 are formed between columns of the protective diffusion layer ground region 4.
  • square active cells 31 are provided between a plurality of sections constituting the protective diffusion layer grounding region 4.
  • the side in the short side direction of the active stripe region 3 in the active cell 31 is composed of two intersecting trenches 308 intersecting with the stripe trench 307, and a gate electrode 304 and a gate insulating film 305 are arranged inside the intersecting trench 308.
  • a protective diffusion layer 306 is provided below the intersection trench 308.
  • a trench extending in the longitudinal direction of the active stripe region 3 is provided at the boundary between the active cell 31 and the protective diffusion layer ground region 4, and a gate electrode 304 is provided inside the trench.
  • the on-current path is increased and the channel width density is also increased. As a result, the on-resistance can be reduced.
  • the active stripe cell 30 is also referred to as a first active cell, and the active cell 31 is also referred to as a second active cell. If an attempt is made to configure only a single-shaped active cell and a protective diffusion layer ground region, it may be difficult to sufficiently adjust the exclusive ratio of active cells in the entire semiconductor device. Therefore, in the semiconductor device 122 shown in FIG. 18, the stripe-shaped first active cell (30) and the square-shaped second active cell (31) having a different planar shape from the first active cell are provided. Since the space in the planar direction can be fully utilized and the area that can be utilized as the on-current path can be increased, the on-resistance can be reduced.
  • the boundary between the protective diffusion layer ground region 4 and the active cell 31 is a half cycle of the pitch in the short side direction of the active stripe cell 30 with respect to the boundary between the active stripe cells 30.
  • the protective diffusion layer grounding region 4 is provided so as to be shifted by the amount.
  • Each active stripe region 3 includes a part (half) of the protective diffusion layer ground region 4.
  • the “active stripe region 3 includes the protective diffusion layer ground region 4.
  • the configuration of “included” includes the active stripe region 3 including a part of the protective diffusion layer ground region 4 as described above.
  • the gate electrode 304 since the gate electrode 304 is integrally formed without being divided, an increase in gate resistance can be suppressed.
  • the protective diffusion layer grounding region 4 has a square shape, but is not limited thereto.
  • FIG. 19 shows a semiconductor device 123 in which the planar shape of the protective diffusion layer ground region 4 is rectangular in the semiconductor device 122 shown in FIG. As shown in FIG. 19, the protective diffusion layer grounding region 4 may have a rectangular shape.
  • the protective diffusion layer ground region 4 has the same shape as that of the active stripe cell 30, and accordingly, the active cell 31 provided between the protective diffusion layer ground regions 4 also has the same rectangular shape as that of the active stripe cell 30. It becomes a shape.
  • the protective diffusion layer grounding region 4 and the active stripe cell 30 are not limited to a rectangular shape, and may be configured in a polygonal shape such as a hexagon.
  • 20 shows a semiconductor device 124 in which the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 in the semiconductor device 122 shown in FIG. 18 is hexagonal.
  • the protective diffusion layer ground region 4 and the active cell 31 are formed in a regular hexagonal shape, and the active stripe cell 30 has a shape in which the regular hexagonal shape is extended in one direction along the stripe trench 307. Further, as shown in FIG.
  • the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 are separated by an intersection trench 308 that intersects with the stripe trench 307. Further, in FIG. 20, the plane orientation of the side wall of the epitaxial layer 2 formed by the intersecting trench 308 having an obtuse angle with respect to the stripe trench 307 is constituted by a plane equivalent to the (10-10) plane. As a result, the influence of the off-angle can be reduced and the reduction in gate breakdown voltage can be suppressed.
  • the ratio of the long side to the short side of the active stripe cell 30 is the distance between the long sides of the active stripe cell 30. It can be considered and calculated as a short side. Even if the shape of the active stripe cell 30 changes, the ratio of the long side to the short side is preferably 1.5 or more, more preferably 2.0 or more.
  • the cross trench 308 provided in the second embodiment is not necessarily orthogonal to the stripe trench 307, and the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 is the same. Accordingly, it may be provided.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is possible to suppress a part of the protective diffusion layer 306 from floating and to suppress deterioration of switching characteristics and the like. be able to.
  • FIG. 23 is a plan view showing a semiconductor device 130 according to the fourth embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that the apex portion of the active cell in plan view has a curvature.
  • the first active cell (active stripe cell 30) and the second active cell (active cell 31) are collectively referred to as an active cell.
  • the trench surrounds the apex portion of the active stripe cell 30 from two directions.
  • the apex portion of the active stripe cell 30 transitions to the on state with a lower gate voltage than the side wall portion.
  • the threshold voltage of the apex portion is lower than that of the side wall portion. Lowering the threshold voltage at the apex is not preferable because it causes phenomena such as lowering the threshold voltage of the entire MOSFET and increasing switching loss.
  • trenches and gate electrodes 304 corresponding to the apex portions of the active stripe cells 30 are formed in an arc shape, and the outline of the active stripe cells 30 is expressed as apexes.
  • the concentration of the gate electric field in the channel region at the apex portion can be relaxed and the applied gate electric field can be weakened. Thereby, the fall of the threshold voltage in a vertex part can be suppressed.
  • the radius of curvature of the apex portion is desirably 10% or more and 50% or less of the length Lm on the short side of the active stripe cell 30. This is because when the curvature is small, a sufficient double gate electric field reduction effect cannot be obtained, and when the curvature is large, the tip of the active stripe cell 30 is sharp, and the gate electric field is applied to this portion twice. It is.
  • Embodiments 2 and 3 can be used in combination with Embodiments 2 and 3 as well as Embodiment 1.
  • An example in combination with Embodiment Mode 2 is shown in FIG. In this case, it is necessary to change the shape of the both sides of the intersection trench 308 to have a similar curvature.
  • the active stripe cell 30 but also the active cell 31 may be provided with a curvature at the apex portion.
  • not only a rounded rectangle but a rounded polygon may be used.
  • the gate electric field applied to the apex portion is reduced, and the phenomenon that the apex portion becomes smaller in threshold than the side wall portion is reduced. can do.
  • FIG. FIG. 25 is a plan view showing a semiconductor device 140 according to the fifth embodiment of the present invention.
  • parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted.
  • 25 the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that a part of the stripe trench 307 is replaced with a dummy trench 309.
  • some stripe trenches 307 are replaced with dummy trenches 309.
  • the dummy trench 309 is separated from the other stripe trenches 307, and the gate electrode (second gate electrode) formed in the dummy trench 309 via the gate insulating film is a gate electrode in the other stripe trench 307.
  • the channel region that is not connected to 304 and adjacent to the second gate electrode does not operate.
  • the dummy trench 309 has the same depth as the stripe trench 307. This is because if the depth is the same, the stripe trench 307 and the dummy trench 309 can be formed simultaneously by changing the mask pattern when forming the trench.
  • the second gate electrode formed in the dummy trench 309 does not operate at all, and the channel region adjacent to the second gate electrode also does not operate. As a result, even when the threshold voltage is small, it is impossible to control the charge in the channel region by applying a negative voltage to the second gate electrode. -There is a concern that the leakage current between the sources will increase. For this, a method in which the source region 302 is not formed only in the region adjacent to the dummy trench 309 can be employed. In addition, when the threshold voltage is sufficiently high, it is not necessary to apply a negative voltage to the gate electrode 304. Therefore, a method of not forming the source region 302 only in the region adjacent to the dummy trench 309 is not necessarily required.
  • the protective diffusion layer 306 at the bottom of each is separated, so that the response speed of the protective diffusion layer 306 provided in the dummy trench 309 is the same as that of the stripe trench 307.
  • the dummy trench 309 is also preferably connected to the protective diffusion layer ground region 4. When the protective diffusion layer ground region 4 is not provided, it is necessary to consider that the protective diffusion layer 306 of the stripe trench 307 and the protective diffusion layer 306 of the dummy trench 309 are connected.
  • the parasitic capacitance of the MOSFET can be reduced and the switching loss can be improved.
  • the MOSFET having a structure in which the drift layer 2 and the SiC substrate 1 (buffer layer) have the same conductivity type has been described.
  • the drift layer 2 and the substrate 1 have different conductivity types.
  • the present invention is also applicable to an IGBT having a structure.
  • the SiC substrate 1 is a p-type substrate with respect to the semiconductor device 100 shown in FIG. 2, an IGBT configuration is obtained.
  • the source region 302 and source electrode 5 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively
  • the drain electrode 7 of the MOSFET corresponds to the collector electrode of the IGBT.
  • the source region and the source electrode in this specification include an emitter region and an emitter electrode, and the drain electrode includes a collector electrode.
  • the n-type SiC substrate serving as the substrate may be deleted, and a p-type region formed by ion implantation in the epitaxial layer 2 may be used as the p-type substrate.
  • the semiconductor device formed using SiC which is one of the wide band gap semiconductors
  • other wide band gap semiconductors such as gallium nitride (GaN) -based materials and diamond are used.
  • the present invention can also be applied to a semiconductor device using silicon and a semiconductor device using a silicon semiconductor.
  • the n-type insulated gate semiconductor device has been described as an example in the above-described embodiment, the present invention may be applied to a p-type insulated gate semiconductor device.
  • a wide band gap semiconductor is a semiconductor having a wider band gap than at least a silicon semiconductor.
  • Embodiment 6 the semiconductor device according to the first to third embodiments described above is applied to a power conversion device.
  • the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a sixth embodiment.
  • FIG. 26 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 26 includes a power supply 1000, a power conversion device 2000, and a load 3000.
  • the power supply 1000 is a DC power supply and supplies DC power to the power converter 2000.
  • the power source 1000 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good.
  • the power supply 1000 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, converts the power supplied from the power source 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 26, the power conversion device 2000 converts a DC power into an AC power and outputs the main conversion circuit 2001, and a drive circuit 2002 that outputs a drive signal that drives each switching element of the main conversion circuit 2001. And a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the drive circuit 2002.
  • the load 3000 is a three-phase motor driven by AC power supplied from the power converter 2000.
  • the load 3000 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 3000 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 2001 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 2001 converts DC power supplied from the power source 1000 into AC power and supplies the AC power to the load 3000.
  • the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes.
  • the semiconductor device according to any of the first to third embodiments described above is applied to each switching element of the main conversion circuit 2001.
  • the six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
  • the drive circuit 2002 generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies it to the control electrode of the switching element of the main conversion circuit 2001. Specifically, in accordance with a control signal from a control circuit 2003 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element.
  • the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
  • the control circuit 2003 controls the switching element of the main conversion circuit 2001 so that desired power is supplied to the load 3000. Specifically, based on the power to be supplied to the load 3000, the time (ON time) during which each switching element of the main converter circuit 2001 is to be turned on is calculated. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 2002 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. In accordance with this control signal, the drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.
  • the semiconductor device according to any one of the first to third embodiments is applied to the switching element of the main conversion circuit 2001, the switching loss of the switching element is reduced and high-speed switching is performed. High frequency and reduction of switching loss can be realized, and a highly efficient power conversion device can be provided.
  • the present invention is not limited to this, and can be applied to various power conversion devices.
  • a two-level power converter is used.
  • a three-level or multi-level power converter may be used.
  • the present invention is applied to a single-phase inverter. You may apply.
  • the present invention can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor.
  • the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • each embodiment can be appropriately modified and omitted.
  • a configuration in which a plurality of base regions 303 are exposed in a single contact hole 301 shown in FIG. 11 as a modification of the first embodiment can be applied to any configuration of the second to fifth embodiments. It is possible, and the modification in each embodiment can be applied as appropriate to other embodiments.

Abstract

This semiconductor device comprises: a plurality of active stripe regions (3) which are separated from one another by a plurality of stripe trenches (307); and protection diffusion layer grounding regions (4) in each of which a source electrode (5) is connected to a protection diffusion layer (306) through an opening (402) provided, in a semiconductor layer (2), between adjacent stripe trenches (307). The plurality of active stripe regions (3) include: a plurality of first active stripe regions (3a) including the protection diffusion layer grounding regions (4); and second active stripe regions (3b) which do not include the protection diffusion layer grounding region (4) and which is provided between the first active stripe regions (3a). The protection diffusion layer (306) and the source electrode (5) are reliably connected to each other so that decrease of a switching speed can be suppressed.

Description

半導体装置および電力変換装置Semiconductor device and power conversion device
　本発明は、トレンチゲート型の半導体装置に関するものである。 The present invention relates to a trench gate type semiconductor device.
　パワーエレクトロニクス機器において、モータ等の負荷への電力供給を制御するスイッチング素子として、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）やＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）などの絶縁ゲート型の半導体装置が広く使用されている。このような絶縁ゲート型の半導体装置の一つに、ゲート電極が半導体層に埋め込み形成されたトレンチゲート型の半導体装置が存在する。 In power electronics equipment, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements for controlling power supply to loads such as motors. Yes. As one of such insulated gate type semiconductor devices, there is a trench gate type semiconductor device in which a gate electrode is embedded in a semiconductor layer.
　スイッチング素子の損失を表す指標として、半導体装置がオンになっているときの主電極間の電気抵抗を表すオン抵抗が知られている。トレンチゲート型の半導体装置は通常のプレーナ型の半導体装置に比べてチャネル幅密度を高くできるため、単位面積当たりのオン抵抗を小さくすることができる。 As an index representing the loss of the switching element, an on-resistance representing the electrical resistance between the main electrodes when the semiconductor device is on is known. Since a trench gate type semiconductor device can have a higher channel width density than an ordinary planar type semiconductor device, an on-resistance per unit area can be reduced.
　さらに、次世代のスイッチング素子として、炭化珪素（ＳｉＣ）や窒化ガリウム（ＧａＮ）系材料、ダイヤモンド等のワイドバンドギャップ半導体を用いたＭＯＳＦＥＴやＩＧＢＴなどが注目されており、ＳｉＣのような六方晶系の材料を使用する場合、トレンチゲート型の半導体装置の電流経路はキャリア移動度の高いａ軸方向と一致するため、オン抵抗の大幅な低減が期待されている。 Further, as next-generation switching elements, silicon carbide (SiC), gallium nitride (GaN) -based materials, MOSFETs and IGBTs using wide band gap semiconductors such as diamond, etc. are attracting attention, and hexagonal systems such as SiC. When this material is used, the current path of the trench gate type semiconductor device coincides with the a-axis direction having a high carrier mobility, so that a significant reduction in on-resistance is expected.
　ところで、トレンチゲート型の半導体装置を、数百Ｖ～数千Ｖの耐圧が求められるパワーエレクトロニクス機器に用いる場合、トレンチ底部に電界が集中しゲート絶縁膜破壊に至りやすいという問題があった。そこで、トレンチ底部の電界集中を緩和するために、トレンチ底部のドリフト層にドリフト層と逆の導電型を有する保護拡散層を設ける技術が広く知られている（例えば、特許文献１参照。）。特許文献１には、トレンチ底部に設けた第２導電型の保護拡散層から第１導電型のドリフト層中に空乏層を広げることによって、トレンチ底部の絶縁膜に印加される電界を低減する技術が示されている。 By the way, when a trench gate type semiconductor device is used in a power electronics device that requires a withstand voltage of several hundred V to several thousand V, there is a problem that an electric field is concentrated on the bottom of the trench and the gate insulating film is easily broken. Therefore, a technique of providing a protective diffusion layer having a conductivity type opposite to that of the drift layer in the drift layer at the bottom of the trench in order to alleviate electric field concentration at the bottom of the trench is widely known (see, for example, Patent Document 1). Patent Document 1 discloses a technique for reducing the electric field applied to the insulating film at the bottom of the trench by spreading a depletion layer from the second conductive type protective diffusion layer provided at the bottom of the trench into the drift layer of the first conductivity type. It is shown.
　さらに、保護拡散層が浮遊電位となると、スイッチング時の空乏層の応答速度が遅くなり、スイッチング速度が遅くなるため、保護拡散層を設ける場合に保護拡散層とソース電極を接続する技術が知られている（例えば、特許文献２参照。）。特許文献２では、格子状のゲート電極で区切られたマトリックス状の９つのセルごとに、中心の１つのセルを保護拡散層とソース電極とが接続される保護コンタクト領域として利用している。 Furthermore, when the protective diffusion layer is at a floating potential, the response speed of the depletion layer at the time of switching becomes slow and the switching speed becomes slow. Therefore, a technique for connecting the protective diffusion layer and the source electrode when providing the protective diffusion layer is known. (For example, refer to Patent Document 2). In Patent Document 2, for each of the nine cells in a matrix shape partitioned by a lattice-like gate electrode, one central cell is used as a protective contact region where the protective diffusion layer and the source electrode are connected.
特開２００５－１４２２４３号公報JP 2005-142243 A ＷＯ２０１２－０７７６１７号WO2012-077617
　保護拡散層から延びる空乏層はドレイン－ソース間で高電圧を遮断している時のみならず、ドレイン－ソース間が導通状態でも一定の広がりを有する。この広がりのため、ドリフト層内でのオン電流経路が狭窄し、ＪＦＥＴ（Ｊｕｎｃｔｉｏｎ　ＦＥＴ）抵抗と呼ばれる抵抗成分が大きくなる。保護拡散層同士が隣接する間では特にオン電流経路が狭くなりオン抵抗増大の一因となりうる。 The depletion layer extending from the protective diffusion layer has a certain spread not only when the high voltage is cut off between the drain and source, but also when the drain and source are conductive. Due to this spreading, the on-current path in the drift layer is narrowed, and a resistance component called a JFET (Junction FET) resistance increases. Especially when the protective diffusion layers are adjacent to each other, the on-current path becomes narrow, which can contribute to an increase in on-resistance.
　上述した特許文献２のように、平面配置が格子状のゲート電極底部に保護拡散層を設ける場合、オン電流経路が４方向から狭窄するため、ＪＦＥＴ抵抗増加の影響が特に問題となる。一方、ゲート電極の平面配置としては、一方向に延在する複数のゲート電極が平行に並ぶストライプ状の平面配置も知られている。ゲート電極がストライプ状に配置される場合には、端部を除いて、オン電流経路は２方向からのみ狭窄されるため、格子状配置の場合と比較するとＪＦＥＴ抵抗の増加を抑制することができる。 As in the above-mentioned Patent Document 2, when the protective diffusion layer is provided at the bottom of the gate electrode having a lattice arrangement, the on-current path is narrowed from four directions, so that the effect of increasing the JFET resistance becomes a particular problem. On the other hand, as a planar arrangement of gate electrodes, a striped planar arrangement in which a plurality of gate electrodes extending in one direction are arranged in parallel is also known. When the gate electrodes are arranged in stripes, the on-current path is narrowed only from two directions except for the end portions, so that an increase in JFET resistance can be suppressed compared to the case of the lattice arrangement. .
　しかしながら、ゲート電極がストライプ状に配置されたトレンチゲート型の半導体装置において、ゲート電極底部に保護拡散層を設けた際にどのようにして保護拡散層とソース電極とを接続するのかについては、従来何ら提案されていなかった。例えば、９つのセルの中心のセルを用いて保護拡散層とソース電極を接続する特許文献２に記載された半導体装置において、ゲート電極の平面配置をそのままストライプ状にしてしまうと、一部の保護拡散層（図２２において、上から２行目、５行目、８行目のゲート電極３０４下方に存在する保護拡散層）がソース電極と接続されず、部分的にスイッチング時の応答が悪化してしまう等の問題を招く恐れがあった。 However, in the trench gate type semiconductor device in which the gate electrodes are arranged in a stripe shape, how to connect the protective diffusion layer and the source electrode when the protective diffusion layer is provided at the bottom of the gate electrode is conventionally known. No suggestion was made. For example, in the semiconductor device described in Patent Document 2 in which the protective diffusion layer and the source electrode are connected using the center cell of nine cells, if the planar arrangement of the gate electrode is directly striped, part of the protection The diffusion layer (the protective diffusion layer existing under the gate electrode 304 in the second, fifth, and eighth rows from the top in FIG. 22) is not connected to the source electrode, and the response during switching partially deteriorates. There was a risk of causing problems such as.
　本発明は、上述のような問題を解決するため、ゲート電極がストライプ状に配置されたトレンチゲート型の半導体装置において、保護拡散層とソース電極を確実に接続し、スイッチング速度の低下を抑制することができる半導体装置を提供することを目的とする。 In order to solve the above-described problems, the present invention reliably connects a protective diffusion layer and a source electrode in a trench gate type semiconductor device in which gate electrodes are arranged in a stripe pattern, and suppresses a decrease in switching speed. An object of the present invention is to provide a semiconductor device that can be used.
　本発明にかかる半導体装置は、第１導電型の半導体層と、半導体層の上部に設けられた第２導電型のベース領域と、ベース領域の上部に設けられたソース領域と、半導体層においてベース領域よりも深い位置にまで達しストライプ状に複数並んで形成されたストライプトレンチ内に設けられたゲート絶縁膜と、ストライプトレンチ内に設けられゲート絶縁膜を介してベース領域と対向する側面を有するゲート電極と、ストライプトレンチの下部に設けられた第２導電型の保護拡散層と、ソース領域とベース領域に接続するソース電極とを備え、複数のストライプトレンチによって区切られた複数の活性ストライプ領域と、隣り合うストライプトレンチの間において半導体層に設けられた開口部を通じてソース電極が保護拡散層に接続する保護拡散層接地領域とを有し、複数の活性ストライプ領域には保護拡散層接地領域を含む複数の第１の活性ストライプ領域と保護拡散層接地領域を含まず第１の活性ストライプ領域に挟まれて設けられた第２の活性ストライプ領域とが存在するものである。 A semiconductor device according to the present invention includes a first conductivity type semiconductor layer, a second conductivity type base region provided above the semiconductor layer, a source region provided above the base region, and a base in the semiconductor layer. A gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the region, and a gate having a side surface that is provided in the stripe trench and faces the base region through the gate insulating film A plurality of active stripe regions each including an electrode, a protective diffusion layer of a second conductivity type provided at a lower portion of the stripe trench, and a source electrode connected to the source region and the base region; A source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches. A plurality of active stripe regions, and a plurality of first active stripe regions including a protective diffusion layer ground region and a first active stripe region not including a protective diffusion layer ground region. There is a second active stripe region provided.
　本発明にかかる半導体装置によれば、保護拡散層接地領域を含まない第２の活性ストライプ領域が保護拡散層接地領域を含む第１の活性ストライプ領域に挟まれて設けられているので、保護拡散層とソース電極をより確実に接続することが可能となり、スイッチング速度の低下を抑制することができる。 According to the semiconductor device of the present invention, the second active stripe region not including the protective diffusion layer ground region is provided between the first active stripe region including the protective diffusion layer ground region. It becomes possible to connect the layer and the source electrode more reliably, and a decrease in switching speed can be suppressed.
本発明の実施の形態１にかかる半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる半導体装置の部分断面図である。1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる半導体装置を示す平面拡大図である。1 is an enlarged plan view showing a semiconductor device according to a first embodiment of the present invention; 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態２にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 3 of this invention. 本発明の比較例にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning the comparative example of this invention. 本発明の比較例にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning the comparative example of this invention. 本発明の実施の形態４にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning Embodiment 4 of this invention. 本発明の実施の形態４にかかる半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device concerning Embodiment 4 of this invention. 本発明の実施の形態５にかかる半導体装置を示す平面図である。It is a top view which shows the semiconductor device concerning Embodiment 5 of this invention. 本発明の実施の形態６にかかる電力変換装置を示す回路ブロック図である。It is a circuit block diagram which shows the power converter device concerning Embodiment 6 of this invention.
実施の形態１．
　まず、本発明の実施の形態１にかかる半導体装置の構成を説明する。図１は、実施の形態１にかかる半導体装置１００を示す平面図であり、図２は実施の形態１にかかる半導体装置１００の部分断面図であり、図１のＡ－Ａ線における部分断面図である。本実施の形態では、炭化珪素を用いたｎ型ＭＯＳＦＥＴを例にして説明する。 Embodiment 1 FIG.
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a plan view showing the semiconductor device 100 according to the first embodiment. FIG. 2 is a partial cross-sectional view of the semiconductor device 100 according to the first embodiment, and is a partial cross-sectional view taken along line AA in FIG. It is. In this embodiment, an n-type MOSFET using silicon carbide will be described as an example.
　図１において、半導体装置１００は、ストライプ状に配列されたゲート電極３０４を備えたトレンチゲート型のＭＯＳＦＥＴであり、活性ストライプ領域３と保護拡散層接地領域４を有する。図１において、ゲート電極３０４は、一方向（図１における左右方向）に延在しており、複数のゲート電極３０４が一定間隔で離間して平行に並んでいる。ゲート電極３０４で区切られた区画のうち、オン電流経路が形成される区画の最小単位が活性ストライプセル３０となる。 In FIG. 1, a semiconductor device 100 is a trench gate type MOSFET having gate electrodes 304 arranged in a stripe shape, and has an active stripe region 3 and a protective diffusion layer ground region 4. In FIG. 1, the gate electrode 304 extends in one direction (the left-right direction in FIG. 1), and a plurality of gate electrodes 304 are arranged in parallel at a predetermined interval. Among the sections partitioned by the gate electrode 304, the minimum unit of the section where the on-current path is formed is the active stripe cell 30.
　一方、活性ストライプ領域３とは、ストライプ状に配置されたゲート電極３０４によって区切られたストライプ状の各領域であり、図１における上下方向に配列された各行を示している。本明細書において、一つの活性ストライプ領域３とは、隣接されたストライプ状のゲート電極３０４によって挟まれた領域（一つの行）であり、両側のゲート電極３０４を含むものとする。すなわち、隣接する活性ストライプ領域３に挟まれたゲート電極３０４は、それぞれの活性ストライプ領域３で共有されているものとする。保護拡散層接地領域４は、後述するソース電極５と保護拡散層３０６とを接続する領域である。そして、活性ストライプ領域３のうち、保護拡散層接地領域４を含む領域（行）を第１の活性ストライプ領域３ａといい、保護拡散層接地領域４を含まない領域（行）を第２の活性ストライプ領域３ｂという。 On the other hand, the active stripe region 3 is each stripe-shaped region partitioned by the gate electrodes 304 arranged in a stripe shape, and indicates each row arranged in the vertical direction in FIG. In the present specification, one active stripe region 3 is a region (one row) sandwiched between adjacent stripe-shaped gate electrodes 304 and includes gate electrodes 304 on both sides. That is, it is assumed that the gate electrode 304 sandwiched between adjacent active stripe regions 3 is shared by each active stripe region 3. The protective diffusion layer ground region 4 is a region for connecting a source electrode 5 and a protective diffusion layer 306 described later. Of the active stripe regions 3, a region (row) including the protective diffusion layer ground region 4 is referred to as a first active stripe region 3a, and a region (row) not including the protective diffusion layer ground region 4 is a second active stripe region 3a. This is referred to as a stripe region 3b.
　図２は、活性ストライプ領域３と保護拡散層接地領域４の双方を含む部分断面図となっている。図２に示すように、半導体装置１００は、ＳｉＣ基板１、エピタキシャル層２、オーミック電極３０１ａ、ソース領域３０２、ベース領域３０３、ゲート電極３０４、ゲート絶縁膜３０５、保護拡散層３０６、オーミック電極４０１ａ、及びドレイン電極７を備えている。ＳｉＣ基板１（半導体基板）は炭化珪素で形成されたｎ型の半導体基板であり、エピタキシャル層２（半導体層）はＳｉＣ基板１上に成長させたｎ型の半導体層である。一方、ＳｉＣ基板１の裏面にはドレイン電極７が形成されている。 FIG. 2 is a partial cross-sectional view including both the active stripe region 3 and the protective diffusion layer ground region 4. As shown in FIG. 2, the semiconductor device 100 includes a SiC substrate 1, an epitaxial layer 2, an ohmic electrode 301a, a source region 302, a base region 303, a gate electrode 304, a gate insulating film 305, a protective diffusion layer 306, an ohmic electrode 401a, And a drain electrode 7. SiC substrate 1 (semiconductor substrate) is an n-type semiconductor substrate formed of silicon carbide, and epitaxial layer 2 (semiconductor layer) is an n-type semiconductor layer grown on SiC substrate 1. On the other hand, a drain electrode 7 is formed on the back surface of the SiC substrate 1.
　活性ストライプ領域３において、エピタキシャル層２の上部にはｐ型のベース領域３０３が形成され、エピタキシャル層２のうちベース領域３０３を除く領域がｎ型のドリフト層２ａとなる。ベース領域３０３上部の一部には、ｎ型のソース領域３０２が形成されている。活性ストライプ領域３の両側には、ソース領域３０２とベース領域３０３を貫通し、ドリフト層２ａに達するストライプトレンチ３０７が形成され、ストライプトレンチ３０７内にはゲート電極３０４とゲート絶縁膜３０５が設けられている。ゲート絶縁膜３０５はゲート電極３０４の側面と底面に設けられており、ゲート電極３０４の側面はゲート絶縁膜３０５を介してベース領域３０３とソース領域３０２とに対向している。 In the active stripe region 3, a p-type base region 303 is formed on the epitaxial layer 2, and a region of the epitaxial layer 2 excluding the base region 303 becomes an n-type drift layer 2a. An n-type source region 302 is formed in part of the upper portion of the base region 303. A stripe trench 307 that penetrates the source region 302 and the base region 303 and reaches the drift layer 2 a is formed on both sides of the active stripe region 3, and a gate electrode 304 and a gate insulating film 305 are provided in the stripe trench 307. Yes. The gate insulating film 305 is provided on the side surface and the bottom surface of the gate electrode 304, and the side surface of the gate electrode 304 faces the base region 303 and the source region 302 with the gate insulating film 305 interposed therebetween.
　ゲート電極３０４の底面にあたる位置のゲート絶縁膜３０５の膜厚は、ゲート電極３０４の側面にあたる位置の膜厚より厚くてもよい。図２に示したゲート絶縁膜３０５は側部、底部とも同じ厚さとしているが、実際にゲート絶縁膜として動作するのは側部のみであり、底部はＭＯＳＦＥＴとしての動作に寄与しない。加えて前述のとおりトレンチ底部には電界が集中しやすく、絶縁膜破壊が起こりやすい。そのため、ゲート電極３０４の底面におけるゲート絶縁膜３０５のみを選択的に厚くすることで、ゲート絶縁膜３０５にかかる電界をさらに緩和することができる。 The film thickness of the gate insulating film 305 at the position corresponding to the bottom surface of the gate electrode 304 may be larger than the film thickness at the position corresponding to the side surface of the gate electrode 304. Although the gate insulating film 305 shown in FIG. 2 has the same thickness at the side and bottom, only the side actually operates as the gate insulating film, and the bottom does not contribute to the operation as the MOSFET. In addition, as described above, the electric field tends to concentrate on the bottom of the trench, and the insulating film is easily broken. Therefore, by selectively thickening only the gate insulating film 305 on the bottom surface of the gate electrode 304, the electric field applied to the gate insulating film 305 can be further reduced.
　ストライプトレンチ３０７底部における電界を緩和するため、ゲート電極３０４の底部（ストライプトレンチ３０７の下部）には、ゲート絶縁膜３０５を介して、ｐ型の保護拡散層３０６が形成されている。また、ゲート電極３０４の上部にはコンタクトホール３０１および４０１を有する層間絶縁膜６が設けられている。 In order to alleviate the electric field at the bottom of the stripe trench 307, a p-type protective diffusion layer 306 is formed on the bottom of the gate electrode 304 (below the stripe trench 307) via the gate insulating film 305. An interlayer insulating film 6 having contact holes 301 and 401 is provided on the gate electrode 304.
　活性ストライプ領域３において、層間絶縁膜６のコンタクトホール３０１を通じてソース電極５がソース領域３０２とベース領域３０３とに接続（オーミックコンタクト）している。より詳細には、コンタクトホール３０１内において、オーミック電極３０１ａが形成されており、ソース電極５はオーミック電極３０１ａを介してソース領域３０２とベース領域３０３とオーミックコンタクトを形成している。 In the active stripe region 3, the source electrode 5 is connected (ohmic contact) to the source region 302 and the base region 303 through the contact hole 301 of the interlayer insulating film 6. More specifically, an ohmic electrode 301a is formed in the contact hole 301, and the source electrode 5 forms an ohmic contact with the source region 302 and the base region 303 via the ohmic electrode 301a.
　一方、保護拡散層接地領域４においては、両側のゲート電極３０４が配設されるストライプトレンチ３０７だけでなく、両側のゲート電極３０４の間の全体においてもベース領域３０３およびソース領域３０２を貫通する開口部４０２が形成されている。すなわち、保護拡散層接地領域４では、両側のゲート電極３０４が配設されるストライプトレンチ３０７とその間の開口部４０２が一体となり、一つの開口部として設けられている。そして、保護拡散層３０６は、保護拡散層接地領域４においては、一方のゲート電極３０４の底部から他方のゲート電極３０４の底部まで、ストライプトレンチ３０７と開口部４０２の下部全体にわたって形成されている。ソース電極５は、保護拡散層接地領域４において、エピタキシャル層２上から開口部４０２の底部にまで延在し、開口部４０２の底部にて、ソース電極５が層間絶縁膜６のコンタクトホール４０１を通じて保護拡散層３０６と接続する。 On the other hand, in the protective diffusion layer grounding region 4, not only the stripe trenches 307 in which the gate electrodes 304 on both sides are disposed, but also the opening between the base region 303 and the source region 302 not only in the gate electrodes 304 on both sides. A portion 402 is formed. That is, in the protective diffusion layer ground region 4, the stripe trench 307 in which the gate electrodes 304 on both sides are disposed and the opening 402 therebetween are integrated and provided as one opening. In the protective diffusion layer ground region 4, the protective diffusion layer 306 is formed from the bottom of one gate electrode 304 to the bottom of the other gate electrode 304 over the entire lower part of the stripe trench 307 and the opening 402. The source electrode 5 extends from above the epitaxial layer 2 to the bottom of the opening 402 in the protective diffusion layer ground region 4, and the source electrode 5 passes through the contact hole 401 of the interlayer insulating film 6 at the bottom of the opening 402. Connected to the protective diffusion layer 306.
　より詳細には、保護拡散層接地領域４の開口部４０２内においてゲート電極３０４の上面と側面を覆うように層間絶縁膜６が設けられており、層間絶縁膜６には保護拡散層接地領域４においてコンタクトホール４０１が形成されている。コンタクトホール４０１内には、オーミック電極４０１ａが形成されており、ソース電極５はオーミック電極４０１ａを介して保護拡散層３０６とオーミックコンタクトを形成している。ゲート電極３０４の側面を覆う層間絶縁膜６は、ゲート電極３０４の上面を覆う層間絶縁膜６と一体に形成されるが、ゲート電極３０４の側面を覆う層間絶縁膜６とゲート電極３０４の上面を覆う層間絶縁膜６とは個別で設けることとしてもよい。ゲート電極３０４の側面を覆う層間絶縁膜６の厚さは、適宜設定することとすれば良いが、ゲート・ソース間の寄生容量を低減するために、ゲート絶縁膜３０５よりも厚さを大きくするのが望ましい。 More specifically, an interlayer insulating film 6 is provided in the opening 402 of the protective diffusion layer grounding region 4 so as to cover the upper surface and side surfaces of the gate electrode 304, and the protective diffusion layer grounding region 4 is provided on the interlayer insulating film 6. A contact hole 401 is formed in FIG. An ohmic electrode 401a is formed in the contact hole 401, and the source electrode 5 forms an ohmic contact with the protective diffusion layer 306 via the ohmic electrode 401a. The interlayer insulating film 6 that covers the side surface of the gate electrode 304 is formed integrally with the interlayer insulating film 6 that covers the upper surface of the gate electrode 304, but the upper surface of the interlayer insulating film 6 and the gate electrode 304 that covers the side surface of the gate electrode 304 is formed. It is good also as providing separately with the interlayer insulation film 6 to cover. The thickness of the interlayer insulating film 6 covering the side surface of the gate electrode 304 may be set as appropriate, but the thickness is made larger than that of the gate insulating film 305 in order to reduce the gate-source parasitic capacitance. Is desirable.
　図１に戻り、活性ストライプ領域３と保護拡散層接地領域４とのレイアウトについて説明する。なお、図１は、視認性を向上させるため、図２に示す半導体装置１００のエピタキシャル層２の表面における平面図となっており、ソース電極５とエピタキシャル層２上の層間絶縁膜６を図示省略した平面図となっている。 Referring back to FIG. 1, the layout of the active stripe region 3 and the protective diffusion layer ground region 4 will be described. FIG. 1 is a plan view of the surface of the epitaxial layer 2 of the semiconductor device 100 shown in FIG. 2 in order to improve visibility, and the source electrode 5 and the interlayer insulating film 6 on the epitaxial layer 2 are not shown. It is a plan view.
　図１に示すように、ゲート電極３０４は図１の左右方向にストライプ状に複数設けられ、隣接するゲート電極３０４に区切られた領域が活性ストライプ領域３として規定される。各ゲート電極３０４は、ゲート電極３０４の短手方向（図１の上下方向）に離間して平行に設けられている。また、各ゲート電極３０４の間隔は一定間隔とするのが望ましく、すなわち、各活性ストライプ領域３の短辺の長さが一定となるように形成されているのが望ましい。仮に、短辺の長さが異なる活性ストライプ領域３が混在した場合、短辺の長い活性ストライプ領域３に電流が集中するおそれがある。そのため、活性ストライプ領域３の短辺の長さを一定とすることで、一部の活性ストライプ領域３に電流集中するのを抑制できる。 As shown in FIG. 1, a plurality of gate electrodes 304 are provided in a stripe shape in the left-right direction of FIG. 1, and a region partitioned by adjacent gate electrodes 304 is defined as an active stripe region 3. Each of the gate electrodes 304 is provided in parallel and spaced apart in the short direction of the gate electrode 304 (up and down direction in FIG. 1). Further, it is desirable that the interval between the gate electrodes 304 be constant, that is, the length of the short side of each active stripe region 3 is desirably constant. If active stripe regions 3 having different short sides are mixed, current may concentrate on the active stripe regions 3 having long short sides. Therefore, by concentrating the length of the short side of the active stripe region 3, current concentration in a part of the active stripe regions 3 can be suppressed.
　図１において、活性ストライプ領域３のうち一部の活性ストライプ領域３には保護拡散層接地領域４が含まれており、上述したように、保護拡散層接地領域４を含む活性ストライプ領域３を第１の活性ストライプ領域３ａと称し、保護拡散層接地領域４を含まない活性ストライプ領域３を第２の活性ストライプ領域３ｂと称する。 In FIG. 1, a part of the active stripe regions 3 in the active stripe region 3 includes the protective diffusion layer ground region 4. As described above, the active stripe region 3 including the protective diffusion layer ground region 4 is changed to the first active stripe region 3. One active stripe region 3a is referred to as an active stripe region 3 that does not include the protective diffusion layer ground region 4 and is referred to as a second active stripe region 3b.
　第１の活性ストライプ領域３ａは、離間して設けられた複数の保護拡散層接地領域４を有している。そして、第１の活性ストライプ領域３ａにおいては、保護拡散層接地領域４と隣接する２つのゲート電極３０４によって区切られた区画が、活性ストライプセル３０となる。活性ストライプセル３０は周囲がゲート電極３０４（保護拡散層接地領域４内のゲート電極３０４も含む）で区切られた長方形状の区画であり、ゲート電極３０４の電位に応じてオン電流が流れる活性セルである。 The first active stripe region 3a has a plurality of protective diffusion layer ground regions 4 that are spaced apart from each other. In the first active stripe region 3 a, a section defined by the two gate electrodes 304 adjacent to the protective diffusion layer ground region 4 becomes the active stripe cell 30. The active stripe cell 30 is a rectangular section whose periphery is partitioned by a gate electrode 304 (including the gate electrode 304 in the protective diffusion layer ground region 4), and an active cell in which an on-current flows according to the potential of the gate electrode 304. It is.
　図３には、活性ストライプセル３０と保護拡散層接地領域４との境界周辺における本実施の形態にかかる半導体装置１００の平面拡大図を示す。図３に示すように、保護拡散層接地領域４において、活性ストライプセル３０の短辺に沿ってゲート電極３０４とゲート絶縁膜３０５が形成される。活性ストライプセル３０の短辺に沿って形成されるゲート電極３０４は、隣接するストライプトレンチ内に形成されるゲート電極３０４同士を接続している。そのため、保護拡散層接地領域４は、ストライプトレンチ３０７に形成されるゲート電極３０４（図３の横方向に延在するゲート電極３０４）と活性ストライプセル３０の短辺に沿って形成されるゲート電極３０４（図３の上下方向に延在するゲート電極３０４）によって区切られた領域となる。 FIG. 3 is an enlarged plan view of the semiconductor device 100 according to the present embodiment around the boundary between the active stripe cell 30 and the protective diffusion layer grounding region 4. As shown in FIG. 3, the gate electrode 304 and the gate insulating film 305 are formed along the short side of the active stripe cell 30 in the protective diffusion layer ground region 4. The gate electrodes 304 formed along the short sides of the active stripe cell 30 connect the gate electrodes 304 formed in adjacent stripe trenches. Therefore, the protective diffusion layer ground region 4 includes a gate electrode 304 formed in the stripe trench 307 (a gate electrode 304 extending in the horizontal direction in FIG. 3) and a gate electrode formed along the short side of the active stripe cell 30. The region is divided by 304 (the gate electrode 304 extending in the vertical direction in FIG. 3).
　活性ストライプセル３０の概形は、図１や図３に示すように長方形となるため、活性ストライプセル３０の短辺周辺を除いて、保護拡散層３０６から伸びる空乏層によるオン電流経路の狭窄は２方向のみとなる。そのため、ゲート電極３０４を格子型にする場合に比べてＪＦＥＴ抵抗の増加を抑制することができる。一方、このようなストライプ型のセルレイアウトの場合、チャネル幅密度が減少するため、チャネル抵抗は増加してしまう。そこで、格子型のセルレイアウトに対するＪＦＥＴ抵抗の低減分がチャネル抵抗の増加分を上回るように活性ストライプセル３０の概形を決定することで、格子型レイアウトと比較してオン抵抗を低減することができる。具体的には、活性ストライプセル３０の長辺は短辺に対して１．５以上、より好ましくは２．０以上とするのが望ましい。 Since the outline of the active stripe cell 30 is rectangular as shown in FIGS. 1 and 3, the ON current path is narrowed by the depletion layer extending from the protective diffusion layer 306 except for the vicinity of the short side of the active stripe cell 30. There are only two directions. Therefore, an increase in JFET resistance can be suppressed as compared with the case where the gate electrode 304 is a lattice type. On the other hand, in such a stripe-type cell layout, the channel resistance increases because the channel width density decreases. Therefore, by determining the outline of the active stripe cell 30 so that the reduction in JFET resistance with respect to the lattice-type cell layout exceeds the increase in channel resistance, the on-resistance can be reduced as compared with the lattice-type layout. it can. Specifically, it is desirable that the long side of the active stripe cell 30 is 1.5 or more, more preferably 2.0 or more with respect to the short side.
　一方、第２の活性ストライプ領域３ｂは、保護拡散層接地領域４を含まないため、第２の活性ストライプ領域３ｂ全体がひとつの活性ストライプセル３０となる。そして、本実施の形態では、図１に示すように、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとが、活性ストライプ領域３の短辺方向において、交互に配列されている。 On the other hand, since the second active stripe region 3b does not include the protective diffusion layer ground region 4, the entire second active stripe region 3b becomes one active stripe cell 30. In the present embodiment, as shown in FIG. 1, the first active stripe region 3 a and the second active stripe region 3 b are alternately arranged in the short side direction of the active stripe region 3.
　図１に示すように、各保護拡散層接地領域４は互いに一定の間隔をおいて配置されることが望ましい。なお、本実施の形態では、保護拡散層接地領域４の概形は略正方形としているが、他の多角形等の任意の形状でもよいし、各辺の長さも活性ストライプ領域３の短辺の長さに必ずしも等しくする必要はない。ただし、活性ストライプ領域３の短辺を全ての活性ストライプ領域３で同じにするため、保護拡散層接地領域４の一辺が活性ストライプ領域３の短辺の整数倍となっていることが望ましい。 As shown in FIG. 1, it is desirable that the protective diffusion layer grounding regions 4 are arranged at regular intervals. In the present embodiment, the protective diffusion layer grounding region 4 is roughly square in shape, but may be any shape such as other polygons, and the length of each side is the short side of the active stripe region 3. It is not necessarily equal to the length. However, in order to make the short side of the active stripe region 3 the same in all the active stripe regions 3, it is desirable that one side of the protective diffusion layer ground region 4 is an integral multiple of the short side of the active stripe region 3.
　次に、半導体装置１００の動作について説明する。半導体装置１００は、ゲート電極３０４に印加される電圧によって、オン状態とオフ状態が切り替わり動作する。ソース電極５を基準電位として、ゲート電極３０４にしきい値電圧以上の電圧（例えば、２０Ｖの電圧）が印加されると、ゲート電極３０４の側面に対向するベース領域３０３にチャネル領域が形成される。その結果、チャネル領域を介してドレイン電極７とソース電極５との間が導通し、オン状態となる。一方、ソース電極５を基準電位として、ゲート電極３０４にしきい値電圧未満の電圧（例えば、０Ｖの電圧）が印加されると、ゲート電極３０４の側面に対向するベース領域３０３にはチャネル領域が形成されず、ドレイン電極７とソース電極５との間が遮断される。その結果、半導体装置１００はオフ状態となる。 Next, the operation of the semiconductor device 100 will be described. The semiconductor device 100 operates by switching between an on state and an off state according to a voltage applied to the gate electrode 304. When a voltage equal to or higher than a threshold voltage (for example, a voltage of 20 V) is applied to the gate electrode 304 with the source electrode 5 as a reference potential, a channel region is formed in the base region 303 facing the side surface of the gate electrode 304. As a result, the drain electrode 7 and the source electrode 5 are brought into conduction through the channel region and are turned on. On the other hand, when a voltage lower than the threshold voltage (for example, a voltage of 0 V) is applied to the gate electrode 304 with the source electrode 5 as a reference potential, a channel region is formed in the base region 303 facing the side surface of the gate electrode 304. The gap between the drain electrode 7 and the source electrode 5 is blocked. As a result, the semiconductor device 100 is turned off.
　半導体装置１００は、ゲート電極３０４に印加される電圧に従って、上述したオン状態とオフ状態とが切り替わり、スイッチング動作を実現している。ところで、半導体装置１００内には、保護拡散層３０６とドリフト層２ａとの間には空乏容量と呼ばれる寄生容量が存在する。そして、半導体装置１００のオン状態とオフ状態とが切り替わるスイッチング時に、保護拡散層３０６とドリフト層２ａとの間の寄生容量が充放電されることになるが、寄生容量の充放電速度が半導体装置１００のスイッチング特性（速度や損失等）に影響を与えることになる。半導体装置１００では、ストライプトレンチ３０７下部に設けられた保護拡散層３０６は少なくともいずれかの保護拡散層接地領域４を通じてソース電極５と接続しているため、保護拡散層接地領域４を介してソース電極５と保護拡散層３０６との間を寄生容量の充放電電流が流れることになる。 The semiconductor device 100 switches between the above-described on-state and off-state according to the voltage applied to the gate electrode 304, thereby realizing a switching operation. Incidentally, in the semiconductor device 100, a parasitic capacitance called a depletion capacitance exists between the protective diffusion layer 306 and the drift layer 2a. When the semiconductor device 100 is switched between the on state and the off state, the parasitic capacitance between the protective diffusion layer 306 and the drift layer 2a is charged / discharged. 100 switching characteristics (speed, loss, etc.) will be affected. In the semiconductor device 100, the protective diffusion layer 306 provided under the stripe trench 307 is connected to the source electrode 5 through at least one of the protective diffusion layer ground regions 4. Thus, a charge / discharge current of parasitic capacitance flows between the protective layer 5 and the protective diffusion layer 306.
　続いて、半導体装置１００の製造方法を説明する。図４～図１０は、半導体装置１００の製造方法の各工程を示す断面図である。以下の説明において、各構成要素の材料や寸法等は一つの例示であり、本発明はこれに限定されるものではない。 Subsequently, a method for manufacturing the semiconductor device 100 will be described. 4 to 10 are cross-sectional views showing the steps of the method for manufacturing the semiconductor device 100. In the following description, the material, dimensions, and the like of each component are merely examples, and the present invention is not limited thereto.
　図４において、ＳｉＣ基板１上にエピタキシャル層２（半導体層）を形成する。ここでは４Ｈのポリタイプを有するｎ型で低抵抗のＳｉＣ基板１を用意し、その上に化学気相堆積（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によりｎ型のエピタキシャル層２をエピタキシャル成長させた。エピタキシャル層２は、１×１０１４ｃｍ－３～１×１０１７ｃｍ－３のｎ型の不純物濃度であり、厚さは５～２００μｍとする。また、ＳｉＣ基板１はＳｉＣ結晶のｃ面である（０００１）面に対して４°の角度（オフ角）をつけた面が表面となっている。 In FIG. 4, epitaxial layer 2 (semiconductor layer) is formed on SiC substrate 1. Here, an n-type low-resistance SiC substrate 1 having a 4H polytype was prepared, and an n-type epitaxial layer 2 was epitaxially grown thereon by a chemical vapor deposition (CVD) method. The epitaxial layer 2 has an n-type impurity concentration of 1 × 10 14 cm −3 to 1 × 10 17 cm −3 and a thickness of 5 to 200 μm. The surface of the SiC substrate 1 is an angle of 4 ° (off angle) with respect to the (0001) plane which is the c-plane of the SiC crystal.
　次に、図４において、エピタキシャル層２の表面に所定のドーパントをイオン注入することにより、ベース領域３０３、および、ソース領域３０２を形成する。 Next, in FIG. 4, a base region 303 and a source region 302 are formed by ion-implanting a predetermined dopant into the surface of the epitaxial layer 2.
　ベース領域３０３はｐ型不純物であるアルミニウム（Ａｌ）のイオン注入により形成する。Ａｌのイオン注入の深さは、エピタキシャル層２の厚さを超えない範囲で、０．５～３．０μｍ程度とする。注入するＡｌの不純物濃度は、エピタキシャル層２のｎ型の不純物濃度より高くする。具体的には、ベース領域３０３のｐ型不純物濃度を１×１０１７ｃｍ－３～１×１０２０ｃｍ－３の範囲とする。このとき、Ａｌの注入深さよりも深いエピタキシャル層２の領域がｎ型のドリフト層２ａとなる。なお、ベース領域３０３はｐ型のエピタキシャル成長によって形成してもよい。かかる場合においても、ベース領域３０３の不純物濃度および厚さは、イオン注入によって形成する場合と同等とする。 The base region 303 is formed by ion implantation of aluminum (Al) which is a p-type impurity. The depth of Al ion implantation is about 0.5 to 3.0 μm within a range not exceeding the thickness of the epitaxial layer 2. The impurity concentration of Al to be implanted is set higher than the n-type impurity concentration of the epitaxial layer 2. Specifically, the p-type impurity concentration of the base region 303 is set to a range of 1 × 10 17 cm −3 to 1 × 10 20 cm −3 . At this time, the region of the epitaxial layer 2 deeper than the Al implantation depth becomes the n-type drift layer 2a. Note that the base region 303 may be formed by p-type epitaxial growth. Even in such a case, the impurity concentration and thickness of the base region 303 are the same as those formed by ion implantation.
　ソース領域３０２は、ベース領域３０３の表面の一部にｎ型の不純物である窒素（Ｎ）をイオン注入することで形成する。ソース領域３０２の平面パターンは、後述する工程で形成されるゲート電極３０４のレイアウトに対応するパターンで形成する。具体的には、ゲート電極３０４が形成されたとき、ゲート電極３０４の両側にソース領域３０２が配設されるよう、ソース領域３０２の平面配置を決定する。Ｎのイオン注入深さは、ベース領域３０３の厚さより浅くする。注入するＮの不純物濃度は、ベース領域３０３のｐ型不純物濃度以上であり、かつ、１×１０２１ｃｍ－３以下の範囲とする。なお、各イオン注入の順序は最終的に図２に示す半導体装置１００の構造になれば上記の通りでなくても構わないし、ｐ型不純物としてはボロン（Ｂ）を、ｎ型不純物としてはリン（Ｐ）を用いることとしても構わない（以下の注入工程においても同様。）。 The source region 302 is formed by ion-implanting nitrogen (N) that is an n-type impurity into part of the surface of the base region 303. The planar pattern of the source region 302 is formed with a pattern corresponding to the layout of the gate electrode 304 formed in a process described later. Specifically, the planar arrangement of the source region 302 is determined so that the source region 302 is disposed on both sides of the gate electrode 304 when the gate electrode 304 is formed. The N ion implantation depth is made shallower than the thickness of the base region 303. The impurity concentration of N to be implanted is not less than the p-type impurity concentration of the base region 303 and not more than 1 × 10 21 cm −3 . Note that the order of each ion implantation may not be as described above as long as the structure of the semiconductor device 100 shown in FIG. 2 is finally obtained. Boron (B) is used as a p-type impurity and phosphorus is used as an n-type impurity. (P) may be used (the same applies to the following injection step).
　また、ベース領域３０３の下部には、ドリフト層２ａよりもｎ型の不純物濃度が高い空乏化抑制層（図示せず）を設けてもよい。図２に示す構造においては、ベース領域３０３と保護拡散層３０６の両方から伸びる空乏層によって電流経路が狭窄し、いわゆるＪＦＥＴ抵抗が両者の間に発生する。上記のように空乏化抑制層を設けると、半導体装置１００のオン時にベース領域３０３からの空乏層の伸長を抑制できるため、ＪＦＥＴ抵抗を低減できる。 Further, a depletion suppression layer (not shown) having an n-type impurity concentration higher than that of the drift layer 2a may be provided below the base region 303. In the structure shown in FIG. 2, a current path is narrowed by a depletion layer extending from both the base region 303 and the protective diffusion layer 306, and a so-called JFET resistance is generated between them. When the depletion suppression layer is provided as described above, since the extension of the depletion layer from the base region 303 can be suppressed when the semiconductor device 100 is turned on, the JFET resistance can be reduced.
　空乏化抑制層はｎ型不純物である窒素（Ｎ）またはリン（Ｐ）をイオン注入することにより形成する。空乏化抑制層の深さは、前記ベース領域３０３より深く、エピタキシャル層２の厚さを超えない範囲で、厚みは０．５～３μｍ程度とすることが望ましい。注入するＮの不純物濃度は、エピタキシャル層２のｎ型不純物濃度より高く、かつ１×１０１７ｃｍ－３以上であることが望ましい。なお、空乏化抑制層はｎ型のエピタキシャル成長によって形成してもよい。かかる場合、空乏化抑制層の不純物濃度および厚さは、イオン注入によって形成する場合と同等とする。また、空乏化抑制層は活性ストライプセル３０の中央部分のみ取り除いた平面パターンとしてもよい。 The depletion suppression layer is formed by ion implantation of nitrogen (N) or phosphorus (P) which are n-type impurities. The depth of the depletion suppressing layer is preferably deeper than the base region 303 and within the range not exceeding the thickness of the epitaxial layer 2, and the thickness is preferably about 0.5 to 3 μm. The impurity concentration of N to be implanted is preferably higher than the n-type impurity concentration of the epitaxial layer 2 and 1 × 10 17 cm −3 or more. Note that the depletion suppression layer may be formed by n-type epitaxial growth. In such a case, the impurity concentration and thickness of the depletion suppression layer are the same as those formed by ion implantation. The depletion suppression layer may be a planar pattern in which only the central portion of the active stripe cell 30 is removed.
　図５において、エピタキシャル層２の表面にシリコン酸化膜８を１～２μｍ程度堆積し、シリコン酸化膜８の上にレジスト材からなるエッチングマスク９を形成する。エッチングマスク９は、フォトリソグラフィ技術により、トレンチの形成領域に対応して開口したパターンに形成される。そして、エッチングマスク９をマスクとする反応性イオンエッチング（ＲＩＥ：Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ）処理により、シリコン酸化膜８をパターニングする。これにより、エッチングマスク９のパターンがシリコン酸化膜８に転写される。パターニングされたシリコン酸化膜８は次の工程のエッチングマスクとなる。 In FIG. 5, a silicon oxide film 8 is deposited on the surface of the epitaxial layer 2 by about 1 to 2 μm, and an etching mask 9 made of a resist material is formed on the silicon oxide film 8. The etching mask 9 is formed in a pattern opened corresponding to a trench formation region by a photolithography technique. Then, the silicon oxide film 8 is patterned by a reactive ion etching (RIE) process using the etching mask 9 as a mask. Thereby, the pattern of the etching mask 9 is transferred to the silicon oxide film 8. The patterned silicon oxide film 8 becomes an etching mask for the next step.
　図６において、パターニングされたシリコン酸化膜８をマスクとするＲＩＥにより、エピタキシャル層２にソース領域３０２およびベース領域３０３を貫通するストライプトレンチ３０７と開口部４０２を形成する。トレンチの深さは、ベース領域３０３の深さ以上であり、１．０～６．０μｍ程度である。また、トレンチの平面パターンは、図１におけるゲート電極３０４とゲート絶縁膜３０５を合わせた平面パターンに対応している。より詳細には、活性ストライプ領域３を規定するように、ストライプ状に複数離間して設けられたストライプトレンチ３０７が形成され、保護拡散層接地領域４にあたる領域のみ隣接するストライプトレンチ３０７の間にも開口部４０２が形成され、保護拡散層接地領域４全体がエッチングされている。なお、本明細書では、活性ストライプ領域３を規定するストライプトレンチ３０７と保護拡散層接地領域４に形成される開口部４０２とを総称してトレンチという。 In FIG. 6, a stripe trench 307 and an opening 402 that penetrate the source region 302 and the base region 303 are formed in the epitaxial layer 2 by RIE using the patterned silicon oxide film 8 as a mask. The depth of the trench is not less than the depth of the base region 303 and is about 1.0 to 6.0 μm. Further, the planar pattern of the trench corresponds to the planar pattern in which the gate electrode 304 and the gate insulating film 305 in FIG. 1 are combined. More specifically, a plurality of stripe trenches 307 are provided in a stripe shape so as to define the active stripe region 3, and only the region corresponding to the protective diffusion layer ground region 4 is also formed between adjacent stripe trenches 307. An opening 402 is formed, and the entire protective diffusion layer grounding region 4 is etched. In this specification, the stripe trench 307 defining the active stripe region 3 and the opening 402 formed in the protective diffusion layer ground region 4 are collectively referred to as a trench.
　また、ストライプトレンチ３０７（活性ストライプ領域３）はＳｉＣ基板１のオフ角によって形成されるエピタキシャル層２のステップフローに対して平行に配設されることが望ましい。オン電流経路が形成される活性領域では、活性ストライプ領域３内でゲート電極３０４に隣接する部分がＭＯＳＦＥＴとして機能する。ＳｉＣ基板１のオフ角に対して平行にストライプトレンチ３０７を配設する場合、ゲート絶縁膜３０５とＳｉＣ（エピタキシャル層２）との界面には原子層ステップが生じないが、垂直に配設した場合には界面に原子層ステップが生じてしまう。原子層ステップの存在は界面準位の多寡に影響しており、ストライプトレンチ３０７をエピタキシャル層２のステップフローに対して平行に配設することで、ゲート耐圧は高くすることができる。 Further, it is desirable that the stripe trench 307 (active stripe region 3) is arranged in parallel to the step flow of the epitaxial layer 2 formed by the off angle of the SiC substrate 1. In the active region where the on-current path is formed, a portion adjacent to the gate electrode 304 in the active stripe region 3 functions as a MOSFET. When the stripe trench 307 is disposed parallel to the off-angle of the SiC substrate 1, no atomic layer step occurs at the interface between the gate insulating film 305 and SiC (epitaxial layer 2), but when the stripe trench 307 is disposed vertically. Causes an atomic layer step at the interface. The presence of atomic layer steps affects the number of interface states, and the gate breakdown voltage can be increased by arranging the stripe trenches 307 in parallel to the step flow of the epitaxial layer 2.
　図７において、トレンチの部分を開口したパターン、すなわちエッチングマスク９とパターンが同様の注入マスク１０を形成し、注入マスク１０をマスクとしたイオン注入により、トレンチの底部にｐ型の保護拡散層３０６を形成する。ここで、ｐ型の不純物としてＡｌを用いる。注入するＡｌの不純物濃度は、１×１０１７ｃｍ－３～１×１０１９ｃｍ－３の範囲、厚さは０．１～２．０μｍの範囲であることが望ましい。保護拡散層３０６のＡｌ不純物濃度はＭＯＳＦＥＴのドレイン－ソース間に使用耐圧を印加した際にゲート絶縁膜３０５にかかる電界から決められる。注入マスク１０の代わりに、トレンチ形成の際のエッチングマスクである（パターニングされた）シリコン酸化膜８を使用してもよい。これにより製造工程の簡略化およびコスト削減を図ることができる。なお、注入マスク１０の代わりにシリコン酸化膜８を使用する場合、トレンチを形成した後十分な厚さのシリコン酸化膜８が残存するように、シリコン酸化膜８の厚さやエッチング条件を調整する必要がある。 In FIG. 7, an implantation mask 10 having the same pattern as the etching mask 9 is formed by opening a trench portion, and ion implantation using the implantation mask 10 as a mask is performed to form a p-type protective diffusion layer 306 at the bottom of the trench. Form. Here, Al is used as a p-type impurity. The impurity concentration of Al to be implanted is preferably in the range of 1 × 10 17 cm −3 to 1 × 10 19 cm −3 and the thickness is preferably in the range of 0.1 to 2.0 μm. The Al impurity concentration of the protective diffusion layer 306 is determined from the electric field applied to the gate insulating film 305 when a working breakdown voltage is applied between the drain and source of the MOSFET. Instead of the implantation mask 10, a (patterned) silicon oxide film 8 that is an etching mask for forming a trench may be used. Thereby, simplification of the manufacturing process and cost reduction can be achieved. When the silicon oxide film 8 is used instead of the implantation mask 10, it is necessary to adjust the thickness and etching conditions of the silicon oxide film 8 so that the silicon oxide film 8 having a sufficient thickness remains after the trench is formed. There is.
　注入マスク１０を除去した後、熱処理装置を用いてアニール処理を行うことで、上記の工程でイオン注入した不純物を活性化させる。アニール処理は、アルゴン（Ａｒ）ガスなどの不活性ガス雰囲気中や真空中で、１３００～１９００℃、３０秒～１時間の条件で行う。 After removing the implantation mask 10, annealing is performed using a heat treatment apparatus, thereby activating the impurities implanted by the above process. The annealing treatment is performed in an inert gas atmosphere such as argon (Ar) gas or in vacuum under conditions of 1300 to 1900 ° C. and 30 seconds to 1 hour.
　図８において、トレンチ内を含むエピタキシャル層２の全面にシリコン酸化膜１１を形成した後、ポリシリコン膜１２を減圧ＣＶＤ法により堆積する。そして、図９において、シリコン酸化膜１１およびポリシリコン膜１２をパターニングまたはエッチバックすることにより、ストライプトレンチ３０７内にゲート絶縁膜３０５およびゲート電極３０４を形成する。ゲート絶縁膜３０５となるシリコン酸化膜１１は、エピタキシャル層２の表面を熱酸化して形成してもよいし、エピタキシャル層２上に堆積させて形成してもよい。 In FIG. 8, after a silicon oxide film 11 is formed on the entire surface of the epitaxial layer 2 including the inside of the trench, a polysilicon film 12 is deposited by a low pressure CVD method. In FIG. 9, the gate insulating film 305 and the gate electrode 304 are formed in the stripe trench 307 by patterning or etching back the silicon oxide film 11 and the polysilicon film 12. The silicon oxide film 11 to be the gate insulating film 305 may be formed by thermally oxidizing the surface of the epitaxial layer 2 or may be formed by being deposited on the epitaxial layer 2.
　図１０において、減圧ＣＶＤ法により、エピタキシャル層２の全面に層間絶縁膜６を形成し、層間絶縁膜６によりゲート電極３０４を覆う。また、層間絶縁膜６をパターニングすることで、活性ストライプ領域３ではソース領域３０２およびベース領域３０３に達するコンタクトホール３０１を形成し、保護拡散層接地領域４では保護拡散層３０６に達するコンタクトホール４０１を形成する。そして、コンタクトホール３０１および４０１の底に露出したエピタキシャル層２の表面に、オーミック電極３０１ａおよび４０１ａを形成する。オーミック電極３０１ａおよび４０１ａの形成方法としては、例えば、各コンタクトホール内を含むエピタキシャル層２の全面にＮｉを主成分とする金属膜を成膜し、６００～１１００℃の熱処理により炭化珪素と反応させてオーミック電極となるシリサイド膜を形成する。 In FIG. 10, the interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 2 by low pressure CVD, and the gate electrode 304 is covered with the interlayer insulating film 6. Further, by patterning the interlayer insulating film 6, a contact hole 301 reaching the source region 302 and the base region 303 is formed in the active stripe region 3, and a contact hole 401 reaching the protective diffusion layer 306 is formed in the protective diffusion layer ground region 4. Form. Then, ohmic electrodes 301 a and 401 a are formed on the surface of the epitaxial layer 2 exposed at the bottoms of the contact holes 301 and 401. As a method of forming the ohmic electrodes 301a and 401a, for example, a metal film containing Ni as a main component is formed on the entire surface of the epitaxial layer 2 including the inside of each contact hole, and reacted with silicon carbide by heat treatment at 600 to 1100 ° C. A silicide film to be an ohmic electrode is formed.
　その後、エピタキシャル層２上にＡｌ合金等の電極材を堆積することで、層間絶縁膜６上並びにコンタクトホール３０１および４０１内に、ソース電極５を形成する（図示せず）。最後に、ＳｉＣ基板１の下面にＡｌ合金等の電極材を堆積してドレイン電極７を形成する（図示せず）。以上の工程により、図２に示した半導体装置１００が得られる。 Thereafter, an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 5 on the interlayer insulating film 6 and in the contact holes 301 and 401 (not shown). Finally, an electrode material such as an Al alloy is deposited on the lower surface of the SiC substrate 1 to form the drain electrode 7 (not shown). Through the above steps, the semiconductor device 100 shown in FIG. 2 is obtained.
　次に、本実施の形態にかかる半導体装置１００の効果について説明する。図２１と図２２には、本実施の形態にかかる半導体装置１００の比較例を示す。図２１は、特許文献２に示されたように、ゲート電極３０４が格子状に配置された格子型レイアウトにおいて、９つの区画の中心の区画に保護拡散層接地領域４を設けた半導体装置２００を示している。図２２は、図２１に示す半導体装置２００において、ゲート電極３０４をストライプ状のレイアウトに置き換えた半導体装置３００を示している。 Next, effects of the semiconductor device 100 according to the present embodiment will be described. 21 and 22 show a comparative example of the semiconductor device 100 according to the present embodiment. FIG. 21 shows a semiconductor device 200 in which a protective diffusion layer grounding region 4 is provided in a central section of nine sections in a lattice layout in which gate electrodes 304 are arranged in a lattice form as shown in Patent Document 2. Show. FIG. 22 shows a semiconductor device 300 in which the gate electrode 304 is replaced with a stripe layout in the semiconductor device 200 shown in FIG.
　図２１に示す半導体装置２００では、格子状のゲート電極３０４で区切られた活性セルは４方向をゲート電極３０４に囲まれているため、各ゲート電極３０４底部に設けられた保護拡散層３０６から伸びる空乏層の影響により、オン電流経路が４方向から狭窄され、オン抵抗の増大を招く恐れがあった。そこで、このようなオン抵抗増大を抑制するため、ゲート電極３０４のレイアウトを格子型からストライプ型に変更すると、図２２に示す半導体装置３００となる。半導体装置３００では、オン電流経路の狭窄は活性ストライプセル３０の短辺近傍を除いて２方向のみからとなるため、オン電流経路を広くすることができ、オン抵抗を低減することができる。 In the semiconductor device 200 shown in FIG. 21, since the active cells divided by the lattice-like gate electrodes 304 are surrounded by the gate electrodes 304 in four directions, they extend from the protective diffusion layer 306 provided at the bottom of each gate electrode 304. Due to the influence of the depletion layer, the on-current path is narrowed from four directions, which may increase the on-resistance. Therefore, when the layout of the gate electrode 304 is changed from the lattice type to the stripe type in order to suppress such an increase in on-resistance, the semiconductor device 300 shown in FIG. 22 is obtained. In the semiconductor device 300, the on-current path is narrowed only in two directions except for the vicinity of the short side of the active stripe cell 30, so that the on-current path can be widened and the on-resistance can be reduced.
　ところが、図２２に示す半導体装置３００では、保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂ同士が並ぶ領域があり、隣接する第２の活性ストライプ領域３ｂ同士の間のストライプトレンチ３０７、具体的には図２２における上から２、５、８行目のストライプトレンチ３０７は、保護拡散層接地領域４と接しないことになる。そのため、これらのストライプトレンチ３０７下部に設けられた保護拡散層３０６も保護拡散層接地領域４と接続しないことになる。そうすると、保護拡散層接地領域４と接していない保護拡散層３０６の電位はフローティングとなり、過渡応答時に他の保護拡散層３０６に比べて空乏層の応答速度が遅れてしまう。その結果、スイッチング損失の増加や、半導体装置３００内での特性ばらつき、ひいては高速動作時の電流集中によるゲート絶縁膜の破壊を招くおそれがあった。 However, in the semiconductor device 300 shown in FIG. 22, there is a region where the second active stripe regions 3b are arranged without including the protective diffusion layer ground region 4, and the stripe trench 307 between the adjacent second active stripe regions 3b. Specifically, the stripe trenches 307 in the second, fifth, and eighth rows from the top in FIG. 22 do not contact the protective diffusion layer ground region 4. Therefore, the protective diffusion layer 306 provided below the stripe trenches 307 is not connected to the protective diffusion layer ground region 4. As a result, the potential of the protective diffusion layer 306 that is not in contact with the protective diffusion layer ground region 4 becomes floating, and the response speed of the depletion layer is delayed as compared with the other protective diffusion layers 306 during the transient response. As a result, there is a risk that the gate insulating film may be destroyed due to an increase in switching loss, characteristic variations in the semiconductor device 300, and eventually current concentration during high-speed operation.
　本実施の形態にかかる半導体装置１００では、保護拡散層接地領域４を含む第１の活性ストライプ領域３ａと保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂとを、活性ストライプ領域３の短手方向に交互に配置しているため、保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂは保護拡散層接地領域４を含む第１の活性ストライプ領域３ａに挟まれることになり、全てのストライプトレンチ３０７が保護拡散層接地領域４と接続する。これにより、ストライプトレンチ３０７下部に設けた保護拡散層３０６がフローティングとなる箇所がなくなり、スイッチング損失の増加や、半導体装置３００内での特性ばらつき、ひいては高速動作時の電流集中によるゲート絶縁膜３０５の破壊といった問題を抑制することができる。 In the semiconductor device 100 according to the present embodiment, the active stripe region 3 includes the first active stripe region 3 a including the protective diffusion layer ground region 4 and the second active stripe region 3 b not including the protective diffusion layer ground region 4. Since the second active stripe regions 3b that do not include the protective diffusion layer ground region 4 are sandwiched between the first active stripe regions 3a that include the protective diffusion layer ground region 4, Thus, all the stripe trenches 307 are connected to the protective diffusion layer ground region 4. As a result, there is no place where the protective diffusion layer 306 provided below the stripe trench 307 is in a floating state, and an increase in switching loss, variation in characteristics within the semiconductor device 300, and further current concentration during high-speed operation, Problems such as destruction can be suppressed.
　よって、本実施の形態にかかる半導体装置１００では、ゲート電極３０４のレイアウトをストライプ状とすることでオン電流経路を広くしオン抵抗を低減するとともに、保護拡散層３０６の一部がフローティングとなってしまうことを抑制し、スイッチング損失の増加や、半導体装置１００内での特性ばらつき、ひいては高速動作時の電流集中によるゲート絶縁膜３０５の破壊といった問題を抑制することができる。 Therefore, in the semiconductor device 100 according to the present embodiment, the layout of the gate electrode 304 is striped to widen the on-current path and reduce the on-resistance, and part of the protective diffusion layer 306 is in a floating state. Therefore, problems such as an increase in switching loss, characteristic variations in the semiconductor device 100, and breakdown of the gate insulating film 305 due to current concentration during high-speed operation can be suppressed.
　また、空乏層が延びる距離は温度上昇とともに長くなるため、保護拡散層３０６を設けたトレンチゲート型の半導体装置では温度上昇とともにＪＦＥＴ抵抗が増加する。本実施の形態にかかる半導体装置１００では、ゲート電極３０４をストライプ状のレイアウトにすることで、格子型のレイアウトに比べて電流経路が広くなるため、温度上昇に伴うＪＦＥＴ抵抗の増加が緩やかになり、オン抵抗の温度特性（温度変化に伴うばらつき）を改善することができる。 In addition, since the distance that the depletion layer extends becomes longer as the temperature rises, in the trench gate type semiconductor device provided with the protective diffusion layer 306, the JFET resistance increases as the temperature rises. In the semiconductor device 100 according to the present embodiment, the gate electrode 304 has a stripe layout, so that the current path becomes wider compared to the lattice layout, so that the increase in JFET resistance with a rise in temperature becomes moderate. In addition, the temperature characteristics of on-resistance (variation due to temperature change) can be improved.
　また、本実施の形態にかかる半導体装置１００では、保護拡散層接地領域４において、ソース電極５と保護拡散層３０６を接続している。本実施の形態にかかる半導体装置１００とは異なり保護拡散層接地領域４において両側のゲート電極３０４の間において部分的に開口を設けることとしてもよいが、本実施の形態のように保護拡散層接地領域４において両側のゲート電極３０４の間の全体に開口を設け、この開口部４０２内でソース電極５と保護拡散層３０６とを接続することで、コンタクト面積を広げ、ソース電極５と保護拡散層３０６とのコンタクト抵抗を低減することが可能となる。 Further, in the semiconductor device 100 according to the present embodiment, the source electrode 5 and the protective diffusion layer 306 are connected in the protective diffusion layer ground region 4. Unlike the semiconductor device 100 according to the present embodiment, an opening may be partially provided between the gate electrodes 304 on both sides in the protective diffusion layer ground region 4, but the protective diffusion layer ground is provided as in the present embodiment. In the region 4, an opening is provided between the gate electrodes 304 on both sides, and the source electrode 5 and the protective diffusion layer 306 are connected within the opening 402, thereby expanding the contact area, and the source electrode 5 and the protective diffusion layer. The contact resistance with 306 can be reduced.
　さらに、保護拡散層接地領域４において、ソース電極５と保護拡散層３０６とがコンタクトする深さ方向の位置は適宜変更しても構わないが、本実施の形態にかかる半導体装置１００のように、保護拡散層接地領域４の開口部４０２内において、ソース電極５がベース領域３０３よりも深い開口部４０２の底部にまで延在し、開口部４０２の底部で保護拡散層３０６と接続することが望ましい。保護拡散層接地領域４でソース電極５と保護拡散層３０６と接続する場合、保護拡散層３０６をエピタキシャル層２の表面上まで形成し、ソース電極５と接続すること等も可能であるが、保護拡散層３０６よりも抵抗率の低いソース電極５を開口部４０２の底部にまで延在させ、ソース電極５と保護拡散層３０６を接続することで、保護拡散層３０６とソース電極５との間の抵抗を低減でき、スイッチング損失を低減できる。 Further, in the protective diffusion layer grounding region 4, the position in the depth direction where the source electrode 5 and the protective diffusion layer 306 are in contact with each other may be appropriately changed, but as in the semiconductor device 100 according to the present embodiment, In the opening 402 of the protective diffusion layer grounding region 4, the source electrode 5 preferably extends to the bottom of the opening 402 deeper than the base region 303 and is connected to the protective diffusion layer 306 at the bottom of the opening 402. . When connecting the source electrode 5 and the protective diffusion layer 306 in the protective diffusion layer grounding region 4, the protective diffusion layer 306 can be formed up to the surface of the epitaxial layer 2 and connected to the source electrode 5. The source electrode 5 having a resistivity lower than that of the diffusion layer 306 is extended to the bottom of the opening 402 and the source electrode 5 and the protective diffusion layer 306 are connected to each other, so that the gap between the protective diffusion layer 306 and the source electrode 5 is reached. Resistance can be reduced and switching loss can be reduced.
　また、本実施の形態にかかる半導体装置１００では、保護拡散層接地領域４の開口部４０２内において、ゲート電極３０４の側面を覆う層間絶縁膜６をゲート絶縁膜３０５よりも厚くしているため、ゲート・ソース間の寄生容量を低減し、スイッチング特性（損失・時間等）を改善することができる。 In the semiconductor device 100 according to the present embodiment, the interlayer insulating film 6 that covers the side surface of the gate electrode 304 is thicker than the gate insulating film 305 in the opening 402 of the protective diffusion layer ground region 4. The parasitic capacitance between the gate and the source can be reduced, and the switching characteristics (loss, time, etc.) can be improved.
　本実施の形態にかかる半導体装置１００は、本発明の趣旨を逸脱しない範囲で適宜修正・変更することが可能である。そこで、図１１～１３を用いて、本実施の形態にかかる半導体装置１００の変形例を示す。図１１ないし１３は、本実施の形態にかかる半導体装置１００の変形例を示す平面図である。以下、本実施の形態にかかる半導体装置１００との相違点についてのみ説明する。 The semiconductor device 100 according to the present embodiment can be appropriately modified and changed without departing from the spirit of the present invention. Accordingly, a modification of the semiconductor device 100 according to the present embodiment will be described with reference to FIGS. 11 to 13 are plan views showing modifications of the semiconductor device 100 according to the present embodiment. Hereinafter, only differences from the semiconductor device 100 according to the present embodiment will be described.
　図１１は示す半導体装置１０１では、本実施の形態に係る半導体装置１００と比較して、活性ストライプ領域３においてコンタクトホール３０１内に露出したベース領域３０３を複数の領域に分割し、ストライプ状から島状に変更されている点のみが異なる。図１に示す半導体装置１００では、コンタクトホール３０１内に露出したベース領域３０３を、長方形状である活性ストライプセル３０の形状に対応させて、単一の長方形状としている。一方、図１１に示す半導体装置１０１では、長方形状である活性ストライプセル３０において、コンタクトホール３０１内のエピタキシャル層２の表面に露出したベース領域３０３が、正方形状の複数の領域からなり、一定間隔で離間して設けられている。 In the semiconductor device 101 shown in FIG. 11, the base region 303 exposed in the contact hole 301 in the active stripe region 3 is divided into a plurality of regions as compared with the semiconductor device 100 according to the present embodiment. The only difference is that it has been changed. In the semiconductor device 100 shown in FIG. 1, the base region 303 exposed in the contact hole 301 has a single rectangular shape corresponding to the shape of the rectangular active stripe cell 30. On the other hand, in the semiconductor device 101 shown in FIG. 11, in the rectangular active stripe cell 30, the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of square regions, and has a constant interval. Are provided apart from each other.
　図１に示す半導体装置１００のように、ゲート電極３０４がストライプ状のレイアウトとなる場合、活性ストライプ領域３の短辺方向のピッチを縮めることで、チャネル幅密度の減少を抑えることができる。しかしながら、コンタクトホール３０１とゲート電極３０４との間の距離を縮めることはゲート－ソース間のリーク発生率を高める懸念があるため、コンタクトホール３０１とゲート電極３０４との間の距離を一定距離確保する必要がある。そのため、活性ストライプ領域３の短辺側のピッチ縮小のためには、コンタクトホール３０１の寸法を縮める必要があるが、コンタクトホールの寸法を縮小することはコンタクト抵抗の増加につながるため、ピッチ縮小によってチャネル抵抗は低減できるものの、コンタクト抵抗は増加してしまう。 In the case where the gate electrode 304 has a stripe layout as in the semiconductor device 100 shown in FIG. 1, the reduction in channel width density can be suppressed by reducing the pitch in the short side direction of the active stripe region 3. However, since reducing the distance between the contact hole 301 and the gate electrode 304 may increase the gate-source leakage rate, a certain distance is ensured between the contact hole 301 and the gate electrode 304. There is a need. Therefore, in order to reduce the pitch on the short side of the active stripe region 3, it is necessary to reduce the size of the contact hole 301. However, reducing the size of the contact hole leads to an increase in contact resistance. Although the channel resistance can be reduced, the contact resistance increases.
　そこで、コンタクトホール３０１内におけるベース領域３０３の占有面積を減らし、ソース領域３０２を増やすことで、ソース領域３０２とソース電極５とのコンタクト面積を大きくし、コンタクト抵抗を低減することができる。図１１に示す半導体装置１０１では、コンタクトホール３０１内のエピタキシャル層２の表面に露出したベース領域３０３が複数の領域に分割されており、分割された複数のベース領域３０３の間にはソース領域３０２が露出している。そのため、図１に示す半導体装置１００に比べて、コンタクトホール３０１内のソース領域３０２の面積を大きくすることができ、ソース領域３０２とソース電極５との間のコンタクト抵抗を低減することができる。ただし、ベース領域３０３の面積が小さくなりすぎるとスイッチングの際のベース領域３０３の応答が遅くなる懸念があるため、コンタクトホール３０１内のベース領域３０３の占有面積は２０％以上とすることが望ましい。 Therefore, by reducing the area occupied by the base region 303 in the contact hole 301 and increasing the source region 302, the contact area between the source region 302 and the source electrode 5 can be increased, and the contact resistance can be reduced. In the semiconductor device 101 shown in FIG. 11, the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is divided into a plurality of regions, and the source region 302 is interposed between the plurality of divided base regions 303. Is exposed. Therefore, compared with the semiconductor device 100 shown in FIG. 1, the area of the source region 302 in the contact hole 301 can be increased, and the contact resistance between the source region 302 and the source electrode 5 can be reduced. However, if the area of the base region 303 becomes too small, there is a concern that the response of the base region 303 at the time of switching may be delayed. Therefore, the occupied area of the base region 303 in the contact hole 301 is desirably 20% or more.
　なお、図１１に示す半導体装置１０１の製造にあたっては、ベース領域３０３、あるいはソース領域３０２形成時のパターンを転写するマスクのレイアウトを変更するだけでよく、工程数の増加を伴うことは無い。 In manufacturing the semiconductor device 101 shown in FIG. 11, it is only necessary to change the layout of the mask for transferring the pattern when the base region 303 or the source region 302 is formed, and the number of processes is not increased.
　図１２に示す半導体装置１０２では、コンタクトホール３０１内のエピタキシャル層２の表面に露出したベース領域３０３が、長方形状の複数の領域からなり、一定間隔で離間して設けられている。表面に露出したベース領域３０３のそれぞれは、活性ストライプ領域３の短辺方向において、隣接するストライプトレンチ３０７の一方から他方にまで延在している。 In the semiconductor device 102 shown in FIG. 12, the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of rectangular regions and is provided at regular intervals. Each of the base regions 303 exposed on the surface extends from one of the adjacent stripe trenches 307 to the other in the short side direction of the active stripe region 3.
　活性ストライプ領域３の短辺方向のピッチを縮小した場合、コンタクトホール３０１が活性ストライプ領域３の短辺方向に位置ずれしてしまうと、コンタクトホール３０１内におけるソース領域３０２の占有面積の変化が顕著となり、各活性ストライプセル３０のオン抵抗のばらつきが大きくなる懸念がある。図１２に示す半導体装置１０２では、表面に露出したベース領域３０３のそれぞれがストライプトレンチ３０７同士の間で活性ストライプ領域３の短辺方向に一様に設けられているため、活性ストライプ領域３の短辺方向にコンタクトホール３０１の位置がずれた場合でも、コンタクトホール３０１内に占めるソース領域３０２の面積は変化しない。そのため、活性ストライプ領域３の短辺方向のピッチをより一層縮小することができ、オン抵抗低減を図ることができる。 When the pitch in the short side direction of the active stripe region 3 is reduced, if the contact hole 301 is displaced in the short side direction of the active stripe region 3, a change in the occupied area of the source region 302 in the contact hole 301 is remarkable. Therefore, there is a concern that the variation in the on-resistance of each active stripe cell 30 becomes large. In the semiconductor device 102 shown in FIG. 12, each of the base regions 303 exposed on the surface is uniformly provided in the short side direction of the active stripe region 3 between the stripe trenches 307. Even when the position of the contact hole 301 is shifted in the side direction, the area of the source region 302 in the contact hole 301 does not change. Therefore, the pitch in the short side direction of the active stripe region 3 can be further reduced, and the on-resistance can be reduced.
　図１３に示す半導体装置１０３では、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとの構成比率を２：１としている。より詳細には、活性ストライプ領域３の短辺方向において、第１の活性ストライプ領域３ａが２つ並び第２の活性ストライプ領域３ｂが１つ並ぶ３つの活性ストライプ領域３を最小単位としてこれが繰り返し並んでいる。また、活性ストライプ領域３の短辺方向において保護拡散層接地領域４の幅は、活性ストライプ領域３の短辺の２倍となっており、隣接する２つの第１の活性ストライプ領域３ａに対して共通の保護拡散層接地領域４が設けられている。なお、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとの構成比率は２：１に限定されるものではなく適宜設定することができる。その際、活性ストライプ領域３の短辺方向において保護拡散層接地領域４の幅は、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとの構成比率に対応して、活性ストライプ領域３の短辺の幅の整数倍とすれば、活性ストライプ領域３の短辺を等しく配置することできる。 In the semiconductor device 103 shown in FIG. 13, the composition ratio of the first active stripe region 3a and the second active stripe region 3b is 2: 1. More specifically, in the short side direction of the active stripe region 3, two first active stripe regions 3a and two second active stripe regions 3b are arranged as a minimum unit, and this is repeatedly arranged. It is out. Further, the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 is twice the short side of the active stripe region 3, and the two adjacent first active stripe regions 3a are adjacent to each other. A common protective diffusion layer ground region 4 is provided. The configuration ratio of the first active stripe region 3a and the second active stripe region 3b is not limited to 2: 1 and can be set as appropriate. At this time, the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 corresponds to the composition ratio of the first active stripe region 3a and the second active stripe region 3b. If the width is an integral multiple of the width of the short side, the short sides of the active stripe region 3 can be arranged equally.
　図１に示す半導体装置１００では、保護拡散層接地領域４を含む第１の活性ストライプ領域３ａと保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂとを交互に並べることとしたが、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとの配置はこれに限定されるものではない。図１３に示すように、複数の第１の活性ストライプ領域３ａごとに１つの第２の活性ストライプ領域３ｂを設けることとしても構わない。その際、図２２に示すように、第２の活性ストライプ領域３ｂ同士が隣接してしまうと第２の活性ストライプ領域３ｂの間のストライプトレンチ３０７の下部に設けられた保護拡散層３０６がフローティングとなる恐れがある。そこで、図１３に示すように、各第２の活性ストライプ領域３ｂの両側には第１の活性ストライプ領域３ａを隣接させ、第２の活性ストライプ領域３ｂが第１の活性ストライプ領域３ａに挟まれるように配置する。これにより、一部の保護拡散層３０６がフローティングとなることを抑制することができる。 In the semiconductor device 100 shown in FIG. 1, the first active stripe region 3a including the protective diffusion layer ground region 4 and the second active stripe region 3b not including the protective diffusion layer ground region 4 are alternately arranged. The arrangement of the first active stripe region 3a and the second active stripe region 3b is not limited to this. As shown in FIG. 13, one second active stripe region 3b may be provided for each of the plurality of first active stripe regions 3a. At this time, as shown in FIG. 22, if the second active stripe regions 3b are adjacent to each other, the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is floated. There is a fear. Therefore, as shown in FIG. 13, the first active stripe region 3a is adjacent to both sides of each second active stripe region 3b, and the second active stripe region 3b is sandwiched between the first active stripe regions 3a. Arrange so that. Thereby, it is possible to prevent a part of the protective diffusion layer 306 from floating.
　本実施の形態によれば、保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂが保護拡散層接地領域４を含む第１の活性ストライプ領域３ａに挟まれるように配置することにより、一部の保護拡散層３０６がフローティングとなることを抑制でき、スイッチング特性の悪化を抑制することができる。 According to the present embodiment, the second active stripe region 3b that does not include the protective diffusion layer ground region 4 is disposed so as to be sandwiched between the first active stripe region 3a that includes the protective diffusion layer ground region 4, Some of the protective diffusion layers 306 can be prevented from floating, and deterioration of switching characteristics can be suppressed.
実施の形態２．
　図１４は、本発明の実施の形態２にかかる半導体装置１１０を示す平面図である。以下、本実施の形態では、実施の形態１と相違する部分について説明し、同一または対応する部分については説明を省略する。図１４において、図１と同一の符号を付けたものは、同一または対応する構成を示している。本実施の形態では、ストライプトレンチ３０７と交差する交差トレンチ３０８を設けた点で、実施の形態１と相違している。 Embodiment 2. FIG.
FIG. 14 is a plan view showing the semiconductor device 110 according to the second embodiment of the present invention. Hereinafter, in the present embodiment, parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted. 14, the same reference numerals as those in FIG. 1 denote the same or corresponding configurations. The present embodiment is different from the first embodiment in that an intersection trench 308 that intersects with the stripe trench 307 is provided.
　実施の形態１では、保護拡散層接地領域４を含む第１の活性ストライプ領域３ａが、保護拡散層接地領域４を含まない第２の活性ストライプ領域３ｂの両側に隣接するように配置することで、第２の活性ストライプ領域３ｂ同士が隣接し、第２の活性ストライプ領域３ｂの間のストライプトレンチ３０７の下部に設けられた保護拡散層３０６がフローティングとなるのを抑制していた。一方、図２２に示す半導体装置３００のように、第２の活性ストライプ領域３ｂ同士が隣接した構造であっても、ストライプトレンチ３０７に交差する交差トレンチ３０８を設けることで、第２の活性ストライプ領域３ｂの間のストライプトレンチ３０７の下部に設けられた保護拡散層３０６をソース電極５に接続することができる。 In the first embodiment, the first active stripe region 3a including the protective diffusion layer ground region 4 is disposed adjacent to both sides of the second active stripe region 3b not including the protective diffusion layer ground region 4. The second active stripe regions 3b are adjacent to each other, and the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is prevented from floating. On the other hand, even if the second active stripe regions 3b are adjacent to each other as in the semiconductor device 300 shown in FIG. 22, the second active stripe region can be obtained by providing the intersecting trench 308 intersecting the stripe trench 307. A protective diffusion layer 306 provided below the stripe trench 307 between 3 b can be connected to the source electrode 5.
　本実施の形態では、図１４に示すように、ストライプトレンチ３０７の長手方向に垂直な方向でストライプトレンチ３０７と交差する交差トレンチ３０８を設けている。交差トレンチには、他のトレンチと同様に、ゲート電極３０４とゲート絶縁膜３０５が配設されており、交差トレンチ下部においても保護拡散層３０６が設けられている。交差トレンチは、隣接する２つ保護拡散層接地領域４の間のそれぞれ設けられ、活性ストライプ領域３の短辺方向に向かって延在している。より詳細には、交差トレンチ３０８は、活性ストライプ領域３の短辺方向で隣接する２つの保護拡散層接地領域４を接続するように、隣接する保護拡散層接地領域４の間に設けられ、隣接する保護拡散層接地領域４の間において、第２の活性ストライプ領域３ｂに挟まれたストライプトレンチ３０７と垂直に交差している。 In the present embodiment, as shown in FIG. 14, an intersection trench 308 that intersects with the stripe trench 307 in a direction perpendicular to the longitudinal direction of the stripe trench 307 is provided. Like the other trenches, a gate electrode 304 and a gate insulating film 305 are disposed in the intersection trench, and a protective diffusion layer 306 is also provided under the intersection trench. The intersecting trenches are respectively provided between two adjacent protective diffusion layer ground regions 4 and extend in the short side direction of the active stripe region 3. More specifically, the intersecting trench 308 is provided between the adjacent protective diffusion layer ground regions 4 so as to connect the two adjacent protective diffusion layer ground regions 4 in the short side direction of the active stripe region 3. Between the protective diffusion layer ground regions 4 to be crossed, the stripes 307 perpendicularly intersect with the second active stripe regions 3b.
　図２２に示す半導体装置３００では、第２の活性ストライプ領域３ｂに挟まれたストライプトレンチ３０７下部に設けられた保護拡散層３０６はフローティングとなってしまうが、本実施の形態にかかる半導体装置１１０では、交差トレンチ３０８下部に設けられた保護拡散層３０６を介して、第２の活性ストライプ領域３ｂによって挟まれたストライプトレンチ下部の保護拡散層３０６も、保護拡散層接地領域４に接続されることになる。よって、保護拡散層３０６をより確実にソース電極５に接続することができるため、スイッチング損失の増加や、半導体装置３００内での特性ばらつき、ひいては高速動作時の電流集中によるゲート絶縁膜の破壊を抑制することができる。 In the semiconductor device 300 shown in FIG. 22, the protective diffusion layer 306 provided below the stripe trench 307 sandwiched between the second active stripe regions 3b is floating, but in the semiconductor device 110 according to the present embodiment, The protective diffusion layer 306 below the stripe trench sandwiched between the second active stripe regions 3b is also connected to the protective diffusion layer ground region 4 via the protective diffusion layer 306 provided below the intersecting trench 308. Become. Accordingly, since the protective diffusion layer 306 can be connected to the source electrode 5 more reliably, an increase in switching loss, a variation in characteristics within the semiconductor device 300, and a breakdown of the gate insulating film due to current concentration during high-speed operation can be prevented. Can be suppressed.
　また、本実施の形態にかかる半導体装置１１０では、ゲート電極３０４が配設される交差トレンチ３０８を設けることで、交差トレンチ３０８の側面にもチャネル形成されることになるため、チャネル幅密度を向上させオン抵抗を低減することができる。一方、交差トレンチ３０８を設けることで、活性ストライプセル３０の長辺の長さが狭くなり、保護拡散層３０６から伸びる空乏層によるＪＦＥＴ抵抗が増大するおそれがあるため、交差トレンチ３０８を設ける間隔は、活性ストライプセル３０が少なくともストライプ状（長方形状）となるように設定され、好ましくは活性ストライプセル３０の長辺の長さが短辺の長さの１．５倍以上、より好ましくは２．０倍以上となるように設定される。 Further, in the semiconductor device 110 according to the present embodiment, by providing the intersecting trench 308 in which the gate electrode 304 is provided, a channel is also formed on the side surface of the intersecting trench 308, so that the channel width density is improved. Thus, the on-resistance can be reduced. On the other hand, by providing the intersection trench 308, the length of the long side of the active stripe cell 30 is narrowed, and the JFET resistance due to the depletion layer extending from the protective diffusion layer 306 may increase. The active stripe cells 30 are set to have at least a stripe shape (rectangular shape), preferably the length of the long side of the active stripe cell 30 is 1.5 times the length of the short side, more preferably 2. It is set to be 0 times or more.
　図２１に示す半導体装置２００では、格子型のゲート電極配置となっているため、保護拡散層接地領域４を少なくとも１つ設ければ、ゲート電極３０４の下部に設けられた全ての保護拡散層３０６は必然的にソース電極５に接続されることになるが、保護拡散層３０６からの空乏層が各活性セルにおいて４方向から伸びることになりＪＦＥＴ抵抗が増加しオン抵抗の増加を招く。一方、このようなオン抵抗増加を抑制するために、図２２に示すように、図２１の半導体装置２００の構造においてゲート電極３０４をそのままストライプ状のレイアウトに変更すると、一部の保護拡散層３０６がフローティングとなり、スイッチング特性の悪化等を招いてしまうのは、上述したとおりである。 Since the semiconductor device 200 shown in FIG. 21 has a lattice-type gate electrode arrangement, if at least one protective diffusion layer ground region 4 is provided, all the protective diffusion layers 306 provided below the gate electrode 304 are provided. Inevitably is connected to the source electrode 5, but the depletion layer from the protective diffusion layer 306 extends from the four directions in each active cell, increasing the JFET resistance and increasing the on-resistance. On the other hand, in order to suppress such an increase in on-resistance, as shown in FIG. 22, when the gate electrode 304 is changed to a striped layout as it is in the structure of the semiconductor device 200 of FIG. As described above, becomes floating and causes deterioration of switching characteristics.
　本実施の形態では、交差トレンチ３０８の下部に設けられた保護拡散層３０６を介して、ストライプトレンチ３０７下部に設けられた保護拡散層３０６同士を接続することで、一部の保護拡散層３０６がフローティングになることを抑制しつつ、活性ストライプセル３０がストライプ状を維持するように交差トレンチ３０８の間隔を設定することで、ＪＦＥＴ抵抗の増加を抑制し、オン抵抗低減を図ることができる。 In the present embodiment, a part of the protective diffusion layers 306 is formed by connecting the protective diffusion layers 306 provided below the stripe trenches 307 via the protective diffusion layers 306 provided below the intersection trenches 308. By setting the interval between the intersecting trenches 308 so that the active stripe cells 30 maintain the stripe shape while suppressing the floating state, an increase in JFET resistance can be suppressed and an on-resistance can be reduced.
　また、交差トレンチ３０８を設ける構成は、本実施の形態のように第２の活性ストライプ領域３ｂ同士が隣接した構造に限られるものではなく、例えば、実施の形態１のように、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂとが交互に並ぶレイアウトにおいて、交差トレンチ３０８を設けることとしてもよい。 The configuration in which the intersection trench 308 is provided is not limited to the structure in which the second active stripe regions 3b are adjacent to each other as in the present embodiment. For example, as in the first embodiment, the first active stripe region 3b is provided. In the layout in which the stripe regions 3a and the second active stripe regions 3b are alternately arranged, the intersection trench 308 may be provided.
　図１５には、本実施の形態の変形例にかかる半導体装置１１１を示す。図１５において、実施の形態１と同様に、第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂと活性ストライプ領域３の短辺方向において交互に並んでおり、第２の活性ストライプ領域３ｂには、活性ストライプ領域３の長辺方向に一定間隔で交差トレンチ３０８が設けられている。また、図１５においては、保護拡散層接地領域４ごとに交差トレンチ３０８が設けられ、各交差トレンチ３０８の一端は保護拡散層接地領域４に接続している。第１の活性ストライプ領域３ａと第２の活性ストライプ領域３ｂと活性ストライプ領域３の短辺方向において交互に並んだ構成においても、交差トレンチ３０８を設けることで、チャネル幅密度を向上させオン抵抗を低減することができる。 FIG. 15 shows a semiconductor device 111 according to a modification of the present embodiment. In FIG. 15, as in the first embodiment, the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short side direction, and the second active stripe region 3b Are provided with intersecting trenches 308 at regular intervals in the long side direction of the active stripe region 3. In FIG. 15, an intersection trench 308 is provided for each protective diffusion layer ground region 4, and one end of each intersection trench 308 is connected to the protection diffusion layer ground region 4. Even in the configuration in which the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short side direction, by providing the intersection trench 308, the channel width density is improved and the on-resistance is increased. Can be reduced.
　本実施の形態によれば、交差トレンチ３０８によってフローティングとなりうるストライプトレンチ３０７と保護拡散層接地領域４とを接続することでスイッチング特性の悪化を抑制することができる。また、交差トレンチ３０８を設けることで、交差トレンチ３０８の側面にチャネル領域を形成することが可能となるため、チャネル幅密度を向上させオン抵抗を低減することが可能となる。 According to the present embodiment, the deterioration of the switching characteristics can be suppressed by connecting the stripe trench 307 that can be floated by the intersection trench 308 and the protective diffusion layer grounding region 4. In addition, since the cross trench 308 is provided, a channel region can be formed on the side surface of the cross trench 308, so that the channel width density can be improved and the on-resistance can be reduced.
実施の形態３．
　図１６は、本発明の実施の形態３にかかる半導体装置１２０を示す平面図である。以下、本実施の形態では、実施の形態１と相違する部分について説明し、同一または対応する部分についての説明は省略する。図１６において、図１と同一の符号を付けたものは、同一または対応する構成を示している。本実施の形態では、全ての活性ストライプ領域３に保護拡散層接地領域４を設けた点で実施の形態１と相違している。 Embodiment 3 FIG.
FIG. 16 is a plan view showing a semiconductor device 120 according to the third embodiment of the present invention. Hereinafter, in the present embodiment, parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted. In FIG. 16, the same reference numerals as those in FIG. 1 denote the same or corresponding components. The present embodiment is different from the first embodiment in that the protective diffusion layer ground region 4 is provided in all the active stripe regions 3.
　図１６において、複数の活性ストライプ領域３のそれぞれに保護拡散層接地領域４が設けられており、すなわち保護拡散層接地領域４を含む第１活性ストライプ領域３ａのみで構成されている。また、各活性ストライプ領域３の保護拡散層接地領域４は、活性ストライプ領域３の短辺方向で連続して形成されている。言い換えると、本実施の形態における保護拡散層接地領域４は、活性ストライプ領域３の短辺方向（図１６における上下方向）に延在した、ストライプ状の一つの開口部によって形成されている。そして、複数のストライプ状の保護拡散層接地領域４が、活性ストライプ領域３の長手方向に一定間隔で離間して設けられている。 In FIG. 16, each of the plurality of active stripe regions 3 is provided with a protective diffusion layer ground region 4, that is, only the first active stripe region 3 a including the protective diffusion layer ground region 4. The protective diffusion layer ground region 4 of each active stripe region 3 is continuously formed in the short side direction of the active stripe region 3. In other words, the protective diffusion layer ground region 4 in the present embodiment is formed by one stripe-shaped opening extending in the short side direction (vertical direction in FIG. 16) of the active stripe region 3. A plurality of stripe-shaped protective diffusion layer ground regions 4 are provided at regular intervals in the longitudinal direction of the active stripe region 3.
　図１６の上下方向に延びるストライプ状の開口部（保護拡散層接地領域４）の両端側面にはゲート電極３０４が設けられている（図示せず）。そのため、図１６の左右方向に延在し活性ストライプセル３０を規定するストライプトレンチ３０７内に設けられる複数のゲート電極３０４は、互いに、保護拡散層接地領域４内に設けられるゲート電極３０４によって接続されることになる。これに伴いストライプトレンチ３０７（ゲート電極３０４）の下部に設けられた保護拡散層３０６は、保護拡散層接地領域４において開口部４０２の下部に設けられた保護拡散層３０６によって互いに接続されるとともに、保護拡散層接地領域４においてソース電極５と接続している。 A gate electrode 304 is provided on both side surfaces of a striped opening (protective diffusion layer grounding region 4) extending in the vertical direction in FIG. 16 (not shown). Therefore, the plurality of gate electrodes 304 provided in the stripe trenches 307 extending in the left-right direction in FIG. 16 and defining the active stripe cell 30 are connected to each other by the gate electrodes 304 provided in the protective diffusion layer ground region 4. Will be. Accordingly, the protective diffusion layer 306 provided below the stripe trench 307 (gate electrode 304) is connected to each other by the protective diffusion layer 306 provided below the opening 402 in the protective diffusion layer ground region 4, and The protective diffusion layer ground region 4 is connected to the source electrode 5.
　本実施の形態にかかる半導体装置１２０では、活性ストライプ領域３のそれぞれに保護拡散層接地領域４が設けられているため、保護拡散層３０６の一部がフローティングとなりスイッチング特性が悪化することを抑制することができる。また、本実施の形態の場合には、活性ストライプ領域３のそれぞれに保護拡散層接地領域４を設けているが、実施の形態１と比較すると相対的に保護拡散層接地領域４の比率が増加するおそれがある。保護拡散層接地領域４ではオン電流経路が形成されないため、保護拡散層接地領域４を密にしてしまうと、オン電流経路が狭窄され、オン抵抗が増加するおそれがある。そのため、保護拡散層接地領域４同士の間隔は、実施の形態１と比べると大きくするのが望ましく、保護拡散層接地領域４の専有面積がオン抵抗に支障がない程度の割合になるように設定するのが望ましい。 In the semiconductor device 120 according to the present embodiment, since the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is prevented that a part of the protective diffusion layer 306 is floated and the switching characteristics are deteriorated. be able to. In the present embodiment, the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, but the ratio of the protective diffusion layer ground region 4 is relatively increased as compared with the first embodiment. There is a risk. Since the on-current path is not formed in the protective diffusion layer ground region 4, if the protective diffusion layer ground region 4 is made dense, the on-current path may be narrowed and the on-resistance may be increased. Therefore, it is desirable that the interval between the protective diffusion layer grounding regions 4 is larger than that in the first embodiment, and the exclusive area of the protective diffusion layer grounding region 4 is set to a ratio that does not hinder the on-resistance. It is desirable to do.
　一方、本実施の形態にかかる半導体装置１２０では、図１６の上下方向に延在するストライプ状の保護拡散層接地領域４によって、ストライプトレンチ３０７内のゲート電極３０４は横方向に独立して分断されているため、ゲート抵抗の増加を招くおそれがある。そこで、ゲート抵抗の低減を図る場合には、各活性ストライプ領域３に含まれる保護拡散層接地領域４同士を隣接して形成されないことが望ましい。図１７には、本実施の形態の変形例にかかる半導体装置１２１の平面図を示す。図１７に示す半導体装置１２１では、活性ストライプ領域３のそれぞれに保護拡散層接地領域４が設けられるとともに、ゲート抵抗を低減するために、各活性ストライプ領域３に含まれる保護拡散層接地領域４が一定間隔で離間して設けられている。そして、正方形状の保護拡散層接地領域４の各辺に沿ってゲート電極３０４を配設されている。これにより、保護拡散層接地領域４によってゲート電極３０４が分断されることがないため、ゲート抵抗の増加を抑制することができる。 On the other hand, in the semiconductor device 120 according to the present embodiment, the gate electrode 304 in the stripe trench 307 is independently divided in the lateral direction by the stripe-shaped protective diffusion layer ground region 4 extending in the vertical direction in FIG. Therefore, there is a risk of increasing the gate resistance. Therefore, when reducing the gate resistance, it is desirable that the protective diffusion layer ground regions 4 included in each active stripe region 3 are not formed adjacent to each other. FIG. 17 shows a plan view of a semiconductor device 121 according to a modification of the present embodiment. In the semiconductor device 121 shown in FIG. 17, the protective diffusion layer ground region 4 is provided in each active stripe region 3, and the protective diffusion layer ground region 4 included in each active stripe region 3 is provided in order to reduce the gate resistance. They are provided at regular intervals. A gate electrode 304 is disposed along each side of the square-shaped protective diffusion layer grounding region 4. Thereby, since the gate electrode 304 is not divided by the protective diffusion layer grounding region 4, an increase in gate resistance can be suppressed.
　また、本実施の形態では、隣接する各活性ストライプ領域３の保護拡散層接地領域４を連続して形成し、一つのストライプ状の開口部によって形成することとしたが、保護拡散層接地領域４を複数の区画に分けて構成することとしても構わない。図１８には、本実施の形態にかかる半導体装置１２０において保護拡散層接地領域４を複数の区画に分けた変形例を示す。図１８に示す半導体装置１２２では、保護拡散層接地領域４は複数の離間した正方形状の区画で構成されており、保護拡散層接地領域４が複数離間して並んだ列が複数設けられている。そして、保護拡散層接地領域４の列の間で活性ストライプセル３０が形成されている。 In the present embodiment, the protective diffusion layer ground region 4 of each adjacent active stripe region 3 is formed continuously and formed by one stripe-shaped opening, but the protective diffusion layer ground region 4 is formed. May be divided into a plurality of sections. FIG. 18 shows a modification in which the protective diffusion layer ground region 4 is divided into a plurality of sections in the semiconductor device 120 according to the present embodiment. In the semiconductor device 122 shown in FIG. 18, the protective diffusion layer grounding region 4 is composed of a plurality of spaced square sections, and a plurality of columns in which the protective diffusion layer grounding regions 4 are arranged in a plurality of spaced apart are provided. . Active stripe cells 30 are formed between columns of the protective diffusion layer ground region 4.
　図１８において、保護拡散層接地領域４を構成する複数の区画の間には、正方形状の活性セル３１が設けられている。活性セル３１における活性ストライプ領域３の短辺方向の辺は、ストライプトレンチ３０７に交差する２本の交差トレンチ３０８で構成されており、交差トレンチ３０８内部にはゲート電極３０４とゲート絶縁膜３０５が配設されており、交差トレンチ３０８の下部には保護拡散層３０６が設けられている。また、活性セル３１と保護拡散層接地領域４との境界には、活性ストライプ領域３の長手方向に延びるトレンチが設けられており、当該トレンチ内部にはゲート電極３０４が設けられている。このように、保護拡散層接地領域４が形成されていた領域の一部に、活性ストライプセル３０とは平面形状の異なる活性セル３１を設けることで、オン電流経路を増加し、チャネル幅密度も向上するため、オン抵抗を低減することができる。 In FIG. 18, square active cells 31 are provided between a plurality of sections constituting the protective diffusion layer grounding region 4. The side in the short side direction of the active stripe region 3 in the active cell 31 is composed of two intersecting trenches 308 intersecting with the stripe trench 307, and a gate electrode 304 and a gate insulating film 305 are arranged inside the intersecting trench 308. A protective diffusion layer 306 is provided below the intersection trench 308. Further, a trench extending in the longitudinal direction of the active stripe region 3 is provided at the boundary between the active cell 31 and the protective diffusion layer ground region 4, and a gate electrode 304 is provided inside the trench. As described above, by providing the active cells 31 having a different planar shape from the active stripe cells 30 in a part of the region where the protective diffusion layer ground region 4 is formed, the on-current path is increased and the channel width density is also increased. As a result, the on-resistance can be reduced.
　なお、本明細書では、活性ストライプセル３０を第１の活性セルと、活性セル３１を第２の活性セルともいう。単一形状の活性セルと保護拡散層接地領域のみで構成しようとすると、半導体装置全体における活性セルの専有比率等を十分に調整することが困難な場合がある。そのため、図１８に示す半導体装置１２２では、ストライプ状の第１の活性セル（３０）と、第１の活性セルとは平面形状の異なる正方形状の第２の活性セル（３１）を設けることで、平面方向のスペースを十分に活用し、オン電流経路として活用できる領域を増加させることができるため、オン抵抗を低減することができる。 In the present specification, the active stripe cell 30 is also referred to as a first active cell, and the active cell 31 is also referred to as a second active cell. If an attempt is made to configure only a single-shaped active cell and a protective diffusion layer ground region, it may be difficult to sufficiently adjust the exclusive ratio of active cells in the entire semiconductor device. Therefore, in the semiconductor device 122 shown in FIG. 18, the stripe-shaped first active cell (30) and the square-shaped second active cell (31) having a different planar shape from the first active cell are provided. Since the space in the planar direction can be fully utilized and the area that can be utilized as the on-current path can be increased, the on-resistance can be reduced.
　さらに、図１８に示す半導体装置１２２では、保護拡散層接地領域４と活性セル３１との境界が、活性ストライプセル３０同士の境界に対して、活性ストライプセル３０の短辺方向におけるピッチの半周期分だけずれるように、保護拡散層接地領域４を設けている。なお、各活性ストライプ領域３には、保護拡散層接地領域４の一部（半分）の領域が含まれることになるが、本明細書でいう「活性ストライプ領域３に保護拡散層接地領域４が含まれる」という構成は、このように活性ストライプ領域３に保護拡散層接地領域４の一部が含まれるものも包含することとする。図１８に示す半導体装置１２２においても、ゲート電極３０４は分断されることなく一体に形成されることになるため、ゲート抵抗の増加を抑制することができる。 Further, in the semiconductor device 122 shown in FIG. 18, the boundary between the protective diffusion layer ground region 4 and the active cell 31 is a half cycle of the pitch in the short side direction of the active stripe cell 30 with respect to the boundary between the active stripe cells 30. The protective diffusion layer grounding region 4 is provided so as to be shifted by the amount. Each active stripe region 3 includes a part (half) of the protective diffusion layer ground region 4. In this specification, the “active stripe region 3 includes the protective diffusion layer ground region 4. The configuration of “included” includes the active stripe region 3 including a part of the protective diffusion layer ground region 4 as described above. Also in the semiconductor device 122 shown in FIG. 18, since the gate electrode 304 is integrally formed without being divided, an increase in gate resistance can be suppressed.
　また、上述したいずれの構成においても、保護拡散層接地領域４は正方形状としたが、これに限定されるものではない。図１９には、図１８に示す半導体装置１２２において保護拡散層接地領域４の平面形状を長方形状とした半導体装置１２３を示す。図１９に示すように、保護拡散層接地領域４を長方形状しても構わない。図１９では、保護拡散層接地領域４を活性ストライプセル３０と同等の形状としており、これに伴い、保護拡散層接地領域４同士の間に設けられる活性セル３１も活性ストライプセル３０と同等の長方形状となる。 In any of the configurations described above, the protective diffusion layer grounding region 4 has a square shape, but is not limited thereto. FIG. 19 shows a semiconductor device 123 in which the planar shape of the protective diffusion layer ground region 4 is rectangular in the semiconductor device 122 shown in FIG. As shown in FIG. 19, the protective diffusion layer grounding region 4 may have a rectangular shape. In FIG. 19, the protective diffusion layer ground region 4 has the same shape as that of the active stripe cell 30, and accordingly, the active cell 31 provided between the protective diffusion layer ground regions 4 also has the same rectangular shape as that of the active stripe cell 30. It becomes a shape.
　さらに、保護拡散層接地領域４や活性ストライプセル３０は四角形状に限定されるものではなく、六角形等の多角形状に構成されることとしてもよい。図２０には、図１８に示す半導体装置１２２において保護拡散層接地領域４、活性ストライプセル３０、および活性セル３１の平面形状を六角形状とした半導体装置１２４を示す。図２０に示すように、保護拡散層接地領域４と活性セル３１を正六角形状して構成し、活性ストライプセル３０は正六角形状をストライプトレンチ３０７に沿って一方向に引き延ばした形状としている。また、図２０に示すように、保護拡散層接地領域４、活性ストライプセル３０、および活性セル３１は、ストライプトレンチ３０７と交差する交差トレンチ３０８によって区切られている。さらに、図２０においてストライプトレンチ３０７に対して鈍角をなす交差トレンチ３０８によって形成されるエピタキシャル層２の側壁の面方位を（１０－１０）面に等価な面で構成する。これにより、オフ角の影響を小さくしゲート耐圧の低下を抑えることができる。 Furthermore, the protective diffusion layer grounding region 4 and the active stripe cell 30 are not limited to a rectangular shape, and may be configured in a polygonal shape such as a hexagon. 20 shows a semiconductor device 124 in which the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 in the semiconductor device 122 shown in FIG. 18 is hexagonal. As shown in FIG. 20, the protective diffusion layer ground region 4 and the active cell 31 are formed in a regular hexagonal shape, and the active stripe cell 30 has a shape in which the regular hexagonal shape is extended in one direction along the stripe trench 307. Further, as shown in FIG. 20, the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 are separated by an intersection trench 308 that intersects with the stripe trench 307. Further, in FIG. 20, the plane orientation of the side wall of the epitaxial layer 2 formed by the intersecting trench 308 having an obtuse angle with respect to the stripe trench 307 is constituted by a plane equivalent to the (10-10) plane. As a result, the influence of the off-angle can be reduced and the reduction in gate breakdown voltage can be suppressed.
　図２０に示す六角形状など、長方形と異なる形状の活性ストライプセル３０を配設する場合、活性ストライプセル３０の長辺と短辺の比は、活性ストライプセル３０の長辺同士の間の距離を短辺として考え、算出することができる。そして、活性ストライプセル３０の形状が変化したとしても、長辺と短辺の比は好ましくは１．５以上、より望ましくは２．０以上とする。 When the active stripe cell 30 having a shape different from the rectangle such as the hexagonal shape shown in FIG. 20 is provided, the ratio of the long side to the short side of the active stripe cell 30 is the distance between the long sides of the active stripe cell 30. It can be considered and calculated as a short side. Even if the shape of the active stripe cell 30 changes, the ratio of the long side to the short side is preferably 1.5 or more, more preferably 2.0 or more.
　図２０に示すように、実施の形態２でも設けていた交差トレンチ３０８はストライプトレンチ３０７に必ずしも直交する必要はなく、保護拡散層接地領域４、活性ストライプセル３０、および活性セル３１の平面形状に応じて、設けることとすればよい。 As shown in FIG. 20, the cross trench 308 provided in the second embodiment is not necessarily orthogonal to the stripe trench 307, and the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 is the same. Accordingly, it may be provided.
　本実施の形態では、活性ストライプ領域３のそれぞれに保護拡散層接地領域４を設けることとしたので、一部の保護拡散層３０６がフローティングとなることを抑制し、スイッチング特性の悪化等を抑制することができる。 In the present embodiment, since the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is possible to suppress a part of the protective diffusion layer 306 from floating and to suppress deterioration of switching characteristics and the like. be able to.
　実施の形態４．
　図２３は、本発明の実施の形態４にかかる半導体装置１３０を示す平面図である。以下、本実施の形態では、実施の形態１と相違する部分について説明し、同一または対応する部分についての説明は省略する。図２３において、図１と同一の符号を付けたものは、同一または対応する構成を示している。本実施の形態では、活性セルの平面視における頂点部分が曲率を有する点で実施の形態１と相違している。なお、本明細書においては、第１の活性セル（活性ストライプセル３０）と第２の活性セル（活性セル３１）を総称して活性セルともいう。 Embodiment 4 FIG.
FIG. 23 is a plan view showing a semiconductor device 130 according to the fourth embodiment of the present invention. Hereinafter, in the present embodiment, parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted. 23, the same reference numerals as those in FIG. 1 denote the same or corresponding configurations. The present embodiment is different from the first embodiment in that the apex portion of the active cell in plan view has a curvature. In the present specification, the first active cell (active stripe cell 30) and the second active cell (active cell 31) are collectively referred to as an active cell.
　実施の形態１に示す半導体装置１００では、図１に示すように、活性ストライプセル３０の頂点部分を、トレンチが二方向から取り囲んでいる。例えば、活性ストライプセル３０の右上の領域では紙面右側と紙面上側の二つの方向にトレンチが設けられている。トレンチ内にはゲート電極３０４が設けられているため、頂点部分のチャネル領域にはゲート電界が二重に印加される。この結果、活性ストライプセル３０の頂点部分は、側壁部分に比べてより低いゲート電圧でオン状態に遷移する。言い換えると、頂点部分のしきい値電圧は側壁部分に比べて低くなる。頂点部分のしきい値電圧の低下は、ＭＯＳＦＥＴ全体のしきい値電圧低下やスイッチング損失増加といった現象を招くため好ましくない。 In the semiconductor device 100 shown in the first embodiment, as shown in FIG. 1, the trench surrounds the apex portion of the active stripe cell 30 from two directions. For example, in the upper right region of the active stripe cell 30, trenches are provided in two directions on the right side and the upper side of the page. Since the gate electrode 304 is provided in the trench, a double gate electric field is applied to the channel region at the apex. As a result, the apex portion of the active stripe cell 30 transitions to the on state with a lower gate voltage than the side wall portion. In other words, the threshold voltage of the apex portion is lower than that of the side wall portion. Lowering the threshold voltage at the apex is not preferable because it causes phenomena such as lowering the threshold voltage of the entire MOSFET and increasing switching loss.
　これに対し本実施の形態の半導体装置１３０は、図２３に示すように、活性ストライプセル３０の頂点部分にあたるトレンチおよびゲート電極３０４を円弧状に形成し、活性ストライプセル３０の概形を、頂点部分が曲率を有する角丸長方形形状としたことにより、頂点部分のチャネル領域へのゲート電界の集中を緩和し、印加されるゲート電界を弱めることができる。これにより、頂点部分におけるしきい値電圧の低下を抑制することができる。このとき、頂点部分が備える曲率半径は、活性ストライプセル３０の短辺側の長さＬｍの１０％以上５０％以下とすることが望ましい。これは、曲率が小さい場合には十分な二重ゲート電界低減効果が得られず、曲率が大きい場合には活性ストライプセル３０の先端が尖り、この部分にゲート電界が二重に印加されるためである。 In contrast, in the semiconductor device 130 of the present embodiment, as shown in FIG. 23, trenches and gate electrodes 304 corresponding to the apex portions of the active stripe cells 30 are formed in an arc shape, and the outline of the active stripe cells 30 is expressed as apexes. By adopting a rounded rectangular shape with a curved portion, the concentration of the gate electric field in the channel region at the apex portion can be relaxed and the applied gate electric field can be weakened. Thereby, the fall of the threshold voltage in a vertex part can be suppressed. At this time, the radius of curvature of the apex portion is desirably 10% or more and 50% or less of the length Lm on the short side of the active stripe cell 30. This is because when the curvature is small, a sufficient double gate electric field reduction effect cannot be obtained, and when the curvature is large, the tip of the active stripe cell 30 is sharp, and the gate electric field is applied to this portion twice. It is.
　本実施の形態は、実施の形態１のみでなく実施の形態２および３と併用することができる。実施の形態２と併用した例を図２４に示す。この場合には交差トレンチ３０８の両側についても同様に曲率を有する形状に変更する必要がある。実施の形態３と併用した場合には、活性ストライプセル３０だけでなく活性セル３１についても頂点部分に曲率を設けてよい。また、角丸長方形に限らず、角丸多角形であればよい。 This embodiment can be used in combination with Embodiments 2 and 3 as well as Embodiment 1. An example in combination with Embodiment Mode 2 is shown in FIG. In this case, it is necessary to change the shape of the both sides of the intersection trench 308 to have a similar curvature. When combined with the third embodiment, not only the active stripe cell 30 but also the active cell 31 may be provided with a curvature at the apex portion. Moreover, not only a rounded rectangle but a rounded polygon may be used.
　本実施の形態では、活性セルの平面視における頂点部分が曲率を有することとしたので、頂点部分にかかるゲート電界を低減し、頂点部分が側壁部分に比べてしきい値が小さくなる現象を低減することができる。 In this embodiment, since the apex portion of the active cell in plan view has a curvature, the gate electric field applied to the apex portion is reduced, and the phenomenon that the apex portion becomes smaller in threshold than the side wall portion is reduced. can do.
　実施の形態５．
　図２５は、本発明の実施の形態５にかかる半導体装置１４０を示す平面図である。以下、本実施の形態では、実施の形態１と相違する部分について説明し、同一または対応する部分についての説明は省略する。図２５において、図１と同一の符号を付けたものは、同一または対応する構成を示している。本実施の形態では、ストライプトレンチ３０７の一部がダミートレンチ３０９に置き換えられている点で実施の形態１と相違している。 Embodiment 5 FIG.
FIG. 25 is a plan view showing a semiconductor device 140 according to the fifth embodiment of the present invention. Hereinafter, in the present embodiment, parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted. 25, the same reference numerals as those in FIG. 1 denote the same or corresponding configurations. The present embodiment is different from the first embodiment in that a part of the stripe trench 307 is replaced with a dummy trench 309.
　実施の形態１に示す半導体装置１００では、ストライプトレンチ３０７に埋め込まれた全てのゲート電極３０４が相互に接続されており、ゲート電極３０４とゲート絶縁膜３０５を介して隣接する全てのチャネル領域が動作する。これはオン抵抗を小さくするという点で有利である。しかしながら、ＭＯＳＦＥＴを駆動する周波数が増加していくと、オン抵抗に伴う静的な損失よりもスイッチングに伴う動的な損失のほうが大きくなる。この場合は多少オン抵抗を犠牲にしてでもスイッチング損失を低減するほうが有利である。 In the semiconductor device 100 described in Embodiment 1, all the gate electrodes 304 embedded in the stripe trench 307 are connected to each other, and all the adjacent channel regions operate through the gate electrode 304 and the gate insulating film 305. To do. This is advantageous in that the on-resistance is reduced. However, as the frequency for driving the MOSFET increases, the dynamic loss associated with switching becomes larger than the static loss associated with on-resistance. In this case, it is advantageous to reduce the switching loss even at the expense of some on-resistance.
　これに対し本実施の形態の半導体装置１４０は、一部のストライプトレンチ３０７をダミートレンチ３０９に置き換えている。ダミートレンチ３０９は他のストライプトレンチ３０７から離隔されており、また、ダミートレンチ３０９内にゲート絶縁膜を介して形成されたゲート電極（第２ゲート電極）は、他のストライプトレンチ３０７内のゲート電極３０４と接続されず、当該第２ゲート電極に隣接したチャネル領域は動作しない。これにより、オン抵抗は増加するものの、ゲート－ソース間、ゲート－ドレイン間の寄生容量を減らすことができる。ＭＯＳＦＥＴの寄生容量とスイッチング損失には正の相関があるため、ダミートレンチ３０９を用いることでスイッチング損失を低減することができる。このとき、ダミートレンチ３０９はその深さがストライプトレンチ３０７と同じであることが望ましい。これは深さが同じであれば、トレンチ形成時のマスクパターンを変更することによってストライプトレンチ３０７とダミートレンチ３０９とを同時に形成することができるためである。 On the other hand, in the semiconductor device 140 of this embodiment, some stripe trenches 307 are replaced with dummy trenches 309. The dummy trench 309 is separated from the other stripe trenches 307, and the gate electrode (second gate electrode) formed in the dummy trench 309 via the gate insulating film is a gate electrode in the other stripe trench 307. The channel region that is not connected to 304 and adjacent to the second gate electrode does not operate. Thereby, although the on-resistance increases, the parasitic capacitance between the gate and the source and between the gate and the drain can be reduced. Since there is a positive correlation between the parasitic capacitance of the MOSFET and the switching loss, the switching loss can be reduced by using the dummy trench 309. At this time, it is desirable that the dummy trench 309 has the same depth as the stripe trench 307. This is because if the depth is the same, the stripe trench 307 and the dummy trench 309 can be formed simultaneously by changing the mask pattern when forming the trench.
　ダミートレンチ３０９内に形成された第２ゲート電極は一切動作せず、第２ゲート電極に隣接したチャネル領域も動作しない。そうすると、しきい値電圧が小さい場合でも第２ゲート電極に負電圧を与えてチャネル領域の電荷を制御することができないため、オフ時に高電圧が印加された際、しきい値電圧を超えてドレイン－ソース間のリーク電流が増加することが懸念される。これに対しては、ダミートレンチ３０９に隣接した領域のみソース領域３０２を形成しないといった方法を取ることができる。また、しきい値電圧が十分に高い場合にはゲート電極３０４に負電圧を与える必要が無いため、ダミートレンチ３０９に隣接した領域のみソース領域３０２を形成しないといった方法は必ずしも必要ではない。 The second gate electrode formed in the dummy trench 309 does not operate at all, and the channel region adjacent to the second gate electrode also does not operate. As a result, even when the threshold voltage is small, it is impossible to control the charge in the channel region by applying a negative voltage to the second gate electrode. -There is a concern that the leakage current between the sources will increase. For this, a method in which the source region 302 is not formed only in the region adjacent to the dummy trench 309 can be employed. In addition, when the threshold voltage is sufficiently high, it is not necessary to apply a negative voltage to the gate electrode 304. Therefore, a method of not forming the source region 302 only in the region adjacent to the dummy trench 309 is not necessarily required.
　特にＭＯＳＦＥＴを高速に駆動する場合、ストライプトレンチ３０７底部に形成された保護拡散層３０６からドリフト層２へと延びる空乏層の応答速度を向上させる必要がある。ストライプトレンチ３０７とダミートレンチ３０９とを設けた場合、それぞれの底部の保護拡散層３０６は分離されるため、ダミートレンチ３０９に設けられた保護拡散層３０６の応答速度がストライプトレンチ３０７のそれと同じになるよう、ダミートレンチ３０９もまた、保護拡散層接地領域４に接続されていることが望ましい。保護拡散層接地領域４を設けない場合、ストライプトレンチ３０７の保護拡散層３０６とダミートレンチ３０９の保護拡散層３０６が接続されるよう、配慮する必要がある。例えばストライプトレンチ３０７とダミートレンチ３０９とを隔てる部分を、保護拡散層３０６を形成するドーパントの拡散長よりも狭くすることや、トレンチの側壁にｐ型領域を形成して両者を接続するといった方法が挙げられる。 Particularly when driving the MOSFET at high speed, it is necessary to improve the response speed of the depletion layer extending from the protective diffusion layer 306 formed at the bottom of the stripe trench 307 to the drift layer 2. When the stripe trench 307 and the dummy trench 309 are provided, the protective diffusion layer 306 at the bottom of each is separated, so that the response speed of the protective diffusion layer 306 provided in the dummy trench 309 is the same as that of the stripe trench 307. As described above, the dummy trench 309 is also preferably connected to the protective diffusion layer ground region 4. When the protective diffusion layer ground region 4 is not provided, it is necessary to consider that the protective diffusion layer 306 of the stripe trench 307 and the protective diffusion layer 306 of the dummy trench 309 are connected. For example, there is a method in which a portion separating the stripe trench 307 and the dummy trench 309 is made narrower than the diffusion length of the dopant forming the protective diffusion layer 306, or a p-type region is formed on the side wall of the trench to connect them. Can be mentioned.
　本実施の形態ではストライプトレンチ３０７の一部をダミートレンチ３０９としたので、ＭＯＳＦＥＴの寄生容量を低減し、スイッチング損失を改善することができる。 In this embodiment, since a part of the stripe trench 307 is the dummy trench 309, the parasitic capacitance of the MOSFET can be reduced and the switching loss can be improved.
　上述した実施の形態１ないし５の説明では、ドリフト層２とＳｉＣ基板１（バッファ層）とが同じ導電型を有する構造のＭＯＳＦＥＴについて述べたが、ドリフト層２と基板１とが異なる導電型を有する構造のＩＧＢＴにも本発明は適用可能である。例えば、図２に示した半導体装置１００に対し、ＳｉＣ基板１をｐ型の基板にすればＩＧＢＴの構成となる。その場合、ＭＯＳＦＥＴのソース領域３０２およびソース電極５は、それぞれＩＧＢＴのエミッタ領域およびエミッタ電極に対応し、ＭＯＳＦＥＴのドレイン電極７はＩＧＢＴのコレクタ電極に対応することになる。本明細書におけるソース領域やソース電極にはエミッタ領域やエミッタ電極も含まれるし、ドレイン電極にはコレクタ電極も含まれることとする。なお、ＩＧＢＴを構成する場合、基板となるｎ型のＳｉＣ基板を削除してエピタキシャル層２にイオン注入により形成したｐ型領域をｐ型の基板としてもよい。 In the description of the first to fifth embodiments described above, the MOSFET having a structure in which the drift layer 2 and the SiC substrate 1 (buffer layer) have the same conductivity type has been described. However, the drift layer 2 and the substrate 1 have different conductivity types. The present invention is also applicable to an IGBT having a structure. For example, if the SiC substrate 1 is a p-type substrate with respect to the semiconductor device 100 shown in FIG. 2, an IGBT configuration is obtained. In that case, the source region 302 and source electrode 5 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively, and the drain electrode 7 of the MOSFET corresponds to the collector electrode of the IGBT. The source region and the source electrode in this specification include an emitter region and an emitter electrode, and the drain electrode includes a collector electrode. When configuring an IGBT, the n-type SiC substrate serving as the substrate may be deleted, and a p-type region formed by ion implantation in the epitaxial layer 2 may be used as the p-type substrate.
　また、実施の形態１ないし５では、ワイドバンドギャップ半導体の１つであるＳｉＣを用いて形成した半導体装置について説明したが、例えば窒化ガリウム（ＧａＮ）系材料、ダイヤモンドなど、他のワイドバンドギャップ半導体を用いた半導体装置やシリコン半導体を用いた半導体装置に対しても適用可能である。さらに、上述した実施の形態ではｎ型の絶縁ゲート型半導体装置を例としたが、ｐ型の絶縁ゲート型半導体装置に適用しても構わない。なお、本明細書において、ワイドバンドギャップ半導体とは、少なくともシリコン半導体よりもバンドギャップの広い半導体とする。 In the first to fifth embodiments, the semiconductor device formed using SiC, which is one of the wide band gap semiconductors, has been described. However, other wide band gap semiconductors such as gallium nitride (GaN) -based materials and diamond are used. The present invention can also be applied to a semiconductor device using silicon and a semiconductor device using a silicon semiconductor. Furthermore, although the n-type insulated gate semiconductor device has been described as an example in the above-described embodiment, the present invention may be applied to a p-type insulated gate semiconductor device. Note that in this specification, a wide band gap semiconductor is a semiconductor having a wider band gap than at least a silicon semiconductor.
　実施の形態６．
　本実施の形態は、上述した実施の形態１から３にかかる半導体装置を電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態６として、三相のインバータに本発明を適用した場合について説明する。 Embodiment 6 FIG.
In the present embodiment, the semiconductor device according to the first to third embodiments described above is applied to a power conversion device. Although the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a sixth embodiment.
　図２６は、本実施の形態にかかる電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 26 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
　図２６に示す電力変換システムは、電源１０００、電力変換装置２０００、負荷３０００から構成される。電源１０００は、直流電源であり、電力変換装置２０００に直流電力を供給する。電源１０００は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成することとしてもよい。また、電源１０００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成されることとしてもよい。 The power conversion system shown in FIG. 26 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power converter 2000. The power source 1000 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good. Further, the power supply 1000 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
　電力変換装置２０００は、電源１０００と負荷３０００の間に接続された三相のインバータであり、電源１０００から供給された電力を交流電力に変換し、負荷３０００に交流電力を供給する。電力変換装置２０００は、図２６に示すように、直流電力を交流電力に変換して出力する主変換回路２００１と、主変換回路２００１の各スイッチング素子を駆動する駆動信号を出力する駆動回路２００２と、主変換回路２００１を制御する制御信号を駆動回路２００２に出力する制御回路２００３とを備えている。 The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, converts the power supplied from the power source 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 26, the power conversion device 2000 converts a DC power into an AC power and outputs the main conversion circuit 2001, and a drive circuit 2002 that outputs a drive signal that drives each switching element of the main conversion circuit 2001. And a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the drive circuit 2002.
　負荷３０００は、電力変換装置２０００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３０００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。 The load 3000 is a three-phase motor driven by AC power supplied from the power converter 2000. Note that the load 3000 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 3000 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
　以下、電力変換装置２０００の詳細を説明する。主変換回路２００１は、スイッチング素子と還流ダイオードを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１０００から供給される直流電力を交流電力に変換し、負荷３０００に供給する。主変換回路２００１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２００１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードから構成することができる。主変換回路２００１の各スイッチング素子には、上述した実施の形態１から３のいずれかにかかる半導体装置を適用する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２００１の３つの出力端子は、負荷３０００に接続される。 Hereinafter, details of the power conversion device 2000 will be described. The main conversion circuit 2001 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 2001 converts DC power supplied from the power source 1000 into AC power and supplies the AC power to the load 3000. Although there are various specific circuit configurations of the main conversion circuit 2001, the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes. The semiconductor device according to any of the first to third embodiments described above is applied to each switching element of the main conversion circuit 2001. The six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
　駆動回路２００２は、主変換回路２００１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２００１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２００３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 The drive circuit 2002 generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies it to the control electrode of the switching element of the main conversion circuit 2001. Specifically, in accordance with a control signal from a control circuit 2003 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When the switching element is kept off, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
　制御回路２００３は、負荷３０００に所望の電力を供給されるよう主変換回路２００１のスイッチング素子を制御する。具体的には、負荷３０００に供給すべき電力に基づいて主変換回路２００１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２００１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、駆動回路２００２に制御指令（制御信号）を出力する。駆動回路２００２は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 2003 controls the switching element of the main conversion circuit 2001 so that desired power is supplied to the load 3000. Specifically, based on the power to be supplied to the load 3000, the time (ON time) during which each switching element of the main converter circuit 2001 is to be turned on is calculated. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 2002 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. In accordance with this control signal, the drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.
　本実施の形態に係る電力変換装置は、主変換回路２００１のスイッチング素子に実施の形態１から３のいずれかにかかる半導体装置を適用するため、スイッチング素子の道通損失を低減しつつ、高速スイッチングによる高周波化やスイッチング損失の低減を実現することができ、高効率な電力変換装置を提供することができる。 In the power conversion device according to the present embodiment, since the semiconductor device according to any one of the first to third embodiments is applied to the switching element of the main conversion circuit 2001, the switching loss of the switching element is reduced and high-speed switching is performed. High frequency and reduction of switching loss can be realized, and a highly efficient power conversion device can be provided.
　本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、本発明は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本発明を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに本発明を適用することも可能である。 In this embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power converter is used. However, a three-level or multi-level power converter may be used. When power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply. In addition, when power is supplied to a direct current load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.
　また、本発明を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触器給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。 In addition, the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor. For example, the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
　なお、本発明は、発明の範囲内において、各実施の形態やその変形例を自由に組み合わせることや、各実施の形態を適宜、変形、省略することが可能である。例えば、実施の形態１の変形例として図１１に示した単一のコンタクトホール３０１内において複数のベース領域３０３が露出する構成は、実施の形態２から５のいずれの構成においても適用することが可能であるし、各実施の形態における変形例は他の実施の形態においても適宜適用することが可能である。 It should be noted that the present invention can be freely combined with each embodiment and its modifications within the scope of the invention, and each embodiment can be appropriately modified and omitted. For example, a configuration in which a plurality of base regions 303 are exposed in a single contact hole 301 shown in FIG. 11 as a modification of the first embodiment can be applied to any configuration of the second to fifth embodiments. It is possible, and the modification in each embodiment can be applied as appropriate to other embodiments.
　１　ＳｉＣ基板、２　エピタキシャル層（半導体層）、３　活性ストライプ領域、３０　活性ストライプセル、３１　活性セル、３０１　コンタクトホール、３０１ａ　オーミック電極、３０２　ソース領域、３０３　ベース領域、３０４　ゲート電極、３０５　ゲート絶縁膜、３０６　保護拡散層、３０７　ストライプトレンチ、３０８　交差トレンチ、３０９　ダミートレンチ、４　保護拡散層接地領域、４０１　コンタクトホール、４０１ａ　オーミック電極、４０２　開口部、５　ソース電極、６　層間絶縁膜、７　ドレイン電極、８　シリコン酸化膜、９　エッチングマスク、１０　注入マスク、１００　半導体装置。 1 SiC substrate, 2 epitaxial layer (semiconductor layer), 3 active stripe region, 30 active stripe cell, 31 active cell, 301 contact hole, 301a ohmic electrode, 302 source region, 303 base region, 304 gate electrode, 305 gate insulating film , 306 protective diffusion layer, 307 stripe trench, 308 cross trench, 309 dummy trench, 4 protective diffusion layer ground region, 401 contact hole, 401a ohmic electrode, 402 opening, 5 source electrode, 6 interlayer insulating film, 7 drain electrode, 8 silicon oxide film, 9 etching mask, 10 implantation mask, 100 semiconductor device.

Claims (20)

  1. 　第１導電型の半導体層と、
    　前記半導体層の上部に設けられた第２導電型のベース領域と、
    　前記ベース領域の上部に設けられたソース領域と、
    　前記半導体層において前記ベース領域よりも深い位置にまで達しストライプ状に複数並んで形成されたストライプトレンチ内に設けられたゲート絶縁膜と、
    　前記ストライプトレンチ内に設けられ、前記ゲート絶縁膜を介して前記ベース領域と対向する側面を有するゲート電極と、
    　前記ストライプトレンチの下部に設けられた第２導電型の保護拡散層と、
    　前記ソース領域と前記ベース領域に接続するソース電極と、
    　を備え、
    　複数の前記ストライプトレンチによって区切られた複数の活性ストライプ領域と、
    　隣り合う前記ストライプトレンチの間において前記半導体層に設けられた開口部を通じて、前記ソース電極が前記保護拡散層に接続する保護拡散層接地領域と、
    　を有し、
    　複数の前記ストライプトレンチによって区切られた複数の活性ストライプ領域のそれぞれに前記保護拡散層接地領域が含まれる、
    　半導体装置。     A first conductivity type semiconductor layer;
    A base region of a second conductivity type provided on the semiconductor layer;
    A source region provided on top of the base region;
    A gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the base region in the semiconductor layer;
    A gate electrode provided in the stripe trench and having a side surface facing the base region via the gate insulating film;
    A second conductive type protective diffusion layer provided under the stripe trench;
    A source electrode connected to the source region and the base region;
    With
    A plurality of active stripe regions separated by a plurality of said stripe trenches;
    A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between the adjacent stripe trenches;
    Have
    The protective diffusion layer grounding region is included in each of a plurality of active stripe regions partitioned by a plurality of the stripe trenches,
    Semiconductor device.
  2. 　第１導電型の半導体層と、
    　前記半導体層の上部に設けられた第２導電型のベース領域と、
    　前記ベース領域の上部に設けられたソース領域と、
    　前記半導体層において前記ベース領域よりも深い位置にまで達しストライプ状に複数並んで形成されたストライプトレンチ内に設けられたゲート絶縁膜と、
    　前記ストライプトレンチ内に設けられ、前記ゲート絶縁膜を介して前記ベース領域と対向する側面を有するゲート電極と、
    　前記ストライプトレンチの下部に設けられた第２導電型の保護拡散層と、
    　前記ソース領域と前記ベース領域に接続するソース電極と、
    　を備え、
    　複数の前記ストライプトレンチによって区切られた複数の活性ストライプ領域と、
    　隣り合う前記ストライプトレンチの間において前記半導体層に設けられた開口部を通じて、前記ソース電極が前記保護拡散層に接続する保護拡散層接地領域と、
    　を有し、
    　前記複数の活性ストライプ領域には、前記保護拡散層接地領域を含む複数の第１の活性ストライプ領域と前記保護拡散層接地領域を含まず前記第１の活性ストライプ領域に挟まれて設けられた第２の活性ストライプ領域とが存在する、
    　半導体装置。     A first conductivity type semiconductor layer;
    A base region of a second conductivity type provided on the semiconductor layer;
    A source region provided on top of the base region;
    A gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the base region in the semiconductor layer;
    A gate electrode provided in the stripe trench and having a side surface facing the base region via the gate insulating film;
    A second conductive type protective diffusion layer provided under the stripe trench;
    A source electrode connected to the source region and the base region;
    With
    A plurality of active stripe regions separated by a plurality of said stripe trenches;
    A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between the adjacent stripe trenches;
    Have
    The plurality of active stripe regions include a plurality of first active stripe regions including the protective diffusion layer ground region and a first active stripe region sandwiched between the first active stripe regions without including the protective diffusion layer ground region. There are two active stripe regions,
    Semiconductor device.
  3. 　第１導電型の半導体層と、
    　前記半導体層の上部に設けられた第２導電型のベース領域と、
    　前記ベース領域の上部に設けられたソース領域と、
    　前記半導体層において前記ベース領域よりも深い位置にまで達しストライプ状に複数並んで形成されたストライプトレンチ内に設けられたゲート絶縁膜と、
    　前記ストライプトレンチ内に設けられ、前記ゲート絶縁膜を介して前記ベース領域と対向する側面を有するゲート電極と、
    　前記ストライプトレンチの下部に設けられた第２導電型の保護拡散層と、
    　前記ソース領域と前記ベース領域に接続するソース電極と、
    　を備え、
    　複数の前記ストライプトレンチによって区切られた複数の活性ストライプ領域と、
    　隣り合う前記ストライプトレンチの間において前記半導体層に設けられた開口部を通じて、前記ソース電極が前記保護拡散層に接続する保護拡散層接地領域と、
    　を有し、
    　前記保護拡散層は前記ストライプトレンチと交差する交差トレンチの下部にも設けられ、
    　複数の前記ストライプトレンチの少なくともいずれか一つの下部に設けられた前記保護拡散層は、前記交差トレンチ下部に設けられた前記保護拡散層を介して、前記保護拡散層接地領域内の前記ソース電極に接続する、
    　半導体装置。     A first conductivity type semiconductor layer;
    A base region of a second conductivity type provided on the semiconductor layer;
    A source region provided on top of the base region;
    A gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the base region in the semiconductor layer;
    A gate electrode provided in the stripe trench and having a side surface facing the base region via the gate insulating film;
    A second conductive type protective diffusion layer provided under the stripe trench;
    A source electrode connected to the source region and the base region;
    With
    A plurality of active stripe regions separated by a plurality of said stripe trenches;
    A protective diffusion layer ground region in which the source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between the adjacent stripe trenches;
    Have
    The protective diffusion layer is also provided in a lower portion of an intersection trench that intersects the stripe trench,
    The protective diffusion layer provided under at least one of the plurality of stripe trenches is connected to the source electrode in the protective diffusion layer ground region via the protective diffusion layer provided under the intersection trench. Connecting,
    Semiconductor device.
  4. 　前記保護拡散層接地領域は複数設けられ、
    　前記ストライプトレンチの長手方向に沿って、複数の前記保護拡散層接地領域は一定間隔で設けられる、
    　ことを特徴とする請求項１から３のいずれか１項に記載の半導体装置。     A plurality of the protective diffusion layer grounding regions are provided,
    A plurality of the protective diffusion layer ground regions are provided at regular intervals along the longitudinal direction of the stripe trench.
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  5. 　前記保護拡散層接地領域は複数設けられ、
    　前記ストライプトレンチの長手方向に垂直な方向に沿って、複数の前記保護拡散層接地領域は一定間隔で設けられる
    　ことを特徴とする請求項１から４のいずれか１項に記載の半導体装置。     A plurality of the protective diffusion layer grounding regions are provided,
    5. The semiconductor device according to claim 1, wherein a plurality of the protective diffusion layer ground regions are provided at regular intervals along a direction perpendicular to a longitudinal direction of the stripe trench.
  6. 　前記保護拡散層接地領域において前記開口部は前記隣り合うストライプトレンチの間全体に形成され、
    　前記開口部内において、前記ゲート電極と前記ソース電極とは絶縁されて設けられる、　ことを特徴とする請求項１から５のいずれか１項に記載の半導体装置。     In the protective diffusion layer ground region, the opening is formed entirely between the adjacent stripe trenches,
    6. The semiconductor device according to claim 1, wherein the gate electrode and the source electrode are insulated from each other in the opening.
  7. 　前記開口部において前記ゲート電極と前記ソース電極との間に設けられ、前記ゲート絶縁膜よりも厚さの厚い層間絶縁膜を備える、
    　ことを特徴とする請求項６記載の半導体装置。     An interlayer insulating film provided between the gate electrode and the source electrode in the opening and having a thickness greater than the gate insulating film;
    The semiconductor device according to claim 6.
  8. 　前記保護拡散層は、前記保護拡散層接地領域の前記開口部の下部にも設けられ、
    　前記ソース電極は、前記開口部の下部に設けられた前記保護拡散層と接続する、
    　ことを特徴とする請求項１から７のいずれか１項に記載の半導体装置。     The protective diffusion layer is also provided below the opening of the protective diffusion layer ground region,
    The source electrode is connected to the protective diffusion layer provided under the opening;
    The semiconductor device according to claim 1, wherein:
  9. 　コンタクトホールを有するとともに、前記ゲート電極を覆い、前記ゲート電極と前記ソース電極とを絶縁する層間絶縁膜を備え、
    　前記ソース電極は前記コンタクトホールを通じて前記ソース領域と前記ベース領域に接続し、
    　前記コンタクトホール内に露出する前記半導体層表面において、複数の前記ベース領域が離間して露出している、
    　ことを特徴とする請求項１から８のいずれか１項に記載の半導体装置。     An interlayer insulating film that has a contact hole, covers the gate electrode, and insulates the gate electrode and the source electrode;
    The source electrode is connected to the source region and the base region through the contact hole;
    In the surface of the semiconductor layer exposed in the contact hole, a plurality of the base regions are exposed separately.
    9. The semiconductor device according to claim 1, wherein:
  10. 　複数の前記ストライプトレンチのうち一部は、他の前記ストライプトレンチから離隔されたダミートレンチであり、
    　前記ダミートレンチ内に形成された前記ゲート電極は、他の前記ストライプトレンチ内に形成された前記ゲート電極と接続されていない、
    　ことを特徴とする請求項１から９のいずれか１項に記載の半導体装置。     Some of the plurality of stripe trenches are dummy trenches separated from other stripe trenches,
    The gate electrode formed in the dummy trench is not connected to the gate electrode formed in another stripe trench;
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  11. 　前記活性ストライプ領域には、前記ゲート電極で区切られた活性セルが含まれる、
    　ことを特徴とする請求項１から１０のいずれか１項に記載の半導体装置。     The active stripe region includes active cells separated by the gate electrode.
    The semiconductor device according to claim 1, wherein:
  12. 　前記活性セルは、ストライプ状の第１の活性セルを含み、
    　平面視において、前記第１の活性セルの長辺の長さは、前記第１の活性セルの短辺の長さの１．５倍以上である、
    　ことを特徴とする請求項１１に記載の半導体装置。     The active cell includes a stripe-shaped first active cell,
    In plan view, the length of the long side of the first active cell is 1.5 times or more the length of the short side of the first active cell.
    The semiconductor device according to claim 11.
  13. 　前記活性セルは、ストライプ状の第１の活性セルと、前記第１の活性セルと平面視における形状が異なり前記第１の活性セルよりも長辺の長さが小さい第２の活性セルを含む、
    　ことを特徴とする請求項１１に記載の半導体装置。     The active cell includes a stripe-shaped first active cell and a second active cell having a shape different from that of the first active cell in plan view and having a longer side length smaller than that of the first active cell. ,
    The semiconductor device according to claim 11.
  14. 　前記活性セルの平面視における頂点部分が曲率を有する、
    　ことを特徴とする請求項１１から１３のいずれか１項に記載の半導体装置。     A vertex portion in plan view of the active cell has a curvature;
    The semiconductor device according to claim 11, wherein:
  15. 　前記頂点部分の有する曲率半径が、前記活性セルの長手方向に垂直な方向の長さの１０％以上５０％以下である、
    　ことを特徴とする請求項１４に記載の半導体装置。     The radius of curvature of the apex portion is 10% or more and 50% or less of the length in the direction perpendicular to the longitudinal direction of the active cell.
    The semiconductor device according to claim 14.
  16. 　前記活性ストライプ領域の短辺方向における前記保護拡散層接地領域の幅は、前記活性ストライプ領域の短辺の整数倍である、
    　ことを特徴とする請求項１から１５のいずれか１項に記載の半導体装置。     The width of the protective diffusion layer ground region in the short side direction of the active stripe region is an integral multiple of the short side of the active stripe region,
    The semiconductor device according to claim 1, wherein:
  17. 　前記ベース領域の下方において、第１導電型の不純物濃度が前記半導体層よりも高い空乏化抑制層を備える、
    　ことを特徴とする請求項１から１６のいずれか１項に記載の半導体装置。     A depletion suppression layer having a first conductivity type impurity concentration higher than that of the semiconductor layer is provided below the base region.
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  18. 　前記半導体装置はオフ角を有し、
    　前記ストライプトレンチの長手方向と、前記オフ角によって形成されるステップフローの方向が一致する、
    　ことを特徴とする請求項１から１７のいずれか１項に記載の半導体装置。     The semiconductor device has an off angle;
    The longitudinal direction of the stripe trenches coincides with the direction of the step flow formed by the off-angle,
    The semiconductor device according to claim 1, wherein:
  19. 　前記半導体層は、ワイドバンドギャップ半導体である、
    　ことを特徴とする請求項１から１８のいずれか１項に記載の半導体装置。     The semiconductor layer is a wide band gap semiconductor.
    The semiconductor device according to claim 1, wherein:
  20. 　請求項１から１９のいずれか１項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
    　前記半導体装置を駆動する駆動信号を前記半導体装置に出力する駆動回路と、
    　前記主変換回路を制御する制御信号を前記駆動回路に出力する制御回路と、
    　を備えた電力変換装置。     A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 19 for converting and outputting input power;
    A drive circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device;
    A control circuit that outputs a control signal for controlling the main conversion circuit to the drive circuit;
    The power converter provided with.
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