JP2005328014A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve crystal defects or the profile of the inner wall of a trench, when a trench type semiconductor element is formed using silicon carbide. <P>SOLUTION: After a trench 6 having aspect ratio of 2 or larger and trench inclination angle of 80° or larger is formed by dry etching in a substrate 20 of silicon carbide (0001)Si plane, damage area on the inner surface of the trench at dry etching is removed, by etching in reduced pressure hydrogen atmosphere at 1,600°C or higher. Damaged region can be removed in a short time, because of the characteristics of high temperature hydrogen. Since surface irregularities and a deterioration layer are not left in the trench after damages have been removed, the level derived from the deterioration layer can be made so as not to exist, and surface irregularities can be reduced to a very low level. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a trench is formed in a silicon carbide semiconductor substrate and an epitaxial layer is embedded therein.

  Conventionally, Non-Patent Document 1 describes a technique for embedding a silicon carbide semiconductor. In this non-patent document 1, epitaxial growth is performed at a growth temperature of 1480 and 1620 ° C. and a C / Si ratio of 1.2 and 4.0, using samples having various trench widths with a trench inclination angle of about 50 degrees and an aspect ratio of 1 or less. The experiment which performed is performed.

  FIGS. 7A and 7B show an example of the growth shape of the epitaxial layer. As can be seen from FIGS. 7A and 7B, according to Non-Patent Document 1, the growth shape of the epitaxial layer strongly depends on the C / Si ratio rather than the growth temperature, and the C / Si ratio is low. In some cases, the surface reaction rate is limited, and facet surface growth in which a plurality of facet surfaces appear, and when the C / Si ratio is high, the gas phase diffusion rate is determined.

  Further, as a conventional technique for filling the trench with an epitaxial film, many techniques related to silicon semiconductors are disclosed. For example, in Patent Document 1, surface roughness and crystal defects on the inner surface (side surface and bottom surface) of the trench generated in the trench etching process are smoothed by performing heat treatment in a non-oxidizing atmosphere, and the crystallinity of the buried layer is increased. It has been shown to improve.

Further, Patent Document 2 describes the effect of rounding the corners of the bottom of the trench, and it is shown that the stress at the bottom of the trench can be relaxed and the growth rate at the bottom of the trench can be prevented from decreasing. In this technique, if the viewpoint of the description fact is changed, the stress increases if the region where the growth of the specific surface (for example, the bottom surface and the side surface) merges with each other is small, but rounds the corner (makes the specific surface not appear). Therefore, it can be seen that the area where the merging is enlarged is intended to relieve stress. That is, it can be said that shaping the bottom corner of the trench to be round is a necessary condition for relaxing the crystal stress during growth and forming a buried layer with good crystallinity.
Japanese Patent No. 3424667 JP 2003-218038 A 1998, Materials Science Forum Vols. 264-268, P. 131-134.

  However, in the case of forming an N-type channel layer or a p + -type gate region formed in the trench in the silicon carbide trench J-FET disclosed in Japanese Patent Laid-Open No. 2003-69041, the aspect ratio of the trench is 2 or more. In the case where the tilt angle is substantially vertical, there arises a problem that cannot be dealt with by the above-described prior art.

That is, in Non-Patent Document 1, regarding the filling of a trench with a vertical inclination angle and a high aspect, the supply of the source gas into the trench is less than that in the non-trench portion under the high C / Si ratio condition. Therefore, in the formation of the N-type channel layer, the shape is overhanged as shown in FIG. 7A, and in the formation of the P ⁺ -type gate region, there is a problem that a cavity is generated in the trench. Further, as shown in FIG. 7B, the growth rate inside the trench is inevitably lower than that in the non-trench portion, so that even if the burying can be performed without generating a cavity, the etching after the burying is performed. There is also a problem that the removal thickness of the unnecessary epitaxial film in the back process is necessarily larger than the trench depth.

  In addition, although facet growth is dominant under low C / Si ratio conditions, the difference in growth rate depending on the plane orientation has not been clarified, and how is the growth rate inside the trench compared to the non-trench part? It has not been shown how to reduce the thickness of the removed unnecessary epitaxial film in the etch-back process after embedding.

  In addition, the smoothing of the trench inner surface in silicon technology takes advantage of the characteristics of Si crystal fluidity during heat treatment (for example, see JP-A-11-74483), and can effectively reduce surface irregularities and crystal defects. it can. In addition, the corners of the trench can be rounded at the same time, the trench opening can be enlarged and the supply of source gas into the trench can be effectively increased without changing the trench width, and there is no corner at the bottom of the trench. The crystallinity of the buried layer is also good, and the electric field concentration when the semiconductor element is turned off can be suppressed due to its shape.

  On the other hand, silicon carbide has no fluidity because there is no liquid phase. Therefore, in the case of silicon carbide, it is necessary to remove the silicon carbide crystal region including the surface roughness and crystal defects on the inner surface (side surface, bottom surface) of the trench generated in the trench etching process. However, silicon carbide has a problem in that the wet etching solution that can effectively remove the trench etching damage and the dry etching conditions are not clear, and the sacrificial oxidation has a low oxidation rate and requires a long oxidation time. there were.

  Other effective etching techniques include hydrogen etching and HCL etching that are commonly used as pre-growth processing for planar epitaxial growth. Usually, these techniques are used even at Si at about 1000 ° C., and it is easy to think that the same mechanism is acting on silicon carbide, but the mechanism is completely different between Si and silicon carbide.

  That is, in the case of Si, surface roughness and crystal defects are removed by recrystallization by promoting Si fluidity by heat treatment at about 1000 ° C. Therefore, a sufficient effect can be obtained if the atmosphere is a non-oxidizing atmosphere. On the other hand, since silicon carbide is composed of two elements, C and Si, and has no fluidity, it is necessary to separate each element from the substrate surface. Usually, the C element reacts with high-temperature hydrogen to be released as hydrocarbon (CxHy), and the Si element is released by a vaporizing action under reduced pressure. Therefore, in etching silicon carbide, a hydrogen atmosphere at 1300 ° C. or higher under reduced pressure or a hydrogen atmosphere to which HCl at 1300 ° C. or higher is added under normal pressure is indispensable. Therefore, when heat treatment is performed in a hydrogen atmosphere without adding HCl at normal pressure, only the C element is released, and the release of the Si element is inhibited, so that only Si remains on the substrate surface and is called a so-called Si droplet phenomenon. A phenomenon that does not exist in Si technology occurs.

  Although silicon carbide etching having such characteristics has not been discussed in detail until now when it is applied to a trench shape. Therefore, the etching rate difference due to the surface orientation of the etching surface is not clear, and the trench corner also has a problem that the condition of how to prevent and round the surface reaction rate control that multiple facet surfaces are generated is not clear. there were. Furthermore, it was not clear how much the surface unevenness and the crystal defect reduction effect were obtained when the trench etching damage region inside the trench (side surface, bottom surface) was removed.

  In view of the above points, the present invention provides a method for manufacturing a silicon carbide semiconductor device capable of improving crystal defects and shape of an inner wall of a trench when a trench type semiconductor element is formed using silicon carbide. With the goal.

  In order to achieve the above-mentioned object, the present inventors first examined a problem when applied to a trench shape of hydrogen etching.

  As described above, as the pre-buried growth treatment, it is necessary to shape the bottom corner of the trench to be rounded. To do so, it is necessary to suppress the surface reaction rate-determining that the facet surface appears by making the etching reaction gas-phase diffusion-controlled. It is. The plurality of facet planes appear according to the difference in surface energy of each crystal plane when the reaction product produced by the etching reaction is sufficiently diffused (discharged) and the reaction temperature is relatively low. When the condition is such that the facet plane is generated, the surface reaction is limited. Therefore, in order to control the gas phase diffusion rate, the reaction temperature may be increased so that the reaction can be sufficiently performed in any plane orientation, or the pressure should be increased so as to suppress the diffusion of the reaction product.

Therefore, the present inventors conducted an experiment of hydrogen etching using a sample in which a trench shape was formed on an actual (0001) Si-plane silicon carbide substrate. At this time, the substrate temperature is set to 1500 to 1650 ° C., and the pressure is set to 2.7 × 10 ⁴ Pa (200 Torr) and 8.6 × 10 ⁴ Pa (600 Torr). FIG. 3 shows the results of this experiment.

As shown in this figure, the corners could be rounded at any pressure above 1625 ° C. On the other hand, at 1500 ° C., a facet surface appeared at any pressure. That is, it has been found that 1625 ° C. or higher is necessary as a hydrogen etching condition before filling in silicon carbide. Further, it was found that no facet surface appeared even at 1600 ° C. at a pressure of 8.6 × 10 ⁴ Pa (600 Torr).

  Further, from another experiment, it was found that the etching rate increases in the order of the Si plane, the a plane, and the C plane under any conditions as the plane direction anisotropy of the etching rate. This is because the ratio of Si atoms to C atoms on the substrate surface determines the etching rate, and it is considered that the detachment process of Si atoms is essentially the rate-determining process.

  Next, the inventors have a problem that the embedded shape is in an overhang state in the initial stage or a cavity is generated in the final stage, and a problem that the growth rate inside the trench is lower than that in the non-trench portion. Was examined.

  First, when the growth reaction is surface reaction-controlled (in Non-Patent Document 1, this corresponds to a low C / Si ratio condition), the growth rate is determined by the crystal plane orientation. It is a very effective means. However, as described above, the region where the growth of specific surfaces merge with each other is gradually reduced due to the surface reaction rate control, and there is a possibility that a buried layer with good crystallinity cannot be finally formed due to the generation of stress. .

  When the growth reaction is vapor phase diffusion-controlled (in Non-Patent Document 1, a high C / Si ratio condition), the supply of source gas to the inside of the trench, particularly to the bottom of the trench, is inevitably reduced as compared with the non-trench portion. Therefore, the problem of an overhang, a cavity, and the increase in film thickness of a non-trench portion occurs.

  However, the growth of the epitaxial film is a reversible reaction, and the substantial growth amount is determined by the balance between deposition and etching. That is, the value obtained by subtracting the etching amount from the deposition amount is a substantial growth amount. In general growth, since the etching amount is negligibly small compared to the deposition amount, the deposition amount is regarded as the growth amount as it is. Therefore, we examined what happens when both deposition and etching are activated, that is, when the substrate temperature is increased.

  FIGS. 8A and 8B are conceptual diagrams of an expected growth mode when a trench is formed on the (0001) Si surface, the side surface is an a surface, and the substrate temperature is increased.

First, FIG. 8A shows a shape by H ₂ etching when the source gas (SiH ₄ , C ₃ H ₈ ) is not added to the carrier gas (H ₂ ). Due to the plane orientation anisotropy of the H ₂ etching described above, the side surface of the trench 100 has a higher etching rate than the bottom surface of the trench 100 and the non-trench portion, so that the side surface of the trench 100 is selectively etched. Become. Further, the corners of the trench 100 are rounded due to the effect of vapor phase diffusion control.

On the other hand, FIG. 8B shows a growth shape when the source gas (SiH ₄ , C ₃ H ₈ ) is added to the carrier gas (H ₂ ). The growth in this case is strongly influenced by the plane orientation anisotropy of H ₂ etching, and the growth rate of the a plane is lower than that of the Si plane. As a result, the growth rate is expected to increase in the order of the upper side surface of the trench 100, the lower side surface of the trench 100, the non-trench portion, and the bottom portion of the trench 100.

  And if this growth rate can be realized, the problems of overhanging in the initial stage and the generation of cavities in the final stage and the problem of a lower growth rate inside the trench compared to the non-trench part can be solved. The confirmation experiment was carried out as follows.

The inventors of the present invention used a sample in which a trench shape was formed on an actual silicon carbide substrate, and performed embedded growth while changing the growth temperature and the amount of material gas supply (substantial growth rate) as growth parameters. The conditions for the hydrogen etching before filling are a temperature of 1625 ° C. and a pressure of 2.7 × 10 ⁴ Pa (200 Torr).

  FIG. 9 shows the result. As a result, the above problems could be solved in a sample having a growth temperature of 1625 ° C. or more and a growth rate of about 2.5 μm or less. In other words, the overhang state did not occur in the initial stage, and no cavities were generated in the final stage. FIGS. 10A, 10B and 10C show changes in the growth shape with time when the growth temperature is 1625 ° C. and the growth rate is about 2.5 μm. The epitaxial growth rate increases in the order of the upper side surface of the trench 100, the lower side surface of the trench 100, the non-trench portion, and the bottom portion of the trench 100. That is, the growth rate inside the trench 100 can be increased as compared with the non-trench portion. This is consistent with the conclusion derived from the fact that the etching rate of the a-plane is larger than that of the Si-plane.

  Therefore, in the first aspect of the invention, the trench etching mask (21, 60) is formed on the upper surface of the (0001) Si-faced semiconductor substrate (20, 45) made of silicon carbide in the trench mask forming step. After that, in the trench formation step, etching using this trench etching mask (21, 60) is performed, so that the semiconductor substrate (20, 45) has a trench with an aspect ratio of 2 or more and a trench inclination angle of 80 degrees or more. 6 and 47), and then, in the damage removing step, the trench etching damage region on the inner surface of the trench (6, 47) formed in the semiconductor substrate (21, 60) is formed in a hydrogen atmosphere at a reduced pressure of 1600 ° C. or higher. It is characterized by etching away.

  In this way, by etching in a hydrogen atmosphere at a reduced pressure of 1600 ° C. or higher, the damaged region can be removed in a short time due to the characteristics of high-temperature hydrogen. In addition, the etching rate of the side a surface is higher than that of the bottom Si surface. Therefore, the unevenness on the side surface larger than the bottom surface generated in the trench formation step can be selectively etched, and the surface unevenness in the trench can be efficiently reduced in a short time.

  As a result, when epitaxial growth is performed in a subsequent process, the surface unevenness becomes extremely small, and the generation of levels in the epitaxial layer caused by the surface unevenness can be prevented. For this reason, the PN junction formed by the layers constituting the semiconductor substrate (20, 45) and the epitaxial layer can be a junction with a small leakage current.

  The invention described in claim 2 is characterized in that a trench mask removing step for removing the trench etching mask (21, 60) is performed before the damage removing step. Thus, by removing the trench etching mask (21, 60) before the damage removing step, the influence of impurities contained in the mask material during the epitaxial growth can be completely eliminated.

  According to the third aspect of the present invention, after the trench mask removing step, the selective epitaxial mask (31) is formed in a part of the region different from the trench (6, 47) on the upper surface of the semiconductor substrate (20, 45). And a selective mask forming step.

  Thus, if a selection mask is formed on the trench region formed for alignment, it is possible to prevent embedding during epitaxial growth and to ensure alignment before and after epitaxial growth. In addition, after removing the selection mask, it is possible to control the etching amount to a desired level by performing etch back while measuring the depth of the trench formed for alignment during the etch back process.

  The invention according to claim 4 is characterized in that, in the damage removal step, the corners of the trenches (6, 47) are rounded by removing the damage by vapor phase diffusion-controlled reaction.

Such a round shape effectively promotes the penetration of the source gas into the trench at the trench opening during the epitaxial growth of the next process. Furthermore, the distance of the non-trench plane part between trench patterns is shortened. Therefore, it is possible not only to prevent the occurrence of an overhang shape when the trench aspect ratio is increased, but also to suppress the growth of the non-trench planar portion.
For this reason, even if an epitaxial layer is formed in a subsequent process, the growth of the non-trench portion can be suppressed by these, and the trench can be buried without a cavity. On the other hand, the trench bottom has an effect of dispersing and relaxing the crystal stress during epitaxial growth, so that an epitaxial film with good crystallinity can be formed.

For example, as shown in claim 5, in the damage removing step, P is an atmospheric pressure (Pa), T is a substrate temperature (° C.), a is 4.16 × 10 ⁶ , and b is 2.54 × 10 ⁴ . In this case, damage removal is performed under the condition satisfying the relationship of P × 1.33 × 10 ² ≧ a / T−b.

  In addition, as shown in Claim 6, it is preferable to perform a damage removal process at 1700 degrees C or less. This is because if the temperature exceeds 1700 ° C., step bunching may occur on the substrate surface. If the temperature is 1700 ° C. or lower, the occurrence of step bunching can be prevented.

  The invention according to claim 7 is characterized in that in the damage removing step, the damage is removed by heat treatment in a hydrogen atmosphere containing hydrocarbons. Thus, by adding hydrocarbon, etching of carbon atoms in the silicon carbide crystal is suppressed, the etching rate is lowered as a whole, and the etching reaction is further shifted to the gas phase diffusion rate controlling side. Therefore, if heat treatment is performed in a hydrogen atmosphere containing hydrocarbons as described above, the round shape of the corners of the trenches (6, 47) can be easily realized as compared with an atmosphere containing only hydrogen.

  The invention according to claim 8 is characterized in that in the damage removing step, the damage is removed by heat treatment in a hydrogen atmosphere containing an inert gas. If the atmospheric pressure does not change, the addition of an inert gas such as Ar will relatively reduce the hydrogen concentration. Therefore, although the diffusion effect of the reaction product is not changed, the etching rate is lowered and is shifted to the gas phase diffusion rate controlling side like the hydrocarbon. Therefore, even when an inert gas such as Ar is added, the round shape of the corners of the trenches (6, 47) can be easily realized as compared with an atmosphere containing only hydrogen.

  The invention according to claim 9 is characterized in that, in the buried layer forming step performed after the damage removing step, the distance between the trench patterns is reduced so that a non-trench flat portion is not generated between the trench patterns.

  By setting the distance between the trench patterns in this manner, the growth of the Si surface having the largest growth rate is eliminated, and the growth rate of the non-trench portion is affected by the a-plane etching from the side surface and the growth rate is lowered. That is, the growth rate increases in the order of the upper side surface of the trench, the lower side surface of the trench, the non-trench portion, and the bottom portion of the trench, and an overhang state is generated in the initial stage and no void is generated in the final stage. Furthermore, the growth rate inside the trench can be increased as compared with the non-trench portion.

  Specifically, the distance between trench patterns is preferably equal to or less than the trench width as described in claim 10.

  The invention described in claim 11 is characterized in that, after the damage removing step, the epitaxial layer (7, 48) is formed in the trench (6, 47) at 1500 ° C. or higher by the epitaxial growth method.

  Even in such epitaxial growth in a low temperature region, if the raw material gas supply amount is limited and the growth rate is reduced so that the etching amount and the deposition amount are balanced, as the growth rate, the trench side, the non-trench portion, A growth pattern that increases in order from the bottom of the trench is realized. At the same time, the growth rate of the lower part can be increased on the side surface compared to the upper part, so that the so-called overhang shape is suppressed.

  As described in claim 12, if the formation temperature of the epitaxial layers (7, 48) is 1550 ° C. or higher, both etching and deposition are activated, and the growth rate can be increased overall. .

  Furthermore, as described in claim 13, if the formation temperature of the epitaxial layers (7, 48) is set to 1625 ° C. or higher, the overhang shape does not occur even if the growth rate inside the trench is increased to about 2.5 μm / h. Therefore, a buried layer without a cavity can be formed in a short time.

  The invention described in claim 14 is characterized in that the damage removing step and the epitaxial layer (7, 48) forming step are continuously performed using the same apparatus.

  In this way, by performing the damage removing step and the epitaxial thin film forming step with the same apparatus, the semiconductor substrate can be prevented from being exposed to the atmosphere, and the adhesion of contaminants to the substrate surface can be reduced. In addition, since the temperature raising / lowering time in the substrate heating can be omitted, it is possible to improve the throughput of manufacturing the semiconductor device.

  The invention according to claim 15 is characterized in that, in the epitaxial layer forming step, epitaxial growth is performed by vapor phase diffusion control, so that corners of the epitaxial layers (7, 48) are rounded.

As described above, if the epitaxial layers (7, 48) are formed so as to have a round shape without a plurality of facet surfaces by gas phase diffusion control, the crystal stress during epitaxial growth can be dispersed and relaxed. The invention according to claim 16 is characterized in that the growth rate is 2.5 μm / h or less in the epitaxial layer forming step.

  With such a growth rate, it is possible to prevent the appearance of a plurality of facet surfaces by forming the epitaxial layer at a vapor phase diffusion-controlled rate.

  The invention according to claim 17 is characterized in that the epitaxial layer forming step is performed at 1700 ° C. or lower. Thereby, the same effect as that of the sixth aspect can be obtained.

  The invention according to claim 18 is characterized in that, in the epitaxial layer forming step, epitaxial growth is performed by containing a gas having an etching action in addition to the source gas and the carrier gas.

  By introducing such an etching gas, it is possible to create a state where the etching and deposition functions are balanced even when epitaxial growth is performed at a relatively low temperature, and the a-plane etching rate is larger than that of the Si surface. It is possible to increase the growth rate inside the trench compared to the non-trench portion. For example, as the gas having such an etching action, hydrogen chloride gas can be used as shown in claim 19.

  The invention according to claim 20 is characterized in that, in the epitaxial layer forming step, the concentration control is performed so that the impurity concentration differs between the initial epitaxial stage and the final stage. For example, as shown in claim 21, the impurity concentration is controlled to be higher in the final stage than in the initial stage.

  By performing such impurity concentration control, in the initial growth layer forming the PN junction interface, the impurity concentration is relatively low, so that a crystal strain is small, crystallinity is good, and a leakage current is small. On the other hand, in the final stage, the impurity concentration is set high to lower the sheet resistance of the buried layer, and the contact resistance with the electrode is reduced. Thus, the switching speed of the power device can be reduced.

  The invention according to claim 22 is characterized in that, in the trench forming step, the surface pattern of the trench (6, 47) is formed in a stripe shape parallel to the off direction of the semiconductor substrate (20, 45).

  As described above, if the trench pattern is a stripe parallel to the off-direction of the substrate, the epitaxial film formed on both side surfaces of the trench becomes completely symmetrical in shape and impurity profile, and the threshold voltage of the semiconductor device, etc. The electrical characteristics can be made uniform. Furthermore, it is possible to prevent the formation of a C-faceted facet generated from the upper corner of the trench. Therefore, an element with excellent on / off performance can be realized.

  The invention as set forth in claim 23 is characterized in that, in the trench forming step, the surface pattern of the trenches (6, 47) has a hexagonal shape with the same internal angle.

  With such a pattern, the epitaxial film formed on the side surface of the trench has substantially the same shape and impurity concentration profile. Therefore, the channel width density of the transistor can be maximized, and a semiconductor device having excellent on / off characteristics like the stripe shape can be provided.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 shows a cross-sectional configuration of a J-FET provided in the silicon carbide semiconductor device according to the first embodiment of the present invention. Hereinafter, the configuration of the J-FET will be described with reference to FIG.

As shown in FIG. 1, for example, an N ⁺ type substrate 1 having a silicon carbide (0001) Si surface having a high impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or higher is used, and on the main surface of the N ⁺ type substrate 1. In addition, an N ⁻ type drift layer 2 having a low impurity concentration of, for example, 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ is formed. A first gate region 3 made of a P ⁺ type layer is epitaxially grown on the surface of the N ⁻ type drift layer 2. The first gate region 3 has a high impurity concentration of, for example, 5 × 10 ^{17 to} 5 × 10 ¹⁹ cm ⁻³ .

Further, the N ⁻ type region 4 is epitaxially grown on the surface of the first gate region 3, and the high impurity concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ is formed on the surface of the N ⁻ type region 4, for example. The N ⁺ type source region 5 is epitaxially grown. The N ⁻ -type region 4 is sandwiched between the N ⁺ -type source region 5 and the P ⁺ -type first gate region 3, thereby performing electric field relaxation between high-concentration PN junctions. Hereinafter, the N ⁻ -type region 4 is referred to as an electric field relaxation region (first electric field relaxation region). The thickness of the electric field relaxation region 4 is, for example, 0.5 μm or less, and the impurity concentration thereof is lower than that of the N ⁺ type source region 5.

Further, the surface of the N ⁺ -type source region 5, the N ⁺ -type source region 5, through the electric-field relaxation region 4 and the first gate region 3, N ^- trench 6 to reach the type drift region 2 is formed. An N ⁻ type channel layer 7 having an impurity concentration substantially equal to that of the N ⁻ type drift region 2 is epitaxially grown on the inner wall of the trench 6, and the trench 6 is embedded in the surface of the N ⁻ type channel layer 7. In addition, a P ⁺ -type second gate region 8 having an impurity concentration substantially equal to that of the first gate region 3 is epitaxially grown. The surfaces of the N ⁻ type channel layer 7 and the second gate region 8 are flush with the surface of the N ⁺ type source region 5.

A second gate electrode 9 is electrically connected to the surface of the second gate region 8, and an interlayer insulating film 10 is formed so as to cover the second gate electrode 9. A source electrode 11 electrically connected to the N ⁺ type source region 5 through a contact hole formed in the interlayer insulating film 10 is formed.

Further, in a cross section different from FIG. 1, the first gate region 3 is also electrically connected to the first gate electrode 12 so that the voltage applied to the first gate region 3 can be controlled via the first gate electrode 12. It has become. Then, a drain electrode 13 is formed on the back surface side of the N ⁺ type substrate 1 to configure the structure shown in FIG.

  The J-FET configured in this way operates normally off. This operation differs depending on the connection mode of the first gate electrode 12 and the second gate electrode 9, and is performed as follows.

In the case where the potentials of the first and second gate electrodes 12 and 9 are controllable, both the first and second gate regions 3 and 8 are based on the potentials of the first and second gate electrodes 12 and 9. Double gate drive is performed to control the extension amount of the depletion layer extending from to the N ⁻ type channel layer 7 side. For example, when no voltage is applied to the first and second gate electrodes 12 and 9, the N ⁻ -type channel layer 7 is pinched off by a depletion layer extending from both the first and second gate regions 3 and 8. Thereby, the source-drain current is turned off. When a forward bias is applied between the first and second gate regions 3 and 8 and the N ⁻ -type channel layer 7, the extension amount of the depletion layer extending to the N ⁻ -type channel layer 7 is reduced. Thereby, a channel is set and a current flows between the source and the drain.

In the case where only the potential of the first gate electrode 12 can be controlled independently and the potential of the second gate electrode 9 is set to the same potential as the source electrode 11, for example, based on the potential of the first gate electrode 12. Single gate driving for controlling the amount of extension of the depletion layer extending from the first gate region 3 side to the N ⁻ -type channel layer 7 side is performed. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the first gate region 3 side.

In the case where only the potential of the second gate electrode 9 can be controlled independently and the potential of the first gate electrode 12 is the same potential as that of the source electrode 11, for example, based on the potential of the second gate electrode 9. Single gate drive is performed to control the amount of depletion layer extending from the second gate region 8 side to the N ⁻ -type channel layer 7 side. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the second gate region 8 side.

  Next, a method for manufacturing the silicon carbide semiconductor device shown in FIG. 1 will be described with reference to the manufacturing steps of the silicon carbide semiconductor device shown in FIG.

[Step shown in FIG. 2 (a)]
First, an N ⁺ type substrate 1 having a silicon carbide (0001) Si surface is prepared. When a substrate having such a plane orientation is used, for example, even if the inclination angle of the trench 6 is not 90 degrees, the ratio of carbon atoms and silicon atoms existing on the side surface of the trench can be made substantially the same. Therefore, parameter design of the semiconductor device can be facilitated.

An N ⁻ type drift layer 2 made of an epitaxial film, a P ⁺ type first gate region 3, an N ⁻ type region 4, and an N ⁺ type source region are formed on the N ⁺ type substrate 1 having such a plane orientation. A semiconductor substrate 20 made of silicon carbide in which 5 is sequentially stacked is prepared, and an LTO film (oxide film) 21 serving as a trench etching mask is formed on the upper surface of the semiconductor substrate 20, and then patterned by photolithography. The pattern is a stripe pattern in which the longitudinal direction of the opening is parallel to the off direction of the substrate, and the width of the opening (trench width) is set to 2 μm, for example, and the distance between the trench patterns is set to 1.5 μm, for example. .

  With such a stripe pattern parallel to the off direction, the crystal planes on both sides are completely symmetrical from the point of crystal plane orientation. Furthermore, it becomes possible to prevent the formation of C-face facets generated from the corners above the trenches during epitaxial growth described later. Therefore, the epitaxial film formed on both side surfaces of the trench becomes completely symmetrical in shape and impurity profile, and the electrical characteristics such as the threshold voltage of the semiconductor device can be made uniform. In addition, since there is no C-plane facet at the top of the trench, it is possible to prevent a leakage current failure of the semiconductor device.

[Step shown in FIG. 2 (b)]
Next, dry etching for trench formation is performed using the LTO film as a mask, the inclination angle reaching the N ⁻ type drift layer 2 through the first gate region 3 is 80 degrees or more, and the trench depth is 4 μm or more, for example, A trench 6 having an aspect ratio of 2 or more is formed. At this time, due to dry etching damage, surface unevenness of about 100 nm is generated on the side surface of the trench and about 10 nm is generated on the bottom surface of the trench. In addition, an altered layer by dry etching is generated to a depth of about 10 nm on the side and bottom surfaces of the trench.

[Step shown in FIG. 2 (c)]
Next, a trench etching damage removing step is performed in a high-temperature hydrogen atmosphere. Specifically, the conditions for the damage removal process at this time are determined based on the experimental results.

  That is, when the relationship between the reciprocal (1 / T) and the pressure P was examined when the substrate temperature was T, the result shown in FIG. 3 was obtained. In this figure, a circle indicates a case where gas phase diffusion is limited, a triangle indicates a case where gas diffusion is basically limited, but a slight amount of surface reaction is included, and a mark X indicates a case where surface reaction is limited. Yes. From this figure, as the boundary between the substrate temperature and the pressure when the gas phase diffusion rate is controlled and when the surface reaction rate is included, the substrate temperature and the pressure when the gas phase diffusion rate is determined from the experimental results. When a straight line was drawn to the maximum value and the straight line was expressed as a linear expression, it was found that if the relationship of the following expression was satisfied, the gas phase diffusion rate was controlled.

(Equation 1)
P × 1.33 × 10 ² ≧ a / Tb
Note that a and b are constants, and a = 4.16 × 10 ⁶ and b = 2.54 × 10 ⁴ .

Therefore, in this embodiment, damage removal by trench etching is performed for about 5 minutes in a hydrogen atmosphere under a reduced pressure of 1600 ° C. or more, for example, a high temperature hydrogen atmosphere of 1625 ° C. and 2.7 × 10 ⁴ Pa (200 Torr). .

  However, at this time, the upper limit temperature of the damage removing step is set to 1700 ° C. This is because if the temperature exceeds 1700 ° C., step bunching may occur on the substrate surface. If the temperature is 1700 ° C. or lower, the occurrence of step bunching can be prevented.

  In this way, by performing the damage removing process for about 5 minutes, the side surface of the trench is etched by about 200 nm and the bottom surface is etched by about 40 nm, and the surface unevenness and the altered layer are completely removed.

  At the same time, the LTO film 21 of the trench etching mask is also completely removed. That is, although the LTO film 21 is used as a mask for trench etching, the semiconductor grade oxide film is easily etched with high-temperature hydrogen and does not contain contaminants such as metals. For this reason, if this feature is utilized, the trench mask removal process can be performed simultaneously with the damage removal process using high-temperature hydrogen. Thereby, the trench mask removal process considered necessary between the trench formation process and the damage removal process using high-temperature hydrogen can be omitted.

At this time, the surface irregularities on the side surfaces of the trench are also reduced to about 5 nm. Under the etching conditions at this time, the etching reaction is gas phase diffusion-controlled. Therefore, the corners of the trench, such as the trench opening and the bottom of the trench, have a round shape with no facet. Due to this round shape, intrusion of the source gas into the trench can be effectively promoted in the trench opening at the time of epitaxial growth in the next process. Can be prevented. For this reason, even if the N ⁻ -type channel layer 7 and the P ⁺ -type second gate region 8 are formed in a later step, the trench 6 can be buried without any cavities. On the other hand, the trench bottom has an effect of dispersing and relaxing the crystal stress during epitaxial growth, so that an epitaxial film with good crystallinity can be formed. Further, at this time, the length of the plane portion (Si surface portion) between the trench patterns is reduced from 1.5 μm to 1.1 μm by etching.

[Step shown in FIG. 2 (d)]
Next, the N ⁻ -type channel layer 7 made of an epitaxial thin film is continuously formed in the same apparatus as that in which the damage removing step is performed. In this way, by performing the damage removing step and the epitaxial thin film forming step with the same apparatus, the semiconductor substrate can be prevented from being exposed to the atmosphere, and the adhesion of contaminants to the substrate surface can be reduced. In addition, since the temperature raising / lowering time in the substrate heating can be omitted, it is possible to improve the throughput of manufacturing the semiconductor device.

In this epitaxial growth step, epitaxial growth is performed by introducing SiH ₄ gas and C ₃ H ₈ gas as source gases into a high-temperature hydrogen atmosphere at 1625 ° C. or higher. For controlling the N-type impurity concentration, N ₂ gas as a doping gas is appropriately used. Also at this time, it is preferable that the upper limit of the temperature of epitaxial growth is 1700 ° C. so that step bunching does not occur.

  Then, the gas flow rate is set so that the growth rate is 2.5 μm / h or less. By setting it as such a growth rate, it can prevent that epitaxial growth advances by vapor phase diffusion controlled reaction, and a facet surface appears after epitaxial growth.

  In this way, by making the epitaxial growth reaction a gas phase diffusion-controlled reaction, an epitaxial film having a good crystallinity with little crystal stress strain can be formed even at the bottom of the trench corner. In addition, both etching and deposition are activated, and the etching amount and deposition amount are balanced. Therefore, the etching of the side surface (a surface) is promoted, and the growth rate is in order of the trench side surface, the non-trench portion, and the trench bottom surface. A growing form of growth is realized. At the same time, the growth rate of the lower part can be increased on the side surface compared to the upper part, so that the so-called overhang shape is suppressed.

  In addition, since the trench pattern is a stripe parallel to the off direction of the substrate, the epitaxial film formed on both sides of the trench is completely symmetrical in shape and impurity profile, and the electrical characteristics such as the threshold voltage of the semiconductor device are uniform. Can be Furthermore, it is possible to prevent the formation of a C-faceted facet generated from the upper corner of the trench. Therefore, an element with excellent on / off performance can be realized.

[Step shown in FIG. 2 (e)]
Next, a P ⁺ -type second gate region 8 is formed under the same epitaxial conditions as the N ⁻ -type channel layer 7 as a buried layer. The formation of the second gate region 8 differs from the formation of the N ⁻ -type channel layer 7 in that trimethylaluminum is used instead of N ₂ because it is P-type. Also in this case, since the etching amount and the deposition amount are balanced, etching of the side surface (a surface) is promoted. In particular, at the stage where the burying has progressed, the plane portion (Si surface portion) between the trench patterns is completely eliminated, and the growth is further suppressed. As a result, the growth rate increases in the order of the trench side surface, the non-trench portion, and the trench bottom surface. Further, since the growth rate of the lower part of the trench can be increased also on the side surface of the trench compared to the upper part of the trench, the generation of cavities can be prevented, and the removal amount in the etch-back process after the formation of the second gate region 8 can be made smaller than the trench depth. It becomes possible.

Furthermore, it is preferable to control the concentration of the P-type concentration so that the impurity concentration differs between the initial stage and the final stage during epitaxial growth. Specifically, the device characteristics are further improved by controlling the trimethylaluminum flow rate so that the impurity concentration is higher in the final stage than in the initial stage. For example, in the initial stage, 5 × 10 ¹⁸ cm ⁻³ is set to 0.2 μm (side surface thickness), and thereafter, 1 × 10 ²⁰ cm ⁻³ is embedded. Then, in the initial growth layer that forms the PN junction interface, the impurity concentration is relatively low, so that a crystal strain is small, a PN junction with good crystallinity and low leakage current can be formed. On the other hand, in the final stage, the impurity concentration is set high to lower the sheet resistance of the buried layer, and the contact resistance with the electrode is reduced. Thus, the switching speed of the power device can be reduced.

[Step shown in FIG. 2 (f)]
Next, after an excess portion of the N ⁻ type channel layer 7 and the P ⁺ type second gate region 8 formed in the non-trench portion is etched back by CMP (Chemical Mechanical Polishing) or the like, an electrode forming process or the like is performed. Then, the N ⁻ type channel layer 7 and the P ⁺ type second gate region 8 of the trench type J-FET shown in FIG. 1 are completed. In this case, since the epitaxial growth rate increases in the order of the trench side surface, non-trench portion, and trench bottom surface, the etching amount required for etch back can be made smaller than the trench depth, and the controllability of the etching amount is also good. It becomes.

  As described above, in this embodiment, after the trench 6 having an aspect ratio of 2 or more and a trench inclination angle of 80 degrees or more is formed on the substrate 20 by dry etching, the damaged region on the inner surface of the trench at the time of dry etching is 1600 ° C. Etching is removed in the above-described reduced-pressure hydrogen atmosphere.

  In the conventional technology using silicon carbide single crystal, a wet etching solution that can effectively remove a so-called trench etching damage region such as a surface unevenness or a deteriorated layer generated by trench etching, a dry etching condition is not clear, and sacrificial A long time was also required for oxidation. On the other hand, according to the method shown in this embodiment, the damaged region can be removed in a short time due to the characteristics of high-temperature hydrogen. And since the surface unevenness | corrugation and a deteriorated layer do not remain in the trench from which the damage was removed, the level which arises from a deteriorated layer can be made not to exist. Further, the surface unevenness can be made extremely small.

As a result, when epitaxial growth is performed in a subsequent process, the surface unevenness is extremely small, so that generation of a level in the epitaxial layer caused by the surface unevenness can be prevented. Therefore, with respect to the PN junction between each layer constituting the substrate 20 and the N ⁻ -type channel layer 7, a junction with a small leakage current can be achieved.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. Since the present embodiment is substantially the same as the first embodiment, differences from the first embodiment will be mainly described.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device in the present embodiment. As in the first embodiment, a manufacturing process of the N ⁻ type channel layer 7 of the trench type J-FET and the second gate region 8 of the P ⁺ type is shown. In this embodiment, the mask for selective epitaxial growth is shown. Is not formed in the trench 6 of the transistor cell portion, but is applied only to the trench of the alignment key region. This ensures alignment after the buried epitaxial step and the subsequent etch-back step.

  First, as shown in FIG. 4A, an LTO film 2 serving as a trench etching mask and an alignment key mask is simultaneously formed in the transistor cell portion and the alignment key portion.

  Next, as shown in FIG. 4B, the trench 6 and the trench 31 are formed in the transistor cell portion and the alignment key portion by using the LTO film 2 as a mask by the same method as in the first embodiment. Thereafter, the LTO film 2 remaining during the trench etching is completely removed with hydrofluoric acid. Thus, by removing the LTO film 2 before the damage removing step, the influence of impurities contained in the etching mask material during the epitaxial growth can be completely eliminated.

  Next, as shown in FIG. 4C, a carbon film 32 is formed at least on the alignment key part trench 31. At this time, the carbon film 32 is prevented from being formed in the vicinity of the trench 6 in the transistor cell portion by photoetching or the like.

  The carbon film 32 has been confirmed to have etching resistance even in a high-temperature hydrogen atmosphere at 1600 ° C. or higher, and can be continuously used in a damage removal process in a high-temperature hydrogen atmosphere and an epitaxial process in a subsequent process. The carbon film 32 is easily formed by heat-treating a photoresist generally used in a semiconductor process in a non-oxidizing atmosphere. When removing a carbon film that is no longer necessary after the epitaxial process, the carbon film 32 has a temperature of about 1000 ° C. And can be easily removed by thermal oxidation for a short time.

Next, as shown in FIG. 4D, the trench etching damage removal, the N ⁻ -type channel layer 7, and the P ⁺ -type second gate region 8 are formed by the same method as in the first embodiment. In this case, since there is no carbon film 32 in the vicinity of the trench 6 in the transistor cell portion, damage removal is performed in the same manner as in the first embodiment, and rounding processing of corner portions of the trench 6 is performed. On the other hand, since the carbon film 32 is formed in the trench 31 of the alignment key portion, damage removal by trench etching is not performed, and the N ⁻ type channel layer 7 and the P ⁺ type second gate region 8 are not formed.

Thereafter, as shown in FIG. 4E, the excess portions of the N ⁻ -type channel layer 7 and the P ⁺ -type second gate region 8 formed outside the trench 6 are etched by CMP (Chemical Mechanical Polishing) or the like. Then, the carbon film 32 formed on the trench 31 of the alignment key part is removed by thermal oxidation. As a result, the transistor shape shown in FIG. 1 is formed in the transistor cell portion, and the trench 31 having a pattern necessary as an alignment mark of the photomask is formed in the alignment key portion.

  When the carbon film 32 serving as a selection mask is not formed, the alignment mark for pattern alignment becomes difficult to see after epitaxial growth, or the alignment mark disappears in the etch-back process after forming the buried layer. For this reason, if the carbon film 32 serving as a selection mask is formed on the trench 31 formed for alignment, embedding during epitaxial growth can be prevented, and alignment before and after epitaxial growth can be ensured. It is also possible to control the etching amount to a desired level by removing the carbon film 32 serving as a selection mask and performing etch back while measuring the depth of the trench 31 formed for alignment during the etch back process. .

  Here, the thermal oxidation process for removing the carbon film is performed after the etch-back process. However, since it is sufficient that the alignment mark is finally left as a pattern, the order of these processes may be reversed.

(Third embodiment)
Next, a third embodiment of the present invention will be described. Since the present embodiment is substantially the same as the first embodiment, differences from the first embodiment will be mainly described.

In the present embodiment, only the growth conditions in the epitaxial process are changed from those in the first embodiment. In addition to SiH ₄ , C ₃ H _{8 as} a source gas, and H ₂ as a carrier gas, hydrogen chloride or the like is used. Etching gas is mixed for epitaxial growth. Specifically, although depending on the substrate temperature, epitaxial growth is performed by mixing hydrogen chloride gas of about 1 to 5% of the hydrogen gas flow rate.

By introducing a gas having such an etching action, it is possible to create a state in which the etching action and the deposition action are balanced even when epitaxial growth is performed at a relatively low temperature. Also in this case, the etching of the side surface (a surface) is promoted, and even if the substrate temperature does not reach 1600 ° C., the N ⁻ -type channel layer 7 is over even in the trench having an aspect ratio of 2 or more as in the case of 1625 ° C. or higher epitaxial growth. The p ⁺ -type second gate region 8 can also be formed so as not to generate a cavity.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. One embodiment of the present invention is applied to the formation of an N ⁻ type channel layer of a trench MOSFET as a semiconductor device. FIG. 5 is a partial cross-sectional perspective view of the trench MOSFET in the present embodiment.

As shown in FIG. 5, a high resistance N ⁻ type drift layer 42, a P ⁺ type base layer 43, and an N ⁺ type source layer 44 are formed on a low resistance N ⁺ type substrate 41 made of hexagonal silicon carbide. They are sequentially stacked. The N ⁺ type substrate 1, N ⁻ type drift layer 42, P ⁺ type base layer 43 and N ⁺ type source layer 44 constitute a semiconductor substrate 45, whose upper surface is a (0001) Si surface.

An N ⁺ type source layer 44 is formed in a predetermined region of the surface layer portion in the P ⁺ type base layer 43. Further, a low resistance P ⁺ type contact region 46 is formed in a predetermined region of the surface layer portion in the P ⁺ type base layer 43. A trench 47 is formed in a predetermined region of the N ⁺ type source layer 44, and this trench 47 penetrates the N ⁺ type source layer 44 and the P ⁺ type base layer 43 and reaches the N ⁻ type drift layer 42. The trench 47 has a side surface 47 a perpendicular to the surface of the semiconductor substrate 45 and a bottom surface 47 b parallel to the surface of the semiconductor substrate 45. Further, the side surface 47a of the trench 47 extends substantially in the [11-20] direction. Furthermore, the planar shape of the side surface 47a of the trench 47 is a hexagonal shape with substantially equal inner angles. That is, when the semiconductor substrate 45 of FIG. 5 is viewed from above, the six sides of the hexagon are indicated by S1, S2, S3, S4, S5, and S6, and the angle (inner angle) between the sides S1 and S2 and the side S2 And S3 (inner angle), sides S3 and S4 (inner angle), sides S4 and S5 (inner angle), sides S5 and S6 (inner angle), and sides S6 and S1 (angle) The inner angle is laid out so as to be approximately 120 °.

N having a lower impurity concentration than the N ⁺ type substrate 1 or the N ⁺ type source layer 44 is formed on the surfaces of the N ⁺ type source layer 44, the P ⁺ type base layer 43 and the N ⁻ type drift layer 42 on the side surface 47 a of the trench 47. ^A -type channel layer 48 is extended. The N ⁻ type channel layer 48 is a thin film having a thickness of about 1000 to 5000 mm, and the crystal type of the N ⁻ type channel layer 48 is the same as the crystal type of the P ⁺ type base layer 43, for example, 4H—SiC. It has become. In addition, although 4H-SiC is used here, 6H-SiC, 3C-SiC, etc. may be used besides this.

Further, a gate insulating film 49 is formed on the surface of the N ⁻ type channel layer 48 and the bottom surface 47 b of the trench 47 in the trench 47. A gate electrode 50 is filled inside the gate insulating film 49 in the trench 47. The gate electrode 50 is covered with an insulating film 51. A source electrode 52 as a first electrode is formed on the surface of the N ⁺ type source layer 44 and the surface of the P ⁺ type contact region 46. On the back surface of the N ⁺ type substrate 41, a drain electrode 53 as a second electrode is formed.

  Next, a method of manufacturing the trench MOSFET shown in FIG. 5 will be described with reference to the manufacturing process diagram shown in FIG.

[Step shown in FIG. 6A]
First, a semiconductor substrate 45 in which an N ⁻ type drift layer 42 made of an epitaxial film, a P ⁺ type base layer 43, and an N ⁺ type source layer 44 are sequentially stacked on an N ⁺ type substrate 41 having a silicon carbide (0001) Si surface. Prepare. Then, an LTO film 60 is sequentially formed on the upper surface as a trench etching mask as in the first embodiment, and then patterned by photolithography. As the pattern, as shown in FIG. 5, a hexagonal pattern having substantially equal inner angles parallel to the <11-20> direction is set, for example, so that the trench width is 2 μm and the distance between the trench patterns is 2 μm.

  With such a pattern, the epitaxial film formed on the side surface of the trench has substantially the same shape and impurity concentration profile. Therefore, the channel width density of the transistor can be maximized, and a semiconductor device having excellent on / off characteristics like the stripe shape can be provided.

[Step shown in FIG. 6B]
Next, dry etching for trench formation is performed using the LTO film 60 as a mask, the inclination angle reaching the N ⁻ type drift layer 42 through the p ⁺ type base layer 43 is 80 degrees or more, and the trench depth is, for example, 4 μm or more. That is, the trench 47 having an aspect ratio of 2 or more is formed. At this time, due to dry etching damage, surface unevenness of about 100 nm is generated on the side surface of the trench and about 10 nm is generated on the bottom surface of the trench. In addition, an altered layer by dry etching is generated to a depth of about 10 nm on the side and bottom surfaces of the trench.

[Step shown in FIG. 6 (c)]
Next, a damage removing step is performed as in the first embodiment. At this time, in particular, if the surface reaction rate is controlled in the first half of the process and the gas phase diffusion rate is controlled in the second half of the process, the surface irregularities on the side surfaces of the trench are reduced to the atomic order by the surface reaction rate control in the first half. By the phase diffusion control, the corners of the bottom of the trench can be round with no facet.

[Step shown in FIG. 6 (d)]
Next, similarly to the first embodiment, an N ⁻ type channel layer 48 made of an epitaxial thin film is continuously formed in the same apparatus as that in which the damage removing process is performed. Thereafter, the trench 47 is filled with an oxide film or the like, and then the excess N ⁻ type channel layer 48 formed in the non-trench portion is etched back by CMP (Chemical Mechanical Polishing) or the like to remove the oxide film or the like in the trench 47. To do. Thereafter, thermal oxidation is performed to form a gate insulating film 49.

After that, the step of forming the P ⁺ -type contact region 46, the source electrode 52, the drain electrode 53, and the like are formed to complete the trench MOSFET shown in FIG.

In the MOSFET manufactured in this manner, the irregularities on the side surfaces of the trench are reduced in the atomic order, and the N ⁻ type channel layer 48 and the gate oxide film 49 formed thereon are also flat in the channel region. That is, a trench MOSFET that eliminates damage due to trench etching can be realized, and a trench MOSFET having improved channel mobility and gate oxide film life can be produced.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. Since this embodiment is substantially the same as the fourth embodiment, differences from the fourth embodiment will be mainly described.

In the present embodiment, the step of forming the N ⁻ -type channel layer 48 in the fourth embodiment and the subsequent step of filling the trench 47 with an oxide film, the etch-back step, and the step of removing the buried oxide film, etc. are omitted. Thus, an inversion type trench MOSFET is manufactured.

  When creating such an inversion-type trench MOSFET, there is no epitaxial process into the trench 47, but after the trench 47 is formed, a damage removing process is performed as in the fifth embodiment. If surface reaction rate control is used in the first half of the process and gas phase diffusion control is used in the second half of the process, the surface irregularities on the side surfaces of the trench are reduced to the atomic order by the surface reaction rate control in the first half, and The bottom corner can be round with no facet. As a result, a trench MOSFET having excellent breakdown voltage at the time of off and excellent MOS characteristics can be manufactured by a simple process.

(Other embodiments)
You may make it perform the damage removal process shown to each said embodiment by the heat processing in the hydrogen atmosphere containing a hydrocarbon.

Etching of carbon atoms in the silicon carbide crystal is suppressed by the addition of hydrocarbons, the etching rate is lowered as a whole, and the etching reaction is further shifted to the gas phase diffusion rate controlling side. Therefore, by performing the heat treatment in a hydrogen atmosphere containing hydrocarbon in this way, isotropic etching can be easily realized as compared with a hydrogen-only atmosphere. More specifically, it is desirable to use C ₃ H ₈ as the hydrocarbon. Since C ₃ H ₈ has a relatively large number of molecules, it can be easily decomposed, and the vapor pressure at 0 ° C. is 4.8 atm. Therefore, it does not liquefy if diluted with hydrogen. Easy to handle.

  Further, the damage removing step may be performed by heat treatment in a hydrogen atmosphere containing an inert gas such as Ar.

  If the atmospheric pressure does not change, the addition of an inert gas such as Ar will relatively reduce the hydrogen concentration. Therefore, although the diffusion effect of the reaction product is not changed, the etching rate is lowered and is shifted to the gas phase diffusion rate controlling side like the hydrocarbon. Therefore, even when an inert gas such as Ar is added, isotropic etching can be easily realized as compared with an atmosphere containing only hydrogen.

  In the first embodiment, the cross-sectional configuration of the J-FET is simply shown in FIG. 1 and described. However, as shown in FIG. 5 of the fourth embodiment, the surface pattern of the trench 6 has a hexagonal shape with the same internal angle. It is also possible to do. Thereby, the surface orientations of the trench side surfaces become substantially equal, and the effects shown in the second embodiment can be obtained.

  The present invention can also be applied to a semiconductor device such as a PN diode in which a trench is formed in a semiconductor substrate made of silicon carbide and then an epitaxial layer is formed in the trench.

  Further, in each of the above embodiments, the semiconductor device in which the first conductivity type is N-type and the second conductivity type is P-type has been described as an example. However, these are merely examples, and of course, each conductivity type is The present invention can also be applied to a semiconductor device that is inverted.

  In addition, when indicating the orientation of a crystal, a bar (-) should be added to a desired number, but there is a limitation in expression based on a personal computer application. A bar shall be placed in front of the number.

It is a figure showing the section composition of the semiconductor device in a 1st embodiment of the present invention. FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1. It is the figure which showed the form of the etching reaction with respect to the relationship between a substrate temperature and a pressure. It is the figure which showed the manufacturing process of the semiconductor device in 3rd Embodiment of this invention. It is a partial cross section perspective view of the semiconductor device in 4th Embodiment of this invention. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 5. It is the schematic diagram which showed an example of the growth shape of the epitaxial layer. It is a conceptual diagram of the expected growth mode when a trench is formed on the (0001) Si surface, the side surface is an a surface, and the substrate temperature is increased. It is the figure which showed the result of the embedding shape when carrying out embedding growth by changing growth temperature and raw material gas supply amount (substantial growth rate). It is a figure which shows the time change of the growth shape in case the growth temperature is 1625 degreeC and the growth rate is about 2.5 micrometers.

Explanation of symbols

1 and 41 ... ^{N +} -type substrate, 2,42 ... N ^- -type drift layer, 3 ... first gate region, 4 ... N ^- -type region, 5 ... ^{N +} -type source region, 6 ... trench, 7 ... N ^- -type Channel layer, 8 ... second gate region, 9 ... second gate electrode, 10 ... layer insulating film, 11 ... source electrode, 12 ... first gate electrode, 13 ... drain electrode, 20, 45 ... semiconductor substrate, 21 ... LTO film, 31 ... trench, 32 ... carbon film, 43 ... ^{P +} -type base layer, 44 ... ^{N +} -type source layer, 47 ... trench, 48 ... N ^- -type channel layer, 49 ... gate insulating film, 60 ... LTO film .

Claims (23)

A trench mask forming step of forming a trench etching mask (21, 60) on an upper surface of a semiconductor substrate (20, 45) having a (0001) Si surface made of silicon carbide;
Etching using the trench etching mask (21, 60) is performed to form trenches (6, 47) having an aspect ratio of 2 or more and a trench inclination angle of 80 degrees or more in the semiconductor substrate (20, 45). A trench forming step;
A damage removing step of etching and removing a trench etching damage region on the inner surface of the trench (6, 47) formed in the semiconductor substrate (21, 60) in a hydrogen atmosphere at a reduced pressure of 1600 ° C. or higher. A method for manufacturing a silicon carbide semiconductor device. 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a trench mask removing step of removing the trench etching mask (21, 60) before the damage removing step. 3. After the trench mask removing step, a selective mask forming step of forming a selective epitaxial mask (31) in a part of a region different from the trenches (6, 47) on the upper surface of the semiconductor substrate (1) is provided. A method for manufacturing a silicon carbide semiconductor device according to claim 2. The said damage removal process WHEREIN: The corner | angular part of the said trench (6, 47) is rounded by performing the said damage removal by a vapor phase diffusion controlled reaction. Of manufacturing a silicon carbide semiconductor substrate. In the damage removing step, when P is the atmospheric pressure (Pa), T is the substrate temperature (° C.), a is 4.16 × 10 ⁶ , and b is 2.54 × 10 ⁴ , P × 1.33 × The method for manufacturing a silicon carbide semiconductor substrate according to claim 4, wherein the damage removal is performed under a condition satisfying a relationship of 10 ² ≧ a / T−b. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the damage removing step is performed at 1700 ° C. or less. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein in the damage removing step, the damage is removed by a heat treatment in a hydrogen atmosphere containing hydrocarbons. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the damage removing step, the damage is removed by heat treatment in a hydrogen atmosphere containing an inert gas. 9. The distance between the trench patterns is set such that a flat portion of the Si surface is eliminated between the trenches in a subsequent buried layer forming step. A method for manufacturing a silicon carbide semiconductor device according to claim 1. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein a distance between the trench patterns is equal to or less than a trench width. 11. A buried layer forming step of forming an epitaxial layer (7, 48) in the trench (6, 47) at 1500 ° C. or higher by an epitaxial growth method after the damage removing step. A method for manufacturing a silicon carbide semiconductor device according to claim 1. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the buried layer forming step is 1550 ° C. or higher. The method for manufacturing a silicon carbide semiconductor device according to claim 12, wherein the buried layer forming step is performed at 1625 ° C. or higher. The silicon carbide semiconductor according to any one of claims 11 to 13, wherein the damage removing step and the epitaxial layer (7, 48) forming step are continuously performed using the same apparatus. Device manufacturing method. 15. The epitaxial layer forming step according to claim 11, wherein epitaxial growth is performed by vapor phase diffusion rate control so that corners of the epitaxial layer (7, 48) are rounded. The manufacturing method of the silicon carbide semiconductor device of description. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein the epitaxial layer forming step has a growth rate of 2.5 μm / h or less. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the epitaxial layer forming step is performed at 1700 ° C. or lower. 17. The silicon carbide semiconductor device according to claim 11, wherein, in the epitaxial layer forming step, epitaxial growth is performed by containing a gas having an etching action in addition to a source gas and a carrier gas. Production method. 19. The method for manufacturing a silicon carbide semiconductor device according to claim 18, wherein a hydrogen chloride gas is used as the gas having an etching action. 20. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein in the epitaxial layer forming step, concentration control is performed so that the impurity concentration is different between an initial epitaxial stage and a final stage. 21. The method for manufacturing a silicon carbide semiconductor device according to claim 20, wherein in the epitaxial layer forming step, the impurity concentration is controlled to be higher in a final stage than in an initial stage. 22. The trench forming process according to claim 1, wherein the surface pattern of the trench (6, 47) is formed in a stripe shape parallel to the off direction of the semiconductor substrate (20, 45). A method for manufacturing the silicon carbide semiconductor device according to claim 1. 23. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in the trench forming step, the surface pattern of the trench (6, 47) is a hexagonal shape having the same internal angle.

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