JP2008108824A - Silicon-carbide semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a facet face consisting of a single crystal face to the face of a silicon carbide layer, and to improve the element characteristics of a silicon-carbide semiconductor element. <P>SOLUTION: The silicon-carbide semiconductor element has a silicon-carbide substrate 1 having an off angle and a silicon carbide layer 10 formed on the silicon-carbide substrate 1. The face of the silicon carbide layer 10 has the facet faces 9 composed of the monocrystal face, and the facet faces 9 are inclined to an envelope on the face of the silicon-carbide substrate 1. The silicon carbide layer 10 contains a first region 10a forming the facet faces 9 and a second region 10b adjacent to lowest sections 9<SB>L</SB>on the facet faces 9. Highest sections 9<SB>H</SB>in the first region 10a are higher than the face of the second region 10b, and a stepped section with a bottom section more recessed than the lowest sections 9<SB>L</SB>in the facet faces 9 is not formed along at least parts of the end sections of the facet faces 9 on the face of the silicon carbide layer 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor element using silicon carbide and a method for manufacturing the same.

  Silicon carbide (silicon carbide: SiC) is a semiconductor that is expected to be applied to the next generation of low-loss power devices because it has a larger band gap and higher dielectric breakdown field strength than silicon (Si). Material. Silicon carbide has many polytypes such as cubic 3C—SiC and hexagonal 6H—SiC and 4H—SiC. Among these, polytypes generally used for producing a practical silicon carbide semiconductor element are 6H—SiC and 4H—SiC.

Silicon carbide semiconductor elements such as MOSFETs, MESFETs, and Schottky diodes are usually manufactured using a 6H-SiC substrate or a 4H-SiC substrate whose main surface is a plane that substantially matches the (0001) plane perpendicular to the c-axis. Is done. On the 6H—SiC or 4H—SiC substrate (SiC substrate), an epitaxial growth layer serving as an active region of the silicon carbide semiconductor element is formed. An impurity doped layer with a controlled conductivity type and carrier concentration is formed in a selected region of the epitaxial growth layer. The impurity doped layer functions as a P-type well region or an n ⁺ source region in a MOSFET, for example.

  Hereinafter, a general method for forming an epitaxial growth layer on a SiC substrate will be described with reference to the drawings. FIG. 11 is a diagram showing a silicon carbide layer formed by epitaxial growth on the SiC substrate.

  The SiC substrate 40 is, for example, an off-angle substrate having a surface (step structure surface) 40s whose step density is increased by inclining several degrees (off-angle) from the (0001) plane. As shown, the surface 40 s of the SiC substrate 40 has a plurality of atomic level steps 50. The off-angle of a standard off-angle substrate is 8 ° in the [11-20] direction with the (0001) plane as the reference plane for the 4H-SiC substrate, and the (0001) plane as the reference plane for the 6H-SiC substrate [ 11-20] direction is 3.5 °.

  Silicon carbide epitaxial layer 41 is obtained by epitaxially growing silicon carbide on surface 40 s of SiC substrate 40 using step flow 42 by lateral growth in step 50. On surface 41 s of obtained silicon carbide epitaxial layer 41, stepped step 43 resulting from step 50 of SiC substrate 40 is formed. In addition, the height of step 43 is usually larger than the height (0.25 nm) of step 50 in SiC substrate 40, for example, 1 nm or more.

  However, even if a semiconductor element is manufactured using silicon carbide epitaxial layer 41 formed by the above method, it is difficult to obtain electrical characteristics expected from the excellent physical properties of silicon carbide. A silicon carbide MOSFET will be described in detail below as an example.

  In the silicon carbide MOSFET, for example, a gate electrode is provided on the silicon carbide epitaxial layer 41 via a gate oxide film, and a channel is formed on the surface 41s of the silicon carbide epitaxial layer 41. Since step 43 exists on the surface 41s of the layer 41, when the carriers move through the channel, they are scattered by step 43, and the channel state density decreases because the interface state density increases. Such a decrease in channel mobility may cause an increase in power loss of the silicon carbide MOSFET.

  In addition, when activation annealing is performed after ion implantation into the silicon carbide epitaxial layer 41, a bunching step due to atomic migration is formed on the surface of the silicon carbide epitaxial layer 41, so that the channel mobility further decreases.

  On the other hand, Patent Document 1 proposes that a bunching step is formed by activation annealing on a silicon carbide epitaxial layer, and a flat portion (also referred to as “terrace”) in the bunching step is used as a channel portion of the MOSFET. .

  The “bunching step” is a result of sublimation of atoms (Si, C) in the silicon carbide epitaxial layer by performing activation annealing on the silicon carbide epitaxial layer having a minute step on the surface, resulting in a plurality of minute steps. This is a step made up of overlapping steps. Therefore, the size of the bunching step is extremely larger than the step before the activation annealing. For example, the step height before activation annealing is about 1 nm and the terrace width is about 7 nm, while the bunching step height is about 7 to 10 nm and the terrace width is about 100 nm. The definition of step height and terrace width will be described later. Further, in this specification, a step before activation annealing such as step 43 shown in FIG. 11 may be called a “minute step” to be distinguished from a bunching step.

  Since the bunching step is formed by utilizing the migration of atoms on the surface of the silicon carbide epitaxial layer, the flat portion (terrace) does not have a good crystallinity and usually includes a large number of defects. For this reason, even if the flat part of the bunching step is used as a channel, carriers are scattered by defects, so that high channel mobility cannot be obtained. Furthermore, the width of the flat part of the bunching step varies, and there is a problem that the channel length in the MOSFET cannot be designed accurately.

  Patent Document 1 discloses, as one embodiment, a method of providing a step on the surface of the silicon carbide epitaxial layer before activation annealing in order to control the position of the flat portion in the bunching step. (FIG. 3 of Patent Document 1). Hereinafter, this method will be described in detail with reference to the drawings.

  FIG. 12 is a cross-sectional view of a MOSFET obtained by using the method of the above-described embodiment disclosed in Patent Document 1.

  First, silicon carbide epitaxial layer 62 is formed on the surface of SiC substrate 61. Next, ion implantation is performed on silicon carbide epitaxial layer 62 to form P type region 63 and N type region 64. After the ion implantation, two steps 70 are provided on the surface of the silicon carbide epitaxial layer 62 by dry etching. Subsequently, activation annealing is performed to form a bunching step on the surface of the silicon carbide epitaxial layer 62. After that, when silicon carbide is further step-flow grown on the bunching step, step 67 grows from the left end to the right end between the two steps 70 to obtain a flat surface 69 composed of the terrace portion of step 67. . By forming the insulating film 65 and the gate electrode 66 on the flat surface 69, the flat surface 69 can be used as a channel.

According to the above method, since the position of the flat surface 69 can be controlled by the step 70, a decrease in carrier mobility due to the bunching step can be suppressed.
JP 2000-294777 A

  However, in the method of Patent Document 1 described with reference to FIG. 12, since the flat portion of the bunching step includes a number of defects, it is sufficiently high even if silicon carbide is step-flow grown on this surface. It is difficult to obtain a flat surface 69 having crystallinity. Therefore, even if a channel is formed on the flat surface 69, high channel mobility cannot be obtained.

  Further, as can be seen from FIG. 12, since there is a step 70 between the region including the flat surface 69 serving as the channel and the surrounding region on the surface of the silicon carbide epitaxial layer 62, the MOSFET is manufactured in the process. May cause various problems. Since the step 70 is considered to be at least the height of the bunching step, for example, when forming an electrode or a wiring on the silicon carbide epitaxial layer 62, it becomes difficult to perform accurate patterning, and the device characteristics are deteriorated. It becomes a factor. Further, the step 70 may cause a disconnection of wiring, which may reduce the reliability of the MOSFET. Furthermore, the step 70 may cause an electric field concentration in the MOSFET, which may cause deterioration of the breakdown voltage of the MOSFET.

  Thus, according to the conventional method for manufacturing a silicon carbide semiconductor element, a channel having a high carrier mobility is formed due to the presence of minute steps and crystal defects at the MOS interface due to the step structure on the surface of the silicon carbide substrate. Could not be formed. Further, the method described with reference to FIG. 12 has a problem that it is necessary to provide a step 70 in the silicon carbide epitaxial layer, which makes subsequent processes difficult.

  The present invention has been made in view of the above circumstances, and an object thereof is to form an element resulting from a step structure on the surface of a silicon carbide substrate by forming a facet surface composed of a single crystal plane on the surface of the silicon carbide layer. It is to suppress the deterioration of the characteristics.

  A silicon carbide semiconductor element of the present invention includes a silicon carbide substrate having an off-angle and a silicon carbide layer formed on the silicon carbide substrate, and the surface of the silicon carbide layer is configured by a single crystal plane. The facet surface is inclined with respect to an envelope surface on a surface of the carbide substrate, the silicon carbide layer includes a first region in which the facet surface is formed, and the facet A second region adjacent to the lowest portion of the surface, the highest portion of the first region being higher than the surface of the second region, and the surface of the silicon carbide layer has an end of the facet surface A step having a bottom that is recessed from the lowest part of the facet surface is not provided along at least a part of the facet.

  In a preferred embodiment, the level difference between the highest portion in the facet surface and the lowest portion in the second region is 1 μm or less.

  In a preferred embodiment, the facet surface is inclined with respect to an envelope surface on the surface of the silicon carbide substrate.

  The facet surface of the silicon carbide layer may be rectangular when viewed from the normal direction of the silicon carbide substrate.

  The silicon carbide semiconductor element preferably includes a plurality of facet surfaces, and some sides of the plurality of facet surfaces are parallel to each other.

  In a preferred embodiment, the facet plane is composed of a (0001) plane.

  In the silicon carbide semiconductor element, the surface of the second region has a minute step, and the width of the facet surface is larger than the width of the minute step in a cross section perpendicular to the ridge line of the minute step.

  You may further provide the oxide film which covers at least one part of the said facet surface, and the electrode provided on the said oxide film.

  In a preferred embodiment, the transistor has a transistor structure in which a channel is formed in the first region.

  In a preferred embodiment, the semiconductor device further includes an electrode provided on the silicon carbide layer so as to be in contact with at least a part of the facet surface, and at least a part of an interface between the silicon carbide layer and the electrode is a Schottky. It forms a barrier.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes a step (A) of preparing a silicon carbide substrate having an off angle and having a first silicon carbide layer formed on a surface thereof, and the first silicon carbide. A step (B) of forming a mask layer on the layer, and a step (C) of epitaxially growing a second silicon carbide layer on a portion of the first silicon carbide layer not covered with the mask layer. And the surface of the said 2nd silicon carbide layer has a facet surface comprised from a single crystal plane.

  In a preferred embodiment, the end face of the mask layer has a portion extending along a direction perpendicular to the progress direction of step flow growth in the second silicon carbide layer in the envelope surface of the surface of the silicon carbide substrate.

  The manufacturing method includes the step (D) of implanting impurity ions into at least a part of the first and second silicon carbide layers, and the first and second silicon carbide layers implanted with the impurity ions. A step (E) of performing activation annealing, and the steps (D) and (E) may be performed after the step (C).

  Including a step of providing a cap layer made of carbon on the surfaces of the first and second silicon carbide layers before the step (E), and a step of removing the cap layer after the step (E). May be included.

  The mask layer may be rectangular when viewed from the normal direction of the silicon carbide substrate.

  When viewed from the normal direction of the silicon carbide substrate, at least one side of the mask layer may be perpendicular to the direction of progress of step flow growth in the second silicon carbide layer.

  In a preferred embodiment, the step (B) is a step of forming a plurality of island-shaped mask layers on the first silicon carbide layer, as viewed from the normal direction of the silicon carbide substrate. At least one side of each of the plurality of mask layers is parallel to each other.

  In a preferred embodiment, the step (B) is a step of forming a plurality of island-shaped mask layers on the first silicon carbide layer, as viewed from the normal direction of the silicon carbide substrate. At least one side of each of the plurality of mask layers is parallel to the direction of progress of step flow growth in the second silicon carbide layer, and the length of at least one side parallel to the direction of progress of step flow growth is: It is smaller than the interval between adjacent mask layers.

  The thickness of the mask layer may be greater than the thickness of the second silicon carbide layer.

  The mask layer may have a thickness of 10 nm to 1 μm.

  The mask layer may include carbon.

  Another method of manufacturing a silicon carbide semiconductor device of the present invention includes (A) a step of preparing a silicon carbide substrate having an off angle, (B) a step of forming a mask layer on the silicon carbide substrate, and (C And a step of epitaxially growing a silicon carbide layer on a portion of the silicon carbide substrate that is not covered with a mask layer, the silicon carbide layer having a facet plane composed of a single crystal plane.

  Another silicon carbide semiconductor device of the present invention includes a silicon carbide substrate having an off-angle and a silicon carbide layer formed on a part of the surface of the silicon carbide substrate, and the surface of the silicon carbide layer is a single surface. Having facet planes composed of crystal planes.

  According to the present invention, since a facet surface having excellent crystallinity can be formed on the surface of the silicon carbide layer, a silicon carbide semiconductor element having high element characteristics can be provided. When the present invention is applied to a MOSFET, by using the facet surface as a channel, scattering of carriers due to a minute step or a bunching step caused by an off angle of the silicon carbide substrate at the MOS interface is suppressed, and the interface state is reduced. Since the density can be suppressed, the channel resistance can be reduced.

  Further, according to the present invention, since the size and position of the facet surface can be controlled without providing a relatively large step on the surface of the silicon carbide layer, it is possible to prevent deterioration of element characteristics and reliability due to such a step.

  Furthermore, according to the present invention, the silicon carbide semiconductor element as described above can be manufactured by a simple process.

  A silicon carbide semiconductor device according to a preferred embodiment of the present invention includes a silicon carbide substrate having a step structure surface and a silicon carbide layer formed on the silicon carbide substrate. A facet plane composed of the crystal plane is formed. In the present specification, the “facet plane” means a flat plane that is composed of a single crystal plane and does not have minute steps corresponding to the step structure of the silicon carbide substrate. By using this facet surface as a channel of, for example, a MOSFET, it is possible to suppress deterioration in element characteristics due to the step structure of the silicon carbide substrate.

  Hereinafter, an example of a method for forming a facet surface in a preferred embodiment of the present invention will be described with reference to FIG. Here, a 4H—SiC substrate having an off angle of 8 ° in the <11-20> direction is used as the silicon carbide substrate.

  First, as shown in FIG. 1A, a silicon carbide epitaxial layer 2 is formed on the silicon surface of silicon carbide substrate 1, that is, on the (0001) surface. As described above, since the surface of silicon carbide substrate 1 has an off angle of 8 °, minute step 4 corresponding to the surface structure of silicon carbide substrate 1 exists on the surface of silicon carbide epitaxial layer 2.

  Here, the structure of step 4 will be described in detail. FIG. 2 is an enlarged cross-sectional view of step 4, showing a cross section perpendicular to the envelope surface placed on the surface of silicon carbide substrate 1 and orthogonal to the ridge line direction of step 4. Note that FIG. 2 is schematically exaggerated for easy understanding. In the illustrated example, the normal line N of the envelope surface S on the surface of the silicon carbide substrate 1 is inclined in the <11-20> direction from the (0001) plane, and the inclination angle is an off angle ( Here, it is equal to 8 °). The cross-sectional shape of step 4 is a substantially triangular shape including a terrace 7t having a width W made of a (0001) plane and a step side wall 7w having a height H. The height H of Step 4 is 0.25 nm or more, which is the lattice spacing of silicon carbide, and is generally 1 nm or more.

  Next, as shown in FIG. 1B, mask layer 5 is formed on the surface of silicon carbide epitaxial layer 2. Here, two island-shaped mask layers 5 are arranged so as to sandwich a portion of the surface of silicon carbide layer 2 where a facet surface is to be formed. The mask layer 5 needs to have sufficient heat resistance that can withstand an epitaxial thin film forming step, which will be described later, and is made of, for example, a carbon film. The mask layer 5 can be formed by sputtering or CVD. Further, the planar shape of mask layer 5 viewed from the normal direction of silicon carbide substrate 1 is, for example, a rectangle having a long side along the <1-100> direction. The thickness of the mask layer 5 is preferably about the same as or larger than the thickness of the epitaxial thin film formed in the process described later, for example, 0.3 μm.

  Next, as shown in FIGS. 1C and 1D, an N-type impurity having the same concentration as that of silicon carbide epitaxial layer 2 is formed on the surface of silicon carbide epitaxial layer 2 where mask layer 5 is not formed. An epitaxial thin film 8 containing is formed. At this time, with the progress of step flow growth, a facet surface 9 made of (0001) appears on the surface of the silicon carbide epitaxial layer 2 where the mask layer 5 is not formed (FIG. 1C). ). When the step flow growth is further advanced, facet surfaces 9 are formed over the interval of the mask layer 5 (FIG. 1 (d)). In this way, silicon carbide layer 10 is obtained. In the present specification, silicon carbide epitaxial layer 2 and epitaxial thin film 8 are collectively referred to as a “silicon carbide layer”.

  The thickness of the epitaxial thin film 8 is set sufficiently larger than the height H in Step 4 and is, for example, 0.3 μm. As described above, when epitaxial growth is performed only on the portion opened by the mask layer 5, the facet plane 9 composed of the (0001) plane can be formed by optimizing the epitaxial growth conditions. In the present embodiment, silicon carbide epitaxial layer 2 and epitaxial thin film 8 are formed under the same epitaxial growth conditions and contain the same impurities at the same concentration, but the growth conditions and the types and concentrations of the impurities are different. It may be.

  Thereafter, although not shown, mask layer 5 is removed from silicon carbide layer 10. When the mask layer 5 is a carbon mask, the mask layer 5 is thermally oxidized to be removed as a reaction product such as carbon monoxide or carbon dioxide, so that the mask is not damaged on the surface of the silicon carbide layer 10. Layer 5 is preferred because it can be removed almost completely.

  The facet surface 9 in this embodiment is a (0001) surface having extremely high crystallinity because it is formed without activation annealing. Therefore, when this facet surface 9 is used as a channel, carrier scattering does not occur at the oxide film-semiconductor (MOS) interface, and the interface state density can be reduced, so that the channel mobility is increased and the current density is reduced. A high current can flow. In addition, a silicon carbide semiconductor element with little variation in electrical characteristics can be realized. Further, since the size and position of the facet surface 9 can be arbitrarily controlled by the design of the mask layer 5, the channel length and the like can be easily designed.

  On the other hand, in Patent Document 1 described above, a bunching step is formed on the surface of the silicon carbide layer by activation annealing, and a flat portion between the bunching steps is used as a channel. Alternatively, a flat surface obtained by step-flowing silicon carbide on such a flat portion is used as a channel. However, since the facet surface in Patent Document 1 is formed by migration on the surface of the silicon carbide layer, it is not a surface with good crystallinity but includes a large number of defects. For this reason, when used as a channel of a MOSFET, carriers are scattered by defects, resulting in a decrease in channel mobility. Moreover, the dimensions of the flat part in the bunching step vary, and the channel length cannot be designed accurately.

  Next, the structure of the silicon carbide semiconductor element of this embodiment is demonstrated.

The silicon carbide semiconductor element of the present embodiment includes a facet surface 9 formed by the above method. Facet surface 9 is inclined with respect to the envelope surface on the surface of silicon carbide substrate 1. The facet surface 9 shown in FIG. 1D is an inclined surface having the lowest end portion 9 _L defined by the end surface of the one mask layer 5 and the highest end portion 9 _H.

Silicon carbide layer 10 has a first region 10a which facet 9 is formed and a second region 10b adjacent to the lowest portion 9 _L of facets 9. Since first region 10a is composed of silicon carbide epitaxial layer 2 and epitaxial thin film 8, it is equivalent to the thickness of epitaxial thin film 8 (for example, 10 nm or more and 1 μm or more) than second region 10b composed only of silicon carbide epitaxial layer 2. Only) is higher. However, the level difference d between the surface of the first region 10a where the facet surface 9 is formed and the surface of the second region 10b is sufficiently larger than the step 70 formed in the conventional MOSFET described above with reference to FIG. Is 10 nm or less, more preferably 1 μm or less. In the present specification, the level difference d refers to a difference between a point 9 _H having the highest level in the first region 10a and a point having the lowest level on the surface of the second region 10b.

In the conventional MOSFET shown in FIG. 12, a step 70 having a bottom portion that is recessed from the lowest portion of the facet surface is provided on the surface of the silicon carbide layer along the end of the facet surface. On the other hand, in the silicon carbide layer 10 in the present embodiment, no step having such a low bottom is formed along the end of the facet surface 9. Level of the surface of the region 10b adjacent to the facet 9, the lowest part (closer to the traveling direction of the starting point of the step flow growth of the ends of the facets 9) 9 _L level comparable among the facets 9 Or higher. When microscopically explained, on the surface of the second region 10b, is typically a plurality of minute step 4 is formed, the level of the lowest portion 9 _L of facets 9, those steps 4 is approximately equal to the level of the valley line portion. Thus, since the silicon carbide layer 10 in the present embodiment is not provided with a relatively large step, a highly reliable silicon carbide semiconductor element can be manufactured without making the subsequent manufacturing process difficult.

  Second region 10b in the present embodiment may have a plurality of minute steps due to the off-angle of silicon carbide substrate 1, or may have a bunching step formed by activation annealing. . In addition, it is preferable that the bunching step is not formed in the 2nd area | region 10b, and such a structure is obtained by performing activation annealing with respect to a silicon carbide layer, for example using a cap layer so that it may mention later.

  In the present embodiment, as shown in FIG. 1 (d), it is preferable that the facet surface 9 is formed from one end of the interval of the mask layer 5 to the other end. Thereby, not only the facet surface 9 having a larger area can be obtained, but also the size of the facet surface 9 can be controlled according to the design of the mask layer 5. The interval between the mask layers 5 can be optimized according to the thickness of the epitaxial thin film 8, which will be described later.

  In addition, the facet surface 9 in this embodiment should just be formed in at least one part among the surfaces of the epitaxial thin film 8. FIG. Depending on the thickness of the epitaxial thin film 8, as shown in FIG. 1C, the facet surface 9 is formed only in the portion near the start point in the step flow growth direction in the interval of the mask layer 5, and in the portion close to the end point There may be steps remaining.

  Since the silicon carbide semiconductor element of this embodiment is provided with facet surface 9 obtained by the above method, high element characteristics and reliability can be realized. For example, when a MOSFET is manufactured by forming an oxide film and an electrode on the facet surface 9 in the silicon carbide layer 10 in this order, a good MOS interface can be formed with a high gate breakdown voltage. it can. Alternatively, when a Schottky diode is manufactured by forming a Schottky electrode that contacts the facet surface 9 in the silicon carbide layer 10, there is no unevenness on the surface of the silicon carbide layer, so that electric field concentration does not occur and high breakdown voltage characteristics can be realized. .

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. Here, a method of forming a silicon carbide layer having a facet surface on the surface will be described in detail.

  First, the structure of a heating furnace used in the process of epitaxially growing silicon carbide in this embodiment will be described with reference to FIG.

  The heating furnace shown in FIG. 3 includes a reaction furnace 150 and a coil 154 for heating the reaction furnace 150. The coil 154 is provided around the reaction furnace 150 and heats the reaction furnace 150 by high frequency induction heating. A chamber 163 supported by a support shaft 153 is provided inside the reaction furnace 150. The chamber 163 is covered with a heat insulating material 162. A susceptor 152 made of carbon is disposed inside the chamber 163. A sample 151 such as a silicon carbide substrate is fixed to the chamber 163 by the susceptor 152. The chamber 163 is connected to a gas exhaust system 159 and a gas supply system 158, respectively. The gas exhaust system 159 includes an exhaust gas pipe 160 and a pressure adjustment valve 161, and exhausts the gas in the chamber 163 as necessary. The gas supply system 158 supplies an argon gas 155, a source gas 156 used for epitaxial growth of silicon carbide, an oxygen gas 157, and the like to the chamber 163 as necessary.

  Next, a method for forming a silicon carbide layer in the present embodiment will be described. 4A to 4C are process cross-sectional views for explaining the method for forming the silicon carbide layer of the present embodiment. FIGS. 5A and 5B are respectively the same as FIG. FIG. 5 is a perspective view corresponding to FIG.

  First, as shown in FIG. 4A, silicon carbide epitaxial layer 2 is grown on silicon carbide substrate 1. As the silicon carbide substrate 1, for example, a silicon carbide substrate (4H−) having a diameter of 75 mm having an off angle of 8 degrees in the [11-20] (112 bar 0) direction with respect to the (0001) plane is normal to the envelope surface of the substrate surface SiC substrate) is used.

Silicon carbide epitaxial layer 2 is formed, for example, as follows. First, silicon carbide substrate 1 is installed in chamber 163 of the heating furnace shown in FIG. Thereafter, high frequency power of 20.0 kHz and 20 kW is applied to induction heating coil 154 to heat silicon carbide substrate 1 to, for example, 1600 ° C. by induction heating. A silicon carbide source gas 156 is supplied from a gas supply system 158 to a chamber 163 together with a carrier gas, and a silicon carbide layer (thickness: 10 μm, for example) 2 is epitaxially grown on the substrate 1 by a CVD method. As the source gas 156, for example, monosilane (SiH ₄ ) and propane (C ₃ H ₈ ) are used. The carrier gas is, for example, hydrogen.

  After silicon carbide epitaxial layer 2 is formed, mask layer 5 made of carbon is formed on the surface of silicon carbide epitaxial layer 2 using a sputtering apparatus, as shown in FIGS. 4B and 5A. In the present embodiment, first, a resist layer (not shown) having an opening is provided on the silicon carbide epitaxial layer 2. The shape of the opening of the resist layer (that is, the planar shape of the mask layer 5) is, for example, a rectangle. Further, the opening is arranged so that the long side thereof coincides with the <1-100> direction. Thereafter, carbon is used as a target of the sputtering apparatus, and a carbon film (not shown) having a thickness of 0.3 μm is formed on the resist layer and the silicon carbide epitaxial layer 2 by sputtering. The carbon film can be formed by sputtering in an Ar gas atmosphere at a pressure of 0.5 Pa and an RF power of 1500 W. Subsequently, by peeling the resist layer from silicon carbide epitaxial layer 2 (lift-off method), rectangular mask layer 5 is formed in the region defined by the opening of the resist layer on the surface of silicon carbide epitaxial layer 2. The

  Next, as shown in FIG. 4C and FIG. 5B, silicon carbide is further epitaxially grown on the portion of the silicon carbide epitaxial layer 2 that is not covered with the mask layer 5, thereby removing the (0001) plane. An epitaxial thin film 8 having a faceted surface 9 is formed. Thereby, silicon carbide layer 10 formed of silicon carbide epitaxial layer 2 and epitaxial thin film 8 is obtained.

The epitaxial thin film 8 is formed as follows, for example. First, silicon carbide substrate 1 on which mask layer 5 is formed is placed in chamber 163 of the heating furnace shown in FIG. Thereafter, a high frequency power of 20.0 kHz and 20 kW is applied to the induction heating coil 154 to heat the substrate 1 to, for example, 1600 ° C. by induction heating. A silicon carbide source gas 156 is supplied from a gas supply system 158 to a chamber 163 together with a carrier gas, and an epitaxial thin film (thickness: 0.2 μm, for example) 8 is formed on the silicon carbide epitaxial layer 2 by a CVD method. As the source gas 156, for example, monosilane (SiH ₄ ) and propane (C ₃ H ₈ ) are used. The carrier gas is, for example, hydrogen.

  Here, since the surface morphology of the epitaxial thin film 8 formed by the above method was examined, the method and result will be described.

  Analysis of the surface morphology of the epitaxial thin film 8 was performed using an atomic force microscope (AFM).

  For comparison, after forming a silicon carbide epitaxial layer on a silicon carbide substrate, an epitaxial thin film is grown on the silicon carbide epitaxial layer without forming a mask layer, and the silicon carbide layer of Comparative Example 1 is formed. Produced. The silicon carbide layer of Comparative Example 1 was formed by the same method and conditions as in Embodiment 1 except that the mask layer was not formed on the surface.

  From the measurement result of the surface morphology, the surface roughness Ra of the facet surface 9 in the silicon carbide layer 10 obtained in the present embodiment is about 0.1 nm, which is below the measurement limit of AFM. On the other hand, the surface roughness Ra of the silicon carbide layer of Comparative Example 1 was 10 nm, and it was confirmed that the surface roughness of the silicon carbide layer can be reduced by two orders of magnitude or more by the epitaxial growth process using the mask layer 5. In addition, "surface roughness Ra" in this specification is defined by arithmetic average roughness Ra standardized by JISB0601-1994.

  The thickness of the mask layer 5 in this embodiment needs to have a sufficient thickness to limit step flow growth, and is, for example, 10 nm or more, more preferably 30 nm or more. Further, if the thickness of the mask layer 5 is equal to or more than the thickness of the epitaxial thin film 8, it is advantageous because the step flow growth can be surely limited. On the other hand, from the viewpoint of the process, the thickness of the mask layer 5 is preferably 1 μm or less.

  In addition, the thickness of the epitaxial thin film 8 in the present embodiment is appropriately selected according to the width of the facet surface to be formed in the step flow growth direction, but is preferably several times the height of Step 4 or more. For example, it is 10 nm or more, more preferably 30 nm or more. Further, assuming that the number of Steps 4 existing in the region sandwiched between the mask layers 5 in the surface of the silicon carbide epitaxial layer 2 is n, if the height H of Step 4 (for example, 1 nm) is n times or more, This is advantageous because the facet surface 9 can be formed over the interval of the mask layer 5. On the other hand, from the viewpoint of process, the thickness of the epitaxial thin film 8 is preferably 1 μm or less.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Here, a method of forming a silicon carbide layer having a plurality of facet surfaces on the surface will be described.

  6A to 6C are schematic cross-sectional views for explaining the method for forming the silicon carbide layer of the present embodiment.

  First, as shown in FIG. 6A, silicon carbide epitaxial layer 2 is grown on silicon carbide substrate 1. As a silicon carbide substrate 1, a silicon carbide substrate (4H-SiC substrate) having a diameter of 75 mm in which the normal of the envelope surface of the substrate has an off angle of 8 degrees in the [11-20] (112 bar 0) direction from the (0001) plane ) Is used. Silicon carbide epitaxial layer 2 is formed by a method similar to the method described above with reference to FIG.

  Next, as shown in FIG. 6B, a plurality of mask layers (thickness: 0.3 μm, for example) 15 are formed on the silicon carbide epitaxial layer 2 using a sputtering apparatus. The mask layer 15 can be formed by the same method as described above with reference to FIG. Specifically, a resist layer (not shown) having an opening is provided on silicon carbide epitaxial layer 2. The resist layer in the present embodiment has a plurality of openings, and each opening has a rectangular shape with long sides extending along the <1-100> direction. Further, these openings are arranged at a predetermined interval so that the long sides thereof are parallel to each other. Thereafter, a plurality of mask layers 15 are obtained by depositing carbon in the openings of the resist layer by sputtering.

  In the present embodiment, the distance D between adjacent mask layers 15 is designed to be larger than the length L of the side extending along the step flow growth direction in each mask layer 15. Thereby, a facet surface having a larger area can be formed. Specifically, the side length L is 0.5 μm, and the distance D between the adjacent mask layers 15 is 1.5 μm.

  Here, as a result of considering how the mask layer 15 should be arranged in order to form facet surfaces parallel to each other, the present inventors have found a method for calculating a preferable distance D between adjacent mask layers 15. So, I will explain in detail.

  FIG. 7 is an enlarged view showing epitaxial thin film 12 formed on silicon carbide epitaxial layer 2 in a process to be described later, and is a direction perpendicular to silicon carbide substrate 1 and in which step flow growth proceeds (arrow G). A cross-section parallel to FIG.

  When the epitaxial thin film 12 having a thickness T is grown on the silicon carbide epitaxial layer 2, when the off angle of the silicon carbide substrate 1 is X, the facet surface 11 has a length of T / tanX ° in the step flow growth direction G. Is formed. Therefore, when the distance D of the mask layer 15 in the step flow growth direction G is T / tanX °, facet surfaces 11 parallel to each other can be formed at each distance of the mask layer 15. In this embodiment, since the off angle X of the silicon carbide substrate 1 is 8 °, when the thickness of the epitaxial thin film 12 is 0.2 μm, a suitable distance D of the mask layer 15, that is, T / tanX ° is about 1.5 μm. It becomes.

  After forming mask layer 15, as shown in FIG. 6C, epitaxial thin film 12 is grown on silicon carbide epitaxial layer 2 to form facet surface 11 composed of a plurality of (0001) planes. The thickness of the epitaxial thin film 12 is 0.2 μm. The method for forming the epitaxial thin film 12 is the same as that described above with reference to FIG. In this way, silicon carbide layer 20 including silicon carbide epitaxial layer 2 and epitaxial thin film 12 is obtained.

  Each of the formed facet surfaces 11 has a rectangular shape extending perpendicularly to the step flow growth direction on the surface of silicon carbide layer 20. When the dimension of facet surface 11 is measured, in the cross section perpendicular to silicon carbide substrate 1 and parallel to the step flow growth direction, the width of each facet surface 11 is 1.5 μm, and the width of adjacent facet surface 11 is 0.5 μm. It was confirmed that the mask layer 15 was formed as designed.

  Next, when the surface morphology of the facet surface 11 in the silicon carbide layer 20 was examined, the surface roughness Ra was about 0.1 nm, which was below the measurement limit of AFM. Similar to the first embodiment described above, the surface roughness Ra can be reduced by two orders of magnitude or more when compared with the silicon carbide layer (surface roughness Ra: 10 nm) of Comparative Example 1 manufactured without forming the mask layer. I understood.

  According to the above method, the plurality of facet surfaces 11 can be formed by forming a plurality of mask layers 15 on the surface of the silicon carbide epitaxial layer 2 and performing epitaxial growth. Further, by optimizing the arrangement of the mask layer 15, the facet surfaces 11 parallel to each other can be formed.

  The method of this embodiment is particularly advantageous when applied to a silicon carbide element composed of a plurality of unit cells.

  The methods of the first and second embodiments described above are not limited to the methods described above with reference to FIGS.

  Silicon carbide substrate 1 in the first and second embodiments may be an off-angle substrate having a step structure surface formed by tilting the substrate plane orientation by several degrees from the basic crystal plane ((0001) plane). In addition, although 4H—SiC is used as the silicon carbide substrate 1 in this embodiment, a substrate made of a polytype other than 4H—SiC may be used. .

  Further, instead of epitaxially growing silicon carbide layer 10 on the silicon surface of silicon carbide substrate 1, that is, (0001) surface, silicon carbide layer 10 may be epitaxially grown on the carbon surface, ie, (000-1) surface.

  The formation method of the mask layers 5 and 15 is not limited to the sputtering method, and a CVD method or a vapor deposition method may be used. The material of the mask layers 5 and 15 is not limited to carbon, and may be diamond or molybdenum.

  Furthermore, the planar shapes of the mask layers 5 and 15 are all rectangular, but the planar shapes of the mask layers 5 and 15 may be other shapes. However, the planar shape of mask layers 5 and 15 preferably has sides extending in a direction perpendicular to the step flow growth direction in the envelope surface of the surface of silicon carbide substrate 1. 11 are obtained. Mask layers 5 and 15 may have a shape surrounding a region of silicon carbide epitaxial layer 2 where a facet plane is to be formed. Furthermore, the mask layers 5 and 15 do not need to be provided discretely, and may be, for example, a continuous film having a plurality of openings that define facet surfaces.

  Regardless of the planar shape of mask layers 5 and 15, the end surfaces of mask layers 5 and 15 have a portion extending in a direction perpendicular to the step flow growth direction on the envelope surface of silicon carbide substrate 1. Preferably, the end portions of the facet surfaces 9 and 11 are defined by such end surfaces.

  In both the first and second embodiments described above, the mask layers 5 and 15 are disposed at both ends of the region of the silicon carbide epitaxial layer 2 where the facet plane is to be formed. The facet surfaces 9 and 11 can appear if they are arranged at at least one end of the region where the facet surface is to be formed.

  Instead of forming silicon carbide epitaxial layer 2 on silicon carbide substrate 1, impurity ions may be implanted into silicon carbide substrate 1 to provide a silicon carbide layer. In that case, a facet surface can be formed on the surface of the epitaxial thin film by forming a mask layer directly on the surface of silicon carbide substrate 1 and forming an epitaxial thin film on a portion not covered with the mask layer.

(Third embodiment)
Hereinafter, a silicon carbide semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. The silicon carbide semiconductor element of this embodiment is a MOSFET.

  The silicon carbide MOSFET of the present embodiment is manufactured by, for example, a method described below. FIGS. 8A to 8C and FIGS. 9A to 9C are process cross-sectional views for explaining the method for manufacturing the silicon carbide MOSFET of this embodiment.

First, as shown in FIG. 8A, mask layer 25 is formed on the surface of silicon carbide epitaxial layer 22 formed on silicon carbide substrate 21. As the silicon carbide substrate 21, for example, a 4H—SiC substrate having a diameter of 75 mm and having an off angle of 8 degrees in the [11-20] (112 bar 0) direction from the (0001) plane is used. Silicon carbide substrate 21 has an N conductivity type and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ . Formation of silicon carbide epitaxial layer 22 can be performed by a CVD method using a heating furnace shown in FIG. Here, a silicon carbide layer (thickness: 10 μm) 22 doped with N-type impurities is epitaxially grown on the main surface of silicon carbide substrate 21. The source gas and carrier gas used to form the silicon carbide epitaxial layer 22 are the same as those used in the first and second embodiments. However, in the present embodiment, a doping gas (N ₂ ) having a constant flow rate is mixed into the source gas. The carrier concentration of the silicon carbide layer 22 is controlled by the flow rate of the doping gas, and is about 5 × 10 ¹⁵ cm ⁻³ here.

  The mask layer 25 is a carbon mask layer formed by a method similar to the method described above with reference to FIG. Each mask layer 25 is a rectangle having a long side along the <1-100> direction when viewed from the normal direction of silicon carbide substrate 21. Here, only two mask layers 25 arranged at intervals are shown, but typically three or more mask layers 25 are arranged in parallel to each other. The thickness of each mask layer 25 is 0.3 μm.

  Next, as shown in FIG. 8B, silicon carbide is further epitaxially grown on a portion of the silicon carbide epitaxial layer 22 that is not covered with the mask layer 25, thereby epitaxially having a (0001) facet surface 91. A thin film 92 is formed. The formation method and conditions of the epitaxial thin film 92 are the same as those described above with reference to FIG. In this embodiment, the thickness of the epitaxial thin film 92 is 0.2 μm.

  Silicon carbide epitaxial layer 22 and epitaxial thin film 92 contain the same impurities at the same concentration. Hereinafter, silicon carbide epitaxial layer 22 and epitaxial thin film 92 are collectively referred to as silicon carbide layer 20.

  Subsequently, as illustrated in FIG. 8C, a plurality of first impurity ion implantation layers (thickness: for example, 1.5 μm to 2 μm) 23 ′ are formed in selected regions of the silicon carbide layer 20.

A specific forming method will be described. First, a first implantation mask 33 made of, for example, a silicon oxide film (SiO ₂ ) is formed on the surface of the silicon carbide layer 20. The first implantation mask 33 has an opening that defines a region of the silicon carbide layer 20 that becomes the first impurity ion implantation layer 23 ′. The shape of the first implantation mask 33 can be arbitrarily formed by photolithography and etching. The thickness of the first implantation mask 33 is determined by its material and implantation conditions, but is preferably set sufficiently larger than the implantation range. Next, P-type impurity ions (Al ions) are implanted into the silicon carbide layer 20 from above the first implantation mask 33. Impurity ion implantation is performed in multiple stages. After the ion implantation, the first implantation mask 33 is removed. Thereby, first impurity ion implanted layer 23 ′ is formed in the region of silicon carbide layer 20 where the impurity ions are implanted. Further, the region of the silicon carbide layer 20 that is left without being implanted with impurity ions is an N-type drift region 35.

  Subsequently, as shown in FIG. 9A, a second impurity ion implantation layer 24 ′ defining a P-type contact region and an N-type source region are defined inside the first impurity ion implantation layer 23 ′. A third impurity ion implantation layer (thickness: 0.5 μm to 2 μm, for example) 26 ′ is formed. Here, similarly to the method described with reference to FIG. 8C, after forming a second implantation mask (not shown) on the silicon carbide layer 20, P-type impurity ions (Al ions) are formed. As a result, a second impurity ion implantation layer 24 'is formed. Similarly, after forming a third implantation mask (not shown) on the silicon carbide layer 20, N-type impurity ions (N ions) are implanted to form a third impurity ion implantation layer 26 ′. Form.

Thereafter, as shown in FIG. 9B, activation annealing is performed on the first, second, and third impurity ion implantation layers 23 ′, 24 ′, and 26 ′, and P-type well regions ( A carrier concentration: 1 × 10 ¹⁷ cm ⁻³ ) 23, a contact region (carrier concentration: 1 × 10 ¹⁹ cm ⁻³ ) 24 and an N-type source region 26 are formed. In the present embodiment, the well region 23 and the source region 26 are arranged so that at least a part of the surface of each P-type well region 23, that is, a region where a channel is formed is constituted by the facet surface 91. When a cap layer described later is not used, a bunching step may be formed in a region other than the facet surface in the surface of the silicon carbide layer 20 by the high-temperature activation annealing process. No bunching step is formed, and its flatness is maintained.

  Finally, as shown in FIG. 9C, a gate insulating film 28, a source electrode 29, a drain electrode 30, and a gate electrode 31 are formed. Thereby, silicon carbide semiconductor element (MOSFET) 100 is obtained.

  Gate insulating film 28 is formed on silicon carbide layer 20 by thermally oxidizing silicon carbide substrate 21 at a temperature of 1100 ° C. The gate insulating film 28 needs to overlap at least part of the facet surface 91. The thickness of the gate insulating film 28 is, for example, 30 nm.

  The source electrode 29 and the drain electrode 30 can be formed as follows, for example. First, a Ni film is deposited so as to be in contact with the contact region 24 using an electron beam (EB) vapor deposition apparatus. A Ni film is also deposited on the back surface of the silicon carbide substrate 21. Subsequently, these Ni films are heated at a temperature of 1000 ° C. using a heating furnace. As a result, a source electrode 29 that is in ohmic contact with the contact region 24 and a drain electrode 30 that is in ohmic contact with the back surface of the substrate 21 are formed. On the other hand, the gate electrode 31 is formed by evaporating aluminum on the gate insulating film 28.

  In the obtained silicon carbide semiconductor device 100, the shallow surface layer of the P-type well region 23 located below the gate electrode 31 is inverted to N-type by the voltage applied to the gate electrode 31 (inversion channel). A current can flow from the drain electrode 30 to the source electrode 29 (ON state).

  8 and 9, only a part of adjacent well region 23 is shown, silicon carbide semiconductor element 100 typically has a structure in which a large number of well regions 23 are arranged. Yes.

  In order to suppress the formation of step bunching by activation annealing, a cap layer may be formed on the surface of silicon carbide layer 20 before the ion implantation step in the above method. The cap layer may be a carbon layer formed by heating the silicon carbide substrate 21 in a vacuum atmosphere to graphitize the surface of the silicon carbide layer 20, or a carbon layer formed by a known deposition method. It may be. After forming the cap layer, impurity ions are implanted into the silicon carbide layer 20 through the cap layer. Subsequently, an annealing process for activating the implanted impurity ions is performed. Thereafter, the cap layer is removed from the surface of silicon carbide layer 20. When the cap layer is a carbon layer, it is preferable to remove the carbon layer by thermal oxidation.

  When activation annealing is performed using the cap layer, a bunching step is not formed in a region other than the region where the facet surface 91 is formed in the surface of the silicon carbide layer 20, and a minute step formed by step flow growth is formed. Remains. Therefore, it is possible to suppress the deterioration of element characteristics due to the bunching step. In this case, the width of the facet surface 91 is larger than the width of the minute step in the step flow growth direction.

  Silicon carbide semiconductor device 100 of the present embodiment is composed of a large number of unit cells defined by well region 23. FIG. 10 is a plan view showing an example of the configuration of silicon carbide semiconductor element 100. The arrangement method of the unit cells is not particularly limited. However, as shown in the drawing, the unit cells may be arranged with a ½ pitch shift in the column direction (or row direction) for each column (or for each row).

  As shown in FIG. 10, in silicon carbide semiconductor device 100, channel portions in a plurality of unit cells are arranged on one rectangular facet surface 91. Therefore, since the above-described inversion channel can be formed on the facet surface 91 having high crystallinity, the channel mobility can be improved as compared with the conventional case. The planar shape and arrangement of the facet surface 91 are not limited to this example, and at least a part of the surface of the well region 23 located below the gate electrode 31 only needs to be configured by the facet surface 91.

  According to the above method, a high performance silicon carbide semiconductor element having a good facet surface 91 on the surface of silicon carbide layer 20 can be formed by a simple process.

  In the above method, facet surface 91 is formed by performing additional epitaxial growth on a part of silicon carbide layer 20 before activation annealing is performed on silicon carbide layer 20. Therefore, compared with the method of Patent Document 1 in which step bunching is formed by activation annealing, a good facet surface with few crystal defects can be formed, and device characteristics can be improved.

  Further, in the above method, mask layer 25 is provided on silicon carbide epitaxial layer 22, and additional epitaxial growth is performed on a portion of silicon carbide epitaxial layer 22 that is not covered with mask layer 25. Therefore, the size and position of the facet surface can be easily controlled. Further, unlike the method of Patent Document 1, it is not necessary to provide a relatively large step in the silicon carbide epitaxial layer in order to control the position where the facet surface is formed. The influence on reliability can be prevented.

  Next, since the surface roughness of facet surface 91 in silicon carbide semiconductor element 100 was examined, the measurement result will be described.

  First, the surface morphology of the epitaxial thin film 92 shown in FIG. 8B was measured by the same method as described in the first embodiment. As a result, it was confirmed that the surface roughness Ra of the facet surface 91 was 0.1 nm or less.

  For comparison, a silicon carbide semiconductor element (MOSFET) of Comparative Example 2 is manufactured in the same manner as described above with reference to FIGS. 8 and 9 except that no mask layer is formed on the surface of the silicon carbide layer. Was made. When the surface morphology of the epitaxial thin film further formed on the silicon carbide layer was examined when producing the silicon carbide semiconductor device of Comparative Example 2, the surface roughness Ra was about 10 nm.

  From the measurement result of the surface morphology, it was found that in the silicon carbide semiconductor element 100, an extremely flat facet surface 91 having a surface roughness Ra reduced by two orders of magnitude or more was formed.

  Next, the current-voltage characteristics of the silicon carbide semiconductor device 100 of the present embodiment and the silicon carbide semiconductor device of Comparative Example 2 were measured, and the results will be described.

  When the drain current values of silicon carbide semiconductor device 100 and silicon carbide semiconductor device of Comparative Example 2 are measured, the drain current of silicon carbide semiconductor device 100 is at least five times the drain current of the silicon carbide semiconductor device of Comparative Example 2. I found it big. This is considered to be due to the following reasons.

  In the silicon carbide semiconductor element of Comparative Example 2, since the surface roughness of the silicon carbide layer surface is large, the carrier mobility in the vicinity of the surface of the silicon carbide layer where the channel is formed is low, and the drain current hardly flows. On the other hand, in silicon carbide semiconductor device 100, there is no step and a channel is formed on facet surface 91 with a reduced surface roughness (0.1 nm or less), so that a decrease in carrier mobility can be suppressed. . Therefore, a drain current having a higher current density can be passed through the channel.

  Subsequently, when the threshold voltage of the silicon carbide semiconductor element 100 and the silicon carbide semiconductor element of Comparative Example 2 is measured, the threshold value of the silicon carbide semiconductor element of Comparative Example 2 varies in the range of 2 to 10 V. It was found that the threshold value of silicon carbide element 100 was stable at 3 to 3.5V. This is considered to be due to the following reasons.

  In the silicon carbide semiconductor device of Comparative Example 2, the threshold voltage varies because the surface is rough at the MOS interface. On the other hand, silicon carbide semiconductor element 100 has a MOS interface composed of a (0001) facet surface, so that a channel having a uniform thickness is formed, and a stable threshold value is obtained.

  As is apparent from the above measurement results, a flat facet (surface roughness Ra: 0.1 nm or less) is formed by further epitaxially growing the mask layer 25 having a step on the silicon carbide epitaxial layer 22. Can be realized. Moreover, the electrical characteristics and reliability of silicon carbide MOSFET can be improved by utilizing the obtained facet surface.

  Although the inversion type MOSFET has been described in the present embodiment, the same effect can be obtained even if the present invention is applied to a storage type MOSFET. Further, the present invention can be applied not only to MOSFETs but also to silicon carbide elements such as MESFETs and Schottky diodes having a Schottky barrier on the substrate surface, and the same effects as those described in the present embodiment can be obtained.

  The present invention can provide a highly reliable silicon carbide element having excellent electrical characteristics without complicating the manufacturing process, and can be widely applied to various silicon carbide elements including MOSFET, MESFET, Schottky diode and the like. The silicon carbide element of the present invention can be used in low-loss power devices that can be used in various electric power / electric equipment such as home appliances, automobiles, electric power transportation / conversion devices, and industrial equipment.

(A)-(d) is process sectional drawing for demonstrating the formation method of the silicon carbide layer in preferable embodiment by this invention. It is a typical expanded sectional view of the step formed in the silicon carbide epitaxial layer surface. It is the schematic which shows the structure of the heating furnace used by embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the formation method of the silicon carbide layer in 1st Embodiment by this invention. (A) And (b) is a perspective view for demonstrating the formation method of the silicon carbide layer in 1st Embodiment by this invention, and respond | corresponds to FIG.4 (b) and (c), respectively. . (A)-(c) is process sectional drawing for demonstrating the formation method of the silicon carbide layer in 2nd Embodiment by this invention. It is a typical expanded sectional view for demonstrating the relationship between the width | variety of a facet surface, and the thickness of an epitaxial thin film. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor element of 3rd Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor element of 3rd Embodiment by this invention. It is a top view which shows the facet surface in the silicon carbide semiconductor element of 3rd Embodiment by this invention. It is sectional drawing for demonstrating the general method of forming a silicon carbide layer by epitaxial growth. It is sectional drawing for demonstrating the structure of the conventional MOSFET.

Explanation of symbols

1, 21, 40 Silicon carbide substrate 2, 22 Silicon carbide epitaxial layer 10, 20 Silicon carbide layer 4, 43 Steps 5, 15, 25 formed on the surface of the silicon carbide epitaxial layer 5, 15, 25 Mask layer 8, 12, 92 Epitaxial thin film 9, DESCRIPTION OF SYMBOLS 11, 91 Facet surface 33 Implant mask 32 Drift region 23, 24, 26 Impurity ion implantation layer 23 Well region 24 Contact region 26 Source region 28 Gate insulating film 29 Source electrode 30 Drain electrode 31 Gate electrode 42 Step flow 100 Silicon carbide semiconductor element 150 Reactor (chamber)
151 Sample 152 Susceptor 153 Susceptor support shaft 154 Coil 155 Argon gas 156 Silicon carbide source gas 157 Oxygen gas 158 Gas supply system 159 Gas exhaust system 160 Exhaust gas piping 161 Pressure adjustment valve 162 Heat insulating material

Claims (22)

A silicon carbide substrate having an off angle;
A silicon carbide layer formed on the silicon carbide substrate,
The surface of the silicon carbide layer has a facet plane composed of a single crystal plane,
The facet surface is inclined with respect to an envelope surface on the surface of the silicon carbide substrate,
The silicon carbide layer includes a first region in which the facet surface is formed, and a second region adjacent to the lowest portion of the facet surface,
The highest portion of the first region is higher than the surface of the second region;
A silicon carbide semiconductor element in which a step having a bottom portion that is recessed from the lowest portion of the facet surface is not provided on a surface of the silicon carbide layer along at least a part of an end portion of the facet surface.   2. The silicon carbide semiconductor device according to claim 1, wherein a level difference between a highest portion in the facet surface and a lowest portion in the second region is 1 μm or less.   3. The silicon carbide semiconductor element according to claim 1, wherein a facet surface of the silicon carbide layer is rectangular when viewed from a normal direction of the silicon carbide substrate.   4. The silicon carbide semiconductor device according to claim 1, comprising a plurality of facet surfaces, wherein some sides of the plurality of facet surfaces are parallel to each other.   The silicon carbide semiconductor element according to any one of claims 1 to 4, wherein the facet surface is formed of a (0001) plane.   The surface of the second region has a plurality of minute steps, and the width of the facet surface is larger than the width of the minute steps in a cross section perpendicular to the ridgeline of the minute steps. A silicon carbide semiconductor device according to any one of the above. An oxide film covering at least part of the facet surface;
The silicon carbide semiconductor device according to claim 1, further comprising an electrode provided on the oxide film.   The silicon carbide semiconductor device according to claim 1, having a transistor structure in which a channel is formed in the first region.   An electrode is further provided on the silicon carbide layer so as to be in contact with at least a part of the facet surface, and at least a part of the interface between the silicon carbide layer and the electrode forms a Schottky barrier. The silicon carbide semiconductor element according to claim 1. (A) preparing a silicon carbide substrate having an off angle and having a first silicon carbide layer formed on the surface;
(B) forming a mask layer on the first silicon carbide layer;
(C) including a step of epitaxially growing a second silicon carbide layer on a portion of the first silicon carbide layer that is not covered with a mask layer,
The method of manufacturing a silicon carbide semiconductor element, wherein the surface of the second silicon carbide layer has a facet plane constituted by a single crystal plane.   11. The silicon carbide according to claim 10, wherein an end surface of the mask layer has a portion extending along a direction perpendicular to a progress direction of step flow growth in the second silicon carbide layer in an envelope surface of the surface of the silicon carbide substrate. A method for manufacturing a semiconductor device. (D) implanting impurity ions into at least a part of the first and second silicon carbide layers;
(E) further including a step of performing activation annealing on the first and second silicon carbide layers implanted with the impurity ions,
The method for manufacturing a silicon carbide semiconductor element according to claim 10 or 11, wherein the steps (D) and (E) are performed after the step (C).   Including a step of providing a cap layer made of carbon on the surfaces of the first and second silicon carbide layers before the step (E), and a step of removing the cap layer after the step (E). The manufacturing method of the silicon carbide semiconductor element of Claim 12 containing.   The method for manufacturing a silicon carbide semiconductor element according to claim 10, wherein the mask layer is rectangular when viewed from a normal direction of the silicon carbide substrate.   The at least one side of the mask layer is perpendicular to the direction of progress of step flow growth in the second silicon carbide layer when viewed from the normal direction of the silicon carbide substrate. The manufacturing method of silicon carbide semiconductor element of this. The step (B) is a step of forming a plurality of island-shaped mask layers on the first silicon carbide layer,
16. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein at least one side of each of the plurality of mask layers is parallel to each other when viewed from a normal direction of the silicon carbide substrate. The step (B) is a step of forming a plurality of island-shaped mask layers on the first silicon carbide layer,
When viewed from the normal direction of the silicon carbide substrate, at least one side of each of the plurality of mask layers is parallel to the progress direction of the step flow growth in the second silicon carbide layer, and the progress of the step flow growth The method for manufacturing a silicon carbide semiconductor element according to any one of claims 10 to 16, wherein a length of at least one side parallel to the direction is smaller than an interval between adjacent mask layers.   18. The method for manufacturing a silicon carbide semiconductor element according to claim 10, wherein a thickness of the mask layer is larger than a thickness of the second silicon carbide layer.   The method for manufacturing a silicon carbide semiconductor element according to claim 10, wherein a thickness of the mask layer is not less than 10 nm and not more than 1 μm.   The method for manufacturing a silicon carbide semiconductor element according to claim 10, wherein the mask layer contains carbon. (A) preparing a silicon carbide substrate having an off angle;
(B) forming a mask layer on the silicon carbide substrate;
(C) including a step of epitaxially growing a silicon carbide layer on a portion of the silicon carbide substrate that is not covered with a mask layer,
The silicon carbide layer is a method for manufacturing a silicon carbide semiconductor element having a facet surface composed of a single crystal plane. A silicon carbide substrate having an off angle;
A silicon carbide layer formed on a part of the surface of the silicon carbide substrate,
The silicon carbide semiconductor element which has the facet surface comprised from the surface of the said silicon carbide layer from a single crystal plane.

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