JP3784393B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP3784393B2
JP3784393B2 JP2004191169A JP2004191169A JP3784393B2 JP 3784393 B2 JP3784393 B2 JP 3784393B2 JP 2004191169 A JP2004191169 A JP 2004191169A JP 2004191169 A JP2004191169 A JP 2004191169A JP 3784393 B2 JP3784393 B2 JP 3784393B2
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JP2005039257A (en
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正雄 内田
真 北畠
賢哉 山下
修 楠本
和幸 澤田
正博 萩尾
邦方 高橋
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松下電器産業株式会社
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Description

  The present invention relates to a power device using a silicon carbide substrate (SiC substrate) used for high breakdown voltage and large current.

  Conventionally, a power device is a semiconductor element that allows a large current to flow with a high breakdown voltage. Conventionally, power devices using silicon (Si) substrates have been the mainstream, but in recent years SiC (silicon carbide) substrates, which are semiconductor materials in which Si and C are combined at a component ratio of 1: 1, have been used. The power devices that have been attracting attention are being developed. Since SiC has a dielectric breakdown electric field higher than that of silicon by an order of magnitude, high reverse breakdown voltage can be maintained even if the depletion layer at the pn junction or the Schottky junction is thinned. Therefore, when the SiC substrate is used, the thickness of the device can be reduced and the doping concentration can be increased. Therefore, the SiC substrate has a low on-resistance and a substrate material for forming a power device with high breakdown voltage and low loss. As expected. Here, the SiC substrate includes one obtained by epitaxially growing a SiC crystal layer on a substrate made of a material different from SiC. Silicon carbide represented by “SiC” is a material having different physical and chemical properties from silicon containing a small amount (several percent or less) of C represented by “Si: C”.

  However, the MISFET using the SiC substrate has a drawback that the carrier mobility in the channel region is lower than the MISFET using the silicon substrate. This is because the thermal oxide film of silicon is pure silicon oxide, whereas the thermal oxide film on the SiC substrate has carbon remaining therein, and the interface between the thermal oxide film and the SiC layer (semiconductor layer). This is because there are many interface states in.

  Therefore, recently, in order to overcome this drawback, a storage MISFET has been proposed as a MISFET using a SiC substrate, instead of a normal inversion MISFET. For example, Patent Document 1 discloses a double-implanted MISFET in which a channel layer on the surface is epitaxially grown as an accumulation-type MISFET using such a SiC substrate.

  FIG. 14 is a cross-sectional view showing the structure of a storage MISFET and a double injection MISFET using a conventional SiC substrate.

  As shown in FIG. 14, this double injection type MISFET includes a SiC substrate 131, a high resistance SiC layer 132 provided on the SiC substrate 131, and a p-type impurity in a part of the surface portion of the high resistance SiC layer 132. A p-well region 133 formed by ion implantation, a channel layer 135 containing n-type impurities formed on the upper surfaces of the p-well region 133 and the high-resistance SiC layer 132, and the channel layer 135 and the p-well region 133. A source region 136 formed by partially implanting n-type impurity ions, a gate insulating film 137 made of a thermal oxide film provided on the surface of the channel layer 135, and a gate insulating film 137. The gate electrode 110 is provided on the wall surface of the groove that penetrates the source region 136 and reaches the p well region 133, and is in contact with the p well region 133 and the source region 137. A source electrode 138 provided so that, and a drain electrode 139 formed to ohmic contact on the back surface of the SiC substrate 131.

  Each of the source region 136, which is an n-type semiconductor layer, and the high-resistance SiC layer 132 are electrically connected via a channel layer 135, which is an n-type semiconductor layer. In addition, a part of the channel layer 135 located above the source region is removed. The source electrode 138, the source region 136, and the p-well region 133 are heat-treated so as to be in ohmic contact with each other. SiC substrate 131 and drain electrode 139 are in ohmic contact with each other.

  15 (a) to 15 (e) and FIGS. 16 (a) to 16 (e) are diagrams showing a manufacturing process of a conventional double injection type MISFET.

  First, in the step shown in FIG. 15A, a high-resistance SiC layer 132 having a higher resistance (lower dopant concentration) than that of the SiC substrate 131 is epitaxially grown on the low-resistance SiC substrate 131.

  Next, in the step shown in FIG. 15B, selective p-type impurity ion implantation is performed on part of the surface portion of the high-resistance SiC layer 132 to form the p-well region 133.

  Next, in the step shown in FIG. 15C, annealing for activating the impurities implanted so far is performed. At this time, the surface of the p-well region 133 is roughened.

  Next, in the step shown in FIG. 15D, a channel layer 135 containing an n-type impurity is epitaxially grown on the surface of the p-well region 133 and the high-resistance SiC layer 132.

  Next, in the step shown in FIG. 15E, high-concentration n-type impurity ions are implanted into part of the channel layer 135 and the p well region 133 to penetrate the channel layer 135 to form the p well region. A source region 136 reaching the inside of 133 is formed. At this time, the source region 136, which is an n-type semiconductor layer, and the high-resistance SiC layer 132 are electrically connected via a channel layer 135, which is an n-type semiconductor layer.

  Next, in the step shown in FIG. 16A, annealing for activating the impurities implanted into the source region 136 is performed. At this time, the surfaces of the channel layer 135 and the source region 136 are roughened.

  Next, in the step shown in FIG. 16B, a trench 134 that penetrates the source region 136 and reaches the top of the p-well region 133 is formed, and then the channel layer 135, the source region 136, and the p-well region 133 are exposed. A surface insulating portion 137 made of a thermal oxide film is formed by thermally oxidizing the surface portion.

  Next, in the step shown in FIG. 16C, the portion of the gate insulating film 137 on the wall surface of the trench 134 and the portion around the trench 134 are removed.

  Next, in the step shown in FIG. 16D, the source electrode 138 is formed on the portion of the source region 136 that is exposed by removing the gate insulating film 137. In addition, drain electrode 139 is formed on the back surface of SiC substrate 131.

  Next, a gate electrode 110 is formed on the gate insulating film 137 in the step shown in FIG. Note that heat treatment is performed so that the source electrode 138 and the source region 137 and the p-well region 133 are in ohmic contact, and the SiC substrate 131 and the drain electrode 139 are in ohmic contact.

  In this MISFET using the conventional SiC substrate, since the channel layer 135 is the same n-type semiconductor layer as the source region 136 and the high-resistance SiC layer 132, an inversion type MISFET utilizing the inversion of the channel layer (general MISFET) Instead, it is a storage MISFET that uses the storage state of the channel layer. A storage type MISFET having a channel layer is less affected by a region near the MIS interface where there are many interface states because a current flows to a deep region far from the MIS interface as compared with an inversion type MISFET. (Carrier mobility) is improved.

In general, as the SiC substrate used for such a semiconductor device, an off-substrate whose main surface is inclined with a deviation from a nominal crystal plane (for example, (0001) plane) is used. The reason is that, when the off-substrate is used when epitaxially growing the high-resistance SiC layer 32, the high-resistance SiC layer grows in a step flow, so that the crystallinity of the high-resistance SiC layer 32 is improved.
JP 2001-144288 A (pages 3-7, FIGS. 5-10) Materials Science Forum Vol.389-393, pp.831-834 (Materials Science Forum Vols.389-393, pp831-834) Materials Science Forum Vol.389-393, pp. 1211-1214 (Materials Science Forum Vols. 389-393, pp1211-1214)

  However, according to Patent Document 1, when such an off-substrate is used, if the channel layer of the MISFET is provided so as to be parallel to the main surface of the substrate, the carrier mobility in the channel layer is reduced, and the main surface When provided so as to be perpendicular to the off direction, carrier mobility in the channel layer is improved. The reason is described that a step exists on the surface of the off-substrate, and that current does not flow easily if a channel is set in a direction crossing the step. That is, the mobility is lowered by the unevenness of the surface.

  Furthermore, it is known that the unevenness on the surface of the SiC layer is further increased by annealing for high-temperature activation after ion implantation. In order to obtain a sufficiently activated carrier density and carrier mobility, it is necessary to set the activation temperature to a high temperature of 1700 ° C. or higher, but the surface roughness of the SiC layer increases as the temperature increases. Further, the longer the annealing time, the larger the annealing time. For example, the average surface roughness Ra before annealing is 1 nm or less, but the activation surface annealing at 1700 ° C. for 30 minutes results in an average surface roughness Ra of about 10 nm. (For example, refer nonpatent literature 1). The step of the macro step is as large as 50 nm or more, and therefore the maximum surface roughness Rmax is also 50 nm or more.

  For example, activation annealing after ion implantation into the well region 133 shown in FIG. 15D causes step bunching to occur on the exposed surface of the well region 133, hillocks are formed, and the surface roughness increases. . Then, in the step shown in FIG. 15E, the channel layer 135 is epitaxially grown on the surface of the well region 133 having a large surface roughness and poor smoothness, so that the surface of the channel layer 135 also has a surface roughness. Big and poor smoothness. The average surface roughness Ra of the channel layer surface is about 10 nm, and the maximum surface roughness Rmax is 50 nm or more. Further, after the deposition of the channel layer 135, ion implantation of the source region 136 is performed in the step shown in FIG. 15F, and activation annealing is performed in the step shown in FIG. Becomes larger and the smoothness is further deteriorated. Thus, as the surface roughness increases, the carrier mobility in the channel layer of the MISFET further decreases.

  Further, the inventors of the present invention, as a channel layer of such an accumulation-type MISFET, have a first semiconductor layer that is not intentionally doped and a very thin second semiconductor layer that is highly doped (δ-doped layer). ), And a MISFET having a channel layer having such a stacked doped layer structure has been demonstrated to exhibit extremely high carrier mobility ( Non-patent document 2). In such a laminated doped layer structure, since the thickness of the second semiconductor layer (δ-doped layer) needs to be extremely thin, such as about 10 nm, the average surface roughness of the channel layer surface is extremely high accordingly. It needs to be small. That is, the surface roughness of the channel layer must be at least equal to or less than the thickness of the second semiconductor layer, and must be at least 10 nm. Moreover, the surface roughness of the channel layer is desirably 1 nm or less in order to actually exhibit high functionality using a wide gap semiconductor.

  Here, the average surface roughness Ra is the centerline average roughness, and is defined in the JIS standard as follows.

“A part of the measurement length L is extracted from the roughness curve in the direction of the center line, the direction of the center line of the extracted part is the X axis, and the direction of the vertical magnification (perpendicular to the X axis) is the Y axis. Y = F (X)
When
Ra = (1 / L) · ∫ (X = 0 to L) {│F (X) │dX}
The value given by

  In addition, when the present inventors have a large step such as step bunching on the surface of the channel layer, the thermal oxide film that is the gate insulating film of the MISFET becomes thin at the step portion, and the dielectric breakdown voltage of the oxide film decreases at this portion. I found out.

  FIG. 17 is an SEM photograph showing the structure in the vicinity of the channel layer of the storage double injection MISFET having substantially the same structure as that disclosed in Non-Patent Document 2.

In FIG. 17, in the n-epi layer (SiC) which is a channel layer, an undoped layer having a thickness of 10 nm which is not intentionally doped, and an n-type doping concentration of 5 × 10 17 cm −3 and a thickness of 40 nm. Three doped layers are alternately stacked, and the outermost surface is an undoped layer having a thickness of 40 nm. The thermal oxide film is formed by dry oxidation at 1180 ° C. for 3 hours. Although not shown in FIG. 17, the p-well region provided below the n-epi layer has a thickness of about 800 nm containing an impurity with a concentration of 1 × 10 18 cm −3 by Al ion implantation. After the ion implantation, activation annealing is performed at 1750 ° C. for 30 minutes. A step having a height of 50 nm or more is formed on the surface of the p-well by this activation annealing. When evaluated by AFM, the average surface roughness Ra was 10 nm or more, and the maximum surface roughness Rmax was 50 nm or more. For this reason, the same level difference is made on the surface of the channel layer. The step is not a vertical cut, but a gentle slope. The thickness of the thermal oxide film is about 56 nm on the flat portion of the channel layer, but about 30 nm on the stepped-slope portion, which is only half of the thickness on the flat portion. . This is presumably because the growth rate of the thermal oxide film is different because the crystallographic plane orientation of the exposed surface is different between the flat portion and the stepped portion. Since the leak current flows in the thin portion of the thermal oxide film at the slope portion of the step, this MISFET has a gate insulation breakdown voltage of 10 V or less, and a sufficient voltage cannot be applied to the gate. No current was obtained.

  As described above, the problem of the conventional power device has been described by taking the vertical MISFET as an example, but the same problem exists also in the lateral MISFET, MESFET, and lateral Schottky diode. This is because these power devices have a structure in which carriers flow in a direction parallel to the main surface of the SiC substrate.

  An object of the present invention is to provide a semiconductor device having a high carrier mobility in a channel layer while using a SiC substrate, and a method for manufacturing the same.

  In the semiconductor device of the present invention, an epitaxial growth layer is provided on a silicon carbide layer including a high-concentration impurity diffusion region, and a channel layer whose upper surface is smoother than the upper surface of the silicon carbide layer is provided on a part of the epitaxial growth layer. It is a thing.

  As a result, the upper surface of the channel layer becomes smooth, so that the carrier mobility in the channel layer is kept high. Even if the silicon carbide layer has a macro step by step bunching or the like, the upper surface of the channel layer is smoothed, so that the leakage current is small and the breakdown voltage is kept high.

  By further providing an electrode that penetrates the epitaxial growth layer and reaches the high concentration impurity region, a semiconductor device having a high driving force can be easily obtained.

  Since the upper surface of the silicon carbide layer is smoothed by polishing, the upper surface of the epitaxial growth layer, that is, the upper surface of the channel layer is also smoothed.

  Since the upper surface of the silicon carbide layer is smoothed by a heat treatment covering the carbon film, a treatment such as polishing is not required, and the practical application is facilitated.

  Since the lateral dimension of the overlap region between the channel layer and the high concentration impurity diffusion region is larger than the thickness of the channel layer, the carrier supply capability from the high concentration impurity diffusion region to the channel layer is ensured.

  The average surface roughness of the surface of the silicon carbide layer that contacts the channel layer is preferably 2 nm or less.

  The average surface roughness of the upper surface of the channel layer is more preferably 1 nm or less.

  Since the channel layer has multiple δ-doping, a semiconductor device with extremely high carrier mobility can be obtained.

  A vertical MISFET, a lateral MISFET, and a lateral MESFET to which this structure is applied can exhibit a high current driving capability.

  The method for manufacturing a semiconductor device according to the present invention includes performing annealing for activating impurities implanted in a high concentration impurity diffusion region formed in a part of a silicon carbide layer of a substrate, followed by CMP, mechanochemical polishing, In this method, the exposed surface of the silicon carbide layer including the high concentration impurity diffusion layer is smoothed by dry etching or the like, and then the channel layer is formed on the silicon carbide layer including the high concentration impurity diffusion region.

  By this method, the surface of the silicon carbide layer including the high-concentration impurity diffusion region is roughened through annealing for ion implantation and activation, but a channel layer is formed on the surface smoothed by the subsequent processing. Therefore, the surface of the channel layer is also smoothed. Therefore, a semiconductor device having high carrier mobility in the channel layer can be obtained.

  According to the present invention, since a channel layer with a smoothed surface is provided in a semiconductor device such as a MISFET or MESFET using an SiC substrate, it is possible to provide a semiconductor device with high carrier mobility and a method for manufacturing the same. it can.

(First embodiment)
In the present embodiment, a first embodiment relating to a storage type double injection MISFET using a bulk SiC substrate will be described. FIG. 1 is a cross-sectional view showing a structure of a double injection MISFET which is a first embodiment of the present invention. Although only a partial cross-sectional structure is disclosed in FIG. 1, the planar structure of the MISFET has a structure as disclosed in FIG. 2 or FIG. 10 of the international application PCT / JP01 / 07810, for example.

As shown in FIG. 1, this double-implant MISFET has a low-resistance SiC substrate 1 containing an n-type impurity (dopant) having a concentration of 1 × 10 18 cm −3 or more, and a main surface of the SiC substrate 1. A high resistance SiC layer 2 which is provided and is doped with an n-type impurity having a concentration of about 1 × 10 15 cm −3 to 1 × 10 16 cm −3, and a concentration on a part of the surface portion of the high resistance SiC layer 2. Is doped with a p-type impurity of 1 × 10 16 cm −3 to 1 × 10 18 cm −3 , and a concentration in a part of the p well region 3 is about 5 × 10 19 cm −. 3 and the p-type impurity p + contact regions 4 formed by doping, the source region concentration in a part of the p-well region 3 is formed by doping n-type impurities of about 1 × 10 19 cm -3 6, epitaxial growth formed across source region 6, p-well region 3 and high-resistance SiC layer 2 5, a channel layer 5x including a laminated doped layer structure, a gate insulating film 7 made of a thermal oxide film provided on the surface of the channel layer 5x, and an Al provided on the gate insulating film 7. Gate electrode 10 made of an alloy film, source electrode 8 made of an Ni alloy film provided so as to be in contact with the side surfaces of channel layer 5x, source region 6 and p + contact region 4, and on the back surface of SiC substrate 1 And a drain electrode 9 made of a Ni alloy film formed so as to be in ohmic contact therewith. Here, in the present embodiment and each embodiment described later, the channel layer means a region located below the gate electrode in the epitaxial growth layer in the MISFET, and a region located between the source region and the drain region in the MESFET. Say.

  During operation of the MISFET, if a bias voltage higher than the threshold voltage is applied to the gate electrode 10 with a predetermined voltage applied between the source electrode 8 and the drain electrode 9, the source electrode 8 passes through the source region 6. Carriers are injected into the channel layer 5x, and the carriers travel from the channel layer 5x to the drain electrode 8 through the high-resistance SiC layer 2 and the SiC substrate 1.

The surfaces of the high resistance SiC layer 2, the well region 3 and the source region 6 are smoothed, and the channel layer 5x is epitaxially grown thereon. The channel layer 5x has a first semiconductor layer 5a that functions as a carrier travel region, and a thickness that is smaller than that of the first semiconductor layer 5a and that can supply carriers to the first semiconductor layer 5a. It has a laminated doped layer structure in which second semiconductor layers 5b containing type impurities are alternately laminated. For example, the impurity concentration in the first semiconductor layer 5a is 1 × 10 16 cm −3 or less and the thickness is about 40 nm, and the impurity concentration in the second semiconductor layer 5b is 1 × 10 17 to 1 × 10 18. The thickness is about cm −3 and about 10 nm. For example, the lowermost layer of the channel layer 5x is the first semiconductor layer 5a, the first semiconductor layer 5a and the second semiconductor layer 5b are alternately deposited for three periods, and the first semiconductor layer 5a is further stacked on the outermost layer. This is the structure. In this case, when the thickness of the first semiconductor layer 5a is 40 nm and the thickness of the second semiconductor layer 5b is 10 nm, the thickness of the channel layer 5x is 190 nm.

  As the laminated doped layer structure, a first semiconductor layer that is not intentionally doped and a very thin second semiconductor layer (δ-doped layer) that is highly doped are alternately found in a t-structure (multiple structure). (δ-doped layer structure) may also be used.

  Each of the source region 6 which is an n-type semiconductor layer and the high-resistance SiC layer 2 is in an electrically conductive state via a channel layer 5x which is an n-type semiconductor layer. In addition, a part of the source region 6 and a portion located above the p + contact region 4 in the channel layer 5x are Ni alloyed by heat treatment and changed to the source electrode 8. Source electrode 8 is in ohmic contact with source region 7 and p + contact region 4, and drain electrode 9 is in ohmic contact with SiC substrate 1.

  FIGS. 2A to 2F and FIGS. 3A to 3E are diagrams showing manufacturing steps of the double injection MISFET of the first embodiment.

First, in the step shown in FIG. 2A, on the main surface of the SiC substrate 1, which is an off substrate having an off angle of 8 degrees from the (0001) plane of 4H-SiC, by means of thermal CVD or the like, The high resistance SiC layer 2 containing a low concentration n-type impurity is epitaxially grown. At this time, for example, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, hydrogen (H 2 ) is used as a carrier gas, and nitrogen (N 2 ) is used as a dopant gas. For example, when a MISFET having a withstand voltage of 600 V is manufactured, the impurity concentration of the high-resistance SiC layer 2 is desirably 1 × 10 15 cm −3 to 1 × 10 16 cm −3 and the thickness thereof is 10 μm or more. It is desirable.

Next, in the step shown in FIG. 2B, p-type impurities (aluminum, boron, etc.) are doped into a part of the epitaxially grown high resistance SiC layer 2 by ion implantation to form the p well region 3. . When forming the p-well region 3, first, a silicon oxide film having a thickness of about 3 μm serving as an implantation mask is deposited on the upper surface of the high-resistance SiC layer 2, and the silicon oxide film is formed by photolithography and dry etching. An opening is provided only in a portion where the p-well region 3 is to be formed. Thereafter, in order to reduce implantation defects, aluminum or boron ions are implanted while maintaining the substrate temperature at a high temperature of 500 ° C. or higher. After the ion implantation, the silicon oxide film used as a mask is removed with hydrofluoric acid. The concentration of the p-type impurity in the p-well region 3 is usually about 1 × 10 17 cm −3 to 1 × 10 18 cm −3 , and the depth of the p-well region 3 is about 1 μm so as not to pinch off.

Next, in the step shown in FIG. 2C, a high-concentration p-type impurity is added to a part of the surface portion of the p-well region 3 in order to make contact between the p-well region 3 and a source electrode to be formed later. A p @ + contact region 4 is formed by doping by ion implantation. The p + contact region 4 has a thickness of about 300 nm and an impurity concentration of about 5 × 10 19 cm −3 or more. At this time, the ion implantation method is the same as the formation of the p-well region 3. Since the activation annealing is performed collectively after the ion implantation of the source region thereafter, it is not performed between the step shown in FIG. 2C and the step shown in FIG.

Next, in the step shown in FIG. 2D, a source region 6 is formed by doping a part of the surface portion of the p-well region 3 with high-concentration n-type impurities by ion implantation. At that time, a silicon oxide film having a thickness of about 1 μm serving as an implantation mask is deposited on the substrate, and an opening is provided only in a portion of the silicon oxide film where the source region 6 is formed by photolithography and dry etching. In order to reduce implantation defects, nitrogen or phosphorus ions are implanted while maintaining the substrate temperature at a high temperature of 500 ° C. or higher. After the ion implantation, the silicon oxide film used as a mask is removed with hydrofluoric acid. The impurity concentration in the source region 6 is about 1 × 10 19 cm −3 , which is lower than the impurity concentration in the p + contact region 4. When the impurity concentration in the source region 6 is approximately the same as the impurity concentration in the p + contact region 4, the implantation mask for forming the source region 6 needs to cover the p + contact region 4. Further, the depth of the source region 6 is shallower than the depth of the p + contact region 4 and is, for example, about 300 nm.

  Next, in the step shown in FIG. 2E, in order to activate the impurities implanted in the steps shown in FIGS. 2B to 2D, 1700 ° C. in an atmosphere of an inert gas such as argon. 30 minutes of activation annealing. At this time, macrosteps or hillocks having a height of about 10 nm to 100 nm occur on the exposed surfaces of the high resistance SiC layer 2, the p well region 3, the p + contact region 4 and the source region 6, and the surface roughness Increases and the surface smoothness deteriorates.

Next, in the step shown in FIG. 2 (f), the exposed surfaces of the high resistance SiC layer 2, the p well region 3, the p + contact region 4 and the source region 6 are smoothed by, for example, mechanochemical polishing (MCP). Turn into. At this time, the smoothing process is performed until the average surface roughness Ra of the surface is 2 nm or less, preferably 1 nm or less. When performing MCP, for example, chromium oxide is used as abrasive grains. Note that reactive ion etching or sacrificial oxidation treatment is performed in order to remove a modified layer formed on the surface portion due to polishing damage. Alternatively, reactive ion etching and sacrificial oxidation treatment may be used in combination. In reactive ion etching, for example, a mixed gas of CF 4 and O 2 is used, and a sample bias is performed at a voltage as low as possible so as not to be damaged by ion bombardment. For example, if ICP-RIE using inductively coupled plasma is used, the sample bias potential can be suppressed to 1 V or less. The etching depth is such that the doping profile is not impaired and the surface is extremely shallow, for example, a region having a depth of 0.1 μm or less. In the sacrificial oxidation, for example, a thermal oxide film having a thickness of about 40 nm is formed on the surface by holding the substrate in a quartz tube and holding dry oxygen at a flow rate of about 1 (l / min) and holding at 1180 ° C. for 90 minutes. can do. Thereafter, the thermal oxide film formed by hydrofluoric acid is removed. In this step, the SiC layer is removed to a depth of about several tens of nm on the surface. The depth of the SiC layer to be removed can be controlled by changing the thermal oxidation conditions.

  Next, in the step shown in FIG. 3A, the epitaxial growth layer 5 including the channel layer 5x is formed on the high resistance SiC layer 2, the p well region 3, the source region 6 and the p + contact region 4 by, for example, thermal CVD. Epitaxially grow. When forming the second semiconductor layer 5b (see FIG. 1) in the epitaxial growth layer 5 (channel layer 5x), for example, silane (SiH4) and propane (C3H8) are used as source gases and hydrogen ( H2) and nitrogen (N2) as dopant gas, respectively. In forming the first semiconductor layer 5a (see FIG. 1) in the epitaxial growth layer 5 (channel layer 5x), silane (SiH4) and propane (C3H8) are used as source gases without supplying the dopant gas. And hydrogen (H2) as a carrier gas. By repeating this thermal CVD alternately, the structure of the laminated doped layer structure shown in FIG. 1 can be realized.

  Next, in the step shown in FIG. 3B, the surface of the epitaxial growth layer 5 (channel layer 5x) (laminated doped layer structure) is thermally oxidized to form a silicon oxide film. At that time, for example, a SiC substrate is installed in a quartz tube, bubbled oxygen is introduced into the quartz tube at a flow rate of 2.5 (l / min), and thermal oxidation is performed for 2.5 hours while maintaining the substrate temperature at 1180 ° C. As a result, a silicon oxide film which is a thermal oxide film having a thickness of about 60 nm is formed.

  Next, a drain electrode 9 made of a nickel film having a thickness of 200 nm is formed on the back surface of the SiC substrate 1 by vapor deposition. The heat treatment of the drain electrode 9 is performed after the source electrode is formed later.

  Next, after forming a resist film Re having a region where the source electrode is to be formed on the silicon oxide film by photolithography, the silicon oxide film is patterned by hydrofluoric acid etching to form the source electrode A gate insulating film 7 surrounding the region to be formed is formed.

  Next, in the step shown in FIG. 3C, a nickel film (Ni film) having a thickness of 200 nm is deposited on the substrate by vacuum evaporation or the like while leaving the resist film Re, and then becomes a source electrode by lift-off. The nickel film 8x is left.

  Next, in the step shown in FIG. 3D, the Ni film 8x is subjected to a heat treatment in an inert gas atmosphere such as nitrogen at a temperature of 1000 ° C. for 2 minutes. During this heat treatment, nickel (Ni) and silicon carbide (SiC) interdiffusion and reaction occur, penetrate the epitaxial growth layer 5 and reach the source region 6 and the p + contact region 4, mainly from nickel silicide. A source electrode 8 is formed. Further, the drain electrode 9 is in ohmic contact with the SiC substrate 1 by this heat treatment. The heat treatment for the ohmic contact between the source electrode 8 and the drain electrode 9 may be performed simultaneously or individually.

  Next, in the step shown in FIG. 3E, the gate electrode 10 is formed on the gate insulating film 7 at a position separated from the source electrode 8. At this time, an aluminum film or the like having a thickness of about 200 nm is deposited by vacuum evaporation or the like, and then the aluminum film is patterned by ordinary photolithography and etching to form the gate electrode 10.

  Although the subsequent steps are not shown, a silicon oxide film having a thickness of about 1 μm is deposited as an interlayer insulating film covering the source electrode 8 and the gate electrode 10, and the source electrode 8 and the gate electrode are penetrated through the interlayer insulating film by RIE or the like. After the via hole reaching 10 is formed, an aluminum film having a thickness of about 2 μm is deposited by vacuum vapor deposition or the like, and patterned by ordinary photolithography and etching to form electrode pads and wirings.

In this way, a double injection type MISFET is completed. When the cross section of the channel portion of the MISFET was evaluated by TEM, only the irregularities having an average surface roughness Ra of 1 nm or less were observed on the lower surface and the surface of the channel layer, and good smoothness could be realized. Moreover, the film thickness of the gate insulating film 7 was uniform within a range of about 50% to 65 nm, and the breakdown voltage of the gate insulating film 7 was maintained at 40 V or more. The channel mobility of this MISFET was as high as 100 cm 2 / Vsec or more, the off breakdown voltage was 600 V, and the on resistance was 10 mΩ · cm 2 or less.

  Therefore, according to the present embodiment, the surface of the underlying layer (in this embodiment, the high-resistance SiC layer 2 and the p-well region 3) is smoothed before the epitaxial growth layer 5 including the channel layer 5x is formed. Since the epitaxial growth layer 5 is epitaxially grown, unevenness that hinders carrier movement in the channel layer 5x can be reduced, and the carrier mobility can be maintained high. In particular, since the upper surface and the lower surface of the channel layer 5x are flat, the carriers are not scattered when traveling, the channel mobility is high, and the on-resistance can be lowered.

  In addition, it is possible to suppress an increase in leakage through the gate insulating film 7 due to the presence of a macro step or the like on the surface and maintain a high gate breakdown voltage.

  In particular, in the case where the channel layer 5x has a δ-doped structure, if the unevenness of the channel layer 5x is larger than the thickness of the δ-doped layer (second semiconductor layer 5b shown in FIG. 1), the carrier travel is adversely affected. I know it will affect. In the present embodiment, the channel layer 5x having a concavo-convex (surface roughness) smaller than the thickness of 10 nm of the δ-doped layer (second semiconductor layer) can be easily obtained. The effects of high driving force and high pressure resistance can be reliably exhibited.

  Further, since the source region 6 is disposed below the channel layer 5x, the activation annealing after the deposition of the channel layer 5x is eliminated, and the surface smoothness after the deposition can be maintained.

  In addition, since the source region is formed after depositing the channel layer in the related art, activation annealing is required once before and after the epitaxial growth step. In the present invention, since the source region 6 is formed below the channel layer 5x, activation annealing of the ion implantation region can be performed at once in a lump. That is, there is also an advantage that the manufacturing process can be simplified.

  Compared to the conventional procedure in which the source region 6 is formed by ion implantation after the deposition of the epitaxial growth layer 5 including the channel layer 5x, the manufacturing process of this embodiment allows the source region 6 and the channel layer 5x to be formed. By adopting a structure in which the two are overlapped, the contact area between the two can be increased, so that the contact resistance can be reduced.

  FIGS. 4A and 4B are cross-sectional views showing the difference in overlap between the source region and the channel layer in the conventional MISFET using the SiC substrate and the MISFET of the present invention, respectively.

  As shown in FIG. 4A, in the conventional MISFET, since the source region 136 penetrates the channel layer 135, the contact length between the source region 136 and the channel layer 135 in this cross section is equal to that of the channel layer 135. Thickness t (about 200 nm) or more cannot be made. On the other hand, as shown in FIG. 4B, in the present embodiment, since the upper surface of the source region 6 and the lower surface of the channel layer 5x are in contact, the channel layer 5x and the source region 6 in this cross section are in contact with each other. The contact length A can be set relatively freely. During the operation of the MISFET, carriers flow from the source electrode 8 through the source region 6 to the channel layer 5x. Therefore, the larger the contact area between the channel layer 5x and the source region 6, the more efficiently carriers can be injected. Therefore, the contact length A in this cross section is preferably equal to or greater than the thickness of the channel layer 5x. For example, the contact length A is preferably 1 μm or more.

In the present embodiment, the channel layer 5x has a structure having a laminated doped layer structure in which the first semiconductor layer 5a and the second semiconductor layer 5b having different concentrations are stacked. However, the n-type channel layer has a substantially uniform concentration. Impurities may be included. In that case, the concentration of the n-type impurity is about 1 × 10 16 cm −3 to 5 × 10 17 cm −3 and the thickness is preferably about 200 nm. In addition, a channel layer having a concentration distribution such that the concentration of the n-type impurity changes in the depth direction may be provided without providing the laminated doped layer structure.

  Further, without etching the epitaxial growth layer 5, the metal film (Ni film in this embodiment) deposited on the surface of the epitaxial growth layer 5 and SiC reach the source region 6 through the epitaxial growth layer 5 by a chemical reaction. Since the source electrode 8 is formed, the manufacturing process is greatly simplified, the manufacturing cost can be reduced, and the practical use is facilitated.

In the present embodiment, mechanochemical polishing (MCP) is used as a process for smoothing the unevenness of the surface caused by annealing after ion implantation. However, a plasma atmosphere using a gas containing a halogen element such as fluorine is used. Isotropic dry etching performed in the inside may be performed. In addition, since MCP directly contacts the surface of the MCP and uses a chemical solution, impurity contamination is likely to occur and cleaning is necessary. On the other hand, dry etching using radicals has an advantage that impurity contamination hardly occurs because it is a dry process. As isotropic dry etching, for example, so-called down-flow etching is performed in which the sample is separated from the plasma generation chamber, only neutral active species (radicals) are transported to the sample, and etching is performed by a chemical reaction between the active species and the sample surface. Just do it. Alternatively, even when etching a sample in the plasma chamber, the sample bias can be set as low as possible by using an etching method that can set the sample bias independently of the plasma generation bias, such as ICP, and the ion energy should be as low as possible. In this case, impurity contamination can be made difficult to occur. As the plasma, a gas containing a halogen element such as a mixed gas of CF 4 and O 2 is used.

  In the present invention, the gate insulating film is not necessarily a thermal oxide film, and may be a silicon oxide film deposited by CVD or the like. Alternatively, the gate insulating film may have a laminated structure of a thermal oxide film and a deposited film. The gate insulating film is not necessarily a silicon oxide film, and may be a metal oxide film such as a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, or a hafnium oxide film.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention apparently has the same structure as the double-injection MISFET shown in FIG. 1 in the first embodiment, so the illustration of the structure of the MISFET is omitted. . In the MISFET of the present embodiment, the surfaces of the high-resistance SiC layer 2, the well region 3, and the source region 6 are not smoothed, and the surface is smoothed by activation annealing with the carbon film covered. Is significantly different from the first embodiment in that the above is maintained. Then, epitaxial growth layer 5 including channel layer 5 x is epitaxially grown on high resistance SiC layer 2, well region 3 and source region 6. The internal structure of the channel layer 5x (epitaxial growth layer 5) is as shown in FIG. 1 of the first embodiment, and has the laminated doped layer structure as described in the first embodiment.

  FIGS. 5A to 5F are cross-sectional views showing manufacturing steps of the double injection MISFET according to the second embodiment.

  First, in the steps shown in FIGS. 5A to 5D, the same steps as those in FIGS. 2A to 2D in the first embodiment are performed, and the high resistance SiC is formed on the main surface of the SiC substrate 1. After the layer 2 is epitaxially grown, p-type impurities (aluminum, boron, etc.) are doped by ion implantation into a portion of the epitaxially grown high resistance SiC layer 2 using an ion implantation mask that is a hard mask individually. The p-well region 3 is formed, and a source region 6 is formed by doping a part of the surface of the p-well region 3 with a high-concentration n-type impurity by ion implantation.

Next, in the step shown in FIG. 5E, after removing the ion implantation mask, a carbon film 9 is deposited on the high resistance SiC layer 2, the well region 3, and the source region 6. The carbon film 9 is deposited by the following procedure. First, an SiC substrate is installed on a substrate attachment portion of a sputter deposition apparatus (not shown), and the inside of the chamber is evacuated by a gas exhaust system. The degree of vacuum at this time is about 10 −4 Pa. After evacuating the inside of the chamber with a gas exhaust system, Ar gas was introduced and high frequency power of 13.56 MHz and 100 W was applied to the carbon plate target at a pressure of about 10 −2 Pa to perform sputter deposition. Do. A carbon film 9 having a thickness of 50 nm is formed by vapor deposition for about 20 minutes. At this time, it is confirmed that there are few components other than carbon such as hydrogen contained in the carbon film 97, and 99% or more of the components of the carbon film 9 are carbon.

  Next, the SiC substrate covered with the carbon film 9 is set in an annealing apparatus (not shown), and an annealing atmosphere gas is supplied from a gas supply system. Argon gas is selected as the annealing atmosphere gas. The flow rate of argon gas was 0.5 liter / min. The pressure in the chamber is constant at 91 kPa. Thereafter, the substrate temperature is raised to 1750 ° C., and while maintaining this temperature, activation annealing of impurities implanted into the high resistance SiC layer 2, the well region 3 and the source region 6 is performed for 30 minutes. Next, while supplying the argon gas, the application of the high-frequency power to the coil is stopped to finish the heating, and the substrate is cooled.

  Next, in the step shown in FIG. 5F, the carbon film 9 is uniformly melted and removed by treatment with a 3: 1 mixture of sulfuric acid and hydrogen peroxide. In this case, the mixed aqueous solution hardly melts the SiC layer, and only the carbon film is removed.

  Subsequently, in order to completely remove the carbon film 9, an SiC substrate is placed in the thermal oxidation chamber, and oxygen is supplied at a flow rate of 5 liters / minute and heated to 800 ° C. By heating for 30 minutes, the carbon film 9 on the surface is almost completely removed, but in this embodiment, heating is performed for 60 minutes. As a result, in this embodiment, the activation rate of aluminum is 90% or more, and a sufficient activation rate is obtained.

  Here, in the present embodiment, the average surface roughness Ra of the high-resistance SiC layer 2, the well region 3, and the source region 6 after the removal of the carbon film 9 is about 2 nm or less, for example, about 0.9 nm to Data of 1.3 nm is obtained. That is, surface roughness accompanying activation annealing is suppressed.

  As described above, since the region into which ions are implanted is covered with the carbon film 9 formed by sputtering, surface roughness due to sublimation of a substance from the region into which ions are implanted is suppressed. That is, the carbon film formed by the sputtering method is dense and stable at a high temperature of 1600 ° C. or higher, so that almost no change in the composition, structure, and film thickness of the carbon film occurs. Therefore, when the surface of the ion-implanted layer before annealing is smooth, the surface of the ion-implanted layer after annealing can also be maintained smooth.

  Next, epitaxial growth layer 5 including channel layer 5 x is epitaxially grown on high resistance SiC layer 2, well region 3, and source region 6 after removal of carbon film 9. The conditions at this time are as described in the step shown in FIG. 3A in the first embodiment.

  Here, the average surface roughness Ra of the channel layer 5x immediately after the epitaxial growth has a value of about 0.08 nm to 0.8 nm, for example. Thus, the inventors have found that the surface roughness of the epitaxial growth layer is smaller than the surface roughness of the underlayer. In other words, it was found that a smoothing phenomenon occurred in the epitaxial growth.

  FIG. 18 is a diagram showing a correlation between the average surface roughness Ra of the base layer before epitaxial growth and the average surface roughness Ra of the epitaxially grown layer epitaxially grown thereon. From the figure, when the average surface roughness Ra of the underlayer is 7 nm or more, the surface roughness Ra of the epitaxially grown layer epitaxially grown thereon is higher than the average surface roughness Ra of the underlayer. On the other hand, when the average surface roughness Ra of the underlayer is 2 nm or less, the average surface roughness Ra of the epitaxial growth layer epitaxially grown thereon is smoothed to 1 nm or less.

  Specifically, when the surface roughness Ra of the high-resistance SiC layer 2, the well region 3 and the source region 6 before epitaxial growth (after annealing covering the carbon film) is 1.3 nm, the channel layer 5x immediately after epitaxial growth The average surface roughness Ra is 0.78 nm, and when the surface roughness Ra of the high-resistance SiC layer 2, the well region 3 and the source region 6 before epitaxial growth (after annealing coated with a carbon film) is 0.9 nm, Data indicating that the average surface roughness Ra of the channel layer 5x immediately after the epitaxial growth is 0.08 nm is obtained.

  As described above, the source layer (the source / drain region in the lateral MISFET and MESFET) is provided in the base layer for epitaxial growth for forming the channel layer, and the surface roughness of the channel layer after the epitaxial growth is higher than the surface roughness of the base layer. The fact that it is smaller, that is, smoother, is a structural feature of the vertical MISFET of the present invention and the MESFET and lateral MISFET of each embodiment described later.

  Since the subsequent steps are as shown in FIGS. 3B to 3E in the first embodiment, illustration and description are omitted.

  According to the manufacturing method of the present embodiment, the following effects can be exhibited in addition to the effects of the first embodiment. By reducing the average surface roughness Ra of the underlying layer for epitaxial growth (in this embodiment, the high-resistance SiC layer 2, the well region 3 and the source region 6) to 2 nm or less by impurity activation processing with the carbon film deposited. The average surface roughness Ra of the channel layer 5x immediately after the epitaxial growth can be further reduced. Such a smoothing phenomenon during epitaxial growth is remarkable when the average surface roughness of the underlayer is about 1.5 nm or less. However, the average surface roughness Ra of the underlayer is not necessarily 1.5 nm or less. As a result, it was found that the MISFET of this embodiment can exhibit a particularly high current driving capability.

  FIGS. 11A and 11B are diagrams showing the IV characteristics of the vertical MISFET of the reference example and the vertical MISFET of this embodiment, respectively, in order. However, the data shown in FIG. 11A is not the structure of the conventional MISFET shown in FIG. 14, and the basic shape is almost the same as the structure shown in FIG. 14, but ion implantation for forming the source region 136 is performed. The carbon film is subsequently coated and subjected to impurity activation annealing, and the average surface roughness Ra of the channel layer 135 is about 1 nm. On the other hand, the average surface roughness Ra of the channel layer 5x in the MISFET of this embodiment shown in FIG. 11B is about 0.1 nm. In each MISFET, the gate length is 3 μm and the well spacing is 3 μm. As shown in FIGS. 11A and 11B, when compared with a common gate bias, the current driving capability of the vertical MISFET of this embodiment is improved as compared with the vertical MISFET of the reference example. Recognize. Since the current driving force of the vertical MISFET of the reference example has a higher current driving force than the current driving force of the conventional vertical MISFET shown in FIG. 14, the vertical MISFET of the present embodiment is It has a much higher current driving force than the conventional vertical MISFET.

FIG. 12 is a diagram showing the IV characteristics of the vertical MISFET of this embodiment. The data shown in the figure is data for a vertical MISFET including 9 cells (an actual vertical MISFET often includes about 1000 cells). The cell structure is the same as the sample from which the data shown in FIGS. 11 (a) and 11 (b) was obtained. When the on-resistance is calculated from the IV characteristics shown in FIG. 12, a value of 12 mΩ · cm 2 is obtained. Since the on-resistance in the vertical MISFET using the Si substrate is about 100 mΩ · cm 2 , it can be seen that the vertical MISFET of this embodiment exhibits a high current driving force and a small on-resistance.

Furthermore, as shown by data on a lateral MISFET described later, it is also known that the vertical MISFET of this embodiment shows a high carrier mobility of 70 cm 2 / Vs) and a small threshold voltage variation.

  Note that, as in the step shown in FIG. 2F in the first embodiment, the surfaces of the high-resistance SiC layer 2, the well region 3, and the source region 6 are smoothed by MCP and then epitaxially grown. The surface of the channel layer 5x immediately after the epitaxial growth can be further smoothed. However, since the smoothing process by MCP requires a long process and a deep etching amount, the manufacturing method of this embodiment can reduce the manufacturing cost more than the manufacturing method of the first embodiment. There are advantages in terms.

(Third embodiment)
FIGS. 6A to 6F are diagrams showing manufacturing steps of the double injection MISFET of the third embodiment.

  First, in the step shown in FIG. 6A, the same process as the step shown in FIG. 2A in the first embodiment is performed, and an off angle having an off angle of 8 degrees from the (0001) plane of 4H-SiC. High resistance SiC layer 2 is epitaxially grown on the main surface of SiC substrate 1 as a substrate.

Next, in the step shown in FIG. 6B, the same process as the step shown in FIG. 2C in the first embodiment is performed to make contact between the p well region and the source electrode to be formed later. Next, a high concentration p-type impurity is doped into a part of the surface portion of the high resistance SiC layer 2 by ion implantation to form the p + contact region 4. The impurity concentration of the p + contact region 4 is about 5 × 10 19 cm −3 .

Next, in the step shown in FIG. 6C, a p-type impurity (aluminum, boron, etc.) is doped into a part of the p-well region 3 by ion implantation to form the p-well region 3. When forming the p-well region 3, first, a silicon oxide film 21 having a thickness of about 3 μm serving as an implantation mask is deposited on the upper surface of the high-resistance SiC layer 2, and the silicon oxide film is formed by photolithography and dry etching. Of these, an opening is provided only in a portion where the p-well region 3 is formed. Thereafter, in order to reduce implantation defects, ion implantation of aluminum (Al) or boron (B) is performed while maintaining the substrate temperature at a high temperature of 500 ° C. or higher. The concentration of the p-type impurity in the p-well region 3 is usually about 1 × 10 17 cm −3 to 1 × 10 18 cm −3 , and the depth of the p-well region 3 is about 1 μm so as not to pinch off.

  Next, in the step shown in FIG. 6D, a polysilicon film covering the silicon oxide film 21, the p well region 3 and the p + contact region 4 used as the implantation mask is deposited, and the polysilicon film is selectively and differently formed. Sidewalls 22 are formed on the side surfaces of the silicon oxide film 21 by performing isotropic etching. When the sidewalls 22 are formed, a photolithography process is not necessary, and it is not necessary to use a photomask. Therefore, the source region 6 is formed in a self-aligned manner with respect to the p-well region 3.

  Then, using the silicon oxide film 21 and the sidewall 22 as a mask, a high concentration n-type impurity is doped into a part of the surface portion of the p-well region 3 by ion implantation to form the source region 6. At that time, in order to reduce implantation defects, nitrogen or phosphorus ions are implanted while maintaining the substrate temperature at a high temperature of 500 ° C. or higher.

Next, in the step shown in FIG. 6E, the silicon oxide film 21 and the sidewalls 22 used as the mask are removed by selective dry etching and hydrofluoric acid treatment. The impurity concentration in the source region 6 is about 1 × 10 19 cm −3 , which is lower than the impurity concentration in the p + contact region 4. Further, the depth of the source region 6 is shallower than the depth of the p + contact region 4 and is, for example, about 300 nm.

Further, a carbon film 9 is deposited on the high resistance SiC layer 2, the well region 3 and the source region 6. The carbon film 9 is deposited by the following procedure. First, an SiC substrate is installed on a substrate attachment portion of a sputter deposition apparatus (not shown), and the inside of the chamber is evacuated by a gas exhaust system. The degree of vacuum at this time is about 10 −4 Pa. After evacuating the inside of the chamber with a gas exhaust system, Ar gas was introduced and high frequency power of 13.56 MHz and 100 W was applied to the carbon plate target at a pressure of about 10 −2 Pa to perform sputter deposition. Do. A carbon film 9 having a thickness of 50 nm is formed by vapor deposition for about 20 minutes. At this time, it is confirmed that there are few components other than carbon such as hydrogen contained in the carbon film 97, and 99% or more of the components of the carbon film 9 are carbon.

  Next, the SiC substrate covered with the carbon film 9 is set in an annealing apparatus (not shown), and an annealing atmosphere gas is supplied from a gas supply system. Argon gas is selected as the annealing atmosphere gas. The flow rate of argon gas was 0.5 liter / min. The pressure in the chamber is constant at 91 kPa. Thereafter, the substrate temperature is raised to 1750 ° C., and while maintaining this temperature, activation annealing of impurities implanted into the high resistance SiC layer 2, the well region 3 and the source region 6 is performed for 30 minutes. Next, while supplying the argon gas, the application of the high-frequency power to the coil is stopped to finish the heating, and the substrate is cooled.

  Next, in the step shown in FIG. 6F, the carbon film 9 is uniformly melted and removed by treatment with a 3: 1 mixed solution of sulfuric acid and hydrogen peroxide. In this case, the mixed aqueous solution hardly melts the SiC layer, and only the carbon film is removed.

  Subsequently, in order to completely remove the carbon film 9, an SiC substrate is placed in the thermal oxidation chamber, and oxygen is supplied at a flow rate of 5 liters / minute and heated to 800 ° C. By heating for 30 minutes, the carbon film 9 on the surface is almost completely removed, but in this embodiment, heating is performed for 60 minutes. As a result, in this embodiment, the activation rate of aluminum is 90% or more, and a sufficient activation rate is obtained.

  Here, also in the present embodiment, as in the second embodiment, the average surface roughness Ra of the high-resistance SiC layer 2, the well region 3, and the source region 6 after the removal of the carbon film 9 is about 2 nm or less. For example, data of about 0.9 nm to 1.3 nm is obtained. That is, the surface roughness accompanying activation annealing does not occur.

  Next, epitaxial growth layer 5 including channel layer 5 x is epitaxially grown on high resistance SiC layer 2, well region 3, and source region 6 after removal of carbon film 9. The conditions at this time are as described in the step shown in FIG. 3A in the first embodiment.

  Also in this embodiment, the average surface roughness Ra of the channel layer 5x immediately after epitaxial growth has a value of about 0.08 nm to 0.8 nm, for example. In other words, it was found that the surface roughness was smaller than the surface roughness of the epitaxially grown underlayer, and a smoothing phenomenon occurred in the epitaxial growth. Specifically, when the surface roughness Ra of the high-resistance SiC layer 2, the well region 3 and the source region 6 before epitaxial growth (after annealing covering the carbon film) is 1.3 nm, the channel layer 5x immediately after epitaxial growth The average surface roughness Ra is 0.78 nm, and when the surface roughness Ra of the high-resistance SiC layer 2, the well region 3 and the source region 6 before epitaxial growth (after annealing coated with a carbon film) is 0.9 nm, Data indicating that the average surface roughness Ra of the channel layer 5x immediately after the epitaxial growth is 0.08 nm is obtained.

  Since the subsequent steps are as shown in FIGS. 3B to 3E in the first embodiment, illustration and description are omitted.

  According to this embodiment, in addition to the effects of the second embodiment, the following effects can be obtained. In this embodiment, sidewalls 22 are formed on the side surfaces of the silicon oxide film 21 that is an implantation mask for forming the p-well region 3 in the step shown in FIG. Ion implantation for forming the source region 6 is performed using the wall 22 as an implantation mask. Therefore, since source region 6 is formed in a self-aligned manner with respect to p well region 3, the width of p well region 3 in the cross section shown in FIG. 6 (e) (from source region 6 to high-resistance SiC layer 2). (Distance) is substantially constant, which makes the channel length substantially uniform. That is, the electrical characteristics of the MISFET using the SiC substrate are stabilized.

(Fourth embodiment)
FIG. 7 is a cross-sectional view showing the structure of a MESFET, which is a lateral transistor in the fourth embodiment.

  As shown in the figure, the MESFET of this embodiment includes an intrinsic SiC substrate 41 which is an insulating substrate, an undoped high-resistance SiC layer 42 formed by epitaxial growth on the SiC substrate 41, and a high-resistance SiC. Epitaxial growth including source region 44 and drain region 45 formed by doping n-type impurities in two regions separated from each other in layer 42, and channel layer 46x formed by epitaxial growth on high-resistance SiC layer 42 A layer 46; a source electrode 49 made of a Ni alloy film that reaches the source region 44 through a portion of the channel layer 46x positioned above the source region 44; and a position above the drain region 45 in the channel layer 46x. Of the Ni alloy film that reaches the drain region 45 through the portion to be In-electrode 50, and a Schottky gate electrode 51 formed on a region located between the source electrode 49 and the drain electrode 50 of the channel layer 46x.

The channel layer 46x is thinner than the first semiconductor layer 46a functioning as a carrier traveling region and the first semiconductor layer 46a, and has a high concentration of n capable of supplying carriers to the first semiconductor layer 46a. It has a laminated doped layer structure in which second semiconductor layers 46b containing type impurities are alternately laminated. For example, the impurity concentration in the first semiconductor layer 46a is 1 × 10 16 cm −3 or less and the thickness thereof is about 40 nm, and the impurity concentration in the second semiconductor layer 46b is 1 × 10 17 to 1 × 10 18. The thickness is about cm −3 and about 10 nm. For example, the lowermost layer of the channel layer 46x is the first semiconductor layer 46a, the first semiconductor layer 46a and the second semiconductor layer 46b are alternately deposited for three periods, and the first semiconductor layer 46a is further stacked on the outermost layer. This is the structure. In this case, when the thickness of the first semiconductor layer 46a is 40 nm and the thickness of the second semiconductor layer 46b is 10 nm, the thickness of the channel layer 46x is 190 nm.

  FIGS. 8A to 8E and FIGS. 9A to 9C are cross-sectional views showing manufacturing steps of the MESFET of this embodiment.

First, in the step shown in FIG. 8A, an undoped high resistance is formed on the main surface of the SiC substrate 41 which is an off substrate having an off angle of 8 degrees from the (0001) plane of 4H-SiC by thermal CVD or the like. The SiC layer 42 is epitaxially grown. At this time, for example, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas. The thickness of the high resistance SiC layer 42 is preferably, for example, several μm.

  Next, in the step shown in FIG. 8B, nitrogen or phosphorus, which is an n-type impurity, is ion-implanted into portions of the high-resistance SiC layer 42 that are separated from each other to form the source region 44 and the drain region 45. When the source region 44 and the drain region 45 are formed, a silicon oxide film 43 having a thickness of about 1 μm serving as an implantation mask is deposited on the high-resistance SiC layer 42 by CVD, followed by photolithography and dry etching. Then, an opening is formed in a portion of the silicon oxide film 43 located above the source region 44 and the drain region 45. Then, in order to reduce implantation defects, nitrogen or phosphorus is ion-implanted while maintaining the substrate temperature at a high temperature of 500 ° C. or higher. After the ion implantation, the silicon oxide film 43 is removed with hydrofluoric acid.

At this time, the concentration of the n-type impurity in the source region 44 and the drain region 45 is usually 1 × 10 18 cm −3 or more and the depth is about 0.3 μm.

  Next, in the step shown in FIG. 8C, in order to activate the impurities implanted in the step shown in FIG. 8B, an inert gas such as argon is deposited with the carbon film 55 deposited on the substrate. In a gas atmosphere, activation annealing is performed at 1750 ° C. for 30 minutes. The deposition method and annealing method of the carbon film 55 are the same as those shown in FIG. 5E in the second embodiment.

  Next, the carbon film 55 is removed in the step shown in FIG. At this time, in order to remove the carbon film 55, the treatment with a 3: 1 mixed solution of sulfuric acid and hydrogen peroxide, the heat treatment in the thermal oxidation chamber, and the conditions of these treatments are as follows. This is the same as the step shown in FIG. 5F in the embodiment.

Next, in the step shown in FIG. 8E, the epitaxial growth layer 46 including the channel layer 46x is epitaxially grown by, for example, thermal CVD. When forming the second semiconductor layer 46b (see FIG. 7) in the channel layer 46x, for example, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases and hydrogen (H 2 is used as a carrier gas). ) And nitrogen (N 2 ) as dopant gas. Further, when forming the first semiconductor layer 46a (see FIG. 7) in the channel layer 46x, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases without supplying a dopant gas. Hydrogen (H 2 ) is supplied as a carrier gas. By repeating this thermal CVD alternately, the structure of the laminated doped layer structure shown in FIG. 7 can be realized.

  Next, in the step shown in FIG. 9A, on the portion of the epitaxial growth layer 46 located above the source region 44 and the drain region 46, the step shown in FIG. Do the same process. That is, Ni films 49x and 50x with a thickness of 200 nm, which will become source and drain electrodes, are left on the substrate by a lift-off method using a resist film Re (not shown).

  Next, in the step shown in FIG. 9B, the Ni films 49x and 50x are heat-treated in an inert gas atmosphere such as nitrogen at a temperature of 1000 ° C. for 2 minutes. During this heat treatment, mutual diffusion and reaction of nickel (Ni) and silicon carbide (SiC) occur, penetrate the channel layer 46x, and reach the source region 44 and the drain region 45, respectively. A source electrode 49 and a drain electrode 50 made of silicide are formed.

  Next, in the step shown in FIG. 9C, the Schottky gate electrode 51 is formed on the channel layer 46x at a portion located between the source electrode 44 and the drain electrode 46. As the Schottky gate electrode 51, for example, a method of lifting off a nickel film or the like can be used. The thickness of the Schottky gate electrode 51 is preferably about 200 nm, for example.

  Although the subsequent steps are not shown, a silicon oxide film having a thickness of about 1 μm is deposited as an interlayer insulating film covering the source electrode 44, the drain electrode 46, the Schottky gate electrode 51 and the channel layer 46x, and the interlayer insulating film is formed by RIE or the like. Via holes reaching the source electrode 44, the drain electrode 46, and the Schottky gate electrode 51 are formed, and an aluminum film having a thickness of about 2 μm is deposited by vacuum evaporation or the like, and patterned by ordinary photolithography and etching. By performing the annealing, electrode pads and wirings are formed.

  Also in the present embodiment, a MESFET with high carrier mobility and high current capability can be obtained by smoothing the surface of the channel layer 46x as in the second embodiment. In particular, in the MESFET of this embodiment, since the channel layer 46x has a laminated doped layer structure, a MESFET having a high breakdown voltage and a high current capability can be obtained.

  When the cross section of the channel layer 46x of the MESFET formed by using the manufacturing process of the present embodiment was evaluated by TEM, the maximum surface roughness Rmax was about 1 nm on the lower surface and the surface of the channel layer 46x, and the average surface When the roughness Ra was obtained, only unevenness of 1 nm or less was observed, and good smoothness was realized.

  In the present embodiment, the semiconductor device is a MESFET having no gate insulating film, but in the case of a lateral MISFET in which a gate insulating film is provided on the channel layer 46x and a gate electrode is provided on the gate insulating film. In addition, the same effects as those of the first embodiment can be exhibited.

  Note that the MESFET and the lateral MISFET of this embodiment can be formed using not only a bulk SiC substrate but also a SiC substrate obtained by epitaxially growing a SiC layer on various oxide substrates.

(Fifth embodiment)
FIG. 10 is a cross-sectional view showing the structure of a MISFET which is a lateral transistor in the fifth embodiment.

As shown in the figure, the MISFET of this embodiment includes a low-resistance P-type SiC substrate 61 and 1 × 10 15 cm −3 to 1 × 10 16 cm formed on the SiC substrate 61 by epitaxial growth. A high-resistance SiC layer 62 containing about −3 P-type impurities, a source region 64 and a drain region 65 formed by doping n-type impurities in two regions separated from each other in the high-resistance SiC layer 62, An epitaxial growth layer 66 including a channel layer 66x formed by epitaxial growth on the high-resistance SiC layer 62, and a Ni alloy film that reaches the source region 64 through a portion of the epitaxial growth layer 66 located above the source region 64 The source electrode 69 and the epitaxial growth layer 66 through the portion located above the drain region 65 are drained. A drain electrode 70 made of a Ni alloy film reaching the in region 65, a gate electrode 71 formed on a region of the channel layer 66x located between the source electrode 69 and the drain electrode 70, a gate electrode 71 and a channel And a gate insulating film 72 interposed between the layer 66x. The thickness of the gate insulating film 72 is about 80 nm, the gate length is 10 μm, and the gate width is 500 μm. On the back surface of SiC substrate 61, a base electrode 73 made of Al is provided.

The channel layer 66x has a first semiconductor layer 66a that functions as a carrier traveling region, and a thickness that is smaller than that of the first semiconductor layer 66a and that can supply carriers to the first semiconductor layer 66a. It has a laminated doped layer structure in which second semiconductor layers 66b containing type impurities are alternately laminated. For example, the impurity concentration in the first semiconductor layer 66a is 1 × 10 16 cm −3 or less and the thickness is about 40 nm, and the impurity concentration in the second semiconductor layer 66b is 1 × 10 17 to 1 × 10 18. The thickness is about cm −3 and about 10 nm. For example, the lowermost layer of the channel layer 66x is the first semiconductor layer 66a, and the first semiconductor layer 66a and the second semiconductor layer 66b are alternately deposited in three cycles, and the first semiconductor layer 66a is further stacked on the outermost layer. This is the structure. In this case, when the thickness of the first semiconductor layer 66a is 40 nm and the thickness of the second semiconductor layer 66b is 10 nm, the thickness of the channel layer 66x is 190 nm.

  The manufacturing method according to the present embodiment is basically the same as the manufacturing method according to the fourth embodiment except that a step of forming the gate insulating film 72 is added.

  According to the lateral MISFET of the present embodiment, since the surface of the channel layer 66x is smoothed, the lateral MISFET that exhibits high current driving force and high carrier mobility is provided as in the vertical MISFET of the second embodiment. Will be obtained. Also, variations in threshold voltage due to the MISFET lot and the position in the wafer are reduced.

FIGS. 13A and 13B are diagrams showing threshold voltage distribution states of the lateral MISFET of the reference example and the lateral MISFET of this embodiment, respectively. In the lateral MISFET of the reference example, after epitaxially growing an epitaxial growth layer including a channel layer, ion implantation is performed for forming a source / drain region from above the epitaxial growth layer, and further, a carbon film is deposited and then impurity activation annealing is performed. It was done. Comparing FIGS. 13A and 13B, the threshold voltage of the lateral MISFET of the reference example varies in a wide range of −7.5 V to 5.0 V, whereas the lateral MISFET of the present embodiment The threshold voltage is concentrated in the range of 2.0 V to 4.5 V, and it can be seen that a lateral MISFET with small variations in threshold voltage can be obtained according to this embodiment. Further, the carrier mobility of the lateral MISFET of the reference example is 20 cm 2 / Vs, whereas the carrier mobility of the lateral MISFET of the present embodiment is 70 cm 2 / Vs, and the carrier mobility is remarkably improved. I understand that.

  The data shown in FIG. 13B is data for the horizontal MISFET, but similar data is obtained for the vertical MISFET. Therefore, in the vertical MISFET and MESFET, after the ion implantation for forming the source region is performed, in the lateral MISFET, the ion implantation for forming the source / drain region is performed, and then the impurity activity is performed in the state where the carbon film is deposited. The channel layer having a smaller surface roughness than that of the underlying layer for epitaxial formation can be obtained by performing annealing for the formation of the film, and then removing the carbon film and performing annealing for forming the channel layer. it can. As a result, it is possible to obtain a vertical MISFET, a horizontal MISFET, a MESFET or the like having a large current driving capability.

  Further, the carrier mobility of these devices can be improved, and MISFETs (including vertical MISFETs and lateral MISFETs) with small variations in threshold voltage can be obtained.

  The semiconductor device and the manufacturing method thereof according to the present invention can be used for MISFET, MESFET, and the like using a SiC substrate, which are particularly suitable for power devices and high-frequency devices.

It is sectional drawing which shows the structure of the double injection type MISFET which is the 1st Embodiment of this invention. (A)-(f) is a figure which shows the first half part in the manufacturing process of the double injection type MISFET of 1st Embodiment. (A)-(e) is a figure which shows the latter half part in the manufacturing process of the double injection type MISFET of 1st Embodiment. (A), (b) is sectional drawing which shows the difference in the overlap of the source region and channel layer in the conventional MISFET which respectively used the SiC substrate, and MISFET of this invention in order. (A)-(f) is a figure which shows the first half part in the manufacturing process of the double injection type MISFET of 2nd Embodiment. (A)-(e) is a figure which shows the first half part in the manufacturing process of the double injection type MISFET of 3rd Embodiment. It is sectional drawing which shows the structure of MESFET which is a horizontal transistor in 4th Embodiment. (A)-(e) is a figure which shows the first half part in the manufacturing process of the double injection type MISFET of 4th Embodiment. (A)-(c) is a figure which shows the second half part in the manufacturing process of the double injection type MISFET of 4th Embodiment. It is sectional drawing which shows the structure of MESFET which is a horizontal transistor in 5th Embodiment. (A), (b) is a figure which shows the IV characteristic of the vertical MISFET of a reference example, and the vertical MISFET of this embodiment in order, respectively. It is a figure which shows the IV characteristic of the vertical MISFET of this embodiment. (A), (b) is a figure which shows the distribution state of the threshold voltage of the lateral MISFET of a reference example, and the lateral MISFET of this embodiment in order, respectively. It is sectional drawing which shows the structure of storage type MISFET using the conventional SiC substrate, and double injection type MISFET. (A)-(e) is a figure which shows the first half part in the manufacturing process of the conventional double injection type MISFET. (A)-(e) is a figure which shows the latter half part in the manufacturing process of the conventional double injection type MISFET. It is a SEM photograph figure which shows the structure of the channel layer vicinity of the storage type double injection MISFET of the structure substantially the same as what is disclosed by the nonpatent literature 2. It is a figure which shows correlation with the average surface roughness Ra of the base layer before epitaxial growth, and the average surface roughness Ra of an epitaxial growth layer in the manufacturing process of the double injection type MISFET of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 High resistance SiC layer 3 p well region 4 p + contact region 5 epitaxial growth layer 5x channel layer 5a first semiconductor layer 5b second semiconductor layer 6 source region 7 gate insulating film 8 source electrode 9 drain electrode 10 gate Electrode 20 Contact hole 21 Silicon oxide film 22 Side wall 41 SiC substrate 42 High resistance SiC layer 43 Silicon oxide film 44 Source region 45 Drain region 46 Epitaxial growth layer 46x Channel layer 46a First semiconductor layer 46b Second semiconductor layer 47 Contact hole 48 Metal thin film 49 Source electrode 50 Drain electrode 51 Schottky gate electrode

Claims (16)

  1. A silicon carbide layer provided on the main surface of the substrate;
    A high concentration impurity diffusion region provided in a part of the silicon carbide layer and including a first conductivity type impurity;
    An epitaxial growth layer formed by epitaxial growth on at least a part of the high-concentration impurity diffusion region and on the silicon carbide layer;
    A semiconductor device comprising: a channel layer provided in a part of the epitaxial growth layer, the upper surface of which is smoother than the upper surface of the silicon carbide layer and straddles the high concentration impurity diffusion region.
  2. The semiconductor device according to claim 1,
    A semiconductor device further comprising an electrode penetrating the epitaxial growth layer and reaching the high concentration impurity region.
  3. The semiconductor device according to claim 1 or 2,
    A semiconductor device, wherein an upper surface of the silicon carbide layer is smoothed by polishing.
  4. The semiconductor device according to claim 1 or 2,
    The semiconductor device, wherein the upper surface of the silicon carbide layer is subjected to an impurity activation process in a state of covering a carbon film.
  5. In the semiconductor device according to any one of claims 1 to 4,
    A semiconductor device, wherein, in a cross section including the channel layer and the high concentration impurity diffusion region, a lateral dimension of an overlap region between the channel layer and the high concentration impurity diffusion region is larger than a thickness of the channel layer.
  6. In the semiconductor device according to any one of claims 1 to 5,
    A semiconductor device, wherein an average surface roughness of a surface of the silicon carbide layer contacting the channel layer is 2 nm or less.
  7. In the semiconductor device according to claim 1,
    A semiconductor device, wherein an average surface roughness of an upper surface of the channel layer is 1 nm or less.
  8. In the semiconductor device according to any one of claims 1 to 7,
    The channel layer includes at least one first semiconductor layer functioning as a carrier traveling region and a carrier impurity having a concentration higher than that of the first semiconductor layer, and is thinner than the first semiconductor layer. A semiconductor device including a stacked doped layer structure configured by alternately stacking at least one second semiconductor layer capable of supplying carriers to the first semiconductor layer.
  9. In the semiconductor device according to claim 1,
    A well region including a second conductivity type impurity formed so as to surround the high concentration impurity diffusion region in a part of the silicon carbide layer;
    A gate insulating film provided on the channel layer;
    A gate electrode provided on the gate insulating film;
    An ohmic electrode provided on the back surface of the silicon carbide substrate;
    The high concentration impurity diffusion region functions as a source region,
    The silicon carbide layer contains a first conductivity type impurity,
    The channel layer straddles the high concentration impurity diffusion region and the well region,
    The silicon carbide substrate functions as a drain region,
    A semiconductor device that functions as a vertical MISFET.
  10. In the semiconductor device according to claim 1,
    Another high-concentration impurity diffusion region containing the first conductivity type impurity provided in the other part of the silicon carbide layer;
    A gate insulating film provided on the channel layer;
    A gate electrode provided on the gate insulating film,
    The high-concentration impurity diffusion region and other high-concentration impurity diffusion regions function as source / drain regions,
    The channel layer straddles the high concentration impurity diffusion region and the other high concentration impurity diffusion region,
    A semiconductor device that functions as a horizontal MISFET.
  11. In the semiconductor device according to claim 1,
    Another high-concentration impurity diffusion region containing the first conductivity type impurity provided in the other part of the silicon carbide layer;
    A gate electrode in Schottky contact with the channel layer;
    The high-concentration impurity diffusion region and other high-concentration impurity diffusion regions function as source / drain regions,
    The channel layer straddles the high concentration impurity diffusion region and the other high concentration impurity diffusion region,
    A semiconductor device that functions as a MESFET.
  12. (A) forming a high-concentration impurity diffusion region by ion-implanting a first conductivity type impurity into a part of the silicon carbide layer of the substrate;
    (B) performing annealing for activating impurities implanted in the high concentration impurity diffusion region;
    Smoothing the upper surface of the silicon carbide layer including the high-concentration impurity diffusion layer (c);
    After the step (c) , a step (d) of forming an epitaxial growth layer including a channel layer over a part of the high-concentration impurity diffusion region on the silicon carbide layer.
  13. In the manufacturing method of the semiconductor device according to claim 12 ,
    The step (c) includes a step (c1) of covering the silicon carbide layer with a carbon film before the step (b) ;
    And a step (c2) of removing the carbon film after the step (b), a method of manufacturing a semiconductor device.
  14. In the manufacturing method of the semiconductor device according to claim 12 ,
    In the step (c), a semiconductor device manufacturing method in which mechanochemical polishing is performed.
  15. In the manufacturing method of the semiconductor device according to any one of claims 12 to 14 ,
    After the step (d) , a step (e) of forming a metal film on a region located above the high concentration impurity diffusion region of the epitaxial growth layer;
    A method of manufacturing a semiconductor device, further comprising a step (f) of reacting the metal film and the epitaxial growth layer by heat treatment to form an electrode made of an alloy film reaching the high-concentration impurity diffusion region.
  16. In the manufacturing method of the semiconductor device according to any one of claims 12 to 15 ,
    Prior to the step (a), ion implantation of a second conductivity type impurity is performed using an implantation mask having an opening in a region located above a part of the silicon carbide layer, and the high concentration impurity diffusion region is formed. Forming a surrounding well region (g) ;
    Forming a sidewall covering a side surface of the opening of the implantation mask (h) ,
    In the step (a), a method of manufacturing a semiconductor device, wherein ion implantation of the first conductivity type impurity is performed using the implantation mask and sidewalls.
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