JPH11297712A - Formation method for compound film and manufacture of semiconductor element - Google Patents

Formation method for compound film and manufacture of semiconductor element

Info

Publication number
JPH11297712A
JPH11297712A JP10099224A JP9922498A JPH11297712A JP H11297712 A JPH11297712 A JP H11297712A JP 10099224 A JP10099224 A JP 10099224A JP 9922498 A JP9922498 A JP 9922498A JP H11297712 A JPH11297712 A JP H11297712A
Authority
JP
Japan
Prior art keywords
film
compound
forming
semiconductor
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10099224A
Other languages
Japanese (ja)
Inventor
Kenichi Kawaguchi
健一 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10099224A priority Critical patent/JPH11297712A/en
Publication of JPH11297712A publication Critical patent/JPH11297712A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the formation method of a compound film for forming a satisfactory compound film, in a short time, while turning a boundary between a semiconductor and the compound film formed on it into a satisfactory state and the manufacturing method of a semiconductor element using it. SOLUTION: This forming method of a compound film is provided with a process for exposing the surfaces of semiconductors 2, 3a, 3b, 4a and 4b to atmospheric gas for forming a compound composed by combining with the constituent elements which constitute the semiconductor and forming a compound thin film 6 on the surfaces of the semiconductors 2, 3a, 3b, 4a and 4b and a process for forming a compound film 7 through a vapor phase formation method on the compound thin film 6.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は化合物膜の形成方法
及び半導体素子の製造方法に関する。
The present invention relates to a method for forming a compound film and a method for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】近年、炭化ケイ素の半導体素子が耐環境
性素子、パワー素子として活発に研究開発されている。
2. Description of the Related Art In recent years, silicon carbide semiconductor devices have been actively researched and developed as environment-resistant devices and power devices.

【0003】斯る炭化ケイ素の半導体素子として、電解
効果型半導体素子(FET)、特にMOS−FETが注
目を浴びている。
As such a silicon carbide semiconductor device, a field effect semiconductor device (FET), particularly a MOS-FET, has received attention.

【0004】このMOS−FETのチャネルとゲ−ト電
極の間に形成される絶縁膜(ゲート絶縁膜)には、通
常、炭化ケイ素表面を熱酸化して形成される酸化ケイ素
(SiOx)膜が使用されるか、またはCVD法(化学
蒸着法)により形成される酸化ケイ素膜が使用される。
The insulating film (gate insulating film) formed between the channel and the gate electrode of the MOS-FET is usually a silicon oxide (SiO x ) film formed by thermally oxidizing the surface of silicon carbide. Or a silicon oxide film formed by a CVD method (chemical vapor deposition method).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前記ゲ
ート絶縁膜は耐電圧等の関係から所定厚以上の厚みが必
要となるが、熱酸化法による酸化ケイ素膜の形成方法で
は、その酸化ケイ素膜の膜厚が大きくなるにしたがっ
て、チャネル上となる炭化ケイ素表面、即ち炭化ケイ素
表面とこの上に形成される酸化ケイ素膜の間の界面の乱
れが大きくなる。
However, the gate insulating film needs to have a predetermined thickness or more from the viewpoint of withstand voltage and the like. However, in the method of forming a silicon oxide film by a thermal oxidation method, the thickness of the silicon oxide film is reduced. As the film thickness increases, the turbulence of the silicon carbide surface on the channel, that is, the interface between the silicon carbide surface and the silicon oxide film formed thereon increases.

【0006】この結果、チャネルを通過する電子の速度
が遅くなり、十分な素子特性が得られないといった問題
が生じる。
As a result, there arises a problem that the speed of electrons passing through the channel becomes slow and sufficient element characteristics cannot be obtained.

【0007】更に、熱酸化法では、酸化膜の成長が遅
く、製造に時間を要するといった問題が生じる。
Further, the thermal oxidation method has a problem that the growth of an oxide film is slow and a long time is required for manufacturing.

【0008】しかも、炭化ケイ素の表面に酸化ケイ素膜
を形成する場合、炭化ケイ素を構成する炭素と炭化ケイ
素表面を酸化させるために供給される酸素とが結合して
CO x(xは0以上)が発生するが、酸化ケイ素膜の厚
みが増すと、上記COxが酸化ケイ素膜から外部への拡
散が十分でなくなる。この結果として、このCOxに起
因して炭化ケイ素表面と前記酸化ケイ素膜の間の界面近
傍に炭素を含む析出物が生成されると共に、酸化ケイ素
膜の成長進行が妨げられ、また酸化ケイ素膜中にCOx
が混入するといった問題が起こる。
In addition, a silicon oxide film is formed on the surface of silicon carbide.
When forming silicon carbide, silicon and silicon carbide
Oxygen supplied to oxidize the element surface
CO x(X is 0 or more), but the thickness of the silicon oxide film
When the amount increases, the COxSpread from the silicon oxide film to the outside
Scattering is not enough. As a result, this COxKi
Due to the vicinity of the interface between the silicon carbide surface and the silicon oxide film
A precipitate containing carbon is generated beside the silicon oxide
The growth of the film is hindered and CO2 is contained in the silicon oxide film.x
Problems occur.

【0009】また、CVD法等の気相成長法による酸化
ケイ素膜などの絶縁膜は、成長面において不飽和結合
(共有結合結晶の場合、ダングリングボンドと呼ばれ
る)が存在する場合、成長面と形成した絶縁膜の間の界
面、絶縁膜の特性が劣化するといった問題がある。
Further, an insulating film such as a silicon oxide film formed by a vapor phase growth method such as a CVD method has a disadvantage that when an unsaturated bond (called a dangling bond in the case of a covalent bond crystal) is present on the growth surface, the insulating film is not formed on the growth surface. There is a problem that the interface between the formed insulating films and the characteristics of the insulating film are deteriorated.

【0010】本発明は上述の問題点を鑑み成されたもの
であり、半導体とその上に形成される化合物膜の間の界
面を良好な状態としつつ、良好な化合物膜を短時間で形
成する化合物膜の形成方法とこれを用いた半導体素子の
製造方法を提供することが目的である。
The present invention has been made in view of the above-mentioned problems, and forms a good compound film in a short time while keeping an interface between a semiconductor and a compound film formed thereon good. An object is to provide a method for forming a compound film and a method for manufacturing a semiconductor device using the same.

【0011】[0011]

【課題を解決するための手段】本発明の化合物膜の形成
方法は、半導体表面に該半導体が構成する構成元素と化
合してなる化合物を形成させるための雰囲気ガスを晒
し、前記半導体表面に化合物薄膜を形成する工程と、前
記化合物薄膜上に気相形成法により化合物膜を形成する
工程と、を備えることを特徴とする。
According to the method of forming a compound film of the present invention, an atmosphere gas for forming a compound formed by combining with a constituent element of the semiconductor is exposed to a semiconductor surface, and the compound is exposed to the semiconductor surface. A step of forming a thin film; and a step of forming a compound film on the compound thin film by a vapor phase formation method.

【0012】本発明では、半導体が構成する構成元素と
化合してなる化合物を形成させるための雰囲気ガスを晒
し、前記半導体表面に形成する化合物薄膜の膜厚が小さ
いので、半導体と化合物薄膜の間の界面の乱れを小さく
抑制できる。
In the present invention, an atmosphere gas for forming a compound formed by combining with the constituent elements of the semiconductor is exposed, and the thickness of the compound thin film formed on the semiconductor surface is small. Can be suppressed to a small extent.

【0013】更に、前記化合物薄膜は膜厚は小さいの
で、前記半導体と前記雰囲気ガスとが反応して生じる不
所望なガスはこの膜厚の薄い化合物薄膜から外部へ放出
されるので、前記半導体と前記化合物薄膜の間の界面近
傍に生じる不所望な析出物の発生を抑制できる。
Further, since the compound thin film has a small thickness, an undesired gas generated by the reaction between the semiconductor and the atmospheric gas is released to the outside from the thin compound thin film. Generation of undesired precipitates generated near the interface between the compound thin films can be suppressed.

【0014】しかも、半導体が構成する構成元素と化合
してなる化合物を形成させるための雰囲気ガスにより不
飽和結合は終端されるので、不飽和結合の存在が低減さ
れる。この結果、半導体と化合物薄膜との界面、化合物
薄膜と化合物膜との界面、該化合物薄膜上に形成される
化合物膜が良好なものとなる。
In addition, since the unsaturated bond is terminated by an atmosphere gas for forming a compound formed by combining with the constituent elements of the semiconductor, the presence of the unsaturated bond is reduced. As a result, the interface between the semiconductor and the compound thin film, the interface between the compound thin film and the compound film, and the compound film formed on the compound thin film are improved.

【0015】そして、成長速度の遅い形成方法で形成さ
れる化合物薄膜の膜厚を小さくし、成長速度の大きい気
相成長法で形成される化合物膜の膜厚を大きくしている
ので、前記半導体と前記化合物薄膜の間の界面を良好に
しつつ、所定の膜厚をもつ良好な化合物膜の製造時間を
短くできる。
Since the thickness of the compound thin film formed by the formation method having a low growth rate is reduced and the thickness of the compound film formed by the vapor growth method having a high growth rate is increased, The production time of a good compound film having a predetermined thickness can be shortened while improving the interface between the compound film and the compound thin film.

【0016】本発明の化合物膜の形成方法は、半導体表
面を該表面の不飽和結合を終端するための雰囲気ガスに
晒し、前記半導体表面に化合物薄膜を形成する工程と、
前記化合物薄膜上に気相形成法により化合物膜を形成す
る工程と、を備えることを特徴とする。
In the method for forming a compound film according to the present invention, a step of exposing a semiconductor surface to an atmosphere gas for terminating an unsaturated bond on the surface to form a compound thin film on the semiconductor surface;
Forming a compound film on the compound thin film by a vapor phase formation method.

【0017】本発明では、半導体表面を該表面の不飽和
結合を終端するための雰囲気ガスに晒し、前記半導体表
面に形成する化合物薄膜は膜厚が小さいので、半導体と
化合物薄膜の間の界面の乱れを小さく抑制できると共
に、不飽和結合の存在が低減されるので、化合物薄膜上
に形成される化合物膜が良好なものとなる。
According to the present invention, the semiconductor surface is exposed to an atmosphere gas for terminating the unsaturated bond on the surface, and the compound thin film formed on the semiconductor surface has a small thickness. Disturbance can be suppressed to a small extent, and the presence of unsaturated bonds is reduced, so that the compound film formed on the compound thin film is good.

【0018】更に、前記化合物薄膜は膜厚は小さいの
で、前記半導体と前記雰囲気ガスとが反応して生じる不
所望なガスは、この膜厚の薄い化合物薄膜から外部へ放
出されるので、前記半導体と前記化合物薄膜の間の界面
近傍に生じる不所望な析出物の発生を抑制できる。
Further, since the compound thin film has a small thickness, an undesired gas generated by the reaction between the semiconductor and the atmospheric gas is released to the outside from the thin compound thin film. And the generation of undesired precipitates generated in the vicinity of the interface between the thin film and the compound thin film.

【0019】そして、成長速度の遅い形成方法で形成さ
れる化合物薄膜の膜厚を小さくし、成長速度の大きい気
相成長法で形成される化合物膜の膜厚を大きくしている
ので、前記半導体と前記化合物薄膜の間の界面を良好に
しつつ、所定の膜厚をもつ良好な化合物膜の製造時間を
短くできる。
Since the thickness of the compound thin film formed by the formation method having a low growth rate is reduced and the thickness of the compound film formed by the vapor deposition method having a high growth rate is increased, The production time of a good compound film having a predetermined thickness can be shortened while improving the interface between the compound film and the compound thin film.

【0020】本発明の化合物膜の形成方法は、炭化ケイ
素からなる半導体の表面を酸化し、該炭化ケイ素の表面
に酸化ケイ素からなる化合物薄膜を形成する工程と、該
酸化ケイ素からなる化合物薄膜上に気相形成法により化
合物膜を形成する工程と、を備えることを特徴とする。
The method of forming a compound film according to the present invention comprises the steps of: oxidizing a surface of a semiconductor made of silicon carbide to form a compound thin film made of silicon oxide on the surface of the silicon carbide; Forming a compound film by a vapor phase formation method.

【0021】本発明では、酸化ケイ素からなる化合物薄
膜は膜厚が小さいので、炭化ケイ素表面と酸化ケイ素膜
の間の界面の乱れを小さく抑制できる。
In the present invention, since the compound thin film made of silicon oxide has a small thickness, disturbance at the interface between the silicon carbide surface and the silicon oxide film can be suppressed to a small level.

【0022】更に、前記酸化ケイ素膜の膜厚は小さいの
で、炭化ケイ素と酸化ガスとが反応して生じるCOx
どのガスは、この膜厚の薄い酸化ケイ素膜から外部へ放
出されるので、前記炭化ケイ素表面と前記酸化ケイ素膜
の間の界面近傍に生じる不所望な析出物の発生を抑制で
きる。
Furthermore, since the thickness of the silicon oxide film is small, gas, such as CO x resulting silicon carbide and oxidizing gas reacts, because is emitted to the outside from the thin silicon oxide film of this thickness, Undesired precipitates generated near the interface between the silicon carbide surface and the silicon oxide film can be suppressed.

【0023】しかも、前記酸化ガスにより不飽和結合は
終端されるので、不飽和結合の存在が低減される。この
結果、炭化ケイ素と酸化ケイ素膜との界面、酸化ケイ素
膜と化合物膜との界面、該酸化ケイ素膜上に形成される
化合物膜が良好なものとなる。
Moreover, since the unsaturated bond is terminated by the oxidizing gas, the presence of the unsaturated bond is reduced. As a result, the interface between the silicon carbide film and the silicon oxide film, the interface between the silicon oxide film and the compound film, and the compound film formed on the silicon oxide film are improved.

【0024】そして、成長速度の遅い形成方法、例えば
熱酸化法で形成される酸化ケイ素膜の膜厚を小さくし、
成長速度の大きい形成方法で形成される化合物膜の膜厚
を大きくしているので、前記炭化ケイ素と前記酸化ケイ
素膜の間の界面を良好にしつつ、所定膜厚をもつ良好な
化合物膜の製造時間を短くできる。
Then, the thickness of the silicon oxide film formed by a formation method having a low growth rate, for example, a thermal oxidation method is reduced,
Since the thickness of the compound film formed by the formation method having a high growth rate is increased, the production of a good compound film having a predetermined film thickness while improving the interface between the silicon carbide and the silicon oxide film is improved. Time can be shortened.

【0025】特に、前記化合物膜は、酸化ケイ素からな
ることを特徴とする。
Particularly, the compound film is made of silicon oxide.

【0026】前記化合物膜としては、AlNなどを用い
ることも可能であるが、酸化ケイ素膜上に形成される化
合物膜が酸化ケイ素である場合、同材料であるので、よ
り良好な化合物膜が形成される。
Although it is possible to use AlN or the like as the compound film, when the compound film formed on the silicon oxide film is silicon oxide, the same material is used, so that a better compound film can be formed. Is done.

【0027】特に、前記化合物薄膜の膜厚は、前記化合
物膜の膜厚に比べて小さいことを特徴とする。
In particular, the thickness of the compound thin film is smaller than the thickness of the compound film.

【0028】更に、前記表面はステップ状形状を有する
ことを特徴とする。
Further, the surface is characterized by having a step-like shape.

【0029】この場合、基板としてオフ基板(傾斜基
板:低指数面から傾斜した面をもつ基板)を用いればよ
い。
In this case, an off-substrate (inclined substrate: a substrate having a surface inclined from a low index surface) may be used as the substrate.

【0030】また、前記化合物薄膜と前記化合物膜のう
ち、少なくとも該化合物膜は絶縁膜であることを特徴と
する。特に、前記化合物薄膜と前記化合物膜の両方とも
絶縁膜であってよい。
Further, among the compound thin film and the compound film, at least the compound film is an insulating film. In particular, both the compound thin film and the compound film may be insulating films.

【0031】前記化合物薄膜が酸化物薄膜である場合
は、その製造には酸化ガス(酸素、オゾン、NO2、又
は酸素と水蒸気の混合ガスなど)又は原子状酸素、酸素
イオンなどの酸化種(活性種)などの雰囲気ガス中でア
ニール処理する熱酸化法が用いられ、窒化物薄膜である
場合は、その製造にはN2、NH3などの窒化ガスの雰囲
気ガス中でアニール処理する方法が用いられる。
When the compound thin film is an oxide thin film, it is manufactured by using an oxidizing gas (such as oxygen, ozone, NO 2 or a mixed gas of oxygen and water vapor) or an oxidizing species such as atomic oxygen and oxygen ions. A thermal oxidation method in which annealing is performed in an atmosphere gas such as an active species) is used. In the case of a nitride thin film, a method of annealing in an atmosphere gas of a nitriding gas such as N 2 or NH 3 is used for manufacturing the thin film. Used.

【0032】また、上述の気相成長法には、CVD法、
スパッタリング法、蒸着法、反応性蒸着法、MBE法な
どを適宜利用できる。
The above-mentioned vapor phase growth method includes a CVD method,
A sputtering method, an evaporation method, a reactive evaporation method, an MBE method, or the like can be appropriately used.

【0033】更に、上記半導体表面は平坦化処理され、
好ましくは表面浄化処理するのがよい。尚、上記半導体
表面は、半導体基板表面でもよく、半導体膜表面でもよ
い。
Further, the semiconductor surface is flattened,
Preferably, a surface cleaning treatment is performed. The semiconductor surface may be a semiconductor substrate surface or a semiconductor film surface.

【0034】本発明の化合物膜の形成方法を用いて半導
体素子を形成する半導体素子の製造方法であって、前記
半導体の表面に前記化合物薄膜を形成する工程と、該化
合物薄膜上に気相形成法により前記化合物膜を形成する
工程と、を備えることを特徴とする。
A method of manufacturing a semiconductor device using the method of forming a compound film according to the present invention, comprising the steps of: forming the compound thin film on the surface of the semiconductor; Forming the compound film by a method.

【0035】この場合、化合物薄膜/化合物膜の膜が良
好となるので、これが絶縁膜である場合には、十分な絶
縁特性が得られる。また、半導体の表面と化合物薄膜の
間の界面が良好であるので、素子特性の向上できる。
In this case, since the compound thin film / compound film becomes favorable, if this is an insulating film, sufficient insulating characteristics can be obtained. In addition, since the interface between the surface of the semiconductor and the compound thin film is good, device characteristics can be improved.

【0036】更に、素子の製造が短時間でできる。Further, the device can be manufactured in a short time.

【0037】更に、前記半導体素子は電解効果型半導体
素子であって、チャネル上の前記半導体の表面にゲート
絶縁膜としての前記化合物薄膜を形成する工程と、該化
合物薄膜上に気相形成法によりゲート絶縁膜の前記化合
物膜を形成する工程と、を備えることを特徴とする。
Further, the semiconductor device is a field effect type semiconductor device, wherein a step of forming the compound thin film as a gate insulating film on the surface of the semiconductor on a channel, and a step of forming the compound thin film on the compound thin film by a vapor phase forming method. Forming the compound film of the gate insulating film.

【0038】この場合、チャネル上の前記半導体の表面
とゲート絶縁膜の間の界面が良好になるので、チャネル
中を走行する電子の速度が向上する。従って、素子が十
分な速さで動作する。
In this case, since the interface between the surface of the semiconductor on the channel and the gate insulating film is good, the speed of electrons traveling in the channel is improved. Therefore, the element operates at a sufficient speed.

【0039】[0039]

【発明の実施の形態】本発明の第1の実施形態に係るM
OS−FETを図を用いて詳細に説明する。図1は本実
施形態のMOS−FETの概略模式構成図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS M according to a first embodiment of the present invention
The OS-FET will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of the MOS-FET of the present embodiment.

【0040】図1中、1はn型SiC基板、2はn型S
iC基板1上に形成されたn型SiCエピタキシャル
膜、3a、3bはn型SiCエピタキシャル膜2内に互
いに離間して形成されたp型不純物注入領域、4a、4
bはp型不純物注入領域3a、3b内にそれぞれ形成さ
れたn型不純物注入領域である。
In FIG. 1, 1 is an n-type SiC substrate and 2 is an n-type S
The n-type SiC epitaxial films 3a and 3b formed on the iC substrate 1 are p-type impurity implanted regions 4a and 4a formed separately from each other in the n-type SiC epitaxial film 2.
b is an n-type impurity implantation region formed in each of the p-type impurity implantation regions 3a and 3b.

【0041】5aはn型SiCエピタキシャル膜2の前
記離間した部分下に形成されるドリフト部、5b、5c
はp型不純物注入領域3a、3b内であってそれぞれn
型不純物注入領域4a、4bと前記離間の間に形成され
るチャネル部である。
5a is a drift portion formed below the spaced portion of the n-type SiC epitaxial film 2, 5b, 5c
Represents n in the p-type impurity implanted regions 3a and 3b, respectively.
This is a channel portion formed between the mold impurity implantation regions 4a and 4b and the separation.

【0042】6はチャネル部5b、5c上、前記ドリフ
ト部5a上のn型SiCエピタキシャル膜2上、及びn
型不純物注入領域4a、4bの一部上に形成された酸化
ケイ素(SiOx)からなる極薄酸化絶縁膜、7は極薄
酸化絶縁膜6上に形成された酸化ケイ素(SiOx)か
らなる堆積酸化絶縁膜である。本発明では、ゲート絶縁
膜として、極薄酸化絶縁膜6とこれに比べて十分膜厚の
大きい堆積酸化絶縁膜7の2層構造で構成される。
Reference numeral 6 denotes a portion on the channel portions 5b and 5c, on the n-type SiC epitaxial film 2 on the drift portion 5a, and n
-Type impurity doped region 4a, a portion on the formed silicon oxide (SiO x) ultrathin oxide insulating film made of 4b, 7 consists of very thin oxide insulating film 6 on which is formed in silicon oxide (SiO x) It is a deposited oxide insulating film. According to the present invention, the gate insulating film has a two-layer structure of an ultra-thin oxide insulating film 6 and a deposited oxide insulating film 7 having a sufficiently large thickness as compared with this.

【0043】8は堆積酸化絶縁膜7上に形成された多結
晶Si膜からなるゲート電極、9aはゲート電極8と離
間してp型不純物注入領域3a及びn型不純物注入領域
4a上に形成されるNi等の金属膜からなるソース電
極、9bはゲート電極8と離間してp型不純物注入領域
3b及びn型不純物注入領域4b上に形成されるNi等
からなるソース電極、10はn型SiC基板1の裏面に
形成されたNi等からなるドレイン電極である。
Reference numeral 8 denotes a gate electrode made of a polycrystalline Si film formed on the deposited oxide insulating film 7, and 9a is formed on the p-type impurity implantation region 3a and the n-type impurity implantation region 4a apart from the gate electrode 8. A source electrode 9b made of a metal film of Ni or the like, 9b is a source electrode made of Ni or the like formed on the p-type impurity implantation region 3b and the n-type impurity implantation region 4b while being separated from the gate electrode 8, and 10 is an n-type SiC A drain electrode formed on the back surface of the substrate 1 and made of Ni or the like.

【0044】斯る素子の製造方法を図を用いて以下に説
明する。
A method for manufacturing such an element will be described below with reference to the drawings.

【0045】まず、図2(a)に示すように、表面清浄
化処理したn型SiC基板(Ndドープ:Nd濃度1×
1018〜1×1021cm-3)1を準備する。
First, as shown in FIG. 2A, a surface-cleaned n-type SiC substrate (Nd-doped: Nd concentration 1 ×
10 18 to 1 × 10 21 cm −3 ) 1 is prepared.

【0046】前記清浄化処理として、n型SiC基板1
の主面をアセトン及びエタノールで有機溶媒洗浄し、こ
の主面を酸素雰囲気中、1150℃、80分〜800分
でアニール処理して表面に酸化ケイ素膜を形成した後、
この酸化ケイ素膜を1〜5%のHF水溶液でエッチング
除去し、次に水素終端処理として、緩衝HF溶液処理、
低溶存酸素純水処理、沸騰純水処理、又は水素雰囲気中
で700〜1200℃のアニール処理を行う。
As the cleaning treatment, an n-type SiC substrate 1
After washing the main surface with acetone and ethanol with an organic solvent, annealing the main surface in an oxygen atmosphere at 1150 ° C. for 80 to 800 minutes to form a silicon oxide film on the surface,
The silicon oxide film is removed by etching with a 1 to 5% HF aqueous solution, and then a buffered HF solution treatment is performed as a hydrogen termination treatment.
A low dissolved oxygen pure water treatment, a boiling pure water treatment, or an annealing treatment at 700 to 1200 ° C. in a hydrogen atmosphere is performed.

【0047】本実施形態では、n型SiC基板1とし
て、4H−SiC又は6H−SiCを使用し、前記主面
として(0001)面又は(000−1)面から[11
−20]方向へ1度から10度傾斜した面を用いた。
In this embodiment, 4H-SiC or 6H-SiC is used as the n-type SiC substrate 1, and the principal surface is defined as (11) from (0001) plane or (000-1) plane.
A surface inclined from 1 degree to 10 degrees in the [-20] direction was used.

【0048】次に、図2(b)に示すように、n型Si
C基板1の主面上にCVD法により1〜50μm厚のn
型SiCエピタキシャル膜(Ndドープ:Nd濃度1×
10 15〜1×1017cm-3)2を形成する。
Next, as shown in FIG.
An n layer having a thickness of 1 to 50 μm is formed on the main surface of the C substrate 1 by the CVD method.
Type SiC epitaxial film (Nd-doped: Nd concentration 1 ×
10 Fifteen~ 1 × 1017cm-32) is formed.

【0049】続いて、図2(c)に示すように、n型S
iCエピタキシャル層2中にp型不純物注入領域3a、
3bをイオン注入法により形成する。ここで、注入不純
物はAl、Ga又はB、注入温度は500〜1000
℃、注入量は1×1015〜1×1018cm-3である。
Subsequently, as shown in FIG.
a p-type impurity implanted region 3a in the iC epitaxial layer 2;
3b is formed by ion implantation. Here, the implantation impurity is Al, Ga or B, and the implantation temperature is 500 to 1000.
C., the injection amount is 1 × 10 15 to 1 × 10 18 cm −3 .

【0050】次に、図2(d)に示すように、p型不純
物注入領域3a、3b内にそれぞれn型不純物注入領域
4a、4bをイオン注入法により形成する。ここで、注
入不純物はN又はP、注入温度は500〜1000℃、
注入量は1×1018〜1×1021cm-3である。
Next, as shown in FIG. 2D, n-type impurity implanted regions 4a and 4b are formed in the p-type impurity implanted regions 3a and 3b by ion implantation. Here, the implantation impurity is N or P, the implantation temperature is 500 to 1000 ° C.,
The injection amount is 1 × 10 18 to 1 × 10 21 cm −3 .

【0051】上記工程後、p型不純物注入領域3a、3
b及びn型不純物注入領域4a、4bに注入された不純
物をキャリアとして機能するように活性化させるため
に、800〜1500℃、真空中又は不活性ガス雰囲気
中でアニール処理する。
After the above steps, the p-type impurity implanted regions 3a, 3a
In order to activate the impurities implanted in the b and n-type impurity implanted regions 4a and 4b so as to function as carriers, annealing is performed at 800 to 1500 ° C. in a vacuum or in an inert gas atmosphere.

【0052】次に、図2(e)に示すように、p型不純
物注入領域3a、3b、n型不純物注入領域4a、4b
及びn型SiCエピタキシャル層2の表面を前記表面浄
化処理と同様の処理を行った後、表面に0.5〜5nm
厚の極薄酸化絶縁膜6を熱酸化法により形成した。
Next, as shown in FIG. 2E, p-type impurity implanted regions 3a and 3b, n-type impurity implanted regions 4a and 4b
After the surface of the n-type SiC epitaxial layer 2 is subjected to the same treatment as the surface cleaning treatment, the surface is
A thick ultra-thin oxide insulating film 6 was formed by a thermal oxidation method.

【0053】前記熱酸化法としては、1〜760Tor
rの酸素雰囲気中で600〜1200℃の熱処理を行う
方法を用いた。この熱処理としては基板主面に紫外線を
照射することによって行ってもよい。
As the thermal oxidation method, 1 to 760 Torr
A method of performing heat treatment at 600 to 1200 ° C. in an oxygen atmosphere of r was used. This heat treatment may be performed by irradiating the main surface of the substrate with ultraviolet rays.

【0054】また、前記雰囲気ガスとして酸素に代えて
オゾン又はNO2雰囲気を用いてもよく、この場合、雰
囲気ガス圧は1×10-6〜10Torr、熱処理温度は
300〜1000℃でよい。
The atmosphere gas may be an ozone or NO 2 atmosphere instead of oxygen. In this case, the atmosphere gas pressure may be 1 × 10 −6 to 10 Torr, and the heat treatment temperature may be 300 to 1000 ° C.

【0055】更に、熱酸化法として、酸素をプラズマ処
理してなる原子状酸素を流量1×1010〜1×1020
scm2、100〜1000℃の条件下で照射して行っ
てもよい。
Further, as a thermal oxidation method, atomic oxygen obtained by plasma treatment of oxygen is supplied at a flow rate of 1 × 10 10 to 1 × 10 20 /.
Irradiation may be performed under the conditions of scm 2 and 100 to 1000 ° C.

【0056】その後、図3(a)に示すように、前記極
薄酸化絶縁膜6上にスパッタリング法、蒸着法又はCV
D法などの気相成長法により20〜500nm厚の堆積
酸化絶縁膜7を形成する。
Thereafter, as shown in FIG. 3A, a sputtering method, a vapor deposition method or a CV
A deposited oxide insulating film 7 having a thickness of 20 to 500 nm is formed by a vapor deposition method such as the D method.

【0057】次に、図3(b)に示すように、チャネル
部5b、5c上、ドリフト部5a上、及びn型不純物注
入領域4a、4bの一部上を残すように極薄酸化絶縁膜
6及び堆積酸化絶縁膜7をエッチング除去してp型不純
物注入領域3a、3b及びn型不純物注入領域4a、4
bを露出させる。
Next, as shown in FIG. 3B, the ultra-thin oxide insulating film is left so as to leave the channel portions 5b and 5c, the drift portion 5a, and a part of the n-type impurity implanted regions 4a and 4b. 6 and the deposited oxide insulating film 7 are removed by etching to remove the p-type impurity implanted regions 3a and 3b and the n-type impurity implanted regions 4a and 4a.
Expose b.

【0058】続いて、図3(c)に示すように、前記エ
ッチングによりパターニングした極薄酸化絶縁膜6及び
堆積酸化絶縁膜7上及び前記露出したp型不純物注入領
域3a、3b及びn型不純物注入領域4a、4b上に2
00nm〜2μm厚みの多結晶Si膜18をCVD法又
はスパッタリング法により形成する。
Subsequently, as shown in FIG. 3C, the p-type impurity-implanted regions 3a, 3b and the n-type impurity are exposed on the ultra-thin oxide insulating film 6 and the deposited oxide insulating film 7 patterned by the etching. 2 on injection regions 4a and 4b
A polycrystalline Si film 18 having a thickness of 00 nm to 2 μm is formed by a CVD method or a sputtering method.

【0059】その後、図4(a)に示すように、前記堆
積酸化絶縁膜7上にのみ存在するように前記多結晶Si
膜18をパターニングしてゲート電極8を形成する。
Thereafter, as shown in FIG. 4A, the polycrystalline Si is formed so as to exist only on the deposited oxide insulating film 7.
The gate electrode 8 is formed by patterning the film 18.

【0060】次に、図4(b)に示すように、ゲート電
極8、露出したp型不純物注入領域3a、3b及びn型
不純物注入領域4a、4b及び露出した堆積酸化絶縁膜
7上にNi等からなる金属膜19を形成すると共に、n
型SiC基板1の裏面上にNi等からなるドレイン電極
10を形成する。
Next, as shown in FIG. 4B, Ni is deposited on the gate electrode 8, the exposed p-type impurity implanted regions 3a and 3b and the n-type impurity implanted regions 4a and 4b and the exposed deposited oxide insulating film 7. While forming a metal film 19 made of
A drain electrode 10 made of Ni or the like is formed on the back surface of the mold SiC substrate 1.

【0061】その後、図4(c)に示すように、前記堆
積酸化絶縁膜7上及びその周囲の金属膜19をエッチン
グ除去してソース電極9a、9bを形成するとともに、
このソース電極9a、9b及びドレイン電極10がオー
ミック接触してなるようにレーザアニールを施して完成
する。
Thereafter, as shown in FIG. 4C, the metal film 19 on and around the deposited oxide insulating film 7 is removed by etching to form source electrodes 9a and 9b.
Laser annealing is performed so that the source electrodes 9a and 9b and the drain electrode 10 are in ohmic contact with each other to complete the process.

【0062】本実施形態の製造方法では、薄酸化絶縁膜
6(化合物薄膜)は膜厚が小さくしているので、この薄
酸化絶縁膜6の形成工程において、チャネル部5b、5
c上のp型不純物注入領域3a、3b表面と薄酸化絶縁
膜6の間等の界面の乱れを小さくできる。
In the manufacturing method of this embodiment, since the thin oxide insulating film 6 (compound thin film) has a small thickness, the channel portions 5b, 5
Disturbance at the interface between the surfaces of the p-type impurity implanted regions 3a and 3b on c and the thin oxide insulating film 6 can be reduced.

【0063】更に、薄酸化絶縁膜6は膜厚は小さいの
で、SiCと前記雰囲気ガスを構成する酸素とが反応し
て生じる不所望なCOxは薄酸化絶縁膜6から外部へ容
易に放出されるので、p型不純物注入領域3a、3b表
面と薄酸化絶縁膜6の間等の界面近傍に不所望な析出物
の発生を抑制できると共に、薄酸化絶縁膜6へCOx
混入するのを低減できる。
Further, since the thin oxide insulating film 6 has a small thickness, undesired CO x generated by the reaction between SiC and oxygen constituting the atmospheric gas is easily released from the thin oxide insulating film 6 to the outside. Therefore, it is possible to suppress the generation of undesired precipitates near the interface such as between the surfaces of the p-type impurity implanted regions 3a and 3b and the thin oxide insulating film 6, and to prevent CO x from being mixed into the thin oxide insulating film 6. Can be reduced.

【0064】しかも、雰囲気ガスの酸素により表面の不
飽和結合(終端のSi)は終端されるので、不飽和結合
の存在が低減される。この結果、薄酸化絶縁膜6とこの
下地との間の界面、薄酸化絶縁膜6と堆積酸化絶縁膜7
との界面、及び薄酸化絶縁膜6上に形成される堆積酸化
絶縁膜7が良好なものとなる。
Further, since the unsaturated bond (terminated Si) on the surface is terminated by oxygen of the atmospheric gas, the existence of the unsaturated bond is reduced. As a result, the interface between the thin oxide insulating film 6 and the base, the thin oxide insulating film 6 and the deposited oxide insulating film 7
And the deposited oxide insulating film 7 formed on the thin oxide insulating film 6 is excellent.

【0065】そして、成長速度の遅い形成方法(熱酸化
法)で形成される薄酸化絶縁膜6の膜厚は小さく、成長
速度の大きい形成方法(気相成長法)で形成される堆積
酸化絶縁膜7の膜厚を大きくしているので、耐絶縁性特
性などの特性を得つつ良好なゲート絶縁膜の製造時間を
短くできる。
The thickness of the thin oxide insulating film 6 formed by the formation method with low growth rate (thermal oxidation method) is small, and the deposited oxide insulation film formed by the formation method with high growth rate (vapor phase growth method). Since the thickness of the film 7 is increased, it is possible to shorten the manufacturing time of a favorable gate insulating film while obtaining characteristics such as insulation resistance characteristics.

【0066】従って、動作特性が良好なMOS−FET
を製造時間短く得ることができる。
Therefore, a MOS-FET with good operating characteristics
Can be obtained in a short production time.

【0067】本発明の第2の実施形態に係るMOS−F
ETを図を用いて詳細に説明する。図5は本実施形態の
MOS−FETの概略模式構成図である。
The MOS-F according to the second embodiment of the present invention
The ET will be described in detail with reference to the drawings. FIG. 5 is a schematic configuration diagram of the MOS-FET of the present embodiment.

【0068】図5中、31はn型SiC基板、32はn
型SiC基板1上に形成されたn型SiCエピタキシャ
ル膜、33はn型SiCエピタキシャル膜32上に形成
されたp型SiCエピタキシャル膜、34はp型SiC
エピタキシャル膜33を貫通しn型SiCエピタキシャ
ル膜32に達するU字型ゲート電極用溝である。
In FIG. 5, 31 is an n-type SiC substrate, and 32 is an n-type SiC substrate.
N-type SiC epitaxial film formed on n-type SiC substrate 1, 33 is a p-type SiC epitaxial film formed on n-type SiC epitaxial film 32, 34 is p-type SiC
This is a U-shaped gate electrode groove that penetrates through the epitaxial film 33 and reaches the n-type SiC epitaxial film 32.

【0069】35a、35bはp型SiCエピタキシャ
ル膜33中に形成され、U字型ゲート電極用溝34に密
接して形成されたn型不純物注入領域である。
Numerals 35 a and 35 b are n-type impurity implanted regions formed in the p-type SiC epitaxial film 33 and formed in close contact with the U-shaped gate electrode trench 34.

【0070】36a、36bは、電極用溝34に密接し
たp型SiCエピタキシャル膜33内であってn型不純
物注入領域35a、35bとn型SiCエピタキシャル
膜32の間に形成されるチャネル部、37a、37bは
チャネル部36a、36bと基板31の間に形成される
ドリフト部である。
Reference numerals 36a and 36b denote channel portions formed in the p-type SiC epitaxial film 33 in close contact with the electrode grooves 34 and between the n-type impurity implanted regions 35a and 35b and the n-type SiC epitaxial film 32. And 37b are drift portions formed between the channel portions 36a and 36b and the substrate 31.

【0071】38はU字型ゲート電極用溝34上及びn
型不純物注入領域35a、35bの一部に跨って形成さ
れる酸化ケイ素(SiOx)からなる極薄酸化絶縁膜、
39は極薄酸化絶縁膜38上に形成された酸化ケイ素
(SiOx)からなる堆積酸化絶縁膜である。本発明で
はゲート絶縁膜として、極薄酸化絶縁膜38とこれに比
べて十分膜厚の大きい堆積酸化絶縁膜39の2層構造で
構成される。
Reference numeral 38 denotes a groove on the U-shaped gate electrode groove 34 and n
Ultra-thin oxide insulating film made of silicon oxide (SiO x ) formed over a part of the type impurity implantation regions 35a and 35b;
Reference numeral 39 denotes a deposited oxide insulating film made of silicon oxide (SiO x ) formed on the ultra-thin oxide insulating film 38. In the present invention, the gate insulating film has a two-layer structure of an ultra-thin oxide insulating film 38 and a deposited oxide insulating film 39 having a sufficiently large thickness as compared with this.

【0072】40は堆積酸化絶縁膜39上に形成された
多結晶Si膜からなるゲート電極、41aはゲート電極
40と離間してn型不純物注入領域35a上及びp型S
iCエピタキシャル膜33上の一部に跨って形成される
Ni等の金属膜からなるソース電極、41bはゲート電
極40と離間してn型不純物注入領域35上及びp型S
iCエピタキシャル膜33上の一部に跨って形成される
Ni等からなるソース電極、42はn型SiC基板31
の裏面に形成されたNi等からなるドレイン電極であ
る。
Reference numeral 40 denotes a gate electrode made of a polycrystalline Si film formed on the deposited oxide insulating film 39. Reference numeral 41a denotes an n-type impurity implanted region 35a separated from the gate electrode 40 and a p-type S
A source electrode 41b made of a metal film of Ni or the like formed over a part of the iC epitaxial film 33 is separated from the gate electrode 40 by a distance above the n-type impurity implantation region 35 and the p-type S
a source electrode 42 made of Ni or the like formed over a part of the iC epitaxial film 33;
Is a drain electrode formed of Ni or the like formed on the back surface of the substrate.

【0073】斯る素子の製造方法を図6を用いて以下に
説明する。
A method for manufacturing such an element will be described below with reference to FIG.

【0074】まず、図6(a)に示すように、第1の実
施形態と同様の表面清浄化処理したn型SiC基板(N
dドープ:Nd濃度1×1018〜1×1021cm-3)3
1を準備する。
First, as shown in FIG. 6 (a), an n-type SiC substrate (N
d-doping: Nd concentration 1 × 10 18 -1 × 10 21 cm −3 ) 3
Prepare 1

【0075】次に、n型SiC基板31の主面上にCV
D法により1〜50μm厚のn型SiCエピタキシャル
膜(Ndドープ:Nd濃度1×1015〜1×1017cm
-3)32を形成した後、n型SiCエピタキシャル膜3
2上にCVD法によりp型SiCエピタキシャル膜(N
dドープ:Nd濃度1×1015〜1×1018cm-3)3
3を形成する。
Next, a CV is placed on the main surface of the n-type SiC substrate 31.
An N-type SiC epitaxial film (Nd doped: Nd concentration: 1 × 10 15 to 1 × 10 17 cm) having a thickness of 1 to 50 μm by the D method
-3 ) After forming 32, n-type SiC epitaxial film 3
P-type SiC epitaxial film (N
d-doping: Nd concentration 1 × 10 15 to 1 × 10 18 cm −3 ) 3
Form 3

【0076】その後、p型SiCエピタキシャル層33
中にn型不純物注入領域35をイオン注入法により形成
し、この注入不純物をキャリアとして機能するように活
性化させるために、800〜1500℃、真空又は不活
性ガス雰囲気中でアニール処理する。ここで、注入不純
物はN又はP、注入温度は500〜1000℃、注入量
は1×1018〜1×1021cm-3である。
Thereafter, the p-type SiC epitaxial layer 33
An n-type impurity implantation region 35 is formed therein by ion implantation, and annealing is performed at 800 to 1500 ° C. in a vacuum or an inert gas atmosphere in order to activate the implanted impurity to function as a carrier. Here, the implantation impurity is N or P, the implantation temperature is 500 to 1000 ° C., and the implantation amount is 1 × 10 18 to 1 × 10 21 cm −3 .

【0077】次に、図6(b)に示すように、CF4
びO2、又はCF4及びH2のガスを用いた反応性イオン
エッチング法(RIE法)により、n型不純物注入領域
35及びこの直下のp型SiCエピタキシャル膜33を
貫通しn型SiCエピタキシャル膜32に達するU字型
ゲート電極用溝34を形成する。
Next, as shown in FIG. 6B, an n-type impurity implanted region 35 is formed by reactive ion etching (RIE) using CF 4 and O 2 , or CF 4 and H 2 gas. Then, a U-shaped gate electrode groove 34 that penetrates the p-type SiC epitaxial film 33 immediately below and reaches the n-type SiC epitaxial film 32 is formed.

【0078】続いて、図5に示すように、U字型ゲート
電極用溝34内壁、n型不純物注入領域35a、35a
及びp型SiCエピタキシャル層33表面を第1の実施
形態と同様の表面清浄化処理を行った後、0.5〜5n
m厚の極薄酸化絶縁膜38を第1実施形態と同様の熱酸
化法により形成し、続いて前記極薄酸化絶縁膜38上に
スパッタリング法、蒸着法又はCVD法などの気相成長
法により20〜500nm厚の堆積酸化絶縁膜39を形
成する。その後、U字型ゲート電極用溝34上及びn型
不純注入領域35a、35bの一部上を残すように極薄
酸化絶縁膜38及び堆積酸化絶縁膜39をエッチング除
去してn型不純物注入領域35a、35bの一部及びp
型SiCエピタキシャル膜33を露出させる。
Subsequently, as shown in FIG. 5, the inner wall of the U-shaped gate electrode groove 34, the n-type impurity implanted regions 35a, 35a
After performing the same surface cleaning treatment as that of the first embodiment on the surface of the p-type SiC epitaxial layer 33, 0.5 to 5 n
An ultrathin oxide insulating film 38 having a thickness of m is formed by the same thermal oxidation method as that of the first embodiment, and subsequently, a vapor deposition method such as a sputtering method, a vapor deposition method or a CVD method is formed on the ultrathin oxide insulating film 38 A deposited oxide insulating film 39 having a thickness of 20 to 500 nm is formed. Thereafter, the ultra-thin oxide insulating film 38 and the deposited oxide insulating film 39 are removed by etching so as to leave the U-shaped gate electrode groove 34 and a part of the n-type impurity implanted regions 35a and 35b. 35a, a part of 35b and p
The type SiC epitaxial film 33 is exposed.

【0079】続いて、前記エッチングによりパターニン
グした極薄酸化絶縁膜38及び堆積酸化絶縁膜39上に
200nm〜2μm厚みのCVD法又はスパッタリング
法により形成した多結晶Si膜からなるゲート電極4
0、露出したn型不純物注入領域35a、35b及びp
型SiCエピタキシャル層33上に蒸着法等により形成
されたNi等からなる金属膜41a、41bを形成する
と共に、n型SiC基板31の裏面上に蒸着法等により
Ni等からなるドレイン電極42を形成する。
Subsequently, a gate electrode 4 made of a polycrystalline Si film formed by a CVD method or a sputtering method with a thickness of 200 nm to 2 μm on the ultra-thin oxide insulating film 38 and the deposited oxide insulating film 39 patterned by the etching.
0, exposed n-type impurity implanted regions 35a, 35b and p
Forming metal films 41a and 41b made of Ni or the like formed on the SiC epitaxial layer 33 by vapor deposition or the like, and forming a drain electrode 42 of Ni or the like on the back surface of the n-type SiC substrate 31 by vapor deposition or the like I do.

【0080】本実施例も第1の実施形態と同様の効果が
得られる。
This embodiment also provides the same effects as those of the first embodiment.

【0081】上述の実施形態では、化合物膜(堆積酸化
絶縁膜)として酸化ケイ素膜を形成したが、AlN膜な
どを用いることも可能である。
In the above embodiment, a silicon oxide film is formed as a compound film (deposited oxide insulating film). However, an AlN film or the like may be used.

【0082】更に、上述の導電型を逆導電型とした構成
でもよい。
Further, a configuration may be adopted in which the above-described conductivity type is reversed conductivity type.

【0083】また、上述では、ゲート絶縁膜の例を示し
たが、本発明はパッシベーション膜などの他の場合にも
利用できる。
In the above description, an example of the gate insulating film has been described, but the present invention can be applied to other cases such as a passivation film.

【0084】更に、SiC以外の半導体に化合物薄膜を
形成した後、化合物膜を気相成長法で形成する場合にも
適用可能である。
Further, the present invention can be applied to a case where a compound film is formed by a vapor phase growth method after forming a compound thin film on a semiconductor other than SiC.

【0085】[0085]

【発明の効果】本発明は、半導体とその上に形成される
化合物膜の間の界面を良好な状態としつつ、良好な化合
物膜を短時間で形成する化合物膜の形成方法を提供でき
る。またこの方法を用いた素子特性の優れた製造時間が
短い半導体素子の製造方法を提供することができる。
According to the present invention, it is possible to provide a compound film forming method for forming a good compound film in a short time while keeping the interface between the semiconductor and the compound film formed thereon in a good state. Further, it is possible to provide a method for manufacturing a semiconductor device having excellent device characteristics and a short manufacturing time using this method.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態に係る半導体素子の概略
模式構成図である。
FIG. 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present invention.

【図2】上記第1実施形態に係る半導体素子の製造方法
を示す図である。
FIG. 2 is a view illustrating a method of manufacturing the semiconductor device according to the first embodiment.

【図3】上記第1実施形態に係る半導体素子の製造方法
を示す図である。
FIG. 3 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment.

【図4】上記第1実施形態に係る半導体素子の製造方法
を示す図である。
FIG. 4 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment.

【図5】本発明の第2実施形態に係る半導体素子の概略
模式構成図である。
FIG. 5 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present invention.

【図6】上記第2実施形態に係る半導体素子の製造方法
を示す図である。
FIG. 6 is a view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

【符号の説明】[Explanation of symbols]

1 n型SiC基板 2 n型SiCエピタキャル層 3a、3b p型不純物注入領域 4a、4b n型不純物注入領域 5b、5c チャネル部 6 極薄酸化絶縁膜(化合物薄膜) 7 堆積絶縁膜(化合物膜) 31 n型SiC基板 32 n型SiCエピタキャル層 33 p型SiCエピタキャル層 35a、35b n型不純物注入領域 36b、36c チャネル部 39 極薄酸化絶縁膜(化合物薄膜) 40 堆積絶縁膜(化合物膜) Reference Signs List 1 n-type SiC substrate 2 n-type SiC epitaxy layer 3 a, 3 b p-type impurity implantation region 4 a, 4 b n-type impurity implantation region 5 b, 5 c channel portion 6 ultra-thin oxide insulating film (compound thin film) 7 deposited insulating film (compound film) Reference Signs List 31 n-type SiC substrate 32 n-type SiC epitaxy layer 33 p-type SiC epitaxy layer 35 a, 35 b n-type impurity implantation region 36 b, 36 c channel portion 39 ultra-thin oxide insulating film (compound thin film) 40 deposited insulating film (compound film)

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体表面に該半導体が構成する構成元
素と化合してなる化合物を形成させるための雰囲気ガス
を晒し、前記半導体表面に化合物薄膜を形成する工程
と、前記化合物薄膜上に気相形成法により化合物膜を形
成する工程と、を備えることを特徴とする化合物膜の形
成方法。
A step of exposing an atmosphere gas for forming a compound formed by combining with a constituent element of the semiconductor to a semiconductor surface to form a compound thin film on the semiconductor surface; Forming a compound film by a forming method.
【請求項2】 半導体表面を該表面の不飽和結合を終端
するための雰囲気ガスに晒し、前記半導体表面に化合物
薄膜を形成する工程と、前記化合物薄膜上に気相形成法
により化合物膜を形成する工程と、を備えることを特徴
とする化合物膜の形成方法。
2. A step of exposing a semiconductor surface to an atmosphere gas for terminating unsaturated bonds on the surface to form a compound thin film on the semiconductor surface, and forming a compound film on the compound thin film by a vapor phase formation method. A method of forming a compound film.
【請求項3】 炭化ケイ素からなる半導体の表面を酸化
し、該炭化ケイ素の表面に酸化ケイ素からなる化合物薄
膜を形成する工程と、該酸化ケイ素からなる化合物薄膜
上に気相形成法により化合物膜を形成する工程と、を備
えることを特徴とする化合物膜の形成方法。
3. A step of oxidizing the surface of a semiconductor made of silicon carbide to form a compound thin film made of silicon oxide on the surface of the silicon carbide; Forming a compound film.
【請求項4】 前記化合物膜は、酸化ケイ素からなるこ
とを特徴とする請求項3記載の化合物膜の形成方法。
4. The method according to claim 3, wherein the compound film is made of silicon oxide.
【請求項5】 前記化合物薄膜の膜厚は、前記化合物膜
の膜厚に比べて小さいことを特徴とする請求項1〜4の
いずれかに記載の化合物膜の形成方法。
5. The method according to claim 1, wherein the thickness of the compound thin film is smaller than the thickness of the compound film.
【請求項6】 前記表面はステップ状形状を有すること
を特徴とする請求項1〜5のいずれかに記載の化合物膜
の形成方法。
6. The method according to claim 1, wherein the surface has a step-like shape.
【請求項7】 前記化合物薄膜と前記化合物膜のうち、
少なくとも該化合物膜は絶縁膜であることを特徴とする
1〜6のいずれかに記載の化合物膜の形成方法。
7. The compound thin film and the compound film,
7. The method for forming a compound film according to any one of 1 to 6, wherein at least the compound film is an insulating film.
【請求項8】 前記請求項1〜7のいずれかに記載の化
合物膜の形成方法を用いて半導体素子を形成する半導体
素子の製造方法であって、前記半導体の表面に前記化合
物薄膜を形成する工程と、該化合物薄膜上に気相形成法
により前記化合物膜を形成する工程と、を備えることを
特徴とする半導体素子の製造方法。
8. A method of manufacturing a semiconductor device using the method of forming a compound film according to claim 1, wherein the compound thin film is formed on a surface of the semiconductor. A method for manufacturing a semiconductor device, comprising: a step of forming the compound film on the compound thin film by a vapor phase formation method.
【請求項9】 前記半導体素子は電解効果型半導体素子
であって、チャネル上の前記半導体の表面にゲート絶縁
膜としての前記化合物薄膜を形成する工程と、該化合物
薄膜上に気相形成法によりゲート絶縁膜としての前記化
合物膜を形成する工程と、を備えることを特徴とする請
求項8記載の半導体素子の製造方法。
9. The semiconductor device according to claim 1, wherein the semiconductor device is a field-effect semiconductor device, wherein the compound thin film as a gate insulating film is formed on a surface of the semiconductor on a channel, and the compound thin film is formed on the compound thin film by a vapor phase forming method. 9. The method according to claim 8, further comprising: forming the compound film as a gate insulating film.
JP10099224A 1998-04-10 1998-04-10 Formation method for compound film and manufacture of semiconductor element Pending JPH11297712A (en)

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Publication Number Publication Date
JPH11297712A true JPH11297712A (en) 1999-10-29

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KR20140049070A (en) 2011-09-21 2014-04-24 미쓰비시덴키 가부시키가이샤 Silicon carbide semiconductor device and method for manufacturing same
US9362391B2 (en) 2011-09-21 2016-06-07 Mitsubishi Electric Corporation Silicon carbide semiconductor device and method of manufacturing the same
US20150235842A1 (en) * 2014-02-17 2015-08-20 Tokyo Electron Limited Transistor and method for manufacturing the same
JP2015153943A (en) * 2014-02-17 2015-08-24 東京エレクトロン株式会社 Transistor and manufacturing method of the same

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