JP2006066439A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2006066439A
JP2006066439A JP2004243853A JP2004243853A JP2006066439A JP 2006066439 A JP2006066439 A JP 2006066439A JP 2004243853 A JP2004243853 A JP 2004243853A JP 2004243853 A JP2004243853 A JP 2004243853A JP 2006066439 A JP2006066439 A JP 2006066439A
Authority
JP
Japan
Prior art keywords
region
source region
conductivity type
semiconductor layer
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004243853A
Other languages
Japanese (ja)
Inventor
Koichi Hashimoto
Makoto Kitahata
Osamu Kusumoto
Ryoko Miyanaga
Kunimasa Takahashi
Masao Uchida
Masaya Yamashita
正雄 内田
真 北畠
良子 宮永
賢哉 山下
修 楠本
浩一 橋本
邦方 高橋
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP2004243853A priority Critical patent/JP2006066439A/en
Publication of JP2006066439A publication Critical patent/JP2006066439A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high reliability semiconductor device by improving the insulating breakdown voltage in a gate insulating film. <P>SOLUTION: The device is provided with a gate electrode 53 forming a conductive channel in a semiconductor layer 42, a source electrode 51 and a drain electrode 55 which are electrically connected via the conductive channel, a gate insulating film 49 installed in between the semiconductor layer 42 and the gate electrode 53, a second conductive source region 47, which is formed inside a first conductive well region 45 and is electrically brought into contact with the source electrode 51, and a second conductive drift region 43. The semiconductor layer 42 has a second conductivity-type auxiliary source region 48 which is brought into contact with the source region 47; the source region 47 is not overlapped with the gate electrode 53, and a part of the auxiliary source region 48 is overlapped with the gate electrode 53; and the total dose of the auxiliary source region 48 is smaller than that of the source region 47. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

Wide band gap semiconductors are attracting attention as semiconductor materials for semiconductor devices (power devices) that have a high withstand voltage and allow a large current to flow. Among wide band gap semiconductors, silicon carbide (silicon carbide: SiC) has a particularly high breakdown electric field, and is expected to be applied to the next generation low-loss power devices and the like. Since a high-quality silicon dioxide (SiO 2 ) film can be formed on SiC by thermal oxidation, development of an insulated gate type SiC power device using such a SiO 2 film as a gate insulating film has been advanced.

When a SiO 2 film formed by thermal oxidation on SiC is used as a gate insulating film, the breakdown electric field of SiC is extremely large (2 to 3 MV / cm), but a high breakdown voltage as expected from the breakdown electric field strength. In order to realize this device, it is necessary to improve the insulating characteristics (insulation breakdown voltage) of the SiO 2 film.

On the other hand, conventionally, it is known that a SiO 2 film having a high withstand voltage can be formed on SiC by performing a thermal oxidation process on SiC at a high temperature of 1200 ° C. or higher and then further performing a heat treatment in an argon atmosphere. It has been. Since the SiO 2 film formed by this method has a breakdown electric field of, for example, 11 MV / cm or more, reliability equivalent to that of the SiO 2 film formed on the Si substrate by thermal oxidation can be realized.

However, the dielectric breakdown voltage of the SiO 2 film formed on the SiC by thermal oxidation is extremely dependent on the surface state and crystal state of the SiC. Therefore, depending on the surface state and crystal state of the SiC, the high dielectric breakdown as described above. There is a problem that an SiO 2 film having an electric field cannot be formed. In a general insulated gate MOSFET, a part of the gate insulating film is formed on a SiC region (source region) in which impurities are highly doped. Since the surface of the source region has relatively large irregularities and many crystal defects exist in the source region, it is extremely difficult to form a high breakdown voltage SiO 2 film on the surface.

  Hereinafter, the above problem will be described in more detail with reference to the drawings.

  First, the configuration of a general gate type MOSFET will be described by taking a vertical MOSFET as an example.

The MOSFET shown in FIG. 7 includes a silicon carbide epitaxial layer 32 formed on the main surface of SiC substrate 31, a gate electrode 38 and a source electrode 36 provided on silicon carbide epitaxial layer 32, and a back surface of SiC substrate 31. And a drain electrode 34 provided thereon. Silicon carbide epitaxial layer 32 has n type drift region 33, p type well region 35, n ++ type source region 37, and p ++ type contact region 40. The source region 37 is connected to the source electrode 36. The well region 35 is electrically connected to the source electrode 36 through a p ++ type contact region 40. Gate insulating film 39 is formed on a region other than the region where source electrode 36 is formed on the surface of silicon carbide epitaxial layer 32. A gate electrode 38 is provided on the silicon carbide epitaxial layer 32 via a gate oxide film 39.

  In the MOSFET having the configuration as shown in FIG. 7, when a voltage is applied to the gate electrode 38, an inversion channel is formed on the surface of the well region 35 below the gate electrode 38, so that the drain electrode 34 passes through the inversion channel. Thus, a current can flow to the source electrode 36.

  In order to form the inversion channel, the surface of the well region 35 (the portion where the inversion channel is formed) located between the source region 37 and the drift region 33 needs to be covered with the gate electrode 38. The gate electrode 38 is disposed so as to overlap not only the surface of the well region 35 but also a part of the source region 37.

  In the MOSFET as shown in FIG. 7, dielectric breakdown is likely to occur in a portion of the gate insulating film 39 located between the source region 37 and the gate electrode 38, which causes a reduction in the reliability of the MOSFET.

As described above, since the surface of the high-concentration source region 37 doped with an impurity having a dose of 10 15 cm −2 or more has irregularities, the crystal plane orientation of the surface is not constant. Since the thermal oxidation rate depends on the plane orientation, when the gate insulating film 39 is formed by thermally oxidizing the surface of the source region 37, the thickness of the gate insulating film (thermal oxide film) 39 is caused by the crystal plane distribution. As a result, the withstand voltage is lowered in the thin portion of the gate insulating film 39. Further, since there are many defects (dislocations) due to impurities in the source region 37 doped with impurities at a high concentration, a thermal oxide film having excellent insulating characteristics can be formed on the source region 37. Have difficulty. Such a problem is a physical property problem of SiC, and it is difficult to overcome this and improve the reliability of the gate insulating film.

  On the other hand, the level difference (step) between the surface of the source region 37 and the surface of the well region 35 causes a problem that the withstand voltage of the gate insulating film 39 formed thereon is lowered.

In order to dope impurities into the epitaxially grown silicon carbide epitaxial layer 32, it is essential to implant impurity ions into the silicon carbide epitaxial layer 32. Further, it is necessary to activate the impurities by performing an annealing process after ion implantation. At this time, for example, if annealing is performed on a region where n-type impurity ions are implanted at a dose of 1 × 10 15 cm −2 or more, a large strain is generated in the crystal. As a result, FIG. As shown, a step of 1 nm or more is formed at the boundary portion 39b between the surface of the source region 37 and the surface of the well region 35 into which impurity ions are implanted at a high concentration.

  When gate insulating film 39 is formed by thermally oxidizing the surface of silicon carbide epitaxial layer 32 having such a step, since the oxidation rate depends on the plane orientation, boundary portion 39b of the surface of silicon carbide epitaxial layer 32 is formed. As a result, the gate insulating film 39 becomes thinner on the step of the boundary portion 39b.

  Therefore, as shown in the drawing, a portion (necking) where the gate insulating film 39 is particularly thin is formed on the boundary portion 39b. In FIG. 7B, “necking” is emphasized for easy understanding, but the actual constriction is gentler than this figure. As shown in FIG. 7B, since the thermal oxidation rate of the source region 37 having a high impurity concentration is higher than that of the well region 35 having a relatively low impurity concentration (accelerated oxidation), the gate insulating film 39 is thick on the source region 37 and thin on the well region 35. This accelerated oxidation can be one of the factors that cause the above-mentioned constriction.

  In the region where the impurity concentration is high, the oxide film is thicker than the well region and it is difficult to break down the dielectric, so there is an advantage. However, in reality, the breakdown voltage is significantly deteriorated due to the influence of crystal defects and the like.

  Further, when a voltage is applied to the gate electrode 38, the electric field concentrates on the constricted portion of the gate insulating film 39, and dielectric breakdown is likely to occur. Furthermore, there is a problem that an inversion channel is hardly formed at the interface between the constricted portion of the gate insulating film 39 and the well region 35.

For example, Patent Documents 1 and 2 disclose an epitaxial layer (n.sup. - type epi layer or channel layer) between a gate insulating film and a source region in order to suppress the surface state of the source region 37 and a decrease in withstand voltage due to the constriction. ) Is disclosed. According to this configuration, n - because a gate insulating film on the type epi layer and the channel layer, can reduce the influence of surface state of the source region has on the breakdown voltage of the gate insulating film, the crystal defects in the source region The resulting decrease in dielectric strength cannot be sufficiently suppressed.
JP 2002-270838 A JP 2002-270837 A

  As described above, in a conventional semiconductor device, it is difficult to form a gate insulating film having excellent insulating characteristics due to a surface state or a crystal state in a source region containing impurities at a high concentration.

  The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a highly reliable semiconductor device by improving the withstand voltage in a gate insulating film.

  The semiconductor device of the present invention includes a substrate, a semiconductor layer provided on the main surface of the substrate, a gate electrode that is electrically insulated from the semiconductor layer and can form a conductive channel in the semiconductor layer. A semiconductor device comprising a source electrode and a drain electrode that are electrically connected via the conductive channel, and a gate insulating film provided between the semiconductor layer and the gate electrode, wherein the semiconductor layer A first conductivity type well region formed in the well region, a second conductivity type source region formed in the well region and in electrical contact with the source electrode, and the well region of the semiconductor layer. A second conductivity type drift region composed of a portion not formed, wherein the semiconductor layer is formed inside the well region and is in contact with the source region. A source region, the source region is not overlapped by the gate electrode, a part of the auxiliary source region is overlapped by the gate electrode, and the total dose of the auxiliary source region is: Less than the total dose of the source region.

  In a preferred embodiment, the semiconductor layer is made of silicon carbide.

  In a preferred embodiment, a size in a gate length direction of a portion of the auxiliary source region overlapped by the gate electrode is smaller than the gate length.

  It is preferable that a step at a boundary portion between a region located on the auxiliary source region and a region located on the well region in the surface of the semiconductor layer is 1 nm or less.

  The auxiliary source region may be thinner than the source region.

  The auxiliary source region may be thicker than the source region.

  The source region may contain nitrogen as an impurity.

  The auxiliary source region may include phosphorus as an impurity.

  In a preferred embodiment, the substrate is a second conductivity type semiconductor substrate, the semiconductor layer is formed on a main surface of the semiconductor substrate, and the drain electrode is formed on a back surface of the semiconductor substrate.

  The method of manufacturing a semiconductor device according to the present invention includes (A) a step of forming a second conductivity type semiconductor layer on a substrate, and (B) ion implantation of a first conductivity type impurity in a selected region of the semiconductor layer. Forming a first conductivity type ion implantation region, and (C) implanting a second conductivity type impurity into a selected region of the first conductivity type ion implantation region to thereby form a second conductivity type ion implantation region. And a step of forming a high concentration ion implantation region in which the second conductivity type impurity is ion implanted at a concentration higher than that of the first conductivity type ion implantation region, and (D) an activation annealing process on the semiconductor layer. To form an auxiliary source region and a source region from the second conductivity type ion implantation region and the high concentration ion implantation region, respectively, and among the first conductivity type ion implantation region, the auxiliary source region and A step of forming a well region from the region where the source region was not formed, (E) a step of forming a gate insulating film on the semiconductor layer, and (F) forming a conductive channel in the semiconductor layer. Forming a gate electrode on the gate insulating film so as to cover the region and a part of the auxiliary source region.

  In certain preferred embodiments. The step (B) includes a step of forming a well region formation mask on the semiconductor layer, and the step (C) is a film having a thickness defining a gate length on the well region formation mask. A step of performing ion implantation of a second conductivity type impurity into the first conductivity type ion implantation region through the film, and a source region having an opening defining the source region on the semiconductor layer Forming a formation mask; and performing ion implantation of a second conductivity type impurity in the first conductivity type ion implantation region using the source region formation mask.

  According to the semiconductor device of the present invention, the surface unevenness is reduced and the gate insulating film is formed on the highly crystalline semiconductor layer, so that the insulating characteristics of the gate insulating film can be improved. Since the dielectric breakdown electric field of the gate insulating film can be improved while suppressing loss (on-resistance) during energization, a semiconductor device with higher reliability than the conventional one can be provided.

  In addition, according to the semiconductor device manufacturing method of the present invention, a highly reliable semiconductor device can be manufactured without complicating the manufacturing process. Furthermore, by using self-alignment to form an auxiliary source region with a smaller layer dose than the source region, the gate length can be kept smaller than before, and a highly reliable and high performance semiconductor device can be manufactured. Particularly advantageous.

  The semiconductor device according to the present invention has an auxiliary source region that is electrically connected to the source region and has a smaller total impurity dose than the source region, and a part of the auxiliary source region is overlapped by the gate electrode. It is characterized by being.

  Hereinafter, a vertical MOSFET which is a preferred embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. 1A and 1B are schematic cross-sectional views showing a part of a vertical MISFET. The semiconductor device of the present invention may be a DIMOSFET (Double Implanted Metal-Oxide-Semiconductor Field-Effect Transistor), and is not limited to a vertical MOSFET.

A semiconductor device 100 shown in FIG. 1A includes a semiconductor layer 42 formed on a main surface of a semiconductor substrate 41, a source electrode 51 and a gate electrode 53 provided on the semiconductor layer 42, and a semiconductor substrate 41. And a drain electrode 55 provided on the back surface. The semiconductor substrate 41 is, for example, a low resistance n + -type silicon carbide substrate, and the semiconductor layer 42 is, for example, a silicon carbide epitaxial layer.

The semiconductor layer 42 includes a well region 45 having a conductivity type (here, p-type) different from the conductivity type of the semiconductor substrate 41 and a drift region 43 composed of a portion of the semiconductor layer 42 where the well region 45 is not formed. And have. Although a single well region 45 is shown in FIG. 1, the semiconductor device 100 typically has a plurality of well regions 45. Drift region 43 is, for example, an n type silicon carbide layer containing n type impurities at a concentration lower than the n type impurity concentration of semiconductor substrate 41.

Inside the well region 45, a source region 47, an auxiliary source region 48, and a contact region 50 are formed. The source region 47 is connected to the source electrode 51. In order to form a good ohmic contact with the source electrode 51, the source region 47 is doped with impurities of the same conductivity type (for example, n-type) as that of the semiconductor substrate 41 at a high concentration of, for example, 1 × 10 18 cm −3 or more. Including. On the other hand, the auxiliary source region 48 is disposed so as to be in contact with the source region 47 and contains impurities of the same conductivity type (for example, n-type) as the conductivity type of the source region 47 with a dose amount smaller than that of the source region 47. Yes. Therefore, the auxiliary source region 48 has a flatter surface than the source region 47, and crystal defects in the auxiliary source region 48 are less than crystal defects in the source region 47. The contact region 50 has the same conductivity type as the well region 45 (here, p ++ type), and is provided to electrically connect the source electrode 51 and the well region 45.

  The gate electrode 53 is provided on the semiconductor layer 42 via the gate insulating film 49 and covers the well region 45 located between the drift region 43 and the auxiliary source region 48. The gate electrode 53 is arranged so as to overlap a part of the auxiliary source region 48 but not the source region 51.

  The semiconductor device 100 has the following advantages compared to the conventional semiconductor device as shown in FIG.

  As described above, in the conventional semiconductor device, since the gate insulating film is formed on the source region containing impurities at a high concentration, the gate insulating film is caused by the level difference between the source region surface and the well region surface. As shown in FIG. 7B, constriction is generated and dielectric breakdown is likely to occur. Further, it is difficult to obtain a gate insulating film having excellent insulating characteristics due to the influence of surface irregularities and crystal defects in the source region. Further, when the gate insulating film is a thermal oxide film, the thickness of the thermal oxide film is likely to change due to the accelerated oxidation at the boundary portion 39b shown in FIG. 7B, which may contribute to the formation of a constriction.

  On the other hand, in the semiconductor device 100, the gate insulating film 49 is formed on the auxiliary source region 48 having a smaller dose than the source region 47. Since the difference in impurity concentration between the auxiliary source region 48 and the well region 45 is reduced, the gate insulating film 49 is less likely to be constricted as shown in FIG. Further, by forming the auxiliary source region 48, the change in the thickness of the thermal oxide film due to the accelerated oxidation as described above becomes more gradual than before, so that the formation of the constriction can be suppressed. Furthermore, since the surface distortion of the auxiliary source region 48 and crystal distortion due to impurities are reduced as compared with the source region 47, the insulating characteristics of the gate insulating film 49 are deteriorated due to the surface state and crystal state of the underlying semiconductor layer. Can be suppressed. Therefore, the withstand voltage of the gate insulating film 49 can be improved while keeping the contact resistance with the source electrode 51 small, and the long-term reliability of the semiconductor device 100 can be improved.

In the present invention, the auxiliary source region 48 contains impurities at a sufficiently low concentration so as to ensure the withstand voltage of the gate insulating film 49, while having a sufficiently low sheet resistance so as not to become a parasitic resistance of the semiconductor device 100. It is desirable. Therefore, the total dose of the auxiliary source region 48 is preferably smaller than the total dose of the source region 47, for example, 1 × 10 15 cm −2 or less. More preferably, it is 1 × 10 14 cm −2 or less. In addition, when the doping concentration is 1 × 10 17 cm −3 or less, it is possible to more effectively suppress the deterioration of the insulating characteristics of the gate insulating film 49. On the other hand, in order to keep the resistance of the auxiliary source region 48 low, for example, when phosphorus is used as the impurity of the auxiliary source region 48, the phosphorus dose in the auxiliary source region 48 is preferably 1 × 10 12 cm −2 or more. .

  The semiconductor device 100 can be manufactured without complicating the manufacturing process. As will be described later, when the auxiliary source region 48 is formed by utilizing self-alignment, it is advantageous because the gate length can be made smaller than before. Although depending on the dose and thickness of the auxiliary source region 48, the gate length can be reduced to, for example, 1 μm or less, more preferably 0.5 μm or less.

  In order to prevent the constriction generated in the gate insulating film 49 more reliably, the surface of the auxiliary source region 48 (interface between the auxiliary source region 48 and the gate insulating film 49) and the surface of the well region 45 (well region 45 and gate). The step difference from the interface with the insulating film 49 is preferably 1 nm or less. Such a step can be realized by controlling the dose amount of the well region 45 and the auxiliary source region 48, the formation method (impurity ion implantation method, etc.) and the formation conditions of the auxiliary source region 48, and the like.

  The kind of impurity doped in the auxiliary source region 48 (in this embodiment, n-type impurity) is not particularly limited. However, when the semiconductor layer 42 is a silicon carbide layer, it is preferable to use phosphorus as the impurity. This is because the diffusion coefficient of phosphorus with respect to silicon carbide is relatively high, so that the sheet resistance of the auxiliary source region 48 can be further reduced even when the concentration of phosphorus is low. In contrast, the impurity doped in the source region 47 (n-type impurity) preferably has a low diffusion coefficient with respect to silicon carbide so as not to evaporate by heat treatment when forming a contact with the source electrode 51. For example, nitrogen can be used as such an impurity. As a result, a source region 47 having a low contact resistance is obtained.

  Although the thickness of the auxiliary source region 48 is not particularly limited, when the auxiliary source region 48 is thinner than the source region 47 as shown in FIG. 1A, the auxiliary source region 48 is easily formed by self-alignment as will be described later. There is an advantage that you can. The thickness of the auxiliary source region 48 is preferably 1 μm or less, more preferably 500 nm or less. For example, in order to form an electrode with low contact resistance in the source region 47, the thickness of the source region 47 may be set to 300 nm or more, and the thickness of the auxiliary source region 48 may be set to about 200 nm, for example.

  Alternatively, the auxiliary source region 48 may be thicker than the source region 47. A configuration of the semiconductor device 100 in this case is shown in FIG. This configuration has an advantage that the sheet resistance in the auxiliary source region 48 can be reduced.

  Even when the dose in the auxiliary source region 48 is suppressed, the auxiliary source region 48 contains a larger amount of impurities (n-type and p-type impurities) than the well region 45. The insulating property of the portion 49 s formed on the region 48 is slightly lower than the insulating property of the portion 49 w formed on the well region 5. Therefore, it is preferable to keep the area of the auxiliary source region 8 overlapped by the gate electrode 13 small. As a result, the area of the portion 49s where the potential difference occurs, that is, the area sandwiched between the auxiliary source region 48 and the gate electrode 53 can be reduced, so that the reliability of the gate insulating film 49 can be further increased.

  Specifically, the size b in the gate length direction in the portion of the auxiliary source region 48 that is overlapped by the gate electrode 53 is preferably smaller, and is preferably smaller than the gate length a, for example. However, considering that the development of a silicon carbide MOSFET having a short gate structure with a gate length a of 1 μm or less is in progress, the size b has only to be kept small enough to allow processing, and the gate length a It may be the above.

The gate insulating film 49 may be a thermal oxide film (SiO 2 film) formed by thermal oxidation of the semiconductor layer 42 such as a silicon carbide layer, or a deposition deposited on the semiconductor layer 42 by a CVD method or the like. It may be a membrane. In any case, it is possible to prevent the deterioration of the characteristics of the gate insulating film 49 due to the surface state or crystal state of the semiconductor layer 42 serving as a base.

(Embodiment 1)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. This embodiment is a vertical MOSFET using silicon carbide.

  The MOSFET of the present embodiment includes a plurality of unit cells, and FIG. 2A is a plan view showing the configuration of four of the unit cells. FIG. 2B is a top view of the semiconductor layer (silicon carbide epitaxial layer) in the MOSFET shown in FIG. FIG. 2C is a cross-sectional view taken along the line I-I ′ in FIGS.

  The MOSFET of this embodiment includes a silicon carbide epitaxial layer (thickness: 10 μm, for example) 2 formed on the main surface of a low-resistance silicon carbide substrate 1 and a source electrode 11 provided on the silicon carbide epitaxial layer 2. And gate electrode 13 and drain electrode 15 provided on the back surface of silicon carbide substrate 1.

The silicon carbide substrate 1 is an off-angle substrate made of, for example, 4H—SiC and having a main surface inclined by 8 ° (off-angle) from the (0001) plane toward the <11-20> direction. Silicon carbide substrate 1 has n-type conductivity, and the n-type impurity doping concentration is about 1 × 10 18 cm −3 to 5 × 10 19 cm −3 .

Silicon carbide epitaxial layer 2 has a plurality of p-type well regions (thickness: 800 nm, for example) 5 and drift region 3. Drift region 3 is formed by epitaxially growing n-type SiC. The doping concentration of the n-type impurity in the drift region 3 is lower than the doping concentration of the silicon carbide substrate 1, and is set to about 1 × 10 15 cm −3 to 1 × 10 16 cm −3 in the case of a MOSFET with a withstand voltage of 600 V, for example. The The plurality of well regions 5 are provided in a selected region near the surface of the silicon carbide epitaxial layer 2, and the p-type impurity doping concentration thereof is set to, for example, about 1 × 10 17 cm −3 .

Inside the well region 5, an n-type source region (thickness 7d: 200 nm, for example) 7 containing nitrogen as an n-type impurity and a p ++ type contact region for connecting the well region 5 and the source electrode 11 are provided. 10 is formed. The nitrogen concentration in the source region 7 is, for example, 1 × 10 18 cm −3 or more. Around the source region 7, an n-type auxiliary source region (thickness 8d: 150 nm, for example) 8 containing phosphorus as an n-type impurity is formed. The phosphorus concentration in the auxiliary source region 8 is, for example, 1 × 10 17 cm −3 . The size 8s of the auxiliary source region 8 in the gate length direction is, for example, 5 μm or less. The distance (gate length) a between the outer edge of the auxiliary source region 8 and the end of the well region 5 is, for example, 1 μm.

The source electrode 11 is provided so as to be in contact with at least a part of the source region 7 and at least a part of the p ++ contact region 10, and an ohmic contact is formed between the source electrode 11 and these regions 7, 10. Has been.

Gate insulating film 9 is formed on silicon carbide epitaxial layer 2. The gate insulating film 9 in the present embodiment is a thermal oxide film (SiO 2 film) formed by thermally oxidizing the silicon carbide epitaxial layer 2. The thickness of the gate insulating film 9 varies depending on the gate voltage when the MOSFET device is driven, but is several 80 nm, for example. Gate insulating film 9 is formed over a region other than the region where source electrode 11 is formed on the surface of silicon carbide epitaxial layer 2. However, the gate insulating film 9 is preferably not in contact with the source electrode 11. When in contact with the source electrode 11, Ni or the like diffuses from the source electrode (for example, Ni electrode) 11 to the gate insulating film 9, and there is a possibility that the withstand voltage of the gate insulating film 9 is lowered.

  The gate electrode 13 is provided on the gate insulating film 9 so as to overlap a part of the auxiliary source region 8 and the well region 5 between the auxiliary source region 8 and the drift region 3. The size b in the gate direction of the portion of the auxiliary source region 8 that is overlapped by the gate electrode 13 is, for example, 0.5 μm.

  The MOSFET of this embodiment operates as follows.

  When a gate voltage is applied to the gate electrode 13, an inversion layer (inversion type channel layer) is formed on the surface of the well region 5 between the auxiliary source region 8 and the drift region 3. When the inversion layer is formed, a current (drain current) flows from the drain electrode 15 to the source region 7 through the drift region 3, the inversion layer, and the auxiliary source region 8.

  Hereinafter, the manufacturing method of the MOSFET of this embodiment will be described with reference to FIGS. 3 to 5 are schematic cross-sectional views for explaining the method of manufacturing the MOSFET of this embodiment. The size of each component in these figures does not correspond to the actual size. For example, in FIG. 3, the implantation mask 21 is shown thinner than the ion implantation region 23, but actually is formed thicker than the ion implantation region 23.

  First, as shown in FIG. 3A, a first implantation mask 21 is formed on the surface of silicon carbide epitaxial layer 2 formed by CVD on the main surface of silicon carbide substrate 1. First implantation mask 21 has an opening that defines a region of silicon carbide epitaxial layer 2 where a first conductivity type (here, p-type) impurity is implanted. The first implantation mask 21 can be formed by depositing, for example, a TEOS (tetra-ethoxysilane) film on the silicon carbide epitaxial layer 2 and then patterning the TEOS film by photolithography and etching processes. When patterning the TEOS film, if only dry etching is performed, a step larger than 1 nm may be formed on the surface of the silicon carbide epitaxial layer 2. Therefore, it is desirable to apply an etching method in which wet etching is combined with dry etching. Specifically, most of the region of the TEOS film that is not covered by a resist mask (not shown) is removed by dry etching, and then the portion that remains thin on the silicon carbide epitaxial layer 2 is removed by wet etching. When such a method is used, damage to the surface of the silicon carbide epitaxial layer 2 can be suppressed by forming the first implantation mask 21. The thickness of the first implantation mask 21 is determined by its material and implantation conditions, but is preferably set sufficiently larger than the implantation range, for example, 2 μm.

  Next, as shown in FIG. 3B, p-type impurity ions (for example, Al ions) 22 are implanted into the silicon carbide epitaxial layer 2 from above the first implantation mask 21. Impurity ion implantation may be performed in multiple stages. Thereby, first conductivity type ion implantation region 23 in which p type impurity ions are implanted is formed in silicon carbide epitaxial layer 2. In addition, a region of the silicon carbide epitaxial layer 2 remaining without being implanted with impurity ions is an n-type drift region 3.

  Subsequently, as shown in FIG. 3C, a second implantation mask 24 made of, for example, a TEOS film is formed on the first implantation mask 21 and the silicon carbide epitaxial layer 2. The thickness of the second implantation mask 24 is, for example, 1 μm, and the gate length of the MOSFET is defined by this thickness. For example, the thickness of the second implantation mask 24 can be made smaller than 1 μm (for example, 0.5 μm), whereby a MOSFET having a gate length smaller than 1 μm can be easily manufactured.

  The second implantation mask 24 is formed by forming a TEOS film over the surfaces of the silicon carbide epitaxial layer 2 and the first implantation mask 21, and then etching back to form the sidewalls of the first implantation mask 21 in the TEOS film. You may form by removing parts other than the part which covers.

Thereafter, as shown in FIG. 3D, second conductivity type (here, n-type) impurity ions 25 are implanted into silicon carbide epitaxial layer 2 from above second implantation mask 24. As the impurity ions 25, it is preferable to use an impurity that easily diffuses into silicon carbide such as phosphorus. At this time, it is necessary to adjust the acceleration voltage in the ion implantation so that impurity ions are not implanted under the first implantation mask 21 and the second implantation mask 24 covering the side wall of the silicon carbide epitaxial layer 2. is there. Such an acceleration voltage depends on the type of the impurity ions 25, but can be set to about 200 keV, for example. Impurity ions 25 need only be implanted relatively shallowly (for example, a depth of 200 nm or less from the surface of silicon carbide epitaxial layer 2). Therefore, the low acceleration voltage as described above may be used. The dose is selected so as to be smaller than the dose in ion implantation for forming a source region described later, and is, for example, 10 13 cm −2 or more and 10 15 cm −2 or less. Thereby, a part of the first conductivity type ion implantation region 23 becomes the second conductivity type ion implantation region 26.

  After the impurity ions 25 are implanted, the first and second implantation masks 21 and 24 are removed. Subsequently, as shown in FIG. 3E, a third implantation mask (thickness: 1.5 μm, for example) 27 made of, for example, a TEOS film is formed on the silicon carbide epitaxial layer 2. The third implantation mask has an opening that defines a region to be a source region in silicon carbide epitaxial layer 2. The third implantation mask 27 is formed by a method similar to that of the first implantation mask 21, for example.

Next, as shown in FIG. 4A, impurity ions 28 are implanted into a region of the silicon carbide epitaxial layer 2 exposed by the third implantation mask 27, and a high-concentration ion implantation region 7 ′ serving as a source region is formed. Form. In the present embodiment, nitrogen is used as the impurity ions 28. At this time, the high-concentration ion implantation region 7 ′ is formed inside the first conductivity type ion implantation region 23 and has a sufficient thickness (for example, 200 nm or more) so as to form a good contact with the source electrode. Next, injection conditions such as acceleration voltage are set. The dose amount is selected to be larger than the dose amount in the ion implantation when forming the second conductivity type ion implantation region 26 described above, and is, for example, 10 14 cm −2 or more and 10 16 cm −2 or less. After the ion implantation, the third implantation mask 27 is removed.

Thereafter, as shown in FIG. 4B, a fourth implantation mask 30 having an opening defining a p ++ type contact region is formed on silicon carbide epitaxial layer 2, and the fourth implantation mask is formed. A first conductivity type (here, p-type) impurity (for example, Al) is ion-implanted from above 30. The dose amount is, for example, 10 15 cm −2 . As a result, a high-concentration ion-implanted region 10 ′ serving as a p ++ type contact region is formed. After the ion implantation, the fourth implantation mask 30 is removed.

  Next, as shown in FIG. 4C, a cap layer 29 is formed on the surface of the silicon carbide epitaxial layer 2. Cap layer 29 is formed to prevent surface roughness of silicon carbide epitaxial layer 2 in an activation annealing step to be described later, and is preferably a carbon film. The carbon film can be deposited using a sputtering method or the like.

  Subsequently, as shown in FIG. 4D, activation annealing for recovering the crystal is performed on the silicon carbide epitaxial layer 2 into which the impurity ions have been implanted, and then the cap layer 29 is removed.

The activation annealing can be performed while the cap layer 29 is formed and is kept in the chamber of the heating furnace. For example, the silicon carbide epitaxial layer 2 is heated at a temperature of 1750 ° C. for about 30 minutes while supplying argon gas to the chamber at a flow rate of 0.5 liter / min. At this time, the pressure in the chamber is constant at 91 kPa. Thereby, the source region 7 and the p ++ type contact region 10 are formed from the high concentration ion implantation regions 7 ′ and 10 ′, respectively. Further, the auxiliary source region 8 is formed from the region of the second conductivity type ion implantation region 26 that is left without the impurity ions 28 being implanted, and the source region 7 and the auxiliary source region 8 of the first conductivity type ion implantation region 23 are formed. The region where no is formed becomes the well region 5.

  Although the removal method of cap layer 29 is not particularly limited, if cap layer 29 is a carbon film, it is applied to the surface of silicon carbide epitaxial layer 2 by performing thermal oxidation of cap layer 29 while it is installed in the chamber of the heating furnace. The cap layer 29 can be easily removed while suppressing damage. Specifically, the temperature in the chamber of the heating furnace is kept constant at 800 ° C., and heat treatment is performed for 30 minutes while supplying oxygen at a flow rate of 5 liters / minute. Note that the cap layer 29 may be removed using a method other than thermal oxidation such as plasma treatment or ozone treatment.

  FIG. 6 is an enlarged view of the surface state of silicon carbide epitaxial layer 2 shown in FIG. In the present embodiment, ion implantation and activation annealing using a cap are performed in the steps as described above, so that the step L at the boundary between the surface of the source region 7 and the surface of the auxiliary source region 8 is suppressed to 1 nm or less. It has been. Although the surface of the source region 7 is slightly uneven, the surfaces of the auxiliary source region 8 and the well region 5 are substantially flat.

  Subsequently, as shown in FIG. 5A, a gate insulating film 9 is formed on a predetermined region of the silicon carbide epitaxial layer 2. In this embodiment, the silicon carbide epitaxial layer 2 from which the cap layer 29 has been removed is thermally oxidized at a temperature of 1200 ° C. in a dry oxygen atmosphere to form a thermal oxide film, and the same temperature (1200 At 30 ° C.) for 30 minutes. By this heat treatment, the gate insulating film 9 having a thickness of, for example, 80 nm can be formed. After thermal oxidation, a part of the gate insulating film 9 is etched to form an opening for forming a source electrode.

  Thereafter, as shown in FIG. 5B, a gate electrode 13, a source electrode 11, and a drain electrode 15 are formed. The source electrode 11 and the drain electrode 15 can be formed as follows. First, an Ni film is deposited so as to be in contact with the source region 7 and the contact region 10 using an electron beam (EB) vapor deposition apparatus. A Ni film is also deposited on the back surface of silicon carbide substrate 1. Subsequently, when these Ni films were heated at a temperature of 1000 ° C. using a heating furnace, they were ohmic-bonded to the source electrode 11 that was ohmic-bonded to the source region 7 and the contact region 10 and to the back surface of the silicon carbide substrate 1. A drain electrode 15 is obtained. On the other hand, the gate electrode 13 can be formed on the gate insulating film 9 using aluminum, polysilicon or the like. The gate electrode 13 is disposed so as to cover the region of the well region 5 where the conductive channel is formed. The gate electrode 13 also covers a part of the auxiliary source region 8, and the size b in the gate length direction of the portion where the gate electrode 13 and the auxiliary source region 8 overlap is, for example, 0.5 μm. In this way, a silicon carbide MOSFET is obtained.

The silicon carbide MOSFET with a withstand voltage of 600 V formed by the above method has a low on-resistance of, for example, 5 mΩcm 2 or less because the resistance of the source region 7 and the auxiliary source region 8 is kept small, and the gate Since the deterioration of the characteristics of the insulating film 9 is suppressed, it has reliability that can withstand continuous use for 10 years.

  In the above method, the auxiliary source region 8 is formed by self-alignment, but ion implantation is performed using a mask having an opening that defines a region to be the auxiliary source region 8 separately from the first mask 21. The auxiliary source region 8 may be formed. However, in this case, since mask alignment is required, it is difficult to suppress the gate length a to less than 1 μm, for example, in consideration of mask alignment accuracy. On the other hand, if self-alignment is used as in the above method, mask alignment is not necessary, and the gate length a can be shortened compared to the prior art.

  A method for manufacturing a short gate transistor by forming a source region by self-alignment has been proposed (for example, Japanese Patent Application Laid-Open No. 2002-299620), but when forming a source region, impurity ions are implanted at a high acceleration voltage. Therefore, it is necessary to make the first mask used when implanting the first conductivity type impurity ions thick (for example, 1 μm or more). Therefore, the mask film cannot be reliably deposited on the side wall of the mask unless the mask film to be deposited on the mask is thickened to some extent (for example, more than 1 μm). Since the thickness of the mask film defines the gate length, it is difficult to reduce the gate length to less than 1 μm.

  On the other hand, when the auxiliary source region 8 is formed by self-alignment as in the present embodiment, the acceleration voltage when the source region is formed by using the first implantation mask 21 and the second implantation mask 24 is used. Since ion implantation may be performed with a low acceleration voltage, the first implantation mask 21 can be made thinner than the first mask used in the above-described conventional method. Therefore, there is an advantage that the thickness of the mask film (second implantation mask) 24 provided on the first implantation mask 21 can be further reduced. The thickness of the second mask 24 is 1 μm in the above method, but may be 0.8 μm or less, for example, 0.5 μm.

  The manufacturing method of the semiconductor device of the present invention is not limited to the above method.

When forming the second conductivity type ion implantation region 26 to be the auxiliary source region, multistage implantation may be performed to control the concentration profile of the impurity ions 25 in the second conductivity type ion implantation region 26. For example, the concentration of the impurity ions 25 in the second conductivity type ion implantation region 26 where the depth from the surface is 10 nm or less is suppressed to less than 1 × 10 17 cm −3 , and the depth in the second conductivity type ion implantation region 26 is reduced. When the concentration of the impurity ions 25 in the portion larger than 10 nm and smaller than or equal to 20 nm is set to 1 × 10 18 cm −3 or more, the auxiliary source region 8 with the surface impurity concentration suppressed can be obtained by the subsequent activation annealing. When the auxiliary source region 8 having such a profile is formed, since the sheet resistance of the auxiliary source region 8 is low, the reliability of the gate insulating film 9 formed on the auxiliary source region 8 is increased without increasing the on-resistance. It can be secured.

In the above method, the gate insulating film 9 is formed by thermal oxidation. However, instead of the thermal oxidation, the gate insulating film 9 made of, for example, SiO 2 may be formed by a known thin film deposition method. Even in this case, since the surface irregularities and steps of the silicon carbide epitaxial layer 2 are reduced, it is possible to form a SiO 2 film having high insulation characteristics with reduced variation in thickness.

Further, in the above method, the activation annealing is performed after all the ion implantation steps for the silicon carbide epitaxial layer 2 are performed, but the activation annealing is performed after performing a part of the ion implantation step, and then the remaining ion implantation is performed. You may perform activation annealing again after performing a process. For example, the activation annealing step shown in FIGS. 4C and 4D can be performed before the ion implantation step into the region to be the p ++ type contact region shown in FIG. 4B. In this case, after this activation annealing, ion implantation may be performed on a region to be a p ++ type contact region, and then activation annealing may be performed again.

  The semiconductor device of the present invention is not limited to a MOSFET, and can be applied to various insulated gate transistors. For example, it can be suitably used for a planar type or trench type insulated gate transistor.

  Furthermore, the present invention can be applied to a semiconductor device using a semiconductor other than silicon carbide, and can also be applied to a MISFET using another wide gap semiconductor such as GaN. When applied to a MISFET using GaN, a substrate other than a semiconductor substrate such as a sapphire substrate may be used as a substrate for forming a semiconductor layer (GaN layer).

  The present invention can be applied to various insulated gate semiconductor devices including vertical MOSFETs and lateral MOSFETs. In particular, it is advantageous for use in a semiconductor device using a wide gap semiconductor such as SiC. Such a semiconductor device can be used for a low-loss power device that can be used for various types of electric power / electric equipment such as home appliances, automobiles, electric power transportation / conversion devices, and industrial equipment.

(A) And (b) is a cross-sectional schematic diagram of a part of a vertical MOSFET which is a preferred embodiment of a semiconductor device according to the present invention. (A) is a top view of MOSFET of embodiment by this invention, (b) is a top view of the silicon carbide epitaxial layer in embodiment, (c) is II 'sectional drawing of (a). is there. (A)-(e) is process sectional drawing for demonstrating the manufacturing method of MOSFET of embodiment by this invention. (A)-(d) is process sectional drawing for demonstrating the manufacturing method of MOSFET of embodiment by this invention. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of MOSFET of embodiment by this invention. FIG. 5 is a cross sectional view for illustrating the surface state of the silicon carbide epitaxial layer shown in FIG. (A) is a cross-sectional schematic diagram showing the configuration of a conventional vertical MOSFET, and (b) is an enlarged cross-sectional view of a gate insulating film in the conventional vertical MOSFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon carbide epitaxial layer 41 Substrate 42 Semiconductor layer 43, 3 Drift region 45, 5 Well region 47, 7 Source region 48, 8 Auxiliary source region 49, 9 Gate insulating film 50, 10 Contact region 51, 11 Source electrode 53, 13 Gate electrode 55, 15 Drain electrode 100 Semiconductor device

Claims (11)

  1. A substrate,
    A semiconductor layer provided on a main surface of the substrate;
    A gate electrode electrically insulated from the semiconductor layer and capable of forming a conductive channel in the semiconductor layer;
    A semiconductor device comprising: a source electrode and a drain electrode that are electrically connected via the conductive channel; and a gate insulating film provided between the semiconductor layer and the gate electrode,
    A first conductivity type well region formed in the semiconductor layer;
    A source region of a second conductivity type formed in the well region and in electrical contact with the source electrode;
    A second conductivity type drift region composed of a portion of the semiconductor layer where the well region is not formed,
    The semiconductor layer further includes an auxiliary source region of a second conductivity type formed in the well region and in contact with the source region,
    The source region is not overlapped by the gate electrode, and a part of the auxiliary source region is overlapped by the gate electrode;
    A semiconductor device in which a total dose of the auxiliary source region is smaller than a total dose of the source region.
  2.   The semiconductor device according to claim 1, wherein the semiconductor layer is made of silicon carbide.
  3.   3. The semiconductor device according to claim 1, wherein a size in a gate length direction of a portion of the auxiliary source region overlapped by the gate electrode is smaller than a gate length.
  4.   4. The semiconductor device according to claim 1, wherein a step in a boundary portion between a region located on the auxiliary source region and a region located on the well region in the surface of the semiconductor layer is 1 nm or less.
  5.   The semiconductor device according to claim 1, wherein the auxiliary source region is thinner than the source region.
  6.   The semiconductor device according to claim 1, wherein the auxiliary source region is thicker than the source region.
  7.   The semiconductor device according to claim 1, wherein the source region contains nitrogen as an impurity.
  8.   The semiconductor device according to claim 1, wherein the auxiliary source region contains phosphorus as an impurity.
  9.   9. The semiconductor device according to claim 1, wherein the substrate is a second conductivity type semiconductor substrate, the semiconductor layer is formed on a main surface of the semiconductor substrate, and the drain electrode is formed on a back surface of the semiconductor substrate. The semiconductor device described.
  10. (A) forming a second conductivity type semiconductor layer on the substrate;
    (B) forming a first conductivity type ion implantation region by ion implantation of a first conductivity type impurity into a selected region of the semiconductor layer;
    (C) A second conductivity type impurity is ion-implanted into a selected region of the first conductivity type ion implantation region, so that the second conductivity type ion implantation region and the first conductivity type ion implantation region have a higher concentration. And (D) performing an activation annealing process on the semiconductor layer to form the second conductivity type ion implantation region and the high concentration, respectively. Forming the auxiliary source region and the source region from the ion implantation region, and forming a well region from a region of the first conductivity type ion implantation region where the auxiliary source region and the source region are not formed;
    (E) forming a gate insulating film on the semiconductor layer;
    (F) a step of forming a gate electrode on the gate insulating film so as to cover a region of the semiconductor layer where a conductive channel is formed and a part of the auxiliary source region. Production method.
  11. The step (B) includes a step of forming a well region forming mask on the semiconductor layer,
    The step (C)
    Forming a film having a thickness defining a gate length on the well region forming mask;
    Performing ion implantation of a second conductivity type impurity into the first conductivity type ion implantation region through the film;
    Forming a source region forming mask having an opening defining the source region on the semiconductor layer;
    11. The method of manufacturing a semiconductor device according to claim 10, further comprising: performing ion implantation of a second conductivity type impurity in the first conductivity type ion implantation region using the source region formation mask.
JP2004243853A 2004-08-24 2004-08-24 Semiconductor device and its manufacturing method Pending JP2006066439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004243853A JP2006066439A (en) 2004-08-24 2004-08-24 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004243853A JP2006066439A (en) 2004-08-24 2004-08-24 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2006066439A true JP2006066439A (en) 2006-03-09

Family

ID=36112683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004243853A Pending JP2006066439A (en) 2004-08-24 2004-08-24 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2006066439A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066438A (en) * 2004-08-24 2006-03-09 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007281005A (en) * 2006-04-03 2007-10-25 Denso Corp Method of manufacturing silicon carbide semiconductor device
JP2009064970A (en) * 2007-09-06 2009-03-26 Central Res Inst Of Electric Power Ind Semiconductor device
JP2009231545A (en) * 2008-03-24 2009-10-08 Fuji Electric Device Technology Co Ltd Silicon carbide mos semiconductor device
JP2012142585A (en) * 2012-02-16 2012-07-26 Central Research Institute Of Electric Power Industry Method of manufacturing semiconductor device
JP2012191056A (en) * 2011-03-11 2012-10-04 Mitsubishi Electric Corp Silicon carbide semiconductor device and method of manufacturing the same
JP2012235001A (en) * 2011-05-06 2012-11-29 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
US20130045593A1 (en) * 2011-08-19 2013-02-21 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device
EP2657959A1 (en) * 2010-12-22 2013-10-30 Sumitomo Electric Industries, Ltd. Process for manufacture of silicon carbide semiconductor device
JP2013236040A (en) * 2012-05-11 2013-11-21 Hitachi Ltd Silicon carbide semiconductor device and manufacturing method therefor
CN103443927A (en) * 2011-03-18 2013-12-11 瑞萨电子株式会社 Semiconductor device and method for manufacturing same
JP2015073123A (en) * 2009-09-07 2015-04-16 ローム株式会社 Semiconductor device
JP2015115570A (en) * 2013-12-16 2015-06-22 住友電気工業株式会社 Silicon carbide semiconductor device and method of manufacturing the same
JP2015156506A (en) * 2015-04-10 2015-08-27 三菱電機株式会社 Silicon carbide semiconductor device and manufacturing method of the same
JP2016115831A (en) * 2014-12-16 2016-06-23 富士電機株式会社 Vertical mosfet and method of manufacturing vertical mosfet
WO2016132417A1 (en) * 2015-02-18 2016-08-25 富士電機株式会社 Semiconductor integrated circuit
JP2017055011A (en) * 2015-09-11 2017-03-16 株式会社東芝 Semiconductor device
JP2017076812A (en) * 2016-12-15 2017-04-20 株式会社東芝 Semiconductor device
WO2017147296A1 (en) * 2016-02-24 2017-08-31 General Electric Company Silicon carbide device and method of making thereof
WO2017169777A1 (en) * 2016-03-29 2017-10-05 三菱電機株式会社 Electric power converter

Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066438A (en) * 2004-08-24 2006-03-09 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007281005A (en) * 2006-04-03 2007-10-25 Denso Corp Method of manufacturing silicon carbide semiconductor device
JP2009064970A (en) * 2007-09-06 2009-03-26 Central Res Inst Of Electric Power Ind Semiconductor device
JP2009231545A (en) * 2008-03-24 2009-10-08 Fuji Electric Device Technology Co Ltd Silicon carbide mos semiconductor device
US9041006B2 (en) 2008-03-24 2015-05-26 Fuji Electric Co., Ltd. Silicon carbide MOS semiconductor device
JP2015073123A (en) * 2009-09-07 2015-04-16 ローム株式会社 Semiconductor device
US10319853B2 (en) 2009-09-07 2019-06-11 Rohm Co., Ltd. Semiconductor device
US9893180B2 (en) 2009-09-07 2018-02-13 Rohm Co., Ltd. Semiconductor device
US9496393B2 (en) 2009-09-07 2016-11-15 Rohm Co., Ltd. Semiconductor device
US10546954B2 (en) 2009-09-07 2020-01-28 Rohm Co., Ltd. Semiconductor device
EP2657959A1 (en) * 2010-12-22 2013-10-30 Sumitomo Electric Industries, Ltd. Process for manufacture of silicon carbide semiconductor device
EP2657959A4 (en) * 2010-12-22 2014-06-25 Sumitomo Electric Industries Process for manufacture of silicon carbide semiconductor device
US9082683B2 (en) 2010-12-22 2015-07-14 Sumitomo Electric Industries, Ltd. Method of manufacturing silicon carbide semiconductor device
JP2012191056A (en) * 2011-03-11 2012-10-04 Mitsubishi Electric Corp Silicon carbide semiconductor device and method of manufacturing the same
US9257551B2 (en) 2011-03-18 2016-02-09 Renesas Electronics Corporation Semiconductor device and method for manufacturing same
KR101898751B1 (en) * 2011-03-18 2018-09-13 르네사스 일렉트로닉스 가부시키가이샤 Semiconductor device and method for manufacturing same
CN103443927A (en) * 2011-03-18 2013-12-11 瑞萨电子株式会社 Semiconductor device and method for manufacturing same
US8963199B2 (en) 2011-03-18 2015-02-24 Renesas Electronics Corporation Semiconductor device and method for manufacturing same
JP5702460B2 (en) * 2011-03-18 2015-04-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR20140012123A (en) * 2011-03-18 2014-01-29 르네사스 일렉트로닉스 가부시키가이샤 Semiconductor device and method for manufacturing same
JP2012235001A (en) * 2011-05-06 2012-11-29 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
WO2013027502A1 (en) * 2011-08-19 2013-02-28 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor device
JP2013042050A (en) * 2011-08-19 2013-02-28 Sumitomo Electric Ind Ltd Manufacturing method of silicon carbide semiconductor device
CN103688342A (en) * 2011-08-19 2014-03-26 住友电气工业株式会社 Method for manufacturing silicon carbide semiconductor device
US20130045593A1 (en) * 2011-08-19 2013-02-21 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device
JP2012142585A (en) * 2012-02-16 2012-07-26 Central Research Institute Of Electric Power Industry Method of manufacturing semiconductor device
JP2013236040A (en) * 2012-05-11 2013-11-21 Hitachi Ltd Silicon carbide semiconductor device and manufacturing method therefor
JP2015115570A (en) * 2013-12-16 2015-06-22 住友電気工業株式会社 Silicon carbide semiconductor device and method of manufacturing the same
JP2016115831A (en) * 2014-12-16 2016-06-23 富士電機株式会社 Vertical mosfet and method of manufacturing vertical mosfet
US9893065B2 (en) 2015-02-18 2018-02-13 Fuji Electric Co., Ltd. Semiconductor integrated circuit
JPWO2016132417A1 (en) * 2015-02-18 2017-06-15 富士電機株式会社 Semiconductor integrated circuit
WO2016132417A1 (en) * 2015-02-18 2016-08-25 富士電機株式会社 Semiconductor integrated circuit
JP2015156506A (en) * 2015-04-10 2015-08-27 三菱電機株式会社 Silicon carbide semiconductor device and manufacturing method of the same
JP2017055011A (en) * 2015-09-11 2017-03-16 株式会社東芝 Semiconductor device
WO2017147296A1 (en) * 2016-02-24 2017-08-31 General Electric Company Silicon carbide device and method of making thereof
US9899512B2 (en) 2016-02-24 2018-02-20 General Electric Company Silicon carbide device and method of making thereof
WO2017169777A1 (en) * 2016-03-29 2017-10-05 三菱電機株式会社 Electric power converter
JP2017076812A (en) * 2016-12-15 2017-04-20 株式会社東芝 Semiconductor device

Similar Documents

Publication Publication Date Title
JP6135709B2 (en) Manufacturing method of trench gate type semiconductor device
US9490338B2 (en) Silicon carbide semiconductor apparatus and method of manufacturing same
US8658503B2 (en) Semiconductor device and method of fabricating the same
US6188104B1 (en) Trench DMOS device having an amorphous silicon and polysilicon gate
JP3959856B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US7846828B2 (en) Semiconductor device and method for fabricating the same
US6759684B2 (en) SiC semiconductor device
US7728336B2 (en) Silicon carbide semiconductor device and method for producing the same
JP4903439B2 (en) Field effect transistor
US9318600B2 (en) Silicon carbide semiconductor device and method for manufacturing same
JP4604241B2 (en) Silicon carbide MOS field effect transistor and manufacturing method thereof
US7557007B2 (en) Method for manufacturing semiconductor device
US7968941B2 (en) Semiconductor device
US9117836B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US8901568B2 (en) Silicon carbide insulating gate type semiconductor device and fabrication method thereof
JP4539684B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP3784393B2 (en) Semiconductor device and manufacturing method thereof
KR101613930B1 (en) Silicon carbide semiconductor device and method for manufacturing the same
US8754422B2 (en) Semiconductor device and process for production thereof
US8841191B2 (en) Semiconductor device and method of manufacturing same
US9818845B2 (en) MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
US8564060B2 (en) Semiconductor device with large blocking voltage and manufacturing method thereof
US6620669B2 (en) Manufacture of trench-gate semiconductor devices
US8748977B2 (en) Semiconductor device and method for producing same
JP4490094B2 (en) Method of manufacturing trench metal oxide semiconductor field effect transistor device