JP2002222950A - Method of manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce on-resistance much more in an insulating gate-type field effect transistor constituted of silicon carbide. SOLUTION: A connection film 7a constituted of a thermal oxidized film is formed on a surface channel layer 5 constituted of silicon carbide and an LTO film 7b is deposited on the connection film 7a. Thus, a gate insulating film 7 is formed. Then, the interface of the LTO film 7b and a surface channel layer 5 is made to be satisfactory by forming the connection film 7a before the LTO film 7b is formed. Then, channel mobility can be improved and on- resistance can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device in which an oxide film is formed on a silicon carbide surface,
In particular, it is suitable for use in an insulated gate field effect transistor, especially for a vertical power MOSFET used for high power.

[0002]

2. Description of the Related Art Hitherto, in an insulated gate field effect transistor using silicon carbide, it has been demanded to reduce on-resistance. For example, JP-A-10-308510 proposes an insulated gate type field effect transistor for the purpose of reducing the on-resistance.

In the insulated gate field effect transistor disclosed in this conventional publication, a channel is formed without inverting the conductivity type of a channel forming layer by using a semiconductor layer formed under a gate oxide film as a storage layer. Operate in induced storage mode and invert mode MOSFET
The channel mobility is set higher than the channel mobility.

[0004]

SUMMARY OF THE INVENTION However, MOS
There is a demand for further reduction in the on-resistance of the FET.

In view of the above, it is an object of the present invention to further reduce on-resistance in an insulated gate field effect transistor made of silicon carbide.

[0006]

Means for Solving the Problems In order to reduce the on-resistance, the present inventors conducted the following study on the channel mobility which is one factor for determining the on-resistance.

Conventionally, it is known that the interface state between silicon carbide and a gate insulating film affects the channel mobility. By improving the interface state, it is possible to improve the channel mobility. Is being done.

[0008] For example, the present inventors previously found that the channel mobility was reduced when SiO ₂ was thermally oxidized.
It is presumed that this is caused by a high interface state density due to residual carbon generated at the / SiC interface, and it is found that high-temperature thermal oxidation at 1200 ° C. or higher is effective.
No. proposes.

Also, D.A1ok et al. (Abstracts of ICSCRM: Int
ernational Conference of SiliconCarbide and Relate
d Materials '99, p322) is LPCVD
(Low Pressure Chemical Vapor Deposition) to improve the interface state by using an LTO film. Here, a high-quality interface cannot be obtained only by depositing the LTO film.
Oxidation in a wet environment at a temperature of ° C allows SiC and LTO
The interface with the belly has been improved.

[0010] However, although there is no residual carbon in the LTO film, it is oxidized at 1100 ° C to improve the quality.
Residual carbon is generated at the interface between the TO film and SiC, and sufficient reforming is not performed.

According to the first aspect of the present invention, there is provided a silicon carbide semiconductor device in which a substrate provided with a semiconductor layer (5) made of silicon carbide is prepared and an insulating film (7b) is deposited on the semiconductor layer. Is characterized by having a bonding layer forming step of forming a bonding layer (7a) for bonding the semiconductor layer and the deposited film on the semiconductor layer before depositing the insulating film. .

As described above, by providing the bonding layer before depositing the insulating film, the bonding between the insulating film and the semiconductor layer made of silicon carbide can be improved, and the bonding region can be formed in advance with good controllability. Becomes Thereby, in the insulated gate type field effect transistor made of silicon carbide, for example, as described in claim 17 or 20, it is possible to further reduce the on-resistance. However, in such a method, it is desirable to improve the state of the interface between silicon carbide and the insulating film, such as an insulating film below a field plate according to claim 18 or an interlayer insulating film as described in claim 29. Is also applicable.

According to a second aspect of the present invention, a thermal oxide film formed on a semiconductor layer by thermal oxidation is used as a bonding layer. If the coupling film is a thermal oxide film, the deposited insulating film and the thermal oxide film can be efficiently coupled.

When such a thermal oxide film is used as a bonding film, the thermal oxidation is performed at a temperature of 1200 ° C. or more as described in claim 3.
The insulating film and the silicon carbide are formed by performing the heat treatment at 400 ° C. or less, performing the thermal oxidation in an oxygen atmosphere as described in claim 4, or reducing the thermal oxide film thickness to 6 nm or less as described in claim 5. Generation of residual carbon at the interface with the semiconductor layer can be suppressed, and these interfaces can be further improved. Note that the temperature of the thermal oxidation may be 1200 ° C. or higher, but the upper limit is set to 1400 ° C. in order to suppress cristobaric formation due to phase transition of silicon oxide.

Further, in the invention according to claim 6,
It is characterized in that an epitaxial layer formed by epitaxially growing silicon on a semiconductor layer is used as a bonding layer. By using the epitaxial layer as described above, a carbon-free bonding layer can be obtained.
In this case, by forming the epitaxial layer with a 3 × 3 structure, the bonding between the bonding layer and the semiconductor layer made of silicon carbide can be reliably performed.

[0016] Further, as shown in claims 8 to 11,
When Si is used for the epitaxial layer, a carbon-free silicon oxide layer can be formed by thermally oxidizing the epitaxial layer, which is suitable as a bonding layer. Further, if the thermal oxidation temperature is set to 1000 ° C. or lower, only Si is oxidized and S
Since the thermal oxidation of iC hardly proceeds, a higher quality bonding layer is obtained.

On the other hand, a silicon oxide film can be used as the deposited film. This silicon oxide film is formed by, for example, a CVD method or an LPCVD method as described in claim 12, but according to the LPCVD method, a higher quality silicon oxide film can be obtained. Note that the silicon oxide film can be of high quality, whether it is an LTO film deposited at a low temperature or an HTO film deposited at a high temperature.

Further, as set forth in claim 15, a silicon nitride film can be used as the deposited film. This silicon nitride film is also formed by, for example, a CVD method or an LPCVD method. By using this silicon nitride film and thermally oxidizing both surfaces of the silicon nitride film, a so-called ONO film structure can be obtained.

According to a twenty-fourth aspect of the present invention, the polymorph of the semiconductor layer made of silicon carbide is 4H. As described above, it is particularly effective to apply the inventions described in the above claims to polymorphs of silicon carbide in which the influence of high interface states formed by residual carbon is greatest.

According to a twenty-fifth aspect of the present invention, the main surface of the semiconductor layer made of silicon carbide is a (0001) Si plane or a (11-20) plane. Thus, if the main surface of the semiconductor layer is the (0001) Si surface,
The present invention works effectively because the unevenness at the interface between the insulating film and the semiconductor layer can be extremely reduced, and the (0001) Si surface has the greatest effect on the interface state of the residual carbon. In addition, if the (11-20) plane is used, the quality of the interface between the insulating film and the semiconductor layer can be significantly improved.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0022]

(First Embodiment) FIG. 1 shows an n-channel type planar MOSFET (hereinafter referred to as a vertical power MOSFET) formed by applying one embodiment of the present invention.
) Is shown. Hereinafter, the configuration of the vertical power MOSFET will be described with reference to FIG.

N ⁺ type substrate 1 made of silicon carbide has upper surface as main surface 1a and lower surface opposite to main surface 1a as back surface 1a.
b. On the main surface 1a of the n ⁺ type substrate 1,
An n ⁻ -type epitaxial layer (hereinafter, referred to as an n ⁻ -type epi layer) 2 made of silicon carbide having a lower dopant concentration than the substrate 1 is stacked.

At this time, the main surface 1a of the n ⁺ type substrate 1 and the upper surface of the n ⁻ type epi layer 2 are (0001) Si plane or (11-20) a plane. This is (0001)
By using a Si surface, a low surface state density can be obtained,
This is because a crystal having a low surface state density and completely having no screw dislocation can be obtained by using the (11-20) a plane.

A p-type base region 3 having a predetermined depth is formed in a predetermined region in the surface layer portion of n ⁻ -type epi layer 2. This p-type base region 3 is formed using B as a dopant, and has a concentration of about 1 × 10 ¹⁷ cm ⁻³ or more. An n ⁺ -type source region 4 shallower than the base region 3 is formed in a predetermined region of the surface layer of the p-type base region 3.

Further, n ⁻ type source region 4 and n ⁻ type epi layer 2 are connected to each other so that n ⁻
The mold SiC layer 5 extends. This n ^- type SiC layer 5
Is formed by epitaxial growth, and the crystal of the epitaxial film is 4H, 6H, or 3C. The n ⁻ -type SiC layer 5 functions as a channel forming layer during operation of the device. Hereinafter, n ^- type SiC
Layer 5 is called a surface channel layer.

The surface channel layer 5 is formed by using N (nitrogen) as a dopant. The dopant concentration is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and , N ⁻ -type epi layer 2 and p-type base region 3 are lower than the dopant concentration. Thereby, low on-resistance is achieved.

The n ⁻ -type epi layer 2 located between the p-type base regions 3 constitutes a so-called J-FET section 6.

On the upper surface of the surface channel layer 5 and the upper surface of the n ⁺ type source region 4, a low temperature oxide (LTO) is formed via a coupling film 7 a made of a thermal oxide film formed by thermal oxidation.
e) The film 7b is formed. The gate insulating film 7 is constituted by the coupling film 7a and the LTO film 7b.

Further, a polysilicon gate electrode 8 is formed on the LTO film 7b. The polysilicon gate electrode 8 is covered with an insulating film 9. L as the insulating film 9
A TO film is used. A source electrode 10 is formed on insulating film 9, and source electrode 10 is in contact with n ⁺ -type source region 4 and p-type base region 3. Also, n ⁺
On the back surface 1b of the mold substrate 1, a drain electrode layer 11 is formed.

The planar type MOSF thus constructed
Since the ET operates in the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer, the channel mobility can be increased as compared with the MOSFET in the inversion mode in which the conductivity type is inverted, and the on-resistance is reduced. Can be done.

The vertical power M in the present embodiment is
In the OSFET, residual carbon at the interface between the surface channel layer 5 and the gate insulating film 7 is reduced by a method described later. Therefore, the channel mobility can be further increased, and the on-resistance can be further reduced.

Hereinafter, the vertical power MO according to this embodiment will be described.
A method for manufacturing the SFET will be described. 2 to 4,
The manufacturing process of the vertical power MOSFET according to the present embodiment is shown, and a description will be given based on these drawings.

[Step shown in FIG. 2A] First, the n-type 4
H, 6H, 3C or 15R-SiC substrate, ie n ⁺
A mold substrate 1 is prepared. Here, the n ⁺ -type substrate 1 has a thickness of 400 μm, and the main surface 1a has (0001) Si
Plane or (112-0) a plane. An n ⁻ -type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface 1 a of the substrate 1. In this example, the n ⁻ type epi layer 2 is
A crystal similar to that of n-type 4H, 6H, 3C or 15 was obtained.
It becomes an R-SiC layer.

[Step shown in FIG. 2B] n^-Type epi layer 2
LTO film 20 is arranged in a predetermined region above
As B⁺ (Or aluminum)
Thus, a p-type base region 3 is formed. Ion injection at this time
The input conditions are a temperature of 700 ° C. and a dose of 1 × 10¹⁶c
m ^-2And

[Step shown in FIG. 2C] After the LTO film 20 is removed, a surface channel layer 5 is formed on the surface of the n ⁻ -type epi layer 2 and the surface of the p-type base region 3 by chemical vapor deposition. (C
VD method).

At this time, the vertical power MOSFET
Is made to be a normally-off type, the thickness (film thickness) of the surface channel layer 5 is determined based on the following formula. To make a vertical power MOSFET a normally-off type,
When no gate voltage is applied, the depletion layer extending to the surface channel layer 5 needs to have a sufficient barrier height so as to prevent electric conduction. This condition is expressed by the following equation.

[0038]

(Equation 1)

Where, Tepi is the height of the depletion layer spreading over the surface channel layer 5, φms is the work function difference (electron energy difference) between metal and semiconductor, Qs is space charge in the gate insulating film 7, and Qfc is gate insulating. The fixed charge at the interface between the film (SiO ₂ ) 7 and the surface channel layer 5, Qi is the mobile ion in the oxide film, Qss is the surface charge at the interface between the gate insulating film 7 and the surface channel layer 5, and Cox is the LTO film. 7 capacity.

The first term on the right-hand side shown in Equation 1 is the amount of extension of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the surface channel layer 5 and the p-type base region 3, that is, from the p-type base region 3 to the surface channel layer 5 The second term is the amount of extension of the depletion layer due to the charge of the gate insulating film 7 and φms, that is, the amount of extension of the depletion layer extending from the gate insulating film 7 to the surface channel layer 5. Therefore, if the sum of the extension amount of the depletion layer extending from the p-type base region 3 and the extension amount of the depletion layer extending from the gate insulating film 7 is equal to or greater than the thickness of the surface channel layer 5, the vertical power MOSFE
Since T can be a normally-off type, the surface channel layer 5 is formed under ion implantation conditions that satisfy this condition.

Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type.

[Step shown in FIG. 3A] An LTO film 21 is disposed in a predetermined region on the surface channel layer 5, and an n-type impurity such as N (nitrogen) is ion-implanted using the LTO film 21 as a mask.
^{A +} type source region 4 is formed. The ion implantation conditions at this time are 700 ° C. and the dose is 1 × 10 ¹⁵ cm ⁻² .

[Step shown in FIG. 3 (b)] After the LTO film 21 is removed, an LTO film 22 is arranged in a predetermined region on the surface channel layer 5 by using a photoresist method, and this is used as a mask by RIE. The surface channel layer 5 on the p-type base region 3 is partially etched away.

[Steps shown in FIG. 3 (c)]
B ⁺ ions are implanted using the film 22 as a mask to form the deep base layer 30. Thereby, the p-type base region 3
Is partly thicker. The deep base layer 30 is formed in a portion that does not overlap the n ⁺ -type source region 4, and a portion of the p-type base region 3 where the deep base layer 30 is formed is thickened. Is formed with a higher impurity concentration than a thin portion where no is formed.

[Step shown in FIG. 4A] After removing the LTO film 22 used as a mask, the SiC substrate is washed. Then, the surface of the SiC substrate is set to 5 m in an oxygen atmosphere of 1200 ° C. or more and 1400 ° C. or less, preferably 1250 ° C.
In-oxidation is performed to form a coupling layer 7 a made of an oxide film on the surface channel layer 5. At this time, for example, H
₂ O or a mixed gas of H ₂ O and O ₂ is used. Note that the formation temperature of the bonding layer 7a may be at least 1200 ° C. or higher, but the upper limit is set to 1400 ° C. in order to suppress cristobalation due to crystallization of silicon oxide.

Thereafter, an LTO film 7b as a gate insulating film is deposited on the coupling layer 7a by using a CVD device or an LPCVD device. For example, a high-quality LTO film 7b is formed by using SiH ₄ and O ₂ as supply gases at a deposition temperature of 450 ° C. and a deposition rate of 6 nm / min. By using the LTO film 7b thus formed, a yield of almost 100% can be secured with a gate area of φ400 μm.

As described above, before forming the LTO film 7b, 1
By forming the bonding layer 7a by heat treatment at about 250 ° C., generation of residual carbon at the interface between the LTO film 7b and the surface channel layer 5 can be suppressed, and these interfaces can be improved. Therefore, the channel mobility can be further improved, and the on-resistance can be reduced.

After that, if necessary, the LTO film 7b
900 ° C, 30 ° C in Ar atmosphere
min heat treatment (annealing treatment) may be performed. After the thermal oxidation step before the deposition of the LTO film 7b is completed, the temperature of the SiC substrate is lowered. Even in this temperature lowering step, residual carbon is formed at the interface between the surface channel layer 5 and the bonding film 7a. Therefore, it is preferable to perform a temperature lowering process that can lower the temperature of the SiC substrate in a short time by, for example, blowing an inert gas onto the SiC substrate. Specifically, it has been confirmed in experiments that when the amount of the oxide film that increases during the lowering temperature step becomes 6 nm or more, the interface state density becomes remarkably high. Therefore, the increase in the amount of the oxide film becomes 6 nm or less. It is preferable to perform the low-temperature step under such conditions.

Thereafter, LPCVD is performed on the gate insulating film 7.
To form a polysilicon layer. The film forming temperature at this time is set to 600 ° C. Thereafter, the gate electrode 8 is formed by patterning the polysilicon layer.

[Step shown in FIG. 4B] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate electrode 8 and the gate insulating film 7. More specifically, the film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation.

[Step shown in FIG. 4C] Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed. Thus, the MOSFE shown in FIG.
T is completed.

(Second Embodiment) In the first embodiment, the case where the present invention is applied to a planar type vertical power MOSFET is shown. However, in the present embodiment, the present invention is applied to a trench gate type vertical power MOSFET. Is applied.

FIG. 5 shows a trench gate type MOSFET.
The trench gate type of MOSFET, for example, on the n ⁺ -type semiconductor substrate 21, n ^- that the type epi layer 22 and the p-type base layer 23 are laminated is used as the substrate 24.

A groove 27 is formed from the surface of the substrate 24 so as to penetrate the p-type base layer 23 together with the source region 25 located on the surface layer of the p-type base layer 23. A channel layer 28 is formed. In addition, a gate electrode 30 is formed in the trench 27 with a gate oxide film 29 interposed therebetween.
A source electrode 32 connected to the source region 25 and the p-type base layer 23 is formed via an interlayer insulating film 31.
Further, a drain electrode 33 is provided on the back surface side of the substrate 24.

A trench gate type MO having such a structure
In the case of the SFET, as in the first embodiment, in the thermal oxidation step performed at the time of forming the gate oxide film 29 and the annealing performed as necessary, the heat treatment temperature is set to, for example, about 1250 ° C. as in the first embodiment. The first
The same effect as that of the embodiment can be obtained.

(Third Embodiment) This embodiment shows a case where the present invention is applied to a lateral MOSFET. FIG. 6 shows a lateral MOSFET. For the lateral MOSFET, for example, a p-type semiconductor substrate 101 is used as a substrate. A surface channel layer 102 is formed in a predetermined region of the substrate 101 by ion implantation or the like, and a source layer 103 and a drain layer 104 are formed on both sides of the surface channel layer 102. The surface channel layer 10
2, a gate electrode is provided via a gate oxide film 105.

The lateral MOSFE constructed as described above
In the case of T as well, in the thermal oxidation step performed at the time of forming the gate oxide film 105 and the annealing treatment performed as necessary thereafter, as in the first embodiment, the heat treatment temperature is set to, for example, about 1250 ° C. as in the above embodiment. By doing so, the same effect as in the first embodiment can be obtained.

(Other Embodiments) In the above embodiment, the oxidation temperature before deposition of the LTO film is 1250 ° C. Specifically, at least Gibbs free energy in Chemical Formula 1 among the following Chemical Formulas is negative. If the silicon carbide recrystallization reaction is allowed to occur spontaneously during thermal oxidation, the LTO film and SiC
Interface is modified. For example, a heat treatment temperature of 120
When the temperature is set to 0 ° C. or higher, both chemical formulas 1 and 2 turn negative, and the interface between the LTO film and SiC can be efficiently modified.

[0059]

Embedded image SiC + 3C → SiC + 2CO

[0060]

## STR2 ## In the _{SiO 2 + 2C → SiC + CO} 2 above embodiment, the oxidizing atmosphere before deposition of the LTO layer is set to O _2, in the same manner as described above, Formula 1
And if the free energy of Gibbs in Chemical Formula 2 is long both turned negative, also it can be performed efficiently modification of the interface between the LTO layer and the SiC with a mixed gas of H ₂ O and O ₂ and H ₂ O.

In each of the above embodiments, the case where the present invention is applied to a gate insulating film of a MOSFET is described. However, the above embodiment is applied to an interface between an insulating film used as a field plate or an interlayer insulating film and SiC. You may.

In the above embodiment, the thermal oxide film is used as the bonding layer. However, an epitaxial layer obtained by epitaxially growing Si may be used. By using such an epitaxial layer, the carbon-free bonding layer 7b can be obtained. In this case, by forming the epitaxial layer in a 3 × 3 structure, the bonding between bonding layer 7b and the semiconductor layer made of silicon carbide (surface channel layer 5) can be reliably performed. In this case, the Si epitaxial layer and the deposited LTO film can be satisfactorily bonded by performing a heat treatment in an Ar atmosphere.

In the above embodiment, the case where the LTO film is used as the deposited film after the thermal oxidation is used. For example, as in the lateral type MOSFET shown in FIG. 7, the silicon nitride film 110 is used as the deposited film. In addition, the silicon nitride film 110 is oxidized by, for example, about 5 to 10 nm to form an oxide film 111, 1 on both surfaces.
The present invention can also be applied to a case where an insulating film on which an insulating film 12 is formed, that is, an ONO film is used. In this case, the silicon nitride film can be formed by a CVD method or an LPCVD method.

[Brief description of the drawings]

FIG. 1 is a planer type M according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional configuration of an OSFET.

FIG. 2 is a view showing a manufacturing process of the MOSFET shown in FIG. 1;

FIG. 3 is a diagram showing a manufacturing step of the MOSFET following FIG. 2;

FIG. 4 is a view showing a manufacturing step of the MOSFET following FIG. 3;

FIG. 5 shows a trench gate type M according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional configuration of an OSFET.

FIG. 6 shows a lateral type M according to a third embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional configuration of an OSFET.

FIG. 7 shows a lateral MOSFET shown in another embodiment.
FIG. 3 is a diagram showing a cross-sectional configuration of FIG.

[Explanation of symbols]

Reference numerals 1 ... n ⁺ type substrate, 2 ... n ^- type epi layer, 3 ... p type base region, 4 ... n ⁺ type source region, 5 ... surface channel layer, 6 ...
J-FET part, 7 gate oxide film, 7a coupling layer, 7b
... LTO film, 8 ... gate electrode, 10 ... source electrode, 11
... Drain electrode.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/336 H01L 29/78 301G 301Q 658F (72) Inventor Shinji Amano 1-1-1 Showa-cho, Kariya-shi, Aichi Pref. F term in DENSO Corporation (reference) 5F040 DA01 DA22 DC02 DC10 EB13 EC07 ED01 ED02 ED03 ED04 EE04 5F058 BA20 BB10 BC02 BF56 BF62 BF63 BJ10

Claims (25)

[Claims] 1. A substrate provided with a semiconductor layer (5) made of silicon carbide is prepared, and an insulating film (7b) is formed on the semiconductor layer.
Forming a bonding layer (7a) for bonding the semiconductor layer and the deposited film on the semiconductor layer before depositing the insulating film. A method for manufacturing a silicon carbide semiconductor device, comprising a bonding layer forming step. 2. A thermal oxidation is performed in the bonding layer forming step.
2. The method according to claim 1, wherein a thermal oxide film formed on the semiconductor layer by the thermal oxidation is used as the bonding layer. 3. The method according to claim 1, wherein the thermal oxidation is performed at a temperature of 1200 ° C. or more and 140 ° C.
3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the method is performed at 0 ° C. or lower. 4. The method of manufacturing a silicon carbide semiconductor device according to claim 2, wherein said thermal oxidation is performed in an oxygen atmosphere. 5. The thermal oxidation method according to claim 2, wherein the thermal oxidation has a thickness of 6 nm or less.
5. A method for manufacturing a silicon carbide semiconductor device according to any one of the above. 6. The silicon carbide semiconductor device according to claim 1, wherein in the bonding layer forming step, an epitaxial layer formed by epitaxially growing silicon on the semiconductor layer is used as the bonding layer. Method. 7. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein said epitaxial layer is formed in a 3 × 3 structure in said epitaxial growth. 8. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein said bonding layer is formed by thermally oxidizing said epitaxial layer. 9. The method of claim 1, wherein the thermal oxidation of the epitaxial layer
The method according to claim 8, wherein the method is performed at 0 ° C. or lower. 10. The method of manufacturing a silicon carbide semiconductor device according to claim 8, wherein said epitaxial thermal oxidation is performed with oxygen. 11. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a silicon oxide film is used as said deposition film. 12. The method according to claim 12, wherein the silicon oxide film as the deposited film is CV
The method of manufacturing a silicon carbide semiconductor device according to claim 11, wherein the method is performed by a D method or an LPCVD method. 13. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein a deposition rate of said silicon oxide film is set to 1 nm / min or more and 5 nm / min or less. 14. The silicon oxide film has a refractive index of 1.35 or more and 1.50 or less.
14. The method for manufacturing a silicon carbide semiconductor device according to any one of items 13 to 13. 15. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a silicon nitride film is used as said deposition film. 16. The method according to claim 16, wherein the silicon nitride film as the deposition film is CV
The method of manufacturing a silicon carbide semiconductor device according to claim 15, wherein the method is performed by a D method or an LPCVD method. 17. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein a deposition rate of said silicon nitride film is set to 1 nm / min or more and 5 nm / min or less. 18. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the silicon nitride film has a refractive index of 1.9 or more and 2.1 or less. 19. The method of manufacturing a silicon carbide semiconductor device according to claim 15, wherein, after depositing said silicon nitride film, the surface of said silicon nitride film is thermally oxidized. . 20. A method for manufacturing a silicon carbide semiconductor device, comprising forming a gate electrode (8) on a semiconductor layer made of silicon carbide with a gate insulating film (7) interposed therebetween, according to claim 1. A method for manufacturing a silicon carbide semiconductor device, wherein a layer forming step is performed before forming the gate insulating film. 21. A method of manufacturing a silicon carbide semiconductor device in which a field plate is formed on a semiconductor layer made of silicon carbide with an insulating film interposed therebetween, wherein the step of forming a coupling layer according to claim 1 is performed under the field plate. A method for manufacturing a silicon carbide semiconductor device, which is performed before forming the insulating film to be arranged. 22. A method of manufacturing a silicon carbide semiconductor device, comprising forming an interlayer insulating film on a semiconductor layer made of silicon carbide, wherein the step of forming a bonding layer according to claim 1 is performed before forming the interlayer insulating film. A method for manufacturing a silicon carbide semiconductor device. 23. A semiconductor device having a main surface and a back surface opposite to the main surface, wherein the first conductive semiconductor substrate made of silicon carbide has a higher resistance than the semiconductor substrate. First conductive type semiconductor layers (2, 2
Forming a second conductive type base region (3, 23) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer; and forming the base region. Forming a first conductive type source region (4, 25) shallower than a depth of the base region in a predetermined region of a surface layer portion of the semiconductor device; and connecting the source region and the semiconductor layer. Forming a first conductive type surface channel layer (5, 28) made of silicon carbide; and a gate insulating film (7, 29) on the surface of the surface channel layer.
Forming a gate electrode (8, 30) on the gate insulating film; and forming a source electrode (10, 32) in contact with the base region and the source region. 20. A method of manufacturing a silicon carbide semiconductor device, comprising: a step of forming a drain electrode (11, 33) on a back surface of the semiconductor substrate. A method for manufacturing a silicon carbide semiconductor device, which is performed before forming a gate insulating film. 24. The method of manufacturing a silicon carbide semiconductor device according to claim 20, wherein the polymorph of the semiconductor layer made of silicon carbide is 4H. 25. The silicon carbide according to claim 24, wherein a main surface of the semiconductor layer made of silicon carbide is a (0001) Si plane or a (11-20) plane.