JPH11238742A - Manufacture of silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high mobility in a planar MOSFET. SOLUTION: Prior to epitaxial growth of a surface channel layer on an n<-> type silicon carbide epitaxial layer 2 and p<-> type silicon carbide base regions 3a and 3b, the base regions 3a, 3b and epitaxial layer 2 are subjected thereon to RIE a reactive ion etching, and further subjected thereon to a heat treatment etching process in a hydrogen atmosphere. Thereby the surface of a wafer for epitaxial growth of the surface channel layer can be mode in a satisfactory condition, and the crystallization of the surface channel layer can be made satisfactory. As a result, the channel modality of the surface channel layer an be improved, and the mobility of a planar power MOSFET can be made high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate field effect transistor, and more particularly to a vertical power MOSFET for high power.

[0002]

2. Description of the Related Art The applicant of the present invention has filed a Japanese Patent Application No. 9-259076 for a vertical MOSFET in which channel mobility is improved and on-resistance is reduced. FIG. 4 shows a cross-sectional view of a planar MOSFET as an example of the vertical MOSFET, and the structure of the planar MOSFET will be described with reference to FIG.

An n ⁺ -type silicon carbide semiconductor substrate 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. Main surface 1a of n ⁺ type silicon carbide semiconductor substrate 1
Above, n ⁻ having a lower dopant concentration than substrate 1
-Type silicon carbide epitaxial layer (hereinafter referred to as n ^- type silicon carbide epi layer) 2 is stacked. In this case, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- but the upper surface of type silicon carbide epitaxial layer 2 is set to (0001) Si plane, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- -type silicon carbide epitaxial layer 2 The upper surface may be the (112-0) a surface. That is, (000
1) A low surface state density can be obtained by using the Si surface, and (1)
The use of the 12-0) a-plane makes it possible to obtain a crystal having a low surface state density and completely free from screw dislocations. At this time, of course, an off-substrate having an inclination of about 3 ° to 10 ° may be used for high-quality growth of n ⁻ -type silicon carbide epilayer 2.

[0004] n^-In the surface layer of silicon carbide epilayer 2
In a predetermined area, p having a predetermined depth ^-Type silicon carbide base
Regions 3a and p^-Type silicon carbide base region 3b is separated
It is formed. Also, p^--Type silicon carbide base region 3
a in a predetermined region in the surface layer portion of the base region 3a
Also shallow n⁺The type source region 4a also has p^-Type silicon carbide
A predetermined area in the surface portion of the base area 3b includes a base
N shallower than region 3b ⁺Each of the mold source regions 4b
Has been established.

Further, the surface of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b have n ⁻ -type SiC Layer 5 extends. That is, n ⁻ -type SiC layer 5 is arranged so as to connect source regions 4a, 4b and n ⁻ -type silicon carbide epilayer 2 at the surface portions of p ⁻ -type silicon carbide base regions 3a, 3b.

[0006] The n ^- type SiC layer 5 has been formed by epitaxial growth, the crystal of the epitaxial film is used 4H, 6H, those 3C. The epitaxial layer can form various crystals regardless of the underlying substrate. This n ⁺ -type SiC layer 5 functions as a channel forming layer on the device surface during device operation. Hereinafter, this n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the surface channel layer 5 is 1
The concentration is as low as about × 10 ¹⁵ cm ⁻³ to about 1 × 10 ¹⁷ cm ⁻³ , and is lower than the dopant concentration of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b. ing. Thereby, low on-resistance is achieved. In addition, concave portions 6a and 6b are formed in the surface portions of p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7, and the polysilicon gate electrode 8 is formed by LTO (Low Tem).
It is covered with an insulating film 9 made of P.O. A source electrode 10 is formed thereon,
The source electrode 10 includes n ⁺ type source regions 4a, 4b and p
^- type silicon carbide base regions 3a, is in contact with 3b. Drain electrode 11 is formed on rear surface 1b of n ⁺ -type silicon carbide semiconductor substrate 1.

Next, a planar type power MOS shown in FIG.
The manufacturing process of the FET will be described with reference to FIGS. [Step shown in FIG. 5A] First, an n-type 4H or 6H or 3C-SiC substrate, that is, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared. Here, n ⁺ -type silicon carbide semiconductor substrate 1 has a thickness of 400 μm and main surface 1a has a thickness of (00).
01) Si plane or (112-0) a plane. An n ^-- type silicon carbide epilayer 2 having a thickness of 5 μm is epitaxially grown on main surface 1a of substrate 1. In this example, n ⁻ -type silicon carbide epilayer 2 has the same crystal as base substrate 1,
It becomes a mold 4H or 6H or 3C-SiC layer.

[Step shown in FIG. 5 (b)] After polishing the surface of n ^- type silicon carbide epilayer 2, L
A TO film 20 is arranged, and B ⁺ (or aluminum) is ion-implanted using the TO film 20 as a mask to form p ⁻ -type silicon carbide base regions 3a and 3b. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ cm.
^-2 .

[Step shown in FIG. 5 (c)] After the LTO film 20 is removed, the surface of the n ⁻ -type silicon carbide epilayer 2 and the upper portions of the p ⁻ -type silicon carbide base regions 3a and 3b are formed by epitaxial growth. The surface channel layer 5 is grown. At this time, the thickness (film thickness) of the surface channel layer 5 is set to a desired thickness in order to make the planar power MOSFET a normally-off type.

[Step shown in FIG. 6 (a)] An LTO film 21 is arranged in a predetermined region on the surface channel layer 5, and N ⁺ ions are implanted using the LTO film 21 as a mask to form an n ⁺ type source region 4a,
4b is formed. The ion implantation condition at this time is 700
C. and the dose is 1 × 10 ¹⁵ cm ⁻² . [Step shown in FIG. 6B] Then, after the LTO film 21 is removed, an LTO film 22 is arranged in a predetermined region on the surface channel layer 5 by using a photoresist method, and the pTO is formed by RIE using the LTO film 22 as a mask. ^- type silicon carbide base regions 3a, 3b
The upper surface channel layer 5 is partially etched away.

[Step shown in FIG. 6 (c)]
B ⁺ ions are implanted using the film 22 as a mask to form the deep base layers 30a and 30b. As a result, a part of base regions 3a and 3b becomes thicker, and n ⁻ -type silicon carbide epitaxial layer 2 under deep base layers 30a and 30b.
, The electric field strength can be increased, so that avalanche breakdown easily occurs at this portion, and the withstand voltage can be improved.

The deep base layers 30a and 30b are
The p ^- type silicon carbide base regions 3a, 3b are formed in portions that do not overlap the n ⁺ -type source regions 4a, 4b, and the portions of the p ⁻ -type silicon carbide base regions 3a, 3b where the deep base layers 30a, 30b are formed are thickened. The impurity concentration is higher than that of the thin portion where the layer 30a is not formed.

[Step shown in FIG. 7A] After removing the LTO film 22, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C. Thereafter, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 7B]
After removing unnecessary portions of the insulating film 7,
An edge film 9 is formed to cover the gate insulating film 7. More specifically,
The film formation temperature is 425 ° C.
Rules. At this time, the annealing atmosphere gas is H_Two, N
_TwoOr Ar.

[Step shown in FIG. 7C] Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed. Thus, the vertical power MOSFET shown in FIG. 1 is completed. Next, the operation (operation) of the power planar type MOSFET will be described.

The MOSFET operates in a storage mode. In surface channel layer 5, carriers are the difference in electrostatic potential between p ⁻ -type silicon carbide base regions 3 a and 3 b and surface channel layer 5, and the work function between surface channel layer 5 and polysilicon gate electrode 8. Depleted by the potential generated by the difference between Therefore, by adjusting the voltage applied to the polysilicon gate electrode 8, the work function difference between the surface channel layer 5 and the polysilicon gate electrode 8 and the potential difference caused by an externally applied voltage are changed. By controlling the channel state, MOSFE
Controls ON and OFF of T.

More specifically, in the off state, the depletion region is formed in surface channel layer 5 by an electric field created by p ⁻ -type silicon carbide base regions 3 a and 3 b and polysilicon gate electrode 8. By supplying a positive bias to the polysilicon gate electrode 8, the n ⁺ -type source regions 4a, 4b to n at the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5
^- a channel region formed extending in a type drift region 2 direction to switch to the ON state.

At this time, electrons are supplied to the n ⁺ type source region 4.
a and 4b flow through the surface channel layer 5 and flow from the surface channel layer 5 to the n ⁻ -type silicon carbide epilayer 2 including the JFET portion. Then, n ⁻ -type silicon carbide epilayer (drift region) 2
, Electrons are transferred to the n ⁺ type silicon carbide semiconductor substrate (n ⁺
Drain) 1 flows vertically. Thus, the gate electrode 8
, A storage channel is induced in the surface channel layer 5, and a current flows between the source electrode 10 and the drain electrode 11.

As described above, in the planar type MOSFET, the operation mode is set to the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer. The on-resistance is reduced by increasing the mobility.

[0022]

In the planar type MOSFET shown in FIG. 1, the surface channel layer 5 constituting the channel region is formed by epitaxial growth. However, the wafer surfaces (surfaces of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b) on which the epitaxial growth is performed are used for polishing or forming p ⁻ -type silicon carbide base regions 3a and 3b. Since the epi surface was damaged by the ion implantation, it was found that the crystallinity did not become good (energy concentration at the time of ion implantation occurred in the epi surface layer and the crystallinity deteriorated).

For this reason, it has been found that a problem occurs in the FET operating characteristics that the channel mobility is reduced. The present invention has been made in view of the above points, and has been made in consideration of a planar type MOS.
It is an object to increase the mobility of an FET.

[0024]

In order to achieve the above object, the following technical means are employed. In the invention described in claim 1, the semiconductor layer (2) and the base region (3)
Before the step of epitaxially growing the surface channel layer (5) on top of the base regions (3a, 3b)
And the surface of the semiconductor layer (2) is subjected to RIE (Riacti).
and a step of etching the surfaces of the base regions (3a, 3b) and the surface of the semiconductor layer (2) by heat treatment in a hydrogen atmosphere.

As described above, if the surfaces of the base regions (3a, 3b) and the semiconductor layer (2) are etched by RIE, the irregularities on the surfaces and the base regions (3a, 3b) can be obtained.
b), the damaged portion of the surface of the semiconductor layer (2) due to ion implantation can be removed, and if the surface is etched by heat treatment in a hydrogen atmosphere, R
The part damaged by the IE can be removed.

Therefore, before the surface channel layer (5) is epitaxially grown, the condition of the surface of the wafer to be grown can be improved, and the crystallinity of the surface channel layer (5) can be improved. Thereby, the channel mobility of the surface channel layer (5) can be improved, and the mobility of the planar power MOSFET can be increased.

According to a second aspect of the present invention, the surfaces of the base region (3a, 3b) and the semiconductor layer (2) are formed by RIE.
After etching by a sacrificial oxide film (3
Even if c) is formed and the sacrificial oxide film (3c) is removed, the same effect as in claim 1 can be obtained.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) Vertical power MO shown in this embodiment
The SFET is different from the conventional one in the manufacturing method,
Since the structure is the same as that of the vertical power MOSFET shown in FIG. 8, only the manufacturing method will be described, and the description of the structure will be omitted. In this embodiment, since a manufacturing process described later is added to the conventional manufacturing process shown in FIGS. 3 to 5, the same parts as those described above are shown in FIGS. Only the added portion will be described.

First, FIG. 5A and FIG.
By performing the step shown in (b), p ^-- type silicon carbide base regions 3a and 3b are formed in predetermined regions of n ^-- type silicon carbide epilayer 2. Next, the following manufacturing process is performed. [Step shown in FIG. 1 (a)] First, the LTO film (low temperature growth oxide film) 20 is removed, and R, which is one of dry etching, is removed.
The entire surface of the wafer (the surface of the n ⁻ -type silicon carbide epilayer 2 and the p ⁻ -type silicon carbide base regions 3a and 3b) is plasma-etched to a thickness of about several nm by the IE method. At this time, RI
As the E gas, only a fluorine-based gas such as SF ₆ , CF ₄ or CH ₃ , or a gas obtained by adding hydrogen to a fluorine-based gas or a gas obtained by adding oxygen to a fluorine-based gas is used. By this step, the irregularities on the wafer surface and the surface roughness when the p ⁻ -type silicon carbide base regions 3a and 3b are formed are removed.

[Step shown in FIG. 1B] Next, after RCA cleaning, a heat treatment at 1500 ° C. is performed in a hydrogen atmosphere. As a result, damage caused at the time of etching by the RIE method is removed by etching, and the wafer surface becomes smooth and has good crystallinity. Then, the step shown in FIG. 5C is performed, and the epitaxial film (surface channel layer) 5 is formed.
Grow. At this time, in the steps shown in FIGS. 1A and 1B, since the wafer surface is smooth and has good crystallinity and a good surface state, the epitaxial film (surface channel layer) 5 to be grown is formed. Also have excellent crystallinity.

Specifically, when the crystallinity of the epitaxial film 5 was observed with an X-ray, the present embodiment shown in FIG. 2B was compared with the conventional one shown in FIG. In the form, the characteristics of the X-ray rocking curve were better, and it was confirmed that the crystallinity was improved. Thereafter, the planar type power MOSFET is completed through the steps shown in FIGS. Thus, the planar type power MOSFET according to the present embodiment
Is manufactured.

Next, the operation (operation) of the vertical power MOSFET will be described. This MOSFET operates in a normally-off type accumulation mode, and when no voltage is applied to the polysilicon gate electrode, the surface channel layer 5
The carrier is a p ^- type silicon carbide base region 3a,
3b and the difference in electrostatic potential between the surface channel layer 5 and the surface channel layer 5 and the polysilicon gate electrode 8
Is fully depleted by the potential created by the work function difference between By applying a voltage to the polysilicon gate electrode 8, a potential difference caused by a sum of a work function difference between the surface channel layer 5 and the polysilicon gate electrode 8 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

That is, the work function of the polysilicon gate electrode 8 is the first work function, the work function of the p ⁻ -type silicon carbide base regions 3a and 3b is the second work function, and the work function of the surface channel layer 5 is Assuming the third work function, the first
Using the difference between the first to third work functions, the first to third work functions, the impurity concentration and the film thickness of the surface channel layer 5 are set so as to deplete the n-type carriers in the surface channel layer 5. be able to.

In the off state, the depletion region is p
^--Type silicon carbide base regions 3a, 3b and polysilicon regions
The electric field created by the gate electrode 8 causes the surface channel
Formed in layer 5. From this state the polysilicon gate
When a positive bias is supplied to the electrode 8, the gate insulation
Film (SiO_Two) At the interface between 7 and the surface channel layer 5
And n⁺From the mold source regions 4a, 4b to n^-Mold drift area
A channel region extending in the direction of region 2 is formed and turned on.
Is switched. At this time, the electron is n⁺Type source
From the regions 4a and 4b via the surface channel layer 5, the surface channel
Flannel layer 5 to n ^-Flows into the epitaxial silicon carbide layer 2. Soshi
And n^--Type silicon carbide epi layer 2 (drift region)
And the electron is n⁺Type silicon carbide semiconductor substrate 1 (n⁺Dray
Flows vertically to

As described above, by applying a positive voltage to the gate electrode 8, a storage channel is induced in the surface channel layer 5, and carriers flow between the source electrode 10 and the drain electrode 11. At this time, as described above, the planar-type power MOSFET of the present embodiment has better crystallinity of the surface channel layer 5 than the conventional planar-type MOSFET. For this reason, in the present embodiment, the surface channel layer 5
Channel mobility can be improved, and a high mobility planar power MOSFET can be obtained.

Specifically, FET operation characteristics after device fabrication are described.
Investigation of the characteristics shows that a conventional planar power MOS
FET has channel mobility of 40cm^Two/ Vsec
The planar type power MOSFET according to the present embodiment
Has a channel mobility of 120 cm ^Two/ Vsec.
That is, in the present embodiment, the channel mobility is higher than in the related art.
The result is that it has increased threefold. This result
High mobility of planar type power MOSFET
It turns out that it is planned.

As described above, before the surface channel layer 5 is epitaxially grown, the damaged layer on the wafer surface is removed by RIE, and the RIE damage is subjected to a heat treatment in a hydrogen atmosphere to improve the condition of the wafer surface. The crystallinity of the epitaxial film (surface channel layer) 5 formed thereon can be improved.

(Second Embodiment) In this embodiment, the state of the wafer surface on which the epitaxial film (surface channel layer) 5 is grown is improved by a method different from that of the first embodiment. Accordingly, a manufacturing process for improving the condition of the wafer surface is shown in FIG. 3, and only this process will be described.

[Step shown in FIG. 3A] First, the LTO film
20 is removed, and the entire surface of the wafer (n^-
-Type silicon carbide epilayer 2 and p^--Type silicon carbide base region 3
a, 3b) is plasma-etched to about several nm.
You. At this time, SF is used as the RIE gas.₆, CF_Four, C
H _ThreeHydrogen gas only or fluorine gas
Oxygen is added to the gas or fluorine gas
Is used. By this process, irregularities on the wafer surface and
p^-When silicon carbide base regions 3a and 3b are formed
Surface roughness is removed.

[Step shown in FIG. 3B] Next, after RCA cleaning, wet oxidation is performed at about 1100 ° C. for 4 hours. Thus, a sacrificial oxide film 3c is formed on the wafer surface. [Step shown in FIG. 3 (c)] Thereafter, the sacrificial oxide film 3c is removed by etching with diluted hydrofluoric acid. With this, RIE
The damage caused during the etching by the method is removed, and the wafer surface becomes smooth and has good crystallinity.

Then, the step shown in FIG.
When the epitaxial film (surface channel layer) 5 is grown, the epitaxial film (surface channel layer) 5 also has excellent crystallinity. Thereby, similarly to the first embodiment,
The mobility of the planar power MOSFET can be increased.

(Other Embodiments) In the above embodiment, n ⁺
Although the surface channel layer 5 is epitaxially grown before forming the mold source regions 4a and 4b, n ⁺
After forming source regions 4a and 4b, n ⁺ source regions 4a and 4b and p ⁻ type silicon carbide base region 3 are formed.
A surface channel layer 40 may be epitaxially grown on the surfaces of the a, 3b and n ⁻ -type silicon carbide epilayers 2.

In the above embodiment, the planar MOSFET has been described as an example. However, a so-called trench (concave) vertical MOSFET in which the channel layer is perpendicular to the substrate surface is an embodiment of the present invention. A form may be applied. In the above embodiment, the plane orientation is specified and described. However, the above effects can be obtained without specifying the substrate plane orientation in the embodiment.

[Brief description of the drawings]

FIG. 1 is a planer type power MOS according to a first embodiment.
It is a figure showing the manufacturing process of FET.

FIGS. 2A and 2B are comparison diagrams showing an X-ray rocking curve in a surface channel layer 5; FIG. 2A is a diagram when a wafer surface treatment is performed; FIG. 2B is a diagram when a wafer surface treatment is not performed; FIG.

FIG. 3 is a planer type power MOS according to a second embodiment.
It is a figure showing the manufacturing process of FET.

FIG. 4 is a vertical power MOSFE filed earlier by the present applicant.
It is sectional drawing which shows the structure of T.

FIG. 5 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 4;

FIG. 6 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 5;

FIG. 7 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 6;

[Explanation of symbols]

1 ... n ⁺ -type silicon carbide semiconductor substrate, 2 ... n ^- -type silicon carbide epitaxial layer, 3a, 3b ... p ^- type silicon carbide base region, 4a, 4b ... n ⁺ -type source region, 5 ... surface channel layer (n ^- 7: gate insulating film, 8: gate electrode, 9: insulating film, 10: source electrode, 11: drain electrode.

Claims (2)

[Claims] 1. A step of forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1). Forming a second conductivity type base region (3a, 3b) having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer (2) by ion implantation; and the base region (3a, 3b). And the semiconductor layer (2)
The surface of the RIE (Reactive Ion Etch)
ing), the base region (3a, 3b) and the semiconductor layer (2).
Etching the surface of the semiconductor layer by heat treatment in a hydrogen atmosphere; and the semiconductor layer (2) and the base regions (3a, 3b).
A step of epitaxially growing a surface channel layer (5) on the upper surface of the base region (3),
Forming a first conductivity type source region (4a, 4b) in contact with the surface channel layer (5) and shallower than the depth of the base region (3a, 3b). . 2. A step of forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductive type semiconductor substrate (1). Forming a second conductivity type base region (3a, 3b) having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer (2) by ion implantation; and the base region (3a, 3b). And the semiconductor layer (2)
Etching the surface of the base region by RIE, the base region (3a, 3b) and the semiconductor layer (2).
Forming a sacrificial oxide film (3c) on the surface of the substrate; removing the sacrificial oxide film (3c); the semiconductor layer (2) and the base regions (3a, 3b)
A step of epitaxially growing a surface channel layer (5) on the upper surface of the base region (3),
Forming a first conductivity type source region (4a, 4b) in contact with the surface channel layer (5) and shallower than the depth of the base region (3a, 3b). .