JP2008205296A - Silicon carbide semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve element characteristics by reducing step bunching of a surface of an SiC epitaxial layer formed on an SiC substrate. <P>SOLUTION: A silicon carbide semiconductor element has a 4H-SiC substrate 1 and the SiC epitaxial layer 3 formed on a surface of a 4H-SiC substrate 1, which has an OFF angle of 3° to 5°, at least a partial surface of the SiC epitaxial layer 3 having a surface roughness of ≤1 nm. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.

  Silicon carbide (silicon carbide: SiC) is a semiconductor that is expected to be applied to the next generation of low-loss power devices because it has a larger band gap and higher dielectric breakdown field strength than silicon (Si). Material. Silicon carbide has many polytypes such as cubic 3C—SiC, hexagonal 4H—SiC, and 6H—SiC. Among these, 4H-SiC is a polytype generally used for producing a practical silicon carbide semiconductor element. Examples of silicon carbide semiconductor elements using 4H—SiC include MOSFETs, MESFETs, and Schottky diodes.

  4H-SiC has a higher electron mobility in the [0001] direction than other hexagonal polytypes (6H-SiC), so when the (0001) plane is used as the main surface, Becomes easier to flow. Therefore, 4H—SiC is widely used especially for power devices having a vertical structure.

A silicon carbide semiconductor element as described above is generally manufactured using a 4H—SiC substrate whose main surface is a surface substantially coinciding with the (0001) plane perpendicular to the c-axis. As the 4H-SiC substrate, when an off-angle substrate having a surface (step structure surface) whose step density is increased by inclining by an off angle of several degrees from the (0001) plane, a step flow is formed on the surface of the 4H-SiC substrate. SiC can be epitaxially grown (step flow growth), and a SiC epitaxial layer with good crystal quality can be formed. The obtained SiC epitaxial layer functions as an active region of the silicon carbide semiconductor element. For example, in a MOSFET, an impurity doped layer such as a p-type well region or an n ⁺ source region whose conductivity type and carrier concentration are controlled is formed in a SiC epitaxial layer.

  Such a silicon carbide semiconductor device has a problem that step bunching is formed on the surface of the SiC epitaxial layer due to the above-described step flow growth. Step bunching is a factor that degrades element characteristics.

  Hereinafter, the mechanism of SiC step flow growth and the mechanism by which step bunching is formed on the surface of the epitaxial layer formed by step flow growth will be described in detail with reference to the drawings.

  FIG. 9 is a schematic enlarged cross-sectional view for explaining a mechanism of step flow growth of a SiC epitaxial layer on the surface of a 4H—SiC substrate (hereinafter simply referred to as “SiC substrate”).

  As shown in FIG. 9, SiC substrate 40 having off angle θ has atomic level steps (hereinafter referred to as “atomic steps”) 41 on the surface. The terrace portion 41t of the atomic step 41 is composed of the (0001) plane. Further, the height of the atomic step 41 is, for example, 0.25 nm.

  When a source gas is supplied to the surface of SiC substrate 40, epitaxial growth of silicon carbide is started using step flow 50 by lateral growth of atomic step 41. As shown in the figure, stepped steps 43 resulting from step flow growth exist on the surface of the growing SiC epitaxial layer 42. The reactive species such as Si and C contained in the source gas are ideally adsorbed on the stepped portion of each step 43 and the lateral growth proceeds.

  However, if this reactive species is adsorbed on the terrace of step 43, step flow growth is inhibited, resulting in overlapping of step 43, resulting in a very large step (step bunching).

  FIGS. 10A to 10C are schematic enlarged cross-sectional views for explaining the mechanism by which step bunching is formed on the surface of the SiC epitaxial layer 42 during step flow growth.

  As shown in FIG. 10A, during step flow growth, reactive species 60 such as C and Si are preferentially adsorbed on the step 43d of step 43 on the surface of the SiC epitaxial layer 42, but some reactive species. 61 a and 61 b are adsorbed on the terrace 43 t of step 43.

  As shown in FIG. 10B, when the reactive species 60 are sequentially adsorbed on the step 43d of step 43, silicon carbide can be grown in the lateral direction. On the other hand, the reactive species 61a and 61b adsorbed on the terrace 43t may inhibit such lateral growth. For example, growth using the reactive species 61a as a nucleus (two-dimensional nuclear growth) proceeds or lateral growth is inhibited by the reactive species 61b.

  As a result, as shown in FIG. 10C, an extremely large step, that is, step bunching 62 occurs in the portion of the surface of the SiC epitaxial layer 42 where the step flow growth is inhibited by the reactive species 61a and 61b.

  Here, the off angle of the SiC substrate 40 will be described. Conventionally, the off-angle θ of the 4H—SiC substrate 40 is 8 ° in the [11-20] direction with the (0001) plane as a reference plane, but the diameter of the substrate has been increased to 3 inches. 4 ° is becoming mainstream. This is because if the off-angle θ is reduced, the number of substrates that can be taken out from the SiC bulk crystal produced by the sublimation method can be increased, so that the SiC material can be used efficiently particularly when taking out a large-diameter substrate.

  However, when the off-angle θ of the SiC substrate 40 decreases, the size of the step bunching 62 (terrace width and step height) as shown in FIG. 10C increases.

  FIGS. 11A and 11B are schematic enlarged cross-sectional views showing the surface shapes of a SiC substrate having an off angle of 4 ° and an SiC substrate having an off angle of 8 °, respectively. In the SiC substrate 40a having an off angle of 4 °, the width A of the terrace 41t of the atomic step 41 is about 14 nm, and in the SiC substrate 40b having an off angle of 8 °, the width B of the terrace 41t of the atomic step 41 is about 7 nm. Therefore, the width A of the terrace 41t of the atomic step 41 of the SiC substrate 40 having an off angle of 4 ° is twice as large as the width B of the terrace 41t of the atomic step 41 of the SiC substrate 40 having an off angle of 8 °. .

  When the terrace width of the atomic step 41 is increased, as described with reference to FIG. 10, there is a high possibility that the reactive species are adsorbed on the terrace 41t and the step flow growth of silicon carbide is hindered. Therefore, when the SiC substrate 40a having an off angle of 4 ° is used, step bunching is more likely to occur than the SiC substrate 40b having an off angle of 8 °.

  Therefore, when a silicon carbide semiconductor element such as a MOSFET or a Schottky diode is formed using a SiC substrate having a small off angle, deterioration of element characteristics due to step bunching becomes a more serious problem.

  In the MOSFET, an oxide film is formed on the surface of the SiC epitaxial layer, and further a gate electrode is provided thereon to form a MOS interface. If step bunching as described above is present at this MOS interface, carriers are likely to be scattered by step bunching when moving through the MOS interface, and the interface state density is increased, resulting in a decrease in channel mobility. As a result, the power loss of the MOSFET increases.

  Further, in a Schottky diode, if step bunching exists between the SiC epitaxial layer and the Schottky electrode provided on the surface thereof, electric field concentration occurs at the tip portion of the step bunching, and the breakdown voltage of the Schottky diode decreases. There is a fear.

  On the other hand, in order to suppress deterioration of device characteristics due to step bunching, Patent Document 1 discloses a method of reducing the surface roughness of a silicon carbide epitaxial growth layer by mechanically or chemically polishing the surface. Is described.

  Further, Patent Document 2 proposes to form a channel layer having a flatter surface by further epitaxially growing SiC on the surface of the SiC epitaxial layer after activation annealing in the method of manufacturing the MISFET. . In the embodiment of Patent Document 2, a method of manufacturing a MISFET having a channel layer with a surface roughness of 1 nm or less using a SiC substrate having an off angle of 8 ° is described.

On the other hand, it has also been proposed to suppress the surface roughness of the epitaxial layer by smoothing the surface of the SiC substrate and growing the epitaxial layer on the smoothed SiC substrate surface. For example, Patent Document 3 discloses a method of smoothing the SiC substrate surface by hydrogen etching, and Patent Document 4 discloses a method of improving the SiC substrate surface by vacuum high-temperature heating.
JP-A-2005-260218 JP 2005-39257 A JP 2005-277229 A Japanese Patent Laid-Open No. 2005-97040

  According to the method of Patent Document 1, even if the surface of the epitaxial growth layer is flattened, the surface of the epitaxial growth layer may be damaged by polishing, or new unevenness may occur on the surface of the epitaxial growth layer due to polishing scratches. . Therefore, even if a silicon carbide semiconductor element is manufactured using such an epitaxial growth layer, it is difficult to obtain desired element characteristics.

  Further, the methods disclosed in Patent Documents 2 to 4 cannot reduce step bunching generated by the mechanism described with reference to FIG. Therefore, particularly when a SiC substrate having a small off angle is used, it is difficult to sufficiently reduce the surface roughness of the epitaxial layer formed on the surface. Although Patent Document 3 also describes an embodiment in which a hydrogen etching process is performed on a SiC substrate having a small off angle, a specific value of the surface roughness of an epitaxial layer formed on the substrate is described. There is no description.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce step bunching on the surface of the SiC epitaxial layer formed on the SiC substrate in the silicon carbide semiconductor element using the SiC substrate. It is to improve device characteristics.

  The silicon carbide semiconductor device of the present invention includes a 4H—SiC substrate and a SiC epitaxial layer formed on the surface of the 4H—SiC substrate, and the 4H—SiC substrate has an off angle of greater than 3 ° and less than or equal to 5 °. And at least part of the surface of the SiC epitaxial layer has a surface roughness of 1 nm or less.

  It is preferable that the at least part of the surface of the SiC epitaxial layer does not have a polishing mark by mechanical or chemical polishing.

  In a preferred embodiment, the at least part of the surface of the SiC epitaxial layer has a plurality of micro steps, and each step includes a plane composed of (0001) planes, and the height of each step is 1 nm or less.

  In a preferred embodiment, the semiconductor device further includes an electrode in contact with the surface of the SiC epitaxial layer, and at least a part of an interface between the electrode and the SiC epitaxial layer forms a Schottky barrier.

  The surface roughness of the SiC epitaxial layer in contact with the electrode is preferably 1 nm or less.

  In a preferred embodiment, a gate insulating film in contact with the surface of the SiC epitaxial layer, a gate electrode provided on the gate insulating film, a source electrode electrically connected to a part of the SiC epitaxial layer, And a drain electrode provided on a surface facing the surface of the 4H-SiC substrate.

  The surface roughness of the surface of the SiC epitaxial layer in contact with the gate oxide film is 1 nm or less.

  An epi-attached wafer of the present invention comprises a wafer-like 4H—SiC substrate and a SiC epitaxial layer formed on the surface of the 4H—SiC substrate, and the 4H—SiC substrate is larger than 3 ° and less than 5 ° in off-state. The SiC epitaxial layer has a corner and has a surface roughness of 1 nm or less.

  It is preferable that the surface of the SiC epitaxial layer does not have a polishing mark by mechanical or chemical polishing.

  In a preferred embodiment, the surface of the SiC epitaxial layer has a plurality of micro steps, each step including a plane composed of (0001) planes, and the step height is 1 nm or less.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes (a) a step of preparing an SiC bulk substrate having an SiC epitaxial layer formed on a surface thereof, and (b) hydrogenation of the SiC bulk substrate having the SiC epitaxial layer formed thereon. A step of reducing the surface roughness of the SiC epitaxial layer by heating in an atmosphere containing the same.

  The SiC bulk substrate may be a 4H-SiC substrate.

  The SiC bulk substrate may have an off-angle greater than 3 ° and less than or equal to 5 °.

  In a preferred embodiment, the step (b) is performed at a pressure of 1 kPa to 10 kPa.

  In a preferred embodiment, the step (b) includes a step of heating the SiC bulk substrate to a temperature of 1200 ° C. or higher and 1500 ° C. or lower.

  The step (b) may be performed in an atmosphere containing hydrogen and a rare gas.

  The step (a) includes a step (a1) of growing the SiC epitaxial layer on the surface of the SiC bulk substrate, and the step (a1) and the step (b) are preferably performed in the same chamber. .

  In a preferred embodiment, after the step (b), a step of implanting impurity ions into the SiC epitaxial layer, a step of providing a cap layer made of carbon on the surface of the SiC epitaxial layer, and the cap layer are provided. And a step of performing activation annealing on the SiC epitaxial layer to activate the impurity ions implanted into the SiC epitaxial layer.

  In a preferred embodiment, the method further includes a step of implanting impurity ions into the SiC epitaxial layer between the step (a) and the step (b), wherein the step (b) includes a surface of the SiC epitaxial layer. This is a step of reducing the roughness and activating the impurity ions implanted into the SiC epitaxial layer.

  The method for manufacturing an epitaxial wafer according to the present invention includes: (a) a step of preparing a wafer-like SiC bulk substrate having a SiC epitaxial layer formed on the surface; and (b) a SiC bulk substrate having the SiC epitaxial layer formed thereon. A step of reducing the surface roughness of the SiC epitaxial layer by heating in an atmosphere containing hydrogen.

  According to the present invention, in a silicon carbide semiconductor device using a 4H—SiC substrate, the productivity is improved by suppressing the off-angle of the 4H—SiC substrate, and the deterioration of device characteristics due to step bunching occurring on the surface of the SiC epitaxial layer is suppressed it can.

  Moreover, according to the method for manufacturing a silicon carbide semiconductor element of the present invention, the surface roughness of the SiC epitaxial layer can be reduced without damaging the surface of the SiC epitaxial layer and without complicating the manufacturing process. A silicon carbide semiconductor element having high reliability and excellent element characteristics can be provided.

  In the present invention, the surface of the silicon carbide epitaxial layer on which step bunching is formed is annealed in a hydrogen atmosphere. Thereby, since the surface roughness of the silicon carbide epitaxial layer is reduced, it is possible to suppress deterioration in element characteristics due to step bunching.

  In this specification, annealing performed in a hydrogen atmosphere in order to reduce the surface roughness of the silicon carbide epitaxial layer is referred to as “hydrogen annealing” and activation for activating impurity ions implanted into the silicon carbide epitaxial layer. It is distinguished from annealing and annealing for forming an ohmic contact between the silicon carbide epitaxial layer and the conductive layer formed on the surface thereof.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. Here, a method will be described in which a SiC epitaxial layer is grown on the surface of a 4H—SiC substrate having an off angle of 4 °, and then hydrogen annealing is performed to planarize the surface of the SiC epitaxial layer.

  In the present embodiment, the formation of the SiC epitaxial layer and the hydrogen annealing for the SiC epitaxial layer are performed using the same heating furnace. The structure of the heating furnace used in this embodiment will be described with reference to FIG.

  A heating furnace 200 shown in FIG. 1 includes a reaction furnace 150 and a coil 154 for heating the reaction furnace 150. The coil 154 is provided around the reaction furnace 150 and heats the reaction furnace 150 by high frequency induction heating. A chamber 163 supported by a support shaft 153 is provided inside the reaction furnace 150. The chamber 163 is covered with a heat insulating material 162. A susceptor 152 made of carbon is disposed inside the chamber 163. A sample 151 such as a silicon carbide substrate is fixed to the chamber 163 by the susceptor 152. The chamber 163 is connected to a gas exhaust system 159 and a gas supply system 158, respectively. The gas exhaust system 159 includes an exhaust gas pipe 160 and a pressure adjustment valve 161, and exhausts the gas in the chamber 163 as necessary. The gas supply system 158 supplies an argon gas 155, a source gas 156 used for epitaxial growth of silicon carbide, an oxygen gas 157, and the like to the chamber 163 as necessary.

  Next, a method for forming the SiC epitaxial layer in the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2A, a SiC epitaxial layer 3 is grown on the surface of the SiC substrate 1. For example, a wafer-like 4H—SiC substrate (diameter: 2 inches, for example) having an off angle of 4 ° in the [11-20] (112 bar 0) direction is used as the SiC substrate 1.

A specific method for growing the SiC epitaxial layer 3 will be described. The SiC epitaxial layer 3 is formed using a heating furnace 200 shown in FIG. First, SiC substrate 1 is installed in chamber 163 of heating furnace 200 shown in FIG. Thereafter, a high frequency power of 20.0 kHz and 20 kW is applied to the induction heating coil 154 to heat the substrate 1 to, for example, 1600 ° C. by induction heating. Using a gas supply system 158, a silicon carbide source gas 156 is supplied to a chamber 163 together with a carrier gas, and a SiC epitaxial layer (thickness: 10 μm, for example) 3 is epitaxially grown on the substrate 1 by a CVD method. As the source gas 156, for example, monosilane (SiH ₄ ) and propane (C ₃ H ₈ ) are used. The carrier gas is, for example, hydrogen.

  On the surface of the SiC epitaxial layer 3 grown in this way, step bunching 2 is generated with a plane 2t substantially parallel to the (0001) plane as a terrace. As described with reference to FIGS. 10 and 11, in this embodiment, the SiC substrate 1 having a small off angle θ (θ = 4 °) is used, so that it is more than the conventional SiC substrate having an off angle of 8 °. Step bunching is likely to occur. Further, the height H of the step bunching 2 is, for example, 10 nm or more. The height H of the step bunching 2 indicates the level difference between the top and bottom of the step bunching 2 along the normal direction of the envelope surface of the substrate surface.

  FIG. 3 is a schematic enlarged cross-sectional view for explaining step bunching 2 generated on the surface of SiC epitaxial layer 3. In FIG. 3, a surface 21 represents a plane parallel to the envelope surface of the surface of the SiC substrate 1, and its normal is inclined by 4 ° (off angle θ) in the <11-20> direction from <0001>. The step bunching 2 has a terrace 2t mainly composed of a (0001) plane and a step 2d.

Next, as shown in FIG. 2B, the SiC substrate 1 on which the SiC epitaxial layer 3 is formed is annealed (hydrogen annealing) in a hydrogen atmosphere under reduced pressure. As a result, the hydrogen atoms 5 in the atmosphere react with the carbon and silicon of the SiC epitaxial layer 3, and the reaction products 7 such as SiH ₄ and CH ₄ generated by the reaction are removed from the surface of the SiC epitaxial layer 3. be able to. In this way, the surface of the SiC epitaxial layer 3 is etched by the hydrogen atoms 5.

  Hereinafter, the method and conditions for hydrogen annealing will be described in detail. The hydrogen annealing is performed in a state where the SiC substrate 1 on which the SiC epitaxial layer 3 is formed is installed in the chamber 163 of the heating furnace 200. First, the temperature of the SiC substrate 1 is lowered to 1500 ° C., and the pressure inside the chamber 163 is lowered to 10 kPa or less. Subsequently, hydrogen gas is introduced into the chamber 163 using the gas supply system 158. At this time, by adjusting conditions such as the pressure inside the chamber 163 and the temperature of the SiC substrate 1, the reaction between the hydrogen atom 5 and the silicon and carbon of the SiC epitaxial layer 3 is performed at the end of the step bunching 2 ( 9) (referred to as “kinks”). At this time, since the hydrogen moves (migrate) on the terrace and reacts with the lower kink, the hydrogen etching reaction proceeds selectively on the terrace with a long step bunching. Accordingly, as etching of the SiC epitaxial layer 3 by the hydrogen atoms 5 proceeds, as shown in FIG. 2C, the wide terrace 2t of the step bunching 2 becomes narrow, and as a result, the height H of the step bunching is reduced. be able to.

  Here, preferable conditions for hydrogen annealing will be described.

  The pressure inside the chamber 163 is preferably 1 kPa to 10 kPa, more preferably 3 kPa to 7 kPa. When annealing is performed under a pressure of less than 1 kPa, in addition to the etching reaction of the SiC epitaxial layer 3 by the hydrogen atoms 5, a sublimation reaction due to a decrease in pressure also proceeds, so the etching rate of the SiC epitaxial layer 3 is about one digit or more And the thickness of the SiC epitaxial layer 3 may decrease. On the other hand, when annealing is performed under a pressure higher than 10 kPa, the density of the hydrogen atoms 5 in the chamber 163 increases, so that the etching reaction proceeds while the shape of the step bunching 2 is maintained. There is a possibility that the height H cannot be effectively reduced.

  Further, the temperature of SiC substrate 1 during the hydrogen annealing is preferably set to 1200 ° C. or higher and 1500 ° C. or lower, and more preferably 1300 ° C. or higher and 1400 ° C. or lower. When the temperature of the SiC substrate 1 is lower than 1200 ° C., the thermal dissociation reaction of hydrogen molecules does not proceed, and the density of the hydrogen atoms 5 inside the chamber 163 decreases by about one digit or more, so that the surface of the SiC epitaxial layer 3 can be efficiently formed. It may not be possible to flatten. On the other hand, if the temperature of the SiC substrate 1 is higher than 1500 ° C., the density of the hydrogen atoms 5 becomes too high, and the etching reaction proceeds while maintaining the shape of the step bunching 2, and the height H of the step bunching 2 is increased. There is a risk that it cannot be effectively reduced. Moreover, since the etching rate of SiC epitaxial layer 3 is increased by about one digit or more, there is a possibility that the thickness of SiC epitaxial layer 3 is reduced.

  The annealing time is not particularly limited, but is set to, for example, 5 minutes or more and 60 minutes or less. If the time is longer than 60 minutes, the SiC epitaxial layer 3 becomes thin, and the breakdown voltage of the device may be reduced. On the other hand, if it is shorter than 5 minutes, the height H of the step bunching 2 may not be sufficiently reduced.

  By performing the annealing, the flatness of the surface of the SiC epitaxial layer 3 can be drastically improved as shown in FIG.

  As shown in the figure, the surface of the obtained SiC epitaxial layer 3 has minute steps (step height H: for example, 1 nm or less) due to the surface structure of the SiC substrate 1. It consists of (0001) plane. Here, “consisting of (0001) plane” is mainly composed of (0001) plane and substantially parallel to (0001) plane. For example, a minute step at atomic level in the plane You may have.

  In the method of Patent Document 1 described above, the surface of the SiC epitaxial layer is flattened by chemical or mechanical polishing, and the flattened surface has polishing marks that may cause deterioration in device characteristics. is doing. On the other hand, according to the method of the present embodiment, the surface of the planarized SiC epitaxial layer 3 does not have such a polishing mark, but also has the same crystal plane ((0001) plane). Therefore, it is possible to provide a silicon carbide semiconductor element having high reliability and excellent element characteristics.

  Further, when a 4H—SiC substrate having a small off angle (greater than 3 ° and less than 5 °) is used, the underlying surface for epitaxial growth is modified as in the methods disclosed in Patent Documents 2 to 4 described above. However, the surface roughness of the epitaxial layer cannot be reduced to 1 nm or less simply by preventing the damage caused by the activation annealing. This is because when the epitaxial layer is formed on the surface of the SiC substrate having a small off angle, the possibility that the reactive species are adsorbed on the terrace of the step increases, and a very large step bunching is formed. On the other hand, according to the method of the present embodiment, after the SiC epitaxial layer is formed, the surface is etched with hydrogen atoms. Therefore, the SiC epitaxial layer is selected by selecting the etching conditions (hydrogen annealing conditions). The surface roughness of the layer can be suppressed to 1 nm or less.

  In addition, when forming a silicon carbide semiconductor element using the SiC epitaxial layer 3 of this embodiment, if at least a part of the SiC epitaxial layer in the silicon carbide semiconductor element is a planarized surface as described above, In addition, a region having a large surface roughness may partially exist on the surface of the SiC epitaxial layer. For example, when forming a Schottky diode, if the portion of the SiC epitaxial layer that is in contact with the Schottky electrode is planarized by hydrogen annealing, it is possible to suppress deterioration in device characteristics due to surface irregularities.

  Next, since the surface morphology of the SiC epitaxial layer in this embodiment was investigated, the method and result are demonstrated.

  First, using the method described with reference to FIGS. 2A to 2D, an SiC epitaxial layer is formed on the surface of the SiC substrate, and then hydrogen annealing is performed to manufacture an epitaxial substrate according to the example. did. Further, an epitaxial substrate with a comparative example was produced in the same manner as the epitaxial substrate with the example except that hydrogen annealing was not performed on the SiC epitaxial layer.

  The surface morphology of the SiC epitaxial layer in the obtained substrates with epi of Examples and Comparative Examples was analyzed using an atomic force microscope (AFM).

  4A and 4B are diagrams showing the AFM measurement results of the epitaxial substrate according to the example, where FIG. 4A is a profile of the surface of the SiC epitaxial layer, and FIG. 4B is an AFM of the surface of the SiC epitaxial layer. It is a statue. Similarly, FIGS. 5A and 5B are diagrams showing the AFM measurement results of the epitaxial substrate of the comparative example, where FIG. 5A is the profile of the surface of the SiC epitaxial layer, and FIG. 5B is the SiC epitaxial layer. It is an AFM image of the surface. FIG. 4B and FIG. 5B show the profile of the surface of the SiC epitaxial layer in a cross section substantially perpendicular to the surface of the SiC substrate and substantially perpendicular to the step direction of the SiC substrate.

  As can be seen from FIG. 4, the SiC epitaxial layer in the example was extremely flat, and its surface roughness was about 1 nm. On the other hand, as can be seen from FIG. 5, stepped surface irregularities (step bunching) existed on the surface of the SiC epitaxial layer in the comparative example, and the surface roughness was 10 nm or more. Therefore, it was confirmed that the planarity of the surface of the SiC epitaxial layer can be significantly improved by performing the hydrogen annealing described with reference to FIGS. 2B and 2C.

  In this specification, the “surface roughness” is defined by the 10-point average roughness specified in JIS B0601-1994. The surface roughness is measured by observing a cross section with a TEM, SEM or the like with a reference length of 1 μm. However, the reference length may be increased to 10 μm when the overall surface roughness can be expressed by a wider evaluation as in step bunching. In this way, when a plurality of measurements are performed while changing the reference length, the maximum value of the measurement results is defined as the surface roughness. Further, when measuring the surface roughness of the surface having step bunching, in order to evaluate the step height H, it is preferable to select a plane substantially perpendicular to the substrate surface and substantially perpendicular to the step direction as the cross section. When measuring the surface roughness of a surface that does not have steps arranged in a specific direction, an arbitrary cross section substantially perpendicular to the substrate surface may be selected. In addition, when the area | region which measures surface roughness is smaller than the said reference length, it measures on the basis of the maximum length measurable in the area | region. Further, if possible, the surface unevenness to be measured may be directly evaluated using the AFM as in the present embodiment.

  In the present embodiment, a 4H—SiC substrate having an off angle of 4 ° is used. Alternatively, a 4H—SiC substrate having another off angle of 3 ° or more and 5 ° or less may be used. The same effect as the embodiment can be obtained.

  Even when a substrate with an off-angle less than the above range is used, the surface of the epitaxial layer can be planarized by the method of the present invention. Unevenness may remain on the surface.

  In the embodiment, when hydrogen annealing is performed, hydrogen gas is supplied to the chamber 163, but a mixed gas of a rare gas and hydrogen may be used instead. When hydrogen is diluted with a rare gas and supplied to the chamber 163, the etching rate of the SiC epitaxial layer 3 by hydrogen annealing can be controlled by adjusting the dilution ratio.

(Embodiment 2)
Hereinafter, a method for manufacturing a silicon carbide Schottky diode according to an embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 6A, an SiC epitaxial layer 33 formed on the SiC substrate 31 is formed. As the SiC substrate 31, for example, a 4H—SiC substrate having a main surface with an off angle of 4 ° from (0001) to [11-20] (112 bar 0) direction is used. The conductivity type of this SiC substrate 31 is n-type, and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . The SiC epitaxial layer 33 can be formed by a CVD method using the heating furnace 200 shown in FIG. Here, an SiC epitaxial layer (thickness: 10 μm) 33 doped with n-type impurities is grown on the main surface (silicon surface) of the SiC substrate 31. The source gas and carrier gas used for forming the SiC epitaxial layer 33 are the same as those described above with reference to FIG. However, in the present embodiment, a doping gas (N ₂ ) having a constant flow rate is mixed into the source gas. The carrier concentration of the SiC epitaxial layer 33 is controlled by the flow rate of the doping gas, and is about 5 × 10 ¹⁵ cm ⁻³ here. Further, as shown in the figure, a step bunching 35 resulting from epitaxial growth using a step flow is formed on the surface of the SiC epitaxial layer 33.

  Next, as shown in FIG. 6B, the SiC substrate 31 on which the SiC epitaxial layer 33 is formed is annealed (hydrogen annealing) in a hydrogen atmosphere under reduced pressure. The hydrogen annealing can be performed using the same furnace as that used for the epitaxial growth. After epitaxial growth, it is preferable to perform hydrogen annealing in a state where the SiC substrate 31 is installed in a chamber in a heating furnace. Conditions such as annealing temperature and pressure are the same as those described above with reference to FIG. Thereby, hydrogen atoms in the atmosphere selectively react with carbon and silicon located in the kink of the step bunching 35 of the SiC epitaxial layer 33, and the obtained reaction product 37 is removed from the surface of the SiC epitaxial layer 33. The In this way, the surface of the SiC epitaxial layer 33 is planarized.

  Thereafter, as shown in FIG. 6C, an ohmic electrode 38 is provided on the back surface (carbon surface) of the SiC substrate 31 and a Schottky electrode 39 is provided on the surface of the SiC epitaxial layer 33 using a vacuum deposition apparatus. . A Schottky barrier is formed at least at a part of the interface between the Schottky electrode 39 and the SiC epitaxial layer 33. The ohmic electrode 38 is formed by depositing nickel (Ni) on the back surface of the SiC substrate 31 and then performing annealing for obtaining an ohmic contact at a temperature of 100 ° for 3 minutes. Schottky electrode 39 is formed by depositing Ni on the surface of SiC epitaxial layer 33 and then patterning. In this way, the Schottky diode of this embodiment is obtained.

  Next, since the current-voltage characteristics of the Schottky diode of this embodiment were examined, the method and result will be described.

  The Schottky diode of the example was manufactured by the above method, and for comparison, the Schottky diode of the comparative example was subjected to the same method and conditions as the above method except that hydrogen annealing shown in FIG. 6B was not performed. Was made.

  First, the surface morphology of the SiC epitaxial layer in the Schottky diodes of Examples and Comparative Examples was analyzed by AFM using the same method as in the first embodiment. As a result, the surface roughness (step height) of the SiC epitaxial layer was 1 nm or less, and the surface roughness of the SiC epitaxial layer in the comparative example was 10 nm or more.

  Next, a reverse bias voltage was applied to the Schottky diodes of the example and the comparative example, and a voltage (reverse breakdown voltage) causing dielectric breakdown was measured. The reverse breakdown voltage of the comparative example Schottky diode was 500V. On the other hand, it was 600 V or more in the Schottky diode of the example. Therefore, it was found that the breakdown voltage characteristic of the Schottky diode of the example was 1.2 times higher than that of the Schottky diode of the comparative example.

  The reason why the breakdown voltage of the Schottky diode of the example is improved is considered to be that the leakage current due to step bunching is reduced. That is, in the Schottky diode of this example, the surface of the SiC epitaxial layer 33 is flattened, so that electric field concentration is less likely to occur and the breakdown voltage is increased.

  The conventional Schottky diode had to be formed with a guard ring structure for securing a breakdown voltage at the periphery thereof, but the Schottky diode of the example has a high breakdown voltage as described above. It was found that a high breakdown voltage (for example, 600 V) was exhibited without forming a guard ring structure.

  In the present embodiment, a Schottky diode is manufactured, but a SiC epitaxial layer 33 is formed on the surface of the SiC substrate 31 using a similar method, and then p-type and n-type doped layers are formed in the SiC epitaxial layer 33. By doing so, a pn diode can also be manufactured.

  In the Schottky diode of this embodiment, the entire surface of the SiC epitaxial layer 33 may not be substantially flat, but the surface roughness of the portion of the surface of the SiC epitaxial layer 33 in contact with the Schottky electrode is 1 nm or less. It is preferable that the high device characteristics as described above can be obtained.

(Embodiment 3)
Hereinafter, a method for manufacturing a silicon carbide MOSFET according to an embodiment of the present invention will be described with reference to the drawings.

  First, as shown in FIG. 7A, the SiC epitaxial layer 102 formed on the SiC substrate 101 is formed. As the SiC substrate 101, a 4H—SiC substrate similar to the SiC substrate 31 used in the first embodiment is used. The SiC epitaxial layer 102 has the same configuration (thickness, carrier concentration, etc.) as the SiC epitaxial layer 33 in the first embodiment, and is formed by the same method and conditions. Step bunching 103 is formed on the surface of SiC epitaxial layer 102 as shown in the figure.

  Next, as shown in FIG. 7B, the SiC substrate 101 on which the SiC epitaxial layer 102 is formed is annealed in a hydrogen atmosphere under reduced pressure. Conditions such as annealing temperature and pressure are the same as those described above with reference to FIG. As a result, hydrogen atoms in the atmosphere selectively react with carbon and silicon located in the kink of the step bunching 103 of the SiC epitaxial layer 102, and the obtained reaction product 104 is removed from the surface of the SiC epitaxial layer 102. The In this way, the surface of SiC epitaxial layer 102 is planarized.

  Thereafter, as shown in FIG. 7C, a first impurity ion implantation layer (thickness: for example, 0.5 μm to 1 μm) 105 ′ to be a well region is formed in a selected region of the SiC epitaxial layer 102. To do.

Specifically, first, an implantation mask 106 made of, for example, a silicon oxide film (SiO ₂ ) is formed on the surface of the SiC epitaxial layer 102. Implant mask 106 has an opening that defines a region to be a well region in SiC epitaxial layer 102. The shape of the implantation mask 106 can be arbitrarily formed by photolithography and etching. The thickness of the implantation mask 106 is determined by its material and implantation conditions, but is preferably set sufficiently larger than the implantation range. Next, p-type impurity ions (Al ions) are implanted into the SiC epitaxial layer 102 from above the implantation mask 106. Al ion implantation is performed in multiple stages by changing the acceleration voltage. After the ion implantation, the implantation mask 106 is removed. As a result, a first impurity ion implantation layer 105 ′ is formed in a region of the SiC epitaxial layer 102 where impurity ions are implanted, and a region remaining without being implanted with impurity ions becomes an n-type drift region 107.

  Subsequently, as shown in FIG. 7D, the second impurity ion implanted layer (thickness: thickness) is implanted by implanting n-type impurity ions (nitrogen ions) into the region to be the source region of the SiC epitaxial layer 102. For example, a third impurity ion implantation layer is formed by implanting p-type impurity ions (Al ions) into a region to be a contact region in the SiC epitaxial layer 102. 109 ′ (thickness: 0.3 μm to 0.5 μm, for example) is formed. These implantation layers can be formed by a method similar to the method for forming the first impurity ion implantation layer 105 'described above.

  Thereafter, as shown in FIG. 7E, a carbon film 110 is formed on the surface of the SiC epitaxial layer 102 as a surface protective film (hereinafter referred to as “cap layer”). Subsequently, activation annealing is performed on the first, second, and third impurity ion implantation layers 105 ′, 108 ′, and 109 ′ to form the p-type well region 105, the source region 108, and the contact region 109, respectively. To do.

Carbon film 110 can be formed by graphitizing the surface of SiC epitaxial layer 102 using heating furnace 200 shown in FIG. Specifically, first, SiC substrate 101 on which SiC epitaxial layer 102 is formed is placed in chamber 163 of heating furnace 200 shown in FIG. Next, the SiC substrate 101 is heated so that the degree of vacuum of the chamber is about 10 ⁻⁴ Pa and the substrate temperature is 1400 ° C. The heating time is 60 minutes. Thereby, Si is sublimated from the surface of the SiC epitaxial layer 102 (graphitization), and the carbon film 110 having a thickness of about 200 nm is obtained.

After forming the carbon film 110, activation annealing is preferably performed while the SiC substrate 101 is placed in the chamber 163 of the heating furnace 200 shown in FIG. The activation annealing was performed, for example, in an argon gas atmosphere by heating the substrate temperature to 1750 ° C. for 30 minutes. The pressure inside the chamber 163 during the activation annealing was fixed at 91 kPa. The carrier concentration of the obtained p-type well region 105 is 1 × 10 ¹⁷ cm ⁻³ , the carrier concentration of the n-type source region 108 is 1 × 10 ¹⁹ cm ⁻³ , and the carrier concentration of the p-type contact region 109 is 1 × 10 ²⁰ cm ⁻³ .

  After the activation annealing, the carbon film 110 is removed from the surface of the SiC epitaxial layer 102. For example, it is preferable to remove the carbon film 110 by thermally oxidizing the SiC substrate 101 in the chamber 163 of the heating furnace 200.

  Subsequently, as shown in FIG. 7F, a gate insulating film 111, a source electrode 112, a gate electrode 113, and a drain electrode 114 are formed.

  Gate insulating film 111 is formed by thermally oxidizing the surface of SiC epitaxial layer 102 at a temperature of 1100 °. The thickness of the gate insulating film 111 is, for example, 30 nm.

  The source electrode 112 and the drain electrode 114 can be formed as follows. First, a Ni film is deposited so as to be in contact with the source region 108 and the contact region 109 using an electron beam (EB) vapor deposition apparatus. A Ni film is also deposited on the back surface of the SiC substrate 101. Subsequently, these Ni films are heated at a temperature of 1000 ° C. using a heating furnace. Thus, source electrode 112 that is ohmic-bonded to source region 108 and contact region 109 and drain electrode 114 that is ohmic-bonded to the back surface of SiC substrate 101 are formed.

  The gate electrode 113 is formed by evaporating aluminum on the gate insulating film 111. In this way, a MOSFET is obtained.

  In the MOSFET obtained by the above method, the surface unevenness of the SiC epitaxial layer 102 is significantly reduced as compared with the conventional case, so that the channel mobility can be increased and the on-resistance can be reduced. Also, by thermally oxidizing the surface of the planarized SiC epitaxial layer 102, a gate oxide film having a small variation in thickness can be formed, so that the device characteristics deteriorate due to the variation in the thickness of the gate insulating film (the breakdown voltage of the MOSFET). Decrease, yield decrease, etc.).

  The advantages of the above method will be described in more detail. In a conventional MOSFET manufacturing method, activation annealing for activating impurity ions implanted into the SiC epitaxial layer 102 is performed in a state where step bunching is formed on the surface of the SiC epitaxial layer 102. At this time, atoms (Si, C) in the SiC epitaxial layer are sublimated, and a plurality of bunching steps are overlapped to form a step (macro step) larger than the bunching step. Therefore, the activation annealing increases the surface roughness of the SiC epitaxial layer to, for example, 10 nm or more.

  In contrast, in the above method, the step bunching 103 of the SiC epitaxial layer 102 is reduced by hydrogen annealing before the activation annealing. Further, since the activation annealing is performed with the carbon film (cap layer) formed on the surface of the SiC epitaxial layer 102, the activation annealing is performed while maintaining the surface of the SiC epitaxial layer 102 flattened by hydrogen annealing. It can be carried out. Accordingly, not only the step bunching 103 on the surface of the SiC epitaxial layer 102 but also the surface roughness due to the activation annealing can be suppressed, so that the deterioration of element characteristics due to the surface irregularities of the SiC epitaxial layer 102 can be greatly improved.

  The carbon film 110 for surface protection may be formed after the hydrogen annealing and before forming the impurity ion layers 105 ', 108', and 109 '. In the above method, the carbon film 110 is formed by utilizing graphitization of the SiC epitaxial layer 102. Alternatively, for example, a carbon film such as a DLC film may be formed by a known deposition method.

  When the surface morphology of the SiC epitaxial layer 102 in this embodiment was analyzed by AFM by the same method as in Embodiment 1, it was confirmed that the surface roughness (step height) of the SiC epitaxial layer 102 was 1 nm or less. . In this embodiment, since the carbon film 110 is formed on the surface of the SiC epitaxial layer 102 before the activation annealing and the activation annealing is performed in this state, the surface roughness of the SiC epitaxial layer 102 after the activation annealing is performed. The surface roughness was substantially the same as the surface roughness (1 nm or less) after planarization by hydrogen annealing.

  Next, since the current-voltage characteristics of the MOSFET of this embodiment were examined, the method and result will be described.

  First, the MOSFET of the example was manufactured using the above method. For comparison, a comparative MOSFET was fabricated using the same method and conditions as the MOSFET fabrication method of Example except that hydrogen annealing shown in FIG. 7B was not performed. The surface roughness of the SiC epitaxial layer before activation annealing and after activation annealing in the comparative example was both about 10 nm.

  When the current-voltage characteristics of the MOSFET of the example and the comparative example were measured, it was found that the drain current of the MOSFET of the example was twice or more larger than the drain current of the MOSFET of the comparative example. This is considered to be due to the following reasons.

  In the MOSFET of the comparative example, since the surface roughness of the SiC epitaxial layer is large, the carrier mobility in the vicinity of the surface is low, and the drain current hardly flows. On the other hand, in the MOSFET of the embodiment, since the surface roughness of the SiC epitaxial layer is as small as 1 nm or less, the region where the channel layer is formed in the SiC epitaxial layer (the surface layer of the p-type well region under the gate electrode) Reduction in carrier mobility can be suppressed. Therefore, a drain current having a higher current density can be passed through the channel layer.

  Subsequently, when the threshold voltages of the MOSFETs of the example and the comparative example were measured, the threshold values of the MOSFETs of the comparative example varied in the range of 2 to 10 V. It was confirmed that the voltage was stable at 3 to 3.5V. This is considered to be due to the following reasons.

  In the MOSFET of the comparative example, since the surface of the SiC epitaxial layer is rough at the MOS interface, the threshold voltage varies. On the other hand, in the MOSFET of the embodiment, the surface of the SiC epitaxial layer is flattened at the MOS interface and the facet surface of (0001) is formed, so that a channel layer having a uniform thickness is formed. And a stable threshold is obtained.

  As is apparent from the above measurement results, when a MOSFET is manufactured using the SiC epitaxial layer (surface roughness: 1 nm or less) 102 whose surface characteristics are improved by hydrogen annealing, carrier scattering is prevented from occurring at the MOS interface. And the interface state density can be reduced. Accordingly, channel mobility can be increased and a drain current having a high current density can be supplied. Moreover, since the variation in the electrical characteristics due to the surface unevenness of the SiC epitaxial layer can be suppressed, the reliability can be improved.

  In the MOSFET of the present embodiment, the surface roughness of the entire surface of the SiC epitaxial layer 102 is reduced to 1 nm or less. However, the surface roughness of at least a portion of the surface of the SiC epitaxial layer 102 that is in contact with the gate insulating film 111. If the thickness is reduced to 1 nm or less, the above-described effects can be obtained.

  The method for manufacturing the MOSFET of the present embodiment is not limited to the method described above with reference to FIGS. For example, before the impurity ions are implanted into the SiC epitaxial layer 102, hydrogen annealing is performed on the SiC epitaxial layer 102 to planarize the surface, but after the impurity ion layers 105 ′, 108 ′, and 109 ′ are formed. Hydrogen annealing can also be performed. At this time, hydrogen annealing for planarizing the surface of the SiC epitaxial layer 102 and activation annealing for the impurity ion layers 105 ′, 108 ′, and 109 ′ are performed in the same process using the same heating furnace. It is advantageous.

  Hereinafter, an example of a MOSFET manufacturing method in the case where hydrogen annealing and activation annealing are performed simultaneously will be described with reference to FIGS. For simplicity, the same components as those in FIGS. 7A to 7F are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 8A, a SiC epitaxial layer 102 is formed on a SiC substrate 101. Step bunching 103 is formed on the surface of SiC epitaxial layer 102.

  Next, as shown in FIG. 8B, first, second and third impurity ion layers 105 ′, 108 ′ and 109 ′ are formed in the SiC epitaxial layer 102. The method for forming these impurity ion layers is the same as that described above with reference to FIGS. 7C and 7D. However, due to the surface shape of the SiC epitaxial layer 102 (step bunching 103), irregularities may occur on the lower surfaces of the impurity ion layers 105 ', 108', and 109 '.

  Thereafter, as shown in FIG. 8C, the impurity ions in the impurity ion layers 105 ′, 108 ′, and 109 ′ are activated, and annealing for flattening the surface of the SiC epitaxial layer 102 is performed.

  Specifically, SiC substrate 101 on which impurity ion layers 105 ′, 108 ′, and 109 ′ are formed is installed in chamber 163 of heating furnace 200 shown in FIG. 1, and the pressure inside chamber 163 is kept at 10 kPa or less. While the hydrogen gas is supplied to the chamber 163, heating is performed so that the substrate temperature becomes 1500 ° C. As a result, the impurity ions are activated, and at the same time, the surface of the SiC epitaxial layer 102 is etched by hydrogen atoms to reduce the step bunching 103, and the surface roughness of the SiC epitaxial layer 102 due to the activation annealing is also reduced. Can be suppressed.

  Thereafter, although not shown, the gate insulating film 111, the source electrode 112, the gate electrode 113, and the drain electrode 114 are formed as described above with reference to FIG.

  According to the method shown in FIG. 8, a MOSFET in which the surface unevenness of the SiC epitaxial layer 102 is significantly reduced can be manufactured by a simpler process without forming a carbon film for surface protection.

  Although the inversion type MOSFET has been described in the present embodiment, the same effect can be obtained even if the present invention is applied to a storage type MOSFET. Further, the present invention can be applied not only to MOSFETs but also to silicon carbide semiconductor elements such as MESFETs having a Schottky barrier on the substrate surface, and the same effects as those described in the present embodiment can be obtained.

  In the above-described embodiments, SiC is epitaxially grown on the silicon surface of the 4H—SiC substrate, but may be grown on the carbon surface. However, when epitaxial growth is performed on the silicon surface, the surface roughness of the epitaxial layer becomes larger than when epitaxial growth is performed on the carbon surface, so that the merit of performing hydrogen annealing is particularly great.

  The present invention can be widely applied to silicon carbide semiconductor elements using an SiC substrate having an off angle. In the embodiment described above, a 4H—SiC substrate having an off angle of 4 ° is used, but the off angle of the SiC substrate used in the present invention is not limited to this. For example, the epitaxial layer formed on the surface of the SiC substrate having an off angle of greater than 0 ° and less than or equal to 10 ° may be planarized by performing hydrogen annealing. As described above, if the off angle is larger than 3 ° and not larger than 5 °, it is advantageous because the surface irregularities of the epitaxial layer can be more effectively reduced.

  Furthermore, the polytype of the SiC substrate is not limited to 4H—SiC, and may be other polytypes (for example, 6H—SiC). However, when the present invention is applied to a silicon carbide semiconductor element using a 4H—SiC substrate. Are particularly advantageous. On the surface of the 4H-SiC substrate, step bunching having a larger terrace width and a larger step height is easier to form than the surface of the 6H-SiC substrate. Therefore, by applying the hydrogen annealing of the present invention to reduce the step bunching, the device This is because the characteristics can be greatly improved.

  According to the present invention, the surface roughness of the silicon carbide epitaxial layer can be reduced without complicating the manufacturing process. Therefore, a highly reliable silicon carbide semiconductor element having excellent electrical characteristics can be provided.

  The present invention can be widely applied to various silicon carbide semiconductor elements including SiC wafers with epi, MOSFETs, MESFETs, Schottky diodes, and the like. The silicon carbide semiconductor element of the present invention can be used in low-loss power devices that can be used in various electric power / electric equipment such as home appliances, automobiles, electric power transportation / conversion devices, and industrial equipment.

It is the schematic which shows the structure of the heating furnace used by embodiment by this invention. (A)-(d) is process sectional drawing for demonstrating the formation method of the SiC epitaxial layer of 1st Embodiment by this invention. It is a typical expanded sectional view for demonstrating the step bunching which generate | occur | produced on the surface of the SiC epitaxial layer. (A) And (b) is a figure which shows the AFM measurement result of the board | substrate with an epi of an Example, (a) is a profile of the surface of a SiC epitaxial layer, (b) is an AFM image of the surface of a SiC epitaxial layer. is there. FIGS. 5A and 5B are views showing the AFM measurement results of the substrate with epi of the comparative example, where FIG. 5A is the profile of the surface of the SiC epitaxial layer, and FIG. 5B is the AFM of the surface of the SiC epitaxial layer. It is a statue. (A)-(c) is process sectional drawing for demonstrating the method to manufacture the Schottky diode of 2nd Embodiment by this invention. (A)-(f) is process sectional drawing for demonstrating the method to manufacture MOSFET of 3rd Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the other method of manufacturing MOSFET of 3rd Embodiment by this invention. It is typical sectional drawing for demonstrating the mechanism of the step flow growth of SiC. (A)-(c) is a typical cross-sectional enlarged view for demonstrating the mechanism in which step bunching is formed in the surface of a SiC epitaxial layer. (A) And (b) is a typical expanded sectional view which shows the surface shape of the SiC substrate which has an off angle of 4 degrees, and the SiC substrate which has an off angle of 8 degrees, respectively.

Explanation of symbols

1, 31, 40, 101 Silicon carbide substrate 41 Atomic step 2, 35, 62, 103 on the surface of silicon carbide substrate Step bunching 2t Step bunching terrace 2d Step bunching step 3, 33, 42, 102 Silicon carbide epitaxial layer 5 Hydrogen Atomic 7, 37, 104 Reaction product 9 Step bunching kink 39 Schottky electrode 38 Ohmic electrode 105 ', 108', 109 'Impurity ion implantation layer 105 P-type well region 106 Implant mask 107 Drift region 108 N-type source region 109 p-type contact region 110 cap layer (carbon film)
111 Gate insulating film 112 Source electrode 114 Drain electrode 113 Gate electrode 150 Reactor 151 Sample 152 Susceptor 153 Susceptor support shaft 154 Coil 155 Argon gas 156 Silicon carbide source gas 157 Oxygen gas 158 Gas supply system 159 Gas exhaust system 160 For exhaust gas Piping 161 Pressure adjusting valve 162 Heat insulating material 163 Chamber

Claims (20)

A 4H-SiC substrate;
A SiC epitaxial layer formed on the surface of the 4H-SiC substrate,
The 4H—SiC substrate has an off angle greater than 3 ° and less than or equal to 5 °,
A silicon carbide semiconductor device, wherein at least a part of the surface of the SiC epitaxial layer has a surface roughness of 1 nm or less.   2. The silicon carbide semiconductor device according to claim 1, wherein the at least part of the surface of the SiC epitaxial layer does not have a polishing mark by mechanical or chemical polishing.   The at least part of the surface of the SiC epitaxial layer has a plurality of minute steps, and each step includes a plane composed of (0001) planes, and the height of each step is 1 nm or less. Item 3. The silicon carbide semiconductor device according to Item 1 or 2. An electrode in contact with the surface of the SiC epitaxial layer;
4. The silicon carbide semiconductor device according to claim 1, wherein at least a part of an interface between the electrode and the SiC epitaxial layer forms a Schottky barrier. 5.   The silicon carbide semiconductor device according to claim 4, wherein the surface roughness of the surface of the SiC epitaxial layer in contact with the electrode is 1 nm or less. A gate insulating film in contact with the surface of the SiC epitaxial layer;
A gate electrode provided on the gate insulating film;
A source electrode electrically connected to a portion of the SiC epitaxial layer;
The silicon carbide semiconductor element according to claim 1, further comprising a drain electrode provided on a surface facing the surface of the 4H—SiC substrate.   The silicon carbide semiconductor device according to claim 6, wherein the surface roughness of the surface of the SiC epitaxial layer in contact with the gate oxide film is 1 nm or less. A wafer-like 4H-SiC substrate;
A SiC epitaxial layer formed on the surface of the 4H-SiC substrate,
The 4H—SiC substrate has an off angle greater than 3 ° and less than or equal to 5 °,
An epitaxial wafer with a surface roughness of the SiC epitaxial layer of 1 nm or less.   The wafer with an epitaxial structure according to claim 8, wherein a surface of the SiC epitaxial layer does not have a polishing mark by mechanical or chemical polishing.   10. The surface of the SiC epitaxial layer has a plurality of minute steps, each step includes a plane composed of (0001) planes, and the step height is 1 nm or less. Epi wafer. (A) preparing a SiC bulk substrate having a SiC epitaxial layer formed on the surface;
(B) A method of manufacturing a silicon carbide semiconductor element, comprising: heating a SiC bulk substrate on which the SiC epitaxial layer is formed in an atmosphere containing hydrogen to reduce the surface roughness of the SiC epitaxial layer.   The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the SiC bulk substrate is a 4H—SiC substrate.   The method for manufacturing a silicon carbide semiconductor element according to claim 11, wherein the SiC bulk substrate has an off angle of greater than 3 ° and less than or equal to 5 °.   The method for manufacturing a silicon carbide semiconductor element according to claim 11, wherein the step (b) is performed at a pressure of 1 kPa to 10 kPa.   The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step (b) includes a step of heating the SiC bulk substrate to a temperature of 1200 ° C. or higher and 1500 ° C. or lower.   The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step (b) is performed in an atmosphere containing hydrogen and a rare gas. The step (a) includes a step (a1) of growing the SiC epitaxial layer on the surface of the SiC bulk substrate,
The method for manufacturing a silicon carbide semiconductor element according to claim 11, wherein the step (a1) and the step (b) are performed in the same chamber. After step (b)
Implanting impurity ions into the SiC epitaxial layer;
Providing a cap layer made of carbon on the surface of the SiC epitaxial layer;
Activating annealing the SiC epitaxial layer provided with the cap layer to activate the impurity ions implanted into the SiC epitaxial layer;
The method for manufacturing a silicon carbide semiconductor element according to claim 11, further comprising: Between the step (a) and the step (b),
Further comprising implanting impurity ions into the SiC epitaxial layer;
The carbonization according to any one of claims 11 to 16, wherein the step (b) is a step of reducing the surface roughness of the SiC epitaxial layer and activating the impurity ions implanted into the SiC epitaxial layer. Silicon semiconductor element. (A) preparing a wafer-like SiC bulk substrate having a SiC epitaxial layer formed on the surface;
(B) A method of manufacturing a wafer with an epi including a step of reducing the surface roughness of the SiC epitaxial layer by heating the SiC bulk substrate on which the SiC epitaxial layer is formed in an atmosphere containing hydrogen.

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