JP6035763B2 - Method for forming gate oxide film and method for manufacturing silicon carbide semiconductor device - Google Patents
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 83
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 82
- 239000004065 semiconductor Substances 0.000 title claims description 57
- 238000000034 method Methods 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
- 229910052710 silicon Inorganic materials 0.000 claims description 51
- 239000010703 silicon Substances 0.000 claims description 51
- 239000012535 impurity Substances 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 37
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 17
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims description 14
- 239000011574 phosphorus Substances 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 239000012159 carrier gas Substances 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 4
- 238000003763 carbonization Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 20
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- Formation Of Insulating Films (AREA)
Description
炭化珪素エピタキシャル半導体基板（以降炭化珪素エピ基板と略記することがある）へのゲート酸化膜の形成方法及び半導体材料として炭化珪素を用いたＭＯＳＦＥＴまたはＩＧＢＴ等の電圧駆動制御のＭＯＳ型半導体装置の製造方法に関する。 Method for forming gate oxide film on silicon carbide epitaxial semiconductor substrate (hereinafter sometimes abbreviated as silicon carbide epi substrate), and manufacture of MOS type semiconductor device of voltage drive control such as MOSFET or IGBT using silicon carbide as semiconductor material Regarding the method.
炭化珪素半導体はシリコン半導体（以降、炭化珪素をＳｉＣ、シリコンをＳｉと略記することがある）に比べ、バンドギャップが約３倍大きいため、ＳｉＣ半導体では絶縁破壊電界がＳｉ半導体に比べ一桁大きく、例えば、耐圧１０００Ｖではドリフト層厚さを１０分の１程度に薄くできる。さらに、オン抵抗は、Ｓｉ半導体と比べ、ＳｉＣ半導体の電子の移動度が低いことを考慮しても数１００分の１に低減でき、次世代の高効率・高耐圧パワーデバイスとして期待されている。 Since silicon carbide semiconductors have a band gap that is about three times larger than silicon semiconductors (hereinafter, silicon carbide may be abbreviated as SiC and silicon as Si), the breakdown electric field of SiC semiconductors is an order of magnitude larger than that of Si semiconductors. For example, at a withstand voltage of 1000 V, the drift layer thickness can be reduced to about 1/10. Furthermore, the on-resistance can be reduced to a few hundredths even considering that the electron mobility of the SiC semiconductor is lower than that of the Si semiconductor, and is expected as a next-generation high-efficiency / high-voltage power device. .
通常、ＳｉＣ半導体デバイスは、ＳｉＣ半導体基板への所要の半導体領域の形成を、シリコン半導体デバイスのようにイオン注入や熱拡散による不純物ドープが簡単にはできないので、炭化珪素エピタキシャル成長による堆積と同時の不純物ドープによる半導体領域の形成が行われる。そのようにＳｉＣ半導体基板上に半導体領域がエピタキシャル成長により堆積形成された基板を、以降、炭化珪素エピ基板（ＳｉＣエピ基板）と言うことにする。 In general, a SiC semiconductor device cannot form impurities in an SiC semiconductor substrate by impurity implantation by ion implantation or thermal diffusion as in the case of a silicon semiconductor device. A semiconductor region is formed by doping. A substrate in which a semiconductor region is deposited and formed on a SiC semiconductor substrate by epitaxial growth is hereinafter referred to as a silicon carbide epi substrate (SiC epi substrate).
さらに、ＳｉＣ半導体を基板として用いて、例えば、ＭＯＳＦＥＴを作製するためには、ゲート酸化膜の形成が欠かせない。しかも、形成されたゲート酸化膜が、電子移動度（チャネル移動度）１００ｃｍ２／Ｖｓ以上、ゲートしきい値電圧Ｖｔｈ＞５Ｖ、ゲートしきい値電圧シフト△デルタ（差分）Ｖｔｈが実質的に０Ｖ等の条件を同時に満たす良質な膜質であることが望ましい。しかし、そのような良好なゲート酸化膜を、ＳｉＣ半導体基板面に形成するのは今のところ、困難であるとされている。 Further, for example, in order to manufacture a MOSFET using an SiC semiconductor as a substrate, formation of a gate oxide film is indispensable. In addition, the formed gate oxide film has an electron mobility (channel mobility) of 100 cm 2 / Vs or more, a gate threshold voltage Vth> 5 V, and a gate threshold voltage shift Δdelta (difference) Vth is substantially 0 V. It is desirable for the film quality to satisfy the above conditions at the same time. However, at present, it is considered difficult to form such a good gate oxide film on the surface of the SiC semiconductor substrate.
ＳｉＣエピ基板上に、前記ゲート酸化膜を形成するためには、Ｓｉ半導体基板の場合と同様にドライ酸化あるいはウエット酸化等の酸化性雰囲気中で高温の熱処理をすることにより形成される。しかし、そのようにして形成されたゲート酸化膜とＳｉＣ半導体基板の界面は炭化珪素由来の残留炭素等の影響で、ゲート特性関連で様々な問題が生じ易いことが知られている。例えば、界面準位密度が高くなってチャネル移動度の低下、しきい値電圧のシフト等の問題が生じる。詳細には、ドライ酸化の場合、Ｓｉ半導体基板面では６００ｃｍ２／Ｖｓ程度の高いバルク電子移動度が得られるのに対し、ＳｉＣ半導体基板面では通常、１０ｃｍ２／Ｖｓ程度と低い電子移動度（以降単に移動度）しか得られない。 In order to form the gate oxide film on the SiC epi substrate, it is formed by performing a high-temperature heat treatment in an oxidizing atmosphere such as dry oxidation or wet oxidation as in the case of the Si semiconductor substrate. However, it is known that the interface between the gate oxide film thus formed and the SiC semiconductor substrate is susceptible to various problems related to gate characteristics due to the influence of residual carbon derived from silicon carbide. For example, the interface state density increases and problems such as a decrease in channel mobility and a shift in threshold voltage occur. Specifically, in the case of dry oxidation, a high bulk electron mobility of about 600 cm 2 / Vs is obtained on the surface of the Si semiconductor substrate, whereas an electron mobility of about 10 cm 2 / Vs is usually low on the surface of the SiC semiconductor substrate ( Thereafter, only mobility) can be obtained.
このような低移動度を改善するために、従来でも、窒素等のドーパントをチャネル面（ゲート酸化膜に接するＳｉＣ基板面）に注入する埋め込みチャネル方法、Ｃ面を使用する方法あるいはシリコンゲート酸化膜形成後に水素アニール等の還元熱処理を加える方法等の処理を加えることにより、チャネル面の移動度を１００ｃｍ２／Ｖｓ程度に向上させる方法等が知られている。 In order to improve such low mobility, a buried channel method in which a dopant such as nitrogen is implanted into the channel surface (SiC substrate surface in contact with the gate oxide film), a method using the C surface, or a silicon gate oxide film has been conventionally used. A method of improving the mobility of the channel surface to about 100 cm 2 / Vs by adding a treatment such as a method of applying a reduction heat treatment such as hydrogen annealing after the formation is known.
またさらに、ＳｉＣ半導体基板は結晶面により酸化速度が異なるため、ＳｉＣ半導体基板上にトレンチＭＯＳＦＥＴのゲート酸化膜を形成する場合など、異なる結晶面が同時に露出する面上には、均一な膜厚のゲート酸化膜を形成することが困難という問題もある。 Furthermore, since the oxidation rate of the SiC semiconductor substrate varies depending on the crystal plane, a uniform film thickness is formed on the surface where the different crystal planes are exposed at the same time, such as when a gate oxide film of a trench MOSFET is formed on the SiC semiconductor substrate. There is also a problem that it is difficult to form a gate oxide film.
このような問題にかかる公知文献としては、炭化珪素基板の表面を水素雰囲気中で還元熱処理して炭素を除去する方法（特許文献１）および通常の熱酸化法でゲート酸化膜を形成するのではなく、炭化珪素基板上に一旦シリコン膜を堆積し、このシリコン膜を熱酸化してゲート酸化膜とする技術などが知られている（特許文献１、２）。 As publicly known literature concerning such problems, there is a method of removing carbon by reducing heat treatment of the surface of a silicon carbide substrate in a hydrogen atmosphere (Patent Literature 1) and a method of forming a gate oxide film by a normal thermal oxidation method. There is also known a technique in which a silicon film is once deposited on a silicon carbide substrate, and the silicon film is thermally oxidized to form a gate oxide film (Patent Documents 1 and 2).
しかしながら、前述の特許文献１、２に記載の方法では、いずれも、電子の移動度は向上するが、しきい値電圧の低下およびしきい値電圧シフトの問題は未解決のまま残り、すべてを満足する界面制御方法であるとは言えない。 However, in both of the methods described in Patent Documents 1 and 2, the mobility of electrons is improved, but the problems of threshold voltage reduction and threshold voltage shift remain unsolved. It cannot be said that it is a satisfactory interface control method.
本発明はこれらの点を踏まえてなされたものである。本発明の目的は前述したゲート酸化膜／炭化珪素半導体基板の界面に特有の高い界面準位密度を低減し、高チャネル移動度を得ることができ、しきい値電圧の低下およびしきい値電圧シフトについても抑えることのできるゲート酸化膜の形成方法を提供することである。また、前記ゲート酸化膜の形成方法により作製されるゲート酸化膜を有する炭化珪素半導体装置の製造方法を提供することも本発明の目的とする。 The present invention has been made in view of these points. The object of the present invention is to reduce the high interface state density peculiar to the gate oxide film / silicon carbide semiconductor substrate interface described above, to obtain a high channel mobility, and to reduce the threshold voltage and the threshold voltage. It is an object of the present invention to provide a method for forming a gate oxide film that can suppress shift. Another object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device having a gate oxide film manufactured by the method for forming a gate oxide film.
本発明は前記発明の目的を達成するために、炭化珪素エピタキシャル半導体基板上に多結晶膜またはアモルファス膜もしくは両方の混在膜のいずれかであるシリコン膜の成膜と同時に窒素、リンのいずれかの不純物をドープし該シリコン膜中の不純物濃度が１×１０ １８ ａｔｏｍｓ／ｃｍ ３ 〜１×１０ ２１ ａｔｏｍｓ／ｃｍ ３ とする工程と、該シリコン膜を熱処理して不純物がドープされたシリコン酸化膜を形成する工程と、前記不純物がドープされたシリコン酸化膜の形成後、ノンドープのシリコン酸化膜を成膜し、前記不純物がドープされたシリコン酸化膜上にノンドープのシリコン酸化膜を加え、該不純物がドープされたシリコン酸化膜とノンドープのシリコン酸化膜をゲート酸化膜とするシリコンゲート酸化膜の形成方法とする。前記シリコン膜の不純物の濃度分布が炭化珪素エピタキシャル半導体基板との界面側で高く、シリコン膜の表面側で低い濃度勾配とすることが望ましい。また、前記シリコン膜の膜厚を１〜５nmとすることが望ましい。さらに、前記熱処理の雰囲気ガスとしてアルゴンをキャリアガスとし、酸素を混合したガスを使用することもできる。さらに、前記熱処理の雰囲気ガスとしてアルゴンをキャリアガスとし、酸素に窒素または水素の少なくとも１つを混合したガスを使用することもできる。さらに、前記前記不純物がドープされたシリコン酸化膜とその上のノンドープのシリコン酸化膜をアルゴンをキャリアガスとして酸素に水素または窒素の少なくとも１つを混合した雰囲気ガス中での熱処理を行うことが好適である
また、前記本発明の目的は、面方位が（０００１）面、（０００−１）面、（１１−２０）面、（１−１００）面のいずれかの面である炭化珪素エピタキシャル半導体基板面に多結晶膜またはアモルファス膜もしくは両方の混在膜のいずれかであるシリコン膜の成膜と同時に窒素、リンのいずれかの不純物をドープする工程と、該シリコン膜を熱処理して不純物がドープされたシリコン酸化膜を形成する工程と、不純物がドープされたシリコン酸化膜上にノンドープのシリコン酸化膜を堆積し熱処理する工程とを有する炭化珪素半導体装置の製造方法とすることによって達成される。前記シリコン膜の成膜と同時に不純物をドープする工程で、炭化珪素エピタキシャル半導体基板上に設けられたトレンチの内面のゲート酸化膜形成領域に成膜することが望ましい。
In order to achieve the object of the present invention , any one of nitrogen and phosphorus is formed simultaneously with the formation of a silicon film which is either a polycrystalline film or an amorphous film or a mixed film of both on a silicon carbide epitaxial semiconductor substrate . A step of doping impurities to have an impurity concentration in the silicon film of 1 × 10 18 atoms / cm 3 to 1 × 10 21 atoms / cm 3; and a silicon oxide film doped with impurities by heat-treating the silicon film And forming a silicon oxide film doped with the impurity, forming a non-doped silicon oxide film, adding a non-doped silicon oxide film on the silicon oxide film doped with the impurity , and the doped silicon oxide film and a non-doped silicon oxide film with a method of forming a silicon gate oxide film and gate oxide film Concentration distribution of the impurity of the previous SL silicon film is high at the interface with the silicon carbide epitaxial semiconductor substrate, it is preferable that the low concentration gradient in the surface of the silicon film. Further, it is desirable that the thickness of the silicon film is 1 to 5 nm. Furthermore, a gas in which argon is used as a carrier gas and oxygen is mixed can be used as the atmosphere gas for the heat treatment. Further, as the atmosphere gas for the heat treatment, a gas in which argon is used as a carrier gas and oxygen is mixed with at least one of nitrogen or hydrogen can be used. Et al is, by performing the heat treatment in the said impurity silicon oxide film which is doped with atmospheric gas a non-doped silicon oxide film thereon were mixed oxygen least one of hydrogen or nitrogen as a carrier gas of argon Further, the object of the present invention is to provide silicon carbide whose plane orientation is any one of the (0001) plane, the (000-1) plane, the (11-20) plane, and the (1-100) plane. A step of doping a silicon film, which is either a polycrystalline film or an amorphous film or a mixed film of both, on the epitaxial semiconductor substrate surface, and simultaneously doping either nitrogen or phosphorus , and heat-treating the silicon film for impurities Forming a silicon oxide film doped with impurity, and depositing a non-doped silicon oxide film on the silicon oxide film doped with impurities and performing a heat treatment. This is achieved by providing a method for manufacturing a silicon carbide semiconductor device. It is desirable to form a film in the gate oxide film formation region on the inner surface of the trench provided on the silicon carbide epitaxial semiconductor substrate in the step of doping impurities simultaneously with the formation of the silicon film.
本発明によれば、ゲート酸化膜／炭化珪素半導体基板の界面に特有の高い界面準位密度を低減させ、高チャネル移動度を得ることができ、しきい値電圧の低下およびしきい値電圧シフトについても抑えることのできるゲート酸化膜の形成方法を提供することができる。また、前記ゲート酸化膜の形成方法により作製されるゲート酸化膜を有する炭化珪素半導体装置の製造方法を提供することもできる。 According to the present invention, a high interface state density peculiar to the interface of the gate oxide film / silicon carbide semiconductor substrate can be reduced, high channel mobility can be obtained, threshold voltage drop and threshold voltage shift can be achieved. It is possible to provide a method for forming a gate oxide film that can suppress the above-described problem. In addition, a method for manufacturing a silicon carbide semiconductor device having a gate oxide film manufactured by the method for forming a gate oxide film can be provided.
以下、本発明のゲート酸化膜の形成方法およびこの形成方法により作製されるゲート酸化膜を有する炭化珪素半導体装置の製造方法の実施例について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。 Hereinafter, embodiments of a method for forming a gate oxide film of the present invention and a method for manufacturing a silicon carbide semiconductor device having a gate oxide film produced by the method will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
図１は、本発明の実施例１にかかるゲート酸化膜の形成工程を説明するためのＳｉＣエピ基板の断面図である。図１（ａ）はＭＯＳ型半導体基板の表面側（図面の上側）に、前工程で形成された所要の半導体領域（図示せず）を備えるＳｉＣエピ基板１の断面図を示す。ＳｉＣエピ基板１は例えば、ＳｉＣ半導体基板上に順に積層される高抵抗のｎ−ドリフト層（図示せず）となるＳｉＣエピタキシャル層とｐベース層（図示せず）となるＳｉＣエピタキシャル層とｎ＋ソース層（図示せず）となるＳｉＣエピタキシャル層を備える基板である。 FIG. 1 is a cross-sectional view of a SiC epi substrate for explaining a gate oxide film forming process according to Embodiment 1 of the present invention. FIG. 1A is a cross-sectional view of a SiC epi substrate 1 having a required semiconductor region (not shown) formed in a previous process on the surface side (upper side of the drawing) of a MOS type semiconductor substrate. The SiC epi substrate 1 includes, for example, a SiC epitaxial layer that becomes a high-resistance n − drift layer (not shown) and a SiC epitaxial layer that becomes a p base layer (not shown) and n + that are sequentially stacked on the SiC semiconductor substrate. It is a board | substrate provided with the SiC epitaxial layer used as a source layer (not shown).
このＳｉＣエピ基板１の表面は、直前の前処理として有機洗浄、ＲＣＡ洗浄および希ＨＦ溶液による自然酸化膜の除去が行われた状態である。次に、図１（ｂ）に示すように、ＳｉＣエピ基板１の表面にシリコン膜２を厚さ２５ｎｍ程度堆積させる。このシリコン膜２はシランガスを圧力２５〜１３０Ｐａで導入し、６００℃〜７００℃（今回の実施例では６５０℃）の温度で堆積し成膜させることにより得られる。しかし、このシリコン膜２はすべて多結晶シリコンでなく、アモルファスシリコンが混在していてもよいし、アモルファスシリコン、多結晶シリコンオンリーでもよい。本発明ではこの時同時にシリコン膜２中に不純物ドーパントとしてリンを不純物濃度１×１０１８ａｔｏｍｓ／ｃｍ３〜１×１０２１ａｔｏｍｓ／ｃｍ３の濃度分布となるようにドープさせる。この点が本発明の特徴とするところであり、最も重要なところである。このように不純物をドープさせながらシリコン膜２を成膜することにより、イオン注入などによる成膜後に不純物をドープした膜に比べ、面荒れを抑制でき、良質なシリコン膜を形成することができる。その結果、酸化後に形成される不純物がドープされたシリコン酸化膜の膜質も界面準位密度の低い良質な酸化膜になり、ゲート酸化膜とした場合、高いチャネル移動度が得られる。さらに、シリコン膜２の成膜時の不純物ドープの際に、ＳｉＣエピ基板１との界面付近は１×１０２１ａｔｏｍｓ／ｃｍ３台の高い不純物濃度とし、シリコン膜２の最表面に向かうほど不純物濃度が低くなるよう濃度勾配を持たせる不純物濃度分布にすることが望ましい。 The surface of the SiC epi substrate 1 is in a state where organic cleaning, RCA cleaning, and removal of the natural oxide film by dilute HF solution are performed as the immediately preceding pretreatment. Next, as shown in FIG. 1B, a silicon film 2 is deposited on the surface of the SiC epitaxial substrate 1 to a thickness of about 25 nm. The silicon film 2 is obtained by introducing silane gas at a pressure of 25 to 130 Pa, depositing it at a temperature of 600 ° C. to 700 ° C. (650 ° C. in this embodiment), and forming it. However, all of the silicon film 2 is not polycrystalline silicon, and amorphous silicon may be mixed, or amorphous silicon or polycrystalline silicon only may be used. In the present invention, at the same time, the silicon film 2 is doped with phosphorus as an impurity dopant so as to have a concentration distribution of an impurity concentration of 1 × 10 18 atoms / cm 3 to 1 × 10 21 atoms / cm 3 . This is a feature of the present invention and is the most important point. By forming the silicon film 2 while doping impurities in this way, surface roughness can be suppressed and a high-quality silicon film can be formed compared to a film doped with impurities after film formation by ion implantation or the like. As a result, the quality of the silicon oxide film doped with impurities formed after oxidation also becomes a high-quality oxide film having a low interface state density, and high channel mobility can be obtained when the gate oxide film is used. Further, when doping the impurities when forming the silicon film 2, the vicinity of the interface with the SiC epitaxial substrate 1 has a high impurity concentration of about 1 × 10 21 atoms / cm 3 , and the impurity concentration increases toward the outermost surface of the silicon film 2. It is desirable that the impurity concentration distribution has a concentration gradient so that the concentration is lowered.
不純物がドープされたシリコン膜２の堆積後、酸化雰囲気中で熱酸化処理を行うことにより、図１（ｃ）に示すように、シリコン膜２はすべて酸化されてシリコン酸化膜３になる。この結果、ＳｉＣエピ基板１上にリンがドープされたシリコン酸化膜３が形成される。このときの熱酸化処理はキャリアガスをアルゴンとする酸素または酸素に窒素または水素の少なくとも１つを混合したガスの雰囲気中とし、処理温度は８００℃〜１２００℃（今回の実施例では８００℃）で行うとよい。処理温度はＳｉＣエピ基板１の酸化がなるべく進まない低温の８００℃程度で行うことが好ましい。この熱酸化処理により厚さ２５ｎｍのシリコン膜２は厚さ約５０ｎｍとなりゲート酸化膜３として必要な膜厚を有する。ゲート酸化膜３は、その上に形成される多結晶シリコンのゲート電極の形状に合わせてソース電極の基板との接続箇所等不要な部分が除去され、パターニングがされる。 After the silicon film 2 doped with impurities is deposited, a thermal oxidation process is performed in an oxidizing atmosphere, whereby the silicon film 2 is entirely oxidized to form a silicon oxide film 3 as shown in FIG. As a result, a silicon oxide film 3 doped with phosphorus is formed on the SiC epitaxial substrate 1. At this time, the thermal oxidation treatment is performed in an atmosphere of oxygen having a carrier gas of argon or a gas in which at least one of nitrogen and hydrogen is mixed with oxygen, and the treatment temperature is 800 ° C. to 1200 ° C. (800 ° C. in this embodiment). It is good to do. The processing temperature is preferably about 800 ° C., which is a low temperature at which the SiC epi substrate 1 is not oxidized as much as possible. By this thermal oxidation treatment, the silicon film 2 having a thickness of 25 nm has a thickness of about 50 nm and has a necessary thickness as the gate oxide film 3. The gate oxide film 3 is patterned by removing unnecessary portions such as a connection portion of the source electrode to the substrate in accordance with the shape of the polycrystalline silicon gate electrode formed thereon.
前述のゲート酸化膜３を形成する方法は、特には、図２に示すように、表面にトレンチ８を有するＳｉＣエピ基板４のトレンチ８の側壁に前述の方法でリンがドープされたシリコン膜５を堆積させ、熱酸化処理により、膜厚の均一なゲート酸化膜６を形成する場合に適している。 As shown in FIG. 2, the method for forming the above-described gate oxide film 3 is, in particular, a silicon film 5 in which phosphorus is doped on the side walls of the trench 8 of the SiC epitaxial substrate 4 having the trench 8 on the surface by the above-described method. Is suitable for forming a gate oxide film 6 having a uniform thickness by thermal oxidation.
リンがドープされたシリコン膜５を表面に有するＳｉＣエピ基板４を熱酸化してゲート酸化膜６とする場合、従来の方法ではゲート酸化膜の界面準位密度が１０１２ａｔｏｍｓ／ｃｍ３台だったのに対し、実施例１の形成方法では一桁少ない１０１１ａｔｏｍｓ／ｃｍ３台まで減少させることができる。さらに、前述の特許文献１、２に記載されている改良されたゲート酸化膜では達成できなかったチャネルの移動度が約８０ｃｍ２／Ｖｓ、しきい値電圧Ｖｔｈが約２Ｖ、しきい値電圧のシフト△デルタ（差分）Ｖｔｈがほぼ０に近い値を示すことも分かった。すなわち、実施例１によればゲート酸化膜３、６中の界面準位密度を低下させるだけでなく、高いしきい値電圧およびしきい値電圧のシフトが小さい高チャネル移動度のゲート酸化膜３、６が得られるのである。 When the SiC epitaxial substrate 4 having the silicon film 5 doped with phosphorus on the surface is thermally oxidized to form the gate oxide film 6, the interface state density of the gate oxide film is 10 12 atoms / cm 3 in the conventional method. On the other hand, in the forming method of Example 1, it can be reduced to 10 11 atoms / cm 3, which is an order of magnitude less. Further, the mobility of the channel which cannot be achieved by the improved gate oxide film described in Patent Documents 1 and 2 is about 80 cm 2 / Vs, the threshold voltage Vth is about 2 V, and the threshold voltage It was also found that the shift Δdelta (difference) Vth showed a value almost close to zero. That is, according to the first embodiment, not only the interface state density in the gate oxide films 3 and 6 is decreased, but also the gate oxide film 3 having a high threshold voltage and a high channel mobility with a small threshold voltage shift. 6 is obtained.
この高チャネル移動度のゲート酸化膜を有するＭＯＳ型炭化珪素半導体装置の製造方法について、図５を参照して以下説明する。図５に示す基板中に示される半導体領域は模式化されており、各領域の厚さおよび各領域の厚さの比を表すようには描かれていない。高濃度ｎ型４Ｈ−ＳｉＣ半導体基板９上に、ＣＶＤ成膜装置により、膜厚４．９μｍ、ｎ型不純物濃度１×１０１６ａｔｏｍｓ／ｃｍ３のｎ−ドリフト層１０、膜厚１．０μｍ、ｐ型不純物濃度１×１０１７ａｔｏｍｓ／ｃｍ３のｐ型ベース層１１、膜厚０．５μｍ、ｎ型不純物濃度１×１０１９ａｔｏｍｓ／ｃｍ３のｎ型ソース層１２をそれぞれＳｉＣエピタキシャル成長させてＳｉＣエピ基板１を形成する（図５（ａ））。ｎ型ソース層１２は、不純物のイオン注入で形成してもよい。このＳｉＣエピ基板１の表面から深さ２．０μｍ程度の垂直トレンチ８をＲＩＥエッチング（反応性イオンエッチング）などで形成する（図５（ｂ））。次に前述のように、ＣＶＤ成膜装置を用いて６５０℃で膜厚２５ｎｍのシリコン膜１３ａを堆積させる。堆積と同時に不純物ドーパントとしてリンを界面で不純物濃度を高く（例えば、１×１０２１ａｔｏｍｓ／ｃｍ３）、シリコン膜１３ａ表面で低く（例えば、１×１０１８ａｔｏｍｓ／ｃｍ３）なる濃度勾配を有するようにドープさせる。不純物ドーパントとして前述の説明ではリンを用いたが、窒素を用いることもできる（図５（ｃ））。次に酸化性雰囲気中での熱処理（約８００℃）によりシリコン膜１３ａを酸化し、リンがドープされたゲート酸化膜１３ｂを形成する。低抵抗の多結晶シリコン層を堆積してトレンチ８に埋め込み、パターンエッチングしてゲート電極１４を形成する。層間絶縁膜１５をＣＶＤ法で形成しゲート電極１４を覆った後、ｎ＋ソース層１２上のゲート酸化膜１３ｂと層間絶縁膜１５を除去後、ｎ＋ソース層１２を選択エッチングにより除去してｐ型ベース層１１を露出させる。ＳｉＣエピ基板１の表面にソース電極１６を形成することにより、ｐ型ベース層１１に導電接触させると同時にｎ＋ソース層１２にも導電接触させる。裏面側の酸化膜を除去した後、裏面にドレイン電極１７を形成すると、実施例１にかかる高チャネル移動度のゲート酸化膜を有するＭＯＳ型炭化珪素半導体装置となる（図５（ｄ））。 A method for manufacturing a MOS type silicon carbide semiconductor device having a gate oxide film having a high channel mobility will be described below with reference to FIG. The semiconductor regions shown in the substrate shown in FIG. 5 are schematic and are not drawn to represent the thickness of each region and the ratio of the thickness of each region. On the high-concentration n-type 4H—SiC semiconductor substrate 9, an n - drift layer 10 with a film thickness of 4.9 μm, an n-type impurity concentration of 1 × 10 16 atoms / cm 3 , a film thickness of 1.0 μm, p-type impurity concentration of 1 × 10 17 atoms / cm 3 of p-type base layer 11, thickness 0.5 [mu] m, the n-type source layer 12 of n-type impurity concentration of 1 × 10 19 atoms / cm 3 respectively by SiC epitaxial SiC The epitaxial substrate 1 is formed (FIG. 5A). The n-type source layer 12 may be formed by impurity ion implantation. A vertical trench 8 having a depth of about 2.0 μm from the surface of the SiC epi substrate 1 is formed by RIE etching (reactive ion etching) or the like (FIG. 5B). Next, as described above, a silicon film 13a having a film thickness of 25 nm is deposited at 650 ° C. using a CVD film forming apparatus. Concurrently with the deposition, phosphorus is used as an impurity dopant, and the impurity concentration is high at the interface (for example, 1 × 10 21 atoms / cm 3 ) and low at the surface of the silicon film 13 a (for example, 1 × 10 18 atoms / cm 3 ). Dope like so. In the above description, phosphorus is used as the impurity dopant, but nitrogen can also be used (FIG. 5C). Next, the silicon film 13a is oxidized by a heat treatment in an oxidizing atmosphere (about 800 ° C.) to form a gate oxide film 13b doped with phosphorus. A low-resistance polycrystalline silicon layer is deposited and embedded in the trench 8, and pattern etching is performed to form the gate electrode 14. After covering the gate electrode 14 to form an interlayer insulating film 15 by the CVD method, after removal of the n + gate oxide film 13b and the interlayer insulating film 15 on the source layer 12, the n + source layer 12 is removed by selective etching The p-type base layer 11 is exposed. By forming the source electrode 16 on the surface of the SiC epi substrate 1, the source electrode 16 is brought into conductive contact with the p-type base layer 11 and simultaneously with the n + source layer 12. When the drain electrode 17 is formed on the back surface after removing the oxide film on the back surface side, the MOS type silicon carbide semiconductor device having the high channel mobility gate oxide film according to the first embodiment is obtained (FIG. 5D).
図３は、実施例１とは異なる膜厚のゲート酸化膜を得るためのゲート酸化膜の形成工程を示す炭化珪素エピ基板の断面図である。前述の図１で説明したゲート酸化膜では、堆積したシリコン膜をすべて酸化によりシリコン酸化膜にする場合である。しかし、さらにシリコン酸化膜を厚くする場合、すべての厚さについて不純物がドープされている必要は無い。 FIG. 3 is a cross-sectional view of a silicon carbide epi-substrate showing a step of forming a gate oxide film for obtaining a gate oxide film having a thickness different from that of the first embodiment. In the gate oxide film described with reference to FIG. 1 described above, the deposited silicon film is entirely oxidized to form a silicon oxide film. However, when the silicon oxide film is made thicker, it is not necessary that impurities are doped for all thicknesses.
図３（ａ）〜（ｄ）の各工程について、以下それぞれ説明する。すなわち、まず、（ａ）前述の実施例１の記載と同様の前処理が施されたＳｉＣエピ基板１表面に、（ｂ）一旦、不純物リンがドープされたシリコン膜２を堆積し、（ｃ）熱酸化処理によりゲート酸化膜３にした後、（ｄ）さらにその上にシリコン酸化膜を堆積させ、熱処理を行う。併せて所要の膜厚のゲート酸化膜を得る。 Each step of FIGS. 3A to 3D will be described below. That is, first, (a) (b) a silicon film 2 doped with impurity phosphorus is once deposited on the surface of the SiC epitaxial substrate 1 that has been subjected to the same pretreatment as described in the first embodiment, and (c ) After the gate oxide film 3 is formed by thermal oxidation, (d) a silicon oxide film is further deposited thereon and heat treatment is performed. In addition, a gate oxide film having a required thickness is obtained.
各工程をさらに詳細に説明する。図３（ｂ）では実施例１と同様の方法で洗浄等の前処理を施したＳｉＣエピ基板１上にリンをドープしたシリコン膜２を１〜５ｎｍの膜厚に堆積させる（今回の実施例２では５ｎｍ）。このシリコン膜２の堆積後、実施例１と同様の条件で熱酸化処理を行うことにより、図３（ｃ）に示すようにＳｉＣエピ基板１上にリンがドープされたゲート酸化膜３を形成する。その後、シリコン酸化膜成膜装置を用いて、シリコン酸化膜を堆積させる（今回の実施例ではシリコン酸化膜成膜装置としてプラズマＣＶＤ装置を用いた）。その後、Ａｒをキャリアガスとして酸素に水素または窒素の少なくとも１つを混合した雰囲気中で熱処理を行いノンドープのゲート酸化膜７とする。処理温度は８００℃〜１２００℃（今回の実施例では９００℃とした）である。この熱処理で、ゲート酸化膜７を焼き締めるのと同時にゲート酸化膜３との界面特性が向上する。ここで、熱処理によりシリコン酸化膜が焼き締め効果により若干収縮するので、熱処理後にゲート酸化膜３とゲート酸化膜７の合計が少なくとも５０ｎｍとなるようにシリコン酸化膜を堆積させることが肝要である。 Each step will be described in more detail. In FIG. 3B, a silicon film 2 doped with phosphorus is deposited to a thickness of 1 to 5 nm on a SiC epitaxial substrate 1 that has been subjected to pretreatment such as cleaning in the same manner as in the first embodiment (the present embodiment). 2 for 5 nm). After the silicon film 2 is deposited, the gate oxide film 3 doped with phosphorus is formed on the SiC epi substrate 1 as shown in FIG. To do. Thereafter, a silicon oxide film is deposited using a silicon oxide film deposition apparatus (in this embodiment, a plasma CVD apparatus is used as the silicon oxide film deposition apparatus). Thereafter, heat treatment is performed in an atmosphere in which at least one of hydrogen or nitrogen is mixed with oxygen using Ar as a carrier gas to form a non-doped gate oxide film 7. The processing temperature is 800 ° C. to 1200 ° C. (in this example, 900 ° C.). With this heat treatment, the interface characteristics with the gate oxide film 3 are improved simultaneously with the gate oxide film 7 being baked. Here, since the silicon oxide film is slightly shrunk by the heat treatment due to the heat treatment, it is important to deposit the silicon oxide film so that the sum of the gate oxide film 3 and the gate oxide film 7 is at least 50 nm after the heat treatment.
また、この実施例２によるゲート酸化膜の形成プロセスは、トレンチゲート型のＳｉＣ半導体装置のゲート酸化膜の形成にも適用することができる。図４は、そのようなゲート酸化膜の形成方法をトレンチゲート型のＳｉＣ半導体装置に適用する場合のプロセス工程を示すＳｉＣエピ基板の断面図であり、トレンチ内の工程だけ示す。図２（ａ）と同様にして周知の方法により形成されたトレンチ８を有するＳｉＣエピ基板４に（図４（ａ））、前述のように膜厚１〜５ｎｍの不純物ドープされたシリコン膜５を堆積させる（図４（ｂ））。図２の（ｃ）と同様に熱酸化処理を施すことによりＳｉＣエピ基板４上の前記シリコン膜５をリンがドープされたゲート酸化膜６とする（図４（ｃ））。ゲート酸化膜６上にノンドープのシリコン酸化膜を堆積させた後、図２（ｄ）と同様にして熱処理する（図４（ｄ））。以上の図４に示すゲート酸化膜の形成方法によれば、結晶面が異なる表面が露出するトレンチを有するＳｉＣエピ基板上にも膜厚が均一で、所要の膜厚のゲート酸化膜を形成することができる。 The gate oxide film formation process according to the second embodiment can also be applied to the formation of a gate oxide film of a trench gate type SiC semiconductor device. FIG. 4 is a cross-sectional view of a SiC epi substrate showing process steps when such a gate oxide film forming method is applied to a trench gate type SiC semiconductor device, and shows only steps in the trench. A SiC epitaxial substrate 4 having a trench 8 formed by a well-known method in the same manner as in FIG. 2A (FIG. 4A), an impurity-doped silicon film 5 having a thickness of 1 to 5 nm as described above. Is deposited (FIG. 4B). The silicon film 5 on the SiC epi substrate 4 is changed to a phosphorus-doped gate oxide film 6 by performing a thermal oxidation process as in FIG. 2C (FIG. 4C). After depositing a non-doped silicon oxide film on the gate oxide film 6, heat treatment is performed in the same manner as in FIG. 2D (FIG. 4D). According to the method for forming a gate oxide film shown in FIG. 4 above, a gate oxide film having a uniform film thickness is formed even on a SiC epi substrate having a trench in which a surface having a different crystal plane is exposed. be able to.
以上説明した実施例１、２に記載のゲート酸化膜の形成方法によれば、ゲート酸化膜／炭化珪素半導体基板の界面に特有の高い界面準位密度を低減させ、高チャネル移動度を得ることができ、しきい値電圧の低下およびしきい値電圧シフトについても抑えることのできるゲート酸化膜の形成方法と、この形成方法により作製されるゲート酸化膜を有する炭化珪素半導体装置の製造方法を提供することができる。 According to the method for forming a gate oxide film described in the first and second embodiments, the high interface state density peculiar to the gate oxide film / silicon carbide semiconductor substrate interface can be reduced and high channel mobility can be obtained. A method for forming a gate oxide film capable of suppressing a decrease in threshold voltage and a threshold voltage shift, and a method for manufacturing a silicon carbide semiconductor device having a gate oxide film manufactured by this formation method are provided. can do.
１ 炭化珪素エピ基板、ＳｉＣエピ基板
２ シリコン膜
３ ゲート酸化膜
４ 炭化珪素エピ基板、ＳｉＣエピ基板
５ シリコン膜
６ ゲート酸化膜
７ ノンドープゲート酸化膜
８ トレンチ
９ ＳｉＣ半導体基板
１０ ｎ−ドリフト層
１１ ｐ型ベース層
１２ ｎ＋ソース層
１３ａ シリコン膜
１３ｂ ゲート酸化膜
１４ ゲート電極
１５ 層間絶縁膜
１６ ソース電極
１７ ドレイン電極
DESCRIPTION OF SYMBOLS 1 Silicon carbide epi substrate, SiC epi substrate 2 Silicon film 3 Gate oxide film 4 Silicon carbide epi substrate, SiC epi substrate 5 Silicon film 6 Gate oxide film 7 Non-doped gate oxide film 8 Trench 9 SiC semiconductor substrate 10 n - Drift layer 11 p Type base layer 12 n + source layer 13a silicon film 13b gate oxide film 14 gate electrode 15 interlayer insulating film 16 source electrode 17 drain electrode
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| CN106340448B (en) * | 2016-11-28 | 2019-03-01 | 清华大学 | The preparation method and SiC power MOSFET device of SiC power MOSFET device gate oxide |
| CN112038237B (en) * | 2020-09-10 | 2023-08-25 | 深圳市芯电元科技有限公司 | Manufacturing method of trench MOSFET |
| CN117238758A (en) * | 2023-11-14 | 2023-12-15 | 深圳天狼芯半导体有限公司 | Method for passivating SiC MOS interface defects by sacrificial oxidation NANO-P doping EPI |
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| JPS56161646A (en) * | 1980-05-19 | 1981-12-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0851110A (en) * | 1994-08-05 | 1996-02-20 | Matsushita Electric Ind Co Ltd | Method for forming insulating film |
| JP2005353877A (en) * | 2004-06-11 | 2005-12-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP4956904B2 (en) * | 2005-03-25 | 2012-06-20 | 富士電機株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
| KR100932348B1 (en) * | 2005-03-31 | 2009-12-16 | 가부시키가이샤 히다치 고쿠사이 덴키 | Manufacturing Method of Semiconductor Device, Manufacturing Method of Substrate and Substrate Processing Apparatus |
| JP5100329B2 (en) * | 2007-11-22 | 2012-12-19 | 三菱電機株式会社 | Semiconductor device |
| JP5266996B2 (en) * | 2008-09-12 | 2013-08-21 | 住友電気工業株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP5440454B2 (en) * | 2010-09-03 | 2014-03-12 | 三菱電機株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
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