JP6108330B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device that realizes low resistance of a MOSFET made of a silicon carbide semiconductor, and a silicon carbide semiconductor device manufactured by the manufacturing method.

  A semiconductor using silicon carbide (hereinafter referred to as SiC) as a material is expected as a semiconductor element of the next generation of silicon (hereinafter referred to as Si). SiC semiconductors can reduce the resistance of the device in the on state to hundreds of times compared to conventional semiconductor devices using Si as a material, and can be used in higher temperature (200 ° C or higher) environments. There are various advantages. This is due to the characteristics of the material itself that the band gap of SiC is about three times as large as that of Si, and that the breakdown field strength is nearly an order of magnitude greater than that of Si.

  As SiC devices, Schottky barrier diodes and planar type vertical MOSFETs have been commercialized so far.

  SiC MOSFETs are expected to have a high breakdown voltage and a low on-resistance, but have not been realized at present. For example, there are Patent Documents 1 to 5 regarding SiC-MOSFETs.

International Publication 2004-036655 JP 2003-86792 A Special table 2004-511101 gazette JP-A-11-121748 Japanese Patent Laid-Open No. 11-251592

  Since SiC-MOSFET mainly has low channel mobility, the channel resistance is high and the expected low on-resistance cannot be obtained. The reason is considered as follows. First, because SiC has a small impurity diffusion coefficient, the channel region must be formed by ion implantation, and crystal defects induced by ion implantation and interstitial impurities that are not activated cause channel mobility. It is lowered. Second, in SiC, carbon remains at the oxide film / SiC interface during oxidation, and the residual carbon increases the interface state and decreases the channel mobility.

Regarding the first problem, a MOSFET in which a channel region is formed by epitaxial growth is known (see Patent Document 1). As for the second problem, a technique is known in which annealing in a hydrogen or N ₂ O atmosphere (POA: Post-Oxidation Annealing) is performed after gate oxidation to passivat the interface state due to residual carbon (Patent Document 2, 3).

  On the other hand, there is a method for suppressing the generation of residual carbon. For example, a method of forming a Si channel layer on SiC and forming a gate oxide film on the surface thereof (refer to Patent Document 4), a SiC surface is passivated with Si atoms, and then an LTO film (Low temperature oxide film) thereon Has been proposed, in which only Si is oxidized by heat treatment (see Patent Document 5). However, since the former uses Si, there is a problem that the strength of the dielectric breakdown field is reduced at the Si portion and the advantage of SiC is lost. Moreover, since the latter needs to oxidize only the passivated surface Si layer, it is necessary to keep the heat treatment temperature low, and there is a problem that the quality of the oxide film is lowered and the breakdown voltage is lowered.

  The present invention is intended to solve these problems, and an object of the present invention is to increase the channel mobility of a MOSFET in a SiC-MOSFET. Another object of the present invention is to provide a technique for reducing residual carbon during oxidation and increasing the channel mobility of a MOSFET.

  The present invention intentionally introduces carbon atomic vacancies (also referred to as carbon vacancies) when forming a channel layer of an SiC-MOSFET. Here, the carbon vacancies means that no carbon atom exists at the position where the carbon atom should be at the lattice point of the SiC single crystal constituting the epitaxial film.

  The structure of the SiC-MOSFET of the present invention and the manufacturing method thereof will be described with reference to FIGS. FIG. 1 is a cross-sectional view in the middle of a MOSFET manufacturing process. FIG. 2 is a sectional view of the MOSFET. An n− type epitaxial layer 2 is formed on n + type SiC substrate 1. Thereafter, an oxide film mask is formed on the n − type epitaxial layer 2, Al is selectively ion-implanted to form a p + type base region 3, and the oxide film is removed. A p − type epitaxial layer 4 is grown thereon as a channel region. In the growth of the epitaxial layer 4, in the present invention, the epitaxial growth conditions are adjusted, and carbon vacancies are introduced into the p − type epitaxial layer 4 (see FIG. 1).

  Thereafter, an n + type source region 5, a p + type contact region (not shown), and a low concentration n − type base region 6 are formed by forming an oxide film mask and ion implantation. Subsequently, an activation heat treatment is performed to activate the implanted ions. Thereafter, a gate insulating film 7 is formed, subsequently a gate electrode 8, an interlayer insulating film 9, and a source electrode 10 are formed, and a drain electrode 11 is formed on the back surface of the n + type SiC substrate 1, thereby manufacturing a MOSFET. (See FIG. 2).

  In the SiC-MOSFET, the carbon vacancies are intentionally introduced when forming the channel layer in the SiC-MOSFET, so that carbon can be previously removed from the SiC layer. Residual carbon at the SiC interface can be reduced. Moreover, since carbon vacancies exist not only on the surface of the channel layer but also on the entire channel layer, an effect can be obtained even if the oxide film / SiC interface moves from the surface of the channel layer to the inside due to oxidation.

The manufacturing method of the present invention further increases the channel mobility by using it in combination with the conventionally proposed method of improving the channel mobility by passivating the interface state due to POA in an atmosphere of hydrogen or N ₂ O. Is possible.

  In order to introduce carbon vacancies, during the epitaxial growth of the channel region, the flow rate ratio of the gas containing Si species and the gas containing C species (hereinafter referred to as C / Si ratio) is controlled to be a low C / Si ratio. Can be realized. However, since the growth rate decreases as the C / Si ratio is lowered, it is necessary to suppress the growth rate to 3 μm / h or more that does not affect the process efficiency.

As a method for confirming the introduced carbon vacancies, the trap level caused by the carbon vacancies represented by HK4 when the channel layer is an n-type epitaxial layer and Z _1/2 when the channel layer is a p-type epitaxial layer is used. There is a method of evaluating the unit density by a DLTS (Deep Level Transient Spectroscopy) method. The electron trap level at 0.65 eV from the Z _1/2 conduction band, and HK4 is the hole trap level at 1.44 eV from the valence band.

The trap level density is 2 × 10 ¹³ cm ⁻³ or less in the average epitaxial layer, but when carbon vacancies are intentionally introduced as in the present invention, it is approximately 5 × 10 ¹³ cm ⁻³ or more. High density. In addition, if the trap level density is too high, the leakage current of the element increases due to crystal imperfections, so that it is preferable to suppress the density to 1 × 10 ¹⁴ cm ⁻³ or less. Since the trap level density caused by the carbon vacancies has a negative correlation with the C / Si ratio, the trap level density can be suppressed to a predetermined value or less by adjusting the C / Si ratio.

  The present invention has the following features in order to achieve the above object. The present invention is characterized in that a channel layer is formed by epitaxial growth, and a large number of carbon vacancies are introduced into the epitaxial film by intentionally controlling the C / Si ratio to be small during the growth.

According to the present invention, in a silicon carbide semiconductor device, carbon atomic vacancies are introduced into a silicon carbide epitaxial film that becomes a channel region of a MOSFET, and the trap state density caused by the carbon atomic vacancies is 5 × 10 ¹³ cm. ^-3 or more and 1 × 10 ¹⁴ cm ^-3 or less. The present invention includes a step of introducing carbon atomic vacancies when forming a silicon carbide epitaxial film that becomes a channel region of a MOSFET in a method for manufacturing a silicon carbide semiconductor device, resulting from carbon atomic vacancies. The trap level density is 5 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁴ cm ⁻³ or less. In the step of introducing carbon vacancies of the present invention, the flow ratio of the gas containing Si species and the gas containing C species is controlled so that the C / Si ratio is 0.4 or more and 0.8 or less. Preferably, the silicon carbide epitaxial film is epitaxially grown.

  The device of the present invention allows carbon vacancies to be introduced into the epitaxial film by growing at a low C / Si ratio during the epitaxial growth of the channel region of the SiC-MOSFET, and as a MOSFET, high channel mobility can be obtained. The resistance of the element can be reduced.

According to the present invention, carbon atomic vacancies are introduced into the silicon carbide epitaxial layer, and the trap level density is 5 × 10 ¹³ cm ⁻³ or more when the C / Si ratio is in the range of 0.4 or more and 0.8 or less. A high density of can be obtained. In the present invention, since the trap state density is suppressed to 1 × 10 ¹⁴ cm ⁻³ or less, the leakage current of the element due to crystal imperfection does not increase.

  According to the present invention, the conventional C / Si ratio is maintained at 3 μm / h or more by controlling the C / Si ratio to be in the range of 0.4 or more and 0.8 or less and performing epitaxial growth. Compared with the ratio of 1.4, the interface state density can be reduced, and as a result, the channel mobility can be improved.

The figure which shows the manufacturing method of Example 1 of this invention. The schematic which shows this invention and the conventional SiC-MOSFET. The figure which shows the relationship between C / Si ratio, an interface state density, and the film-forming speed | rate.

  A method for intentionally introducing carbon vacancies when forming a channel layer of a SiC-MOSFET of the present invention and a SiC-MOSFET manufactured by the method will be described in detail below.

(Embodiment 1)
The present embodiment is a method of intentionally introducing carbon vacancies in the step of epitaxially growing a silicon carbide epitaxial film.

First, as a preliminary experiment, the prepared epitaxial layers were examined for a plurality of cases in which the C / Si ratio of the reaction gas when forming the epitaxial layers was different. An n + type SiC substrate with 4 ° -off of 4H-SiC (000-1) plane is placed in the epitaxial growth furnace, and maintained at a temperature of 1670 ° C. and a pressure of 10000 Pa. 0.3 to 6.7 sccm (corresponding to a C / Si ratio of 1.4 to 0.4), and 0.1 sccm of nitrogen as a dopant gas, about 5 μm thickness, doping concentration 1 × 10 ¹⁶ cm ⁻³ An n-type epitaxial layer was formed. Then, an oxide film of 50 nm is formed by wet oxidation, an Al electrode is formed on the oxide film, and patterning is performed. A test device for evaluating an oxide film is created, and an interface between SiC and the oxide film is measured by capacitance-voltage (CV) method measurement. The interface state density of was evaluated.

  The evaluation results are shown in FIG. FIG. 3 is a graph showing the relationship between the C / Si ratio, the interface state density, and the film formation rate. As a result of comparing the interface state density between the SiC and the oxide film interface at a depth of 0.1 to 0.2 eV from the conduction band edge of the semiconductor energy band (which is an evaluation condition of the CV method), the C / Si ratio It has been found that the interface state density decreases as the value is lowered to 0.8 or less. Further, when the film formation rate was examined, it was found that the film formation rate gradually decreased as the C / Si ratio was decreased, and that the film formation rate decreased to 3 μm / h when the C / Si ratio was decreased to 0.4.

Next, the present embodiment will be described below with reference to FIGS. FIG. 1 is a diagram showing an epitaxial film growth process of SiC-MOSFET, and FIG. 2 is a diagram showing a cross-sectional structure of the SiC-MOSFET element. As an example of this embodiment, a planar type vertical MOSFET having a withstand voltage of 1.2 kV was experimentally manufactured. First, an n − type epitaxial layer 2 having a thickness of 10 μm, doped with nitrogen at 1 × 10 ¹⁶ cm ⁻³ on an n + type SiC substrate 1 with 4 ° off of 4H—SiC (000-1) plane, is formed into C / Si. Films were formed at a ratio of 1.3. Subsequently, an oxide film mask was formed thereon, Al was selectively ion-implanted to form the p + -type base region 3, and the oxide film was removed. A p − type epitaxial layer 4 having a thickness of 0.5 μm was grown thereon as a channel region. The p-type epitaxial layer 4 was formed by epitaxial growth at a C ₃ H ₈ / SiH ₄ gas flow rate ratio such that the C / Si ratio was 0.6. FIG. 1 is a cross-sectional view at this time.

  Thereafter, an n + -type source region 5 was formed by forming an oxide film mask and phosphorus ions, a p + -type contact region (not shown) was formed by aluminum ion implantation, and a low-concentration n − -type base region 6 was formed by nitrogen ion implantation. Subsequently, an activation heat treatment was performed to activate the implanted ions. Thereafter, the gate oxide film 7 was formed by wet oxidation in a water vapor atmosphere. Subsequently, a gate electrode 8 made of polysilicon, an interlayer insulating film 9 made of a deposited oxide film, a source electrode 10 made of nickel, and a drain electrode 11 were formed, and the MOSFET 1 was produced.

For comparison, a MOSFET in which a p-type epitaxial layer (p-type epitaxial layer 4) is grown at a C ₃ H ₈ / SiH ₄ gas flow rate ratio such that the conventional C / Si ratio is 1.4. (Comparative example) was created. Processes other than the growth of the p-type epitaxial layer are the same as those for MOSFET 1. The cross-sectional structures of MOSFET 1 and MOSFET (comparative example) are the same as those in FIG.

Comparison of the effective channel mobility of the prototype MOSFET 1 and MOSFET (comparative example) showed that the MOSFET (comparative example) prepared under the conventional p-type epitaxial layer formation condition was 15 cm ² / Vs. In MOSFET 1 formed by forming the channel layer under the epitaxial layer formation conditions of the form, the improvement was 25 cm ² / Vs. Using the method of this embodiment, a low-resistance MOSFET having improved channel mobility compared to the prior art could be produced.

In the first embodiment, monosilane and propane are used as the reaction gas. However, even when hydrogen chloride is added, there is an effect of introducing carbon vacancies in the range of C / Si ratio of 0.4 to 0.8. It was. Hydrogen chloride (HCl gas) accelerates the decomposition of SiH ₄ and improves the deposition rate.

  Further, when dichlorosilane, trichlorosilane, or silicon tetrachloride is used instead of monosilane in the first embodiment, carbon vacancies are formed in the range of C / Si ratio of 0.4 to 0.8. There was an effect to introduce.

  In addition, the example shown by the said embodiment etc. was described in order to make invention easy to understand, and is not limited to this form.

1 n + type SiC substrate 2 n− type epitaxial layer 3 p + type base region 4 p− type epitaxial layer 5 n + type source region 6 low concentration n− base region 7 gate oxide film 8 gate electrode 9 interlayer insulating film 10 source electrode 11 drain electrode

Claims (1)

A silicon carbide semiconductor device,
A silicon carbide substrate;
A first silicon carbide epitaxial layer formed on the silicon carbide substrate;
A first base region selectively formed in the first silicon carbide epitaxial layer;
A second silicon carbide epitaxial layer formed on the first silicon carbide epitaxial layer and the first base region and serving as a channel region of the MOSFET into which carbon atomic vacancies are introduced;
A source region selectively formed in the second silicon carbide epitaxial layer;
A second base region penetrating the second silicon carbide epitaxial layer and contacting the first silicon carbide epitaxial layer and the first base region;
A gate insulating film formed to be in contact with the second silicon carbide epitaxial layer, the source region, and the second base region;
Have
A silicon carbide semiconductor device, wherein a trap state density due to carbon vacancies in the second silicon carbide epitaxial layer is 5 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁴ cm ⁻³ or less.

Images