JP5921089B2 - Epitaxial wafer manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a technique for improving the quality of an epitaxial layer in a semiconductor device using silicon carbide.

  A semiconductor device using SiC (silicon carbide) is known as a device having excellent temperature characteristics and breakdown voltage characteristics. However, many problems to be solved remain in the manufacturing technology of a semiconductor device using SiC, and there are many problems especially for a high-voltage device.

  As an element structure, an epitaxial layer grown on a low resistance substrate is often used as an operation layer. In a power device, an epitaxial layer operates as a breakdown voltage layer, and an epitaxial layer composed of a single layer is usually used (for example, Patent Document 1).

The breakdown voltage layer made of an epitaxial layer has a thickness of 3 to 100 μm or more depending on the operating voltage, and its doping concentration is at most 10 ¹⁶ / cm ³ , rather 10 ¹⁵ / cm ³ or 10 ^14. / Cm ³ is often the case. In particular, in order to realize a device having a withstand voltage exceeding several kV, it is required to obtain a doping concentration of about 10 ¹⁴ / cm ³ with good reproducibility after setting the layer thickness to around 100 μm or close to 200 μm.

On the other hand, the low resistance crystal serving as the substrate is often doped with about 10 ¹⁹ / cm ³ . Therefore, since the doping concentration is greatly different between the breakdown voltage layer made of the epitaxial layer and the substrate, the lattice constant is different. Therefore, when the thickness of the epitaxial layer is large, the crystal quality of the epitaxial layer deteriorates due to the introduction of crystal defects due to the difference in lattice constant (lattice mismatch), leading to a decrease in carrier mobility and a decrease in carrier time constant. As a result, there arises a problem that the element resistance increases.

  In addition, the low resistance crystal used as the substrate is doped with nitrogen at a high concentration in order to lower the resistivity. However, it is known that basal plane dislocations occur at a high density in a region doped with nitrogen at a high concentration. (For example, Non-Patent Document 1). The generated dislocations also propagate in the drift layer epitaxially grown on the substrate. In the case of a device having a breakdown voltage exceeding several kV, the electric conduction in the drift layer is often a bipolar operation in which both carriers of electrons and holes contribute, and in a crystal containing many crystal defects such as dislocations, Crystal defects may grow during recombination of holes with holes. Therefore, there is a problem that the influence of crystal defects on device characteristics becomes more severe as compared to a relatively low breakdown voltage device in which electric conduction of the drift layer is performed in a unipolar operation in which only electrons contribute.

  On the other hand, when the breakdown voltage of the device exceeds several kV, the drift layer thickness is about 100 μm or close to 200 μm, so the bulk crystal itself may be used as the drift layer. The bulk crystal is manufactured by a sublimation method (for example, Patent Documents 2 and 3), a method using a sublimation method and neutron conversion doping (for example, Patent Document 4), high temperature chemical vapor deposition at 1900 ° C., and subsequent annealing. What is used (for example, patent document 5) is shown.

JP 2003-197921 A International Patent Publication No. 2008/111269 Special table 2008-541480 gazette Special table 2007-535800 gazette JP 2005-537657 Gazette

Tomohisa Kato et al., “Crystal Defects in SiC Bulk Single Crystals Generated by Highly Concentrated Nitrogen Doping”, Japan Society of Applied Physics, The 67th Japan Society of Applied Physics, Proceedings, 30a-ZG-4 (2006)

However, in the manufacturing methods shown in Patent Documents 2 to 5, the doping concentration of the drift layer having a thickness of 100 μm to 200 μm required for a device having a breakdown voltage exceeding several kV is 10 ¹⁴ / cm ³ with good reproducibility. It could not be realized, and it was difficult to realize a sufficiently long carrier time constant.

  In view of the above-described problems, an object of the present invention is to provide a method for producing a high-quality epitaxial wafer with few crystal defects and a method for producing a semiconductor element using the epitaxial wafer.

The method for producing an epitaxial wafer of the present invention includes (a) a SiC substrate doped with nitrogen having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less , or 1 × on the SiC substrate to which no impurity is intentionally added. Forming an epitaxial layer doped with nitrogen having an impurity concentration of 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻³ or less by epitaxial growth with a layer thickness of 100 to 200 μm ; and (b) obtained by the step (a). A step of continuously removing all of the SiC substrate and a part of the epitaxial layer while leaving a predetermined thickness of the epitaxial layer from the SiC substrate side of the structure.

The method for producing an epitaxial wafer of the present invention includes (a) a SiC substrate doped with nitrogen having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less , or 1 × on the SiC substrate to which no impurity is intentionally added. Forming an epitaxial layer doped with nitrogen having an impurity concentration of 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻³ or less by epitaxial growth with a layer thickness of 100 to 200 μm ; and (b) obtained by the step (a). A step of continuously removing all of the SiC substrate and a part of the epitaxial layer while leaving a predetermined thickness of the epitaxial layer from the SiC substrate side of the structure. Thus, an epitaxial wafer in which crystal defects due to the difference in lattice constant are suppressed is formed. Further, if a drain layer having a thickness of a little less than 100 μm to 200 μm is formed using this epitaxial wafer, a semiconductor device having a sufficiently low carrier time constant and a small element resistance can be obtained.

5 is a diagram showing a manufacturing process of the IGBT which is the semiconductor device according to the first embodiment. FIG. 10 is a diagram showing a manufacturing process of an IGBT which is a semiconductor device according to a modification of the first embodiment. FIG. 7 is a cross-sectional view showing a structure of a MOSFET which is a semiconductor device according to a modification of the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a structure of a pin diode that is a semiconductor device according to a modification of the first embodiment. 6 is a cross-sectional view showing a structure of an MPS diode that is a semiconductor device according to a modification of the first embodiment. FIG.

(Embodiment 1)
FIG. 1 is a diagram illustrating a manufacturing process of an insulated gate bipolar transistor (IGBT) which is a semiconductor device according to the first embodiment. Hereafter, the manufacturing process of IGBT is demonstrated along FIG.

First, an SiC epitaxial layer 13 is formed by epitaxial growth on an SiC substrate 12 having an off-angle from the (0001) plane (FIG. 1A). The epitaxial layer 13 becomes a drift layer for maintaining a withstand voltage in the IGBT, and the doping concentration thereof is 10 ¹⁴ to 10 ¹⁶ / cm ³ depending on the required withstand voltage. For epitaxial growth, silane (SiH ₄ ) or silane containing chlorine is used as a raw material for silicon, and propane (C ₃ H ₈ ) is used as a raw material for carbon. Alternatively, organic silicon may be used in combination, or only organic silicon may be used.

  When silane and propane are used as raw materials, the growth temperature is 1400 ° C. to 1700 ° C. Even when other raw materials are used, the growth temperature is the same or lower. By performing epitaxial growth at 1700 ° C. or lower, generation of crystal defects due to contamination of impurities during growth or desorption of constituent elements can be suppressed.

  The SiC substrate 12 is preferably non-doped in order to avoid unexpected impurities, but in the bulk growth of compound semiconductors, crystal defects may be reduced by performing a certain amount of doping. On the other hand, for example, when the SiC substrate 12 is doped with nitrogen, which is often used as a dopant, the lattice constant decreases with increasing doping concentration, so that the lattice constant difference with the epitaxial layer 13 increases.

A case is assumed where the doping concentration of the epitaxial layer 13 is 10 ¹⁶ cm ⁻³ or less. For example, the lattice constant difference between the epitaxial layer 13 having a doping concentration of 10 ¹⁶ cm ⁻³ , 10 ¹⁵ cm ^−3, or 10 ¹⁴ cm ⁻³ and the SiC substrate 12 is 3 × 10 ¹⁸ cm. ^-3 is about 0.01%, and the SiC substrate 12 has a nitrogen concentration of 1.5 × 10 ¹⁸ cm ^-3 and is about 0.005%, and the SiC substrate 12 has a nitrogen concentration of 6 × 10 ¹⁷ cm. ^-3 , it can be suppressed to about 0.002%.

  As a result of trial and error through experiments and simulations, the inventor has confirmed that the introduction of crystal defects can be sufficiently suppressed when the lattice constant difference is about 0.01%, about 0.005%, and about 0.002%.

Therefore, in the present embodiment, the doping concentration of SiC substrate 12 is set to 3 × 10 ¹⁸ cm ⁻³ or less, further 1.5 × 10 ¹⁸ cm ⁻³ or less, more preferably 6 × 10 ¹⁷ cm ^−3. Even when the epitaxial layer 13 having a doping concentration of 10 ¹⁴ to 10 ¹⁶ cm ⁻³ is grown to a thickness of 100 to 200 μm, the introduction of crystal defects can be sufficiently suppressed, and the carrier time constant in the drift layer can be reduced. Can be bigger. SiC substrate 12 may be non-doped (including a case where impurities are not intentionally added).

  Prior to the element fabrication process, the entire SiC substrate 12 and a part of the epitaxial layer 13 are removed from the SiC substrate 12 side by a process such as polishing, grinding, or etching. The epitaxial layer 13 is continuously removed leaving a thickness necessary for maintaining the assumed breakdown voltage, and thus an SiC epitaxial wafer 23 shown in FIG. 1B is formed.

Next, p body region 4 is selectively formed on the surface of epitaxial wafer 23 by ion implantation and subsequent activation heat treatment. Further, n emitter region 5 is selectively formed on the surface of p body region 4 by the same process. The p body region 4 has a thickness of about 0.5 to 2 μm and a doping concentration of about 3 to 20 × 10 ¹⁷ cm ⁻³ . The channel may be formed during device operation, or the doping concentration may be lowered on the outermost surface of the p body region 4 close to the channel as compared with other portions of the p body region 4. By reducing the doping concentration on the outermost surface, scattering due to impurities can be reduced, carrier mobility in the channel can be increased, and device resistance can be lowered.

Further, in the p body region 4, a region opposite to the region where the channel is formed across the n emitter region 5 is defined as a contact region 6, and the doping concentration of the outermost surface region of the contact region 6 is 5 to 50 × 10 ^18. Alternatively, ion implantation may be selectively performed so that the doping is higher than that of the p body region 4 by about cm ⁻³ . The n emitter region 5 has a thickness of about 0.3 to 1 μm and a doping concentration of about 5 to 50 × 10 ¹⁸ cm ⁻³ .

  Next, a high concentration p collector region 2 is formed on the surface of the epitaxial wafer 23 opposite to the surface where the p body region 4 and the n emitter region 5 are formed by ion implantation and activation heat treatment. A portion of the epitaxial wafer 23 other than the p collector region 2, the p body region 4, and the n emitter region 5 operates as the n drift layer 3, and the breakdown voltage of the element is determined by the doping concentration and thickness of the n drift layer 3.

  Therefore, the thickness and doping concentration of the epitaxial layer 13 and the epitaxial wafer 23 are set so that the n drift layer 3 having a predetermined thickness and a predetermined doping concentration can be obtained after the element manufacturing process.

  The p collector region 2 may be formed by epitaxial growth.

  On the layer structure thus formed, a channel layer, a gate insulating film 7, and a gate electrode 8 are formed in this order to produce a gate portion. In FIG. 1C, the channel layer is not shown, and the channel layer is not necessarily provided. However, when provided, the conductivity type may be n-type or p-type. Further, in order to improve the surface roughness generated in the p body layer 4 and the n emitter layer 5 by the activation heat treatment of the ion implantation species, it is desirable to form a channel layer by, for example, epitaxial growth. However, if the surface roughness is small, it may be formed by selective ion implantation.

  In addition, the activation heat treatment process of the ion implantation species described so far may be performed at once, or the activation heat treatment may be performed for each implantation process.

  As the gate insulating film 7, a silicon oxide film, a silicon oxynitride film, or the like is formed at a thickness of about 10 to 100 nm in a region facing the channel region in the p body region 4. The formation method is based on thermal oxidation or nitridation of a silicon carbide semiconductor, deposition of an insulating film, or a combination thereof.

  The gate electrode 8 is formed on the gate insulating film 7 in a region facing the channel region in the p body region 4 by forming a polycrystalline silicon film or a metal film.

  Thereafter, the channel layer, the gate insulating film 7 and the gate electrode 8 formed in unnecessary places are removed. Alternatively, the gate insulating film 7 may be formed after removing the channel layer other than the predetermined region including the channel region in the p body region 4.

  Next, an interlayer insulating film 9 is formed on the gate electrode 8 and the semiconductor layer, and the interlayer insulating film 9 is removed from a part of the n emitter layer 5 and the p contact layer 6. Then, an emitter electrode 10 is formed in the region where the interlayer insulating film 9 has been removed.

  Further, the collector electrode 1 is formed on the surface of the p collector region 2, and the emitter wiring 11 is formed on the emitter electrode 10 and the interlayer insulating film 9.

  Although not shown, the emitter wiring 11 on the interlayer insulating film 9 is removed in a partial region of the outer periphery of the element where the gate electrode pad is formed.

Thus, an IGBT made of SiC, which is the semiconductor element of the present embodiment shown in FIG. 1C, is formed. According to the manufacturing process of the semiconductor device of the present embodiment, since the doping concentration of the epitaxial wafer 23 is formed on the order of 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility, there are few crystal defects in the drift layer 3. The carrier time constant can be made sufficiently small. Therefore, an IGBT having a small element resistance can be obtained. Further, by forming the drift layer 3 with a thickness of slightly less than 100 μm to 200 μm, it is possible to ensure a withstand voltage.

  Although the drift layer 3 has been described as n-type, it may be p-type. In that case, the collector region 2, the body region 4, and the body contact region 6 are n-type, and the emitter region 5 is p-type.

<Modification 1>
In FIG. 1, after a part of the epitaxial layer 13 and the SiC substrate 12 are removed to form the epitaxial wafer 23, the element process on the surface side of the epitaxial wafer 23, that is, formation of the p body region 4 and n emitter region 5, gate The part was formed. However, part of the epitaxial layer 13 and the SiC substrate 12 may be removed after the p body region 4, the n emitter region 5 and the p contact region 6 are formed and before the gate portion is formed. Alternatively, it may be performed during the gate process, such as after the formation of the gate insulating film 7, after the formation of the gate electrode 8, or after the formation of the interlayer insulating film 9.

  FIG. 2 shows an example in which a part of the epitaxial layer 13 and the SiC substrate 12 are removed after the gate process. First, as shown in FIG. 2A, after forming the epitaxial layer 13 on the SiC substrate 12, an element process on the surface side of the epitaxial layer 13 is performed (FIG. 2B). After the emitter wiring 11 is formed by the element process on the surface side, the substrate 12 and the epitaxial layer 13 are partially removed to leave the epitaxial layer 13 necessary for ensuring the assumed breakdown voltage, and then the p collector region 2 and the collector electrode 1 is formed. At the stage where the p collector region 2 is formed, an epitaxial layer 13 other than the p collector region 2 and the p body region 4 is defined as the drift layer 3 (FIG. 2C).

  The p collector region 2 is formed by ion implantation and an activation heat treatment process. In order not to affect the gate portion formed of the gate insulating film 7, gate electrode 8, interlayer insulating film 9, source electrode 10, and source wiring 11 that has already been formed, the activation heat treatment is performed using laser annealing or the like, This is performed in a situation where only the vicinity of region 2 is heated. The same applies to the heat treatment of the collector electrode 1.

  The p collector region 2 may be formed by epitaxial growth as long as epitaxial growth can be performed at a sufficiently low temperature by using unsaturated hydrocarbon as a carbon raw material.

<Modification 2>
1 and 2 show an example in which the epitaxial wafer of the present invention is applied to an IGBT, but it can also be applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  FIG. 3 shows a cross-sectional view of a MOSFET formed using the epitaxial wafer 23 of the present invention. The MOSFET of FIG. 3 has a configuration in which an n drain region 22 is formed instead of the p collector region 2 and a drain electrode 21 is formed instead of the collector electrode 1 in the IGBT of FIG. The n source region 25 and the emitter electrode 10 are called a source electrode 30. Other than that, the configuration is the same as that of the IGBT of FIG.

  Also in the MOSFET having such a configuration, by forming the n drift layer 3 from the epitaxial wafer 23, the crystal drift of the n drift layer 3 is small, and the carrier time constant can be sufficiently reduced. Therefore, a MOSFET having a low element resistance can be obtained. Further, by forming the drift layer 3 with a thickness of slightly less than 100 μm to 200 μm, it is possible to ensure a withstand voltage.

<Modification 3>
The epitaxial wafer 23 of the present invention can be applied not only to a transistor but also to a diode element such as a pin diode shown in FIG. 4 or an MPS (Merged pin and Schottky) diode shown in FIG.

  By ion implantation and activation heat treatment, an anode region 44 and an anode contact region 54 are sequentially formed on the first main surface side of the epitaxial wafer 23, and a cathode region 42 is formed on the second main surface side. A region of the epitaxial wafer 23 in which the anode region 44, the anode contact region 54, and the cathode region 42 are not formed is defined as the drain layer 3.

  Further, the anode electrode 60 is formed on the anode contact region 54, and the cathode electrode 41 is formed on the cathode region 42.

  Even in the diode having such a configuration, there are few crystal defects in the n drift layer 3 and the carrier time constant can be sufficiently reduced. Therefore, a diode having a low element resistance can be obtained. Further, by forming the drift layer 3 with a thickness of slightly less than 100 μm to 200 μm, it is possible to ensure a withstand voltage.

  In the above embodiments, the plane orientation of the SiC substrate 12 is a plane having an off-angle from the (0001) plane, but the (0001) plane, (000-1) plane, (11-20) plane, (03- 38) In any crystal plane orientation such as a plane, an element having a small element resistance with little influence of crystal defects can be obtained.

<Effect>
The epitaxial wafer manufacturing method of the present invention has the following effects. That is, the method for producing an epitaxial wafer according to the present invention includes (a) 1 × 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻³ or less on SiC substrate 12 having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less. Since the epitaxial layer 13 having an impurity concentration is formed by epitaxial growth, crystal defects generated in the epitaxial layer 13 due to the lattice constant difference between the epitaxial layer 13 and the SiC substrate 12 are suppressed.

The epitaxial wafer manufacturing method of the present invention includes (a) 1 × 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻³ or less on SiC substrate 12 having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less. A step of forming an epitaxial layer 13 having an impurity concentration by epitaxial growth; and (b) a SiC substrate leaving a predetermined thickness of the epitaxial layer 13 from the side of the SiC substrate 12 having the structure obtained by the step (a). 12 and a part of the epitaxial layer 13 are continuously removed, so that the doping concentration of the epitaxial layer 13 can be formed at 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility. . Therefore, crystal defects that occur in epitaxial layer 13 due to the lattice constant difference between epitaxial layer 13 and SiC substrate 12 are suppressed.

Further, in the epitaxial wafer manufacturing method of the present invention, the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 having an impurity concentration of 1.5 × 10 ¹⁸ cm ⁻³ or less. The doping concentration of the epitaxial layer 13 can be formed with a reproducibility of 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ . Therefore, crystal defects that occur in epitaxial layer 13 due to the lattice constant difference between epitaxial layer 13 and SiC substrate 12 are suppressed.

In the epitaxial wafer manufacturing method of the present invention, the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 having an impurity concentration of 6 × 10 ¹⁷ cm ⁻³ or less. The layer 13 can be formed with a doping concentration of 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility. Therefore, crystal defects that occur in epitaxial layer 13 due to the lattice constant difference between epitaxial layer 13 and SiC substrate 12 are suppressed.

In the epitaxial wafer manufacturing method of the present invention, the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 to which impurities are not intentionally added. It can be formed at 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility. Therefore, crystal defects that occur in epitaxial layer 13 due to the lattice constant difference between epitaxial layer 13 and SiC substrate 12 are suppressed.

  In the epitaxial wafer manufacturing method of the present invention, since the step (a) is a step of performing epitaxial growth at 1700 ° C. or lower, generation of crystal defects due to contamination of impurities and desorption of constituent elements during the epitaxial growth is suppressed. can do.

In the epitaxial wafer manufacturing method of the present invention, since the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 doped with nitrogen at the impurity concentration, the doping of the epitaxial layer 13 is performed. It can be formed at a density of 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility. Therefore, crystal defects that occur in epitaxial layer 13 due to the lattice constant difference between epitaxial layer 13 and SiC substrate 12 are suppressed.

Since the epitaxial wafer of the present invention is manufactured by the above-described method for manufacturing an epitaxial wafer of the present invention, crystal defects are suppressed, and the doping concentration is 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility.

Since the semiconductor device of the present invention uses the above-described epitaxial wafer of the present invention as the drift layer 3, the doping concentration is 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ , and the crystal defects are suppressed. Resistance becomes smaller. It is also possible to secure a withstand voltage by the drift layer 3 having a predetermined thickness.

The first semiconductor device manufacturing method of the present invention uses the epitaxial wafer manufactured by the above-described epitaxial wafer manufacturing method as the drift layer 3 of the semiconductor device, and the step (b) in the above-described epitaxial wafer manufacturing method includes the step Since this step is to leave the epitaxial layer 13 having a predetermined thickness necessary for maintaining the breakdown voltage of the semiconductor device as the drift layer 3, the doping concentration of the drift layer 3 is 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility. By suppressing crystal defects caused by the difference in lattice constant from the SiC substrate 12, the element resistance is reduced. In addition, by forming the drift layer 3 with a predetermined thickness, it is possible to ensure a breakdown voltage.

The second method for manufacturing a semiconductor device according to the present invention includes: (a) 1 × 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻³ or less on an SiC substrate 12 having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less. And (b) selectively implanting ions into the first main surface of the epitaxial layer 13 on the opposite side of the SiC substrate 12 to form an active layer of the device. A step of forming, (c) a step of forming an electrode structure on the first main surface of the epitaxial layer 13 after the step (b), and (d) after the step (b), of the epitaxial layer 13 A step of continuously removing all of the SiC substrate 12 and a part of the epitaxial layer 13 from the side of the SiC substrate 12 while leaving a thickness necessary for maintaining the withstand voltage, and the step (d) includes the step (B) and said process It is performed during (c) or after the step (c). Regardless of the removal of part of the SiC substrate 12 and the epitaxial layer 13 and the element process, the drift layer 3 is formed with a doping concentration of 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ with good reproducibility, The element resistance can be reduced by suppressing crystal defects caused by the difference in lattice constant from the SiC substrate 12. In addition, by forming the drift layer 3 with a predetermined thickness, it is possible to ensure a breakdown voltage.

In the second method for manufacturing a semiconductor device of the present invention, the step (a) includes a step of forming the epitaxial layer 13 on the SiC substrate 12 having an impurity concentration of 1.5 × 10 ¹⁸ cm ⁻³ or less. Therefore, crystal defects generated in the epitaxial layer 13 due to the lattice constant difference between the epitaxial layer 13 and the SiC substrate 12 can be suppressed, and the element resistance of the semiconductor device using the epitaxial layer 13 as a drift layer can be reduced.

Moreover, in the second method for manufacturing a semiconductor device of the present invention, the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 having an impurity concentration of 6 × 10 ¹⁷ cm ⁻³ or less. Therefore, crystal defects generated in the epitaxial layer 13 due to the lattice constant difference between the epitaxial layer 13 and the SiC substrate 12 can be suppressed, and the element resistance of the semiconductor device using the epitaxial layer 13 as a drift layer can be reduced.

  Further, in the second method for manufacturing a semiconductor device of the present invention, the step (a) is a step of forming the epitaxial layer 13 on the SiC substrate 12 to which impurities are not intentionally added. Crystal defects generated in the epitaxial layer 13 due to the lattice constant difference of the SiC substrate 12 can be suppressed, and the element resistance of a semiconductor device using the epitaxial layer 13 as a drift layer can be reduced.

  Further, in the second method for manufacturing a semiconductor device of the present invention, since the step (a) is a step of performing epitaxial growth at 1700 ° C. or lower, crystal defects caused by contamination of impurities or desorption of constituent elements during the epitaxial growth are obtained. Occurrence can be suppressed.

  In the second method for manufacturing a semiconductor device of the present invention, the step (a) is a step of forming an epitaxial layer 13 on the SiC substrate 12 doped with nitrogen at the impurity concentration. The crystal defects generated in the epitaxial layer 13 due to the lattice constant difference between the silicon substrate 13 and the SiC substrate 12 can be suppressed, and the element resistance of the semiconductor device using the epitaxial layer 13 as a drift layer can be reduced.

  1 collector electrode, 2 collector region, 3 drift layer, 4 p body region, 5 n emitter region, 6 p contact region, 7 gate insulating film, 8 gate electrode, 9 interlayer insulating film, 10 emitter electrode, 11 emitter wiring, 22 n drain region, 23 epitaxial wafer, 25 n source region, 42 cathode region, 44 anode region.

Claims (9)

(A) 1 × 10 ¹⁴ cm ⁻³ or more and 10 ¹⁶ cm ⁻ on a SiC substrate doped with nitrogen having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or less, or on the SiC substrate to which no impurity is intentionally added. Forming an epitaxial layer doped with nitrogen having an impurity concentration of ³ or less by epitaxial growth with a layer thickness of 100 to 200 μm;
(B) From the side of the SiC substrate having the structure obtained in the step (a), the entire SiC substrate and a part of the epitaxial layer are continuously formed while leaving a predetermined thickness of the epitaxial layer. A step of removing,
Epitaxial wafer manufacturing method. The step (a) is a step of forming the epitaxial layer on the SiC substrate doped with nitrogen having an impurity concentration of 1.5 × 10 ¹⁸ cm ⁻³ or less.
The method for manufacturing an epitaxial wafer according to claim 1. The step (a) is a step of forming the epitaxial layer on the SiC substrate doped with nitrogen having an impurity concentration of 6 × 10 ¹⁷ cm ⁻³ or less.
The manufacturing method of the epitaxial wafer of Claim 2. The step (a) is a step of performing epitaxial growth at 1700 ° C. or lower.
The manufacturing method of the epitaxial wafer in any one of Claims 1-3.   A method for manufacturing a semiconductor device, comprising the method for manufacturing an epitaxial wafer according to claim 1.   (A) 3 × 10 ¹⁸ cm ^-3 On a SiC substrate doped with nitrogen of the following impurity concentration or on the SiC substrate to which no impurity is intentionally added: ¹⁴ cm ^-3 10 or more ¹⁶ cm ^-3 Forming an epitaxial layer doped with nitrogen having an impurity concentration of not more than a stand by epitaxial growth with a layer thickness of 100 to 200 μm;
  (B) selectively implanting ions into the first main surface of the epitaxial layer on the side opposite to the SiC substrate to form an active layer of the device;
  (C) after the step (b), forming an electrode structure on the first main surface of the epitaxial layer;
  (D) After the step (b), the entire SiC substrate and a part of the epitaxial layer are continuously formed from the side of the SiC substrate, leaving a thickness necessary for maintaining the breakdown voltage in the epitaxial layer. A step of removing,
  The step (d) is performed between the step (b) and the step (c) or after the step (c).
A method for manufacturing a semiconductor device.   In the step (a), 1.5 × 10 ¹⁸ cm ^-3 The step of forming the epitaxial layer on the SiC substrate doped with nitrogen of the following impurity concentration:
A method for manufacturing a semiconductor device according to claim 6.   The step (a) is 6 × 10 ¹⁷ cm ^-3 The step of forming the epitaxial layer on the SiC substrate doped with nitrogen of the following impurity concentration:
A method for manufacturing a semiconductor device according to claim 7.   The step (a) is a step of performing epitaxial growth at 1700 ° C. or lower.
The manufacturing method of the semiconductor device in any one of Claims 6-8.

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