JP4185215B2 - SiC wafer, SiC semiconductor device, and method of manufacturing SiC wafer - Google Patents

SiC wafer, SiC semiconductor device, and method of manufacturing SiC wafer Download PDF

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JP4185215B2
JP4185215B2 JP12747199A JP12747199A JP4185215B2 JP 4185215 B2 JP4185215 B2 JP 4185215B2 JP 12747199 A JP12747199 A JP 12747199A JP 12747199 A JP12747199 A JP 12747199A JP 4185215 B2 JP4185215 B2 JP 4185215B2
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substrate
buffer layer
density
active layer
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JP2000319099A (en
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弘 塩見
恒暢 木本
弘之 松波
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住友電気工業株式会社
恒暢 木本
弘之 松波
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a SiC wafer suitable for a semiconductor electronic component, a SiC semiconductor device provided with the SiC wafer, and a method for manufacturing a SiC wafer.
[0002]
[Prior art]
In recent years, research on compound semiconductors composed of light elements such as silicon carbide (SiC) or gallium nitride (GaN) has been actively conducted. Since such compound semiconductors are composed of light elements, the bond energy is strong, and as a result, the forbidden band width (band gap), dielectric breakdown electric field, and thermal conductivity are large. Taking advantage of the characteristics of this wide band gap, it is attracting attention as a material for high efficiency and high voltage power devices, high frequency power devices, high temperature operation devices, or blue to ultraviolet light emitting devices. However, due to the strong binding energy, these compounds do not melt even at high temperatures at atmospheric pressure, and it is difficult to grow bulk crystals by recrystallization of melts used in other semiconductors such as silicon (Si). .
[0003]
For example, in order to use SiC as a semiconductor material, it is necessary to obtain a high-quality single crystal having a certain size. For this reason, SiC single crystal pieces have been conventionally obtained by a method utilizing a chemical reaction called the Atchison method and a method utilizing a sublimation recrystallization method called the Rayleigh method. Recently, a SiC ingot is grown by an improved Rayleigh method in which a single crystal of silicon carbide produced by these methods is used as a substrate, and sublimation recrystallization is performed thereon, and this SiC ingot is sliced and mirror polished. It came to be manufactured. Then, an active layer with a controlled impurity density and film thickness is formed by growing a SiC single crystal of a target scale on the substrate by vapor phase epitaxy or liquid phase epitaxy, and using this, a pn junction diode, SiC semiconductor devices such as Schottky diodes and various transistors have been manufactured.
[0004]
However, among the above methods, the Atchison method heats a mixture of silica and coke in an electric furnace and precipitates crystals by spontaneous nucleation, so there are many impurities and it is difficult to control the shape and crystal plane of the crystals obtained. It is. In the Rayleigh method, the crystal grows by spontaneous nucleation, so it is difficult to control the crystal shape and crystal plane. In the modified Rayleigh method, for example, in the invention described in Japanese Patent Publication No. 59-48792, a large SiC ingot composed of a single crystal polymorph is obtained. However, such an ingot usually has a large defect called a micropipe (a small hole penetrating in the <0001> axial direction) of 1 to 50 cm. -2 Contained at a density of about. In addition, there are 10 screw dislocations with Burgers vector in the c-axis direction. Three -10 Four cm -2 Exists to a certain extent.
[0005]
Usually, a SiC {0001} plane or a substrate provided with an off angle of 3 to 8 degrees from this plane is used for epitaxial growth. At this time, it is known that most of the micropipe defects and screw dislocations existing in the substrate penetrate the SiC epitaxial growth layer, and that the device characteristics are significantly deteriorated if the SiC device manufactured using the epitaxial growth layer contains micropipe defects. It has been. Therefore, micropipe defects are the greatest barrier when manufacturing large capacity (high current, high breakdown voltage) SiC semiconductor devices with high yield. In addition, when SiC homoepitaxial growth is performed using a commonly used SiC {0001} plane or a SiC substrate having an off angle of several degrees from this plane, atomic step aggregation (step bunching) occurs on the crystal surface. easy. As the degree of step bunching increases, the surface roughness of the SiC epitaxial growth layer increases and the flatness of the metal-oxide-semiconductor (MOS) interface deteriorates. Therefore, the channel movement of the inversion layer of the MOS field effect transistor (MOSFET) The degree decreases. In addition, the flatness of the pn junction and the Schottky barrier interface deteriorates, and electric field concentration occurs at the junction interface, causing problems such as a decrease in breakdown voltage and an increase in leakage current.
[0006]
Many crystal polymorphs exist in SiC. Among them, 4H polytype (4H-SiC) has high mobility and low ionization energy of donors and acceptors, making it ideal for SiC semiconductor device fabrication. SiC polytype is considered. However, when a MOSFET is fabricated using the 4H-SiC {0001} plane or an epitaxial growth layer on the substrate having an off angle of 3 to 8 degrees from this plane, the channel mobility is 1 to 10 cm. 2 / Vs is very small, and a high-performance transistor cannot be realized.
[0007]
In order to solve these problems, in Japanese Patent Publication No. 2804860, growth is performed by an improved Rayleigh method using a seed crystal having a surface other than the (0001) plane of SiC, for example, a (1-100) plane. The SiC ingot with a small number of micropipes has been obtained. However, when epitaxial growth is performed on the SiC (1-100) plane, stacking faults are likely to occur during growth, and it is difficult to obtain a high-quality SiC single crystal sufficient for semiconductor device fabrication.
[0008]
In recent years, studies have been made on producing SiC wafers using 6H type polytype SiC (11-20) substrates in addition to SiC (1-100) substrates. If such a 6H polytype SiC (11-20) substrate is used, micropipes and screw dislocations extending in the <0001> axial direction do not reach the epitaxial layer on the substrate. Can be reduced.
[0009]
[Problems to be solved by the invention]
However, the SiC wafer using the 6H polytype SiC (11-20) substrate has the following problems. That is, when a SiC epitaxial layer is grown on a conventional SiC (11-20) substrate, distortion due to lattice mismatch occurs at the interface between the SiC epitaxial growth and the SiC substrate. This strain adversely affects the crystallinity of the epitaxial growth layer, making it difficult to produce a high-quality SiC epitaxial growth layer.
[0010]
Further, when a device is manufactured using a 6H-type polytype 6H—SiC (11-20) substrate, anisotropy of electron mobility becomes a problem. Specifically, in the 6H—SiC crystal, the electron mobility in the <0001> axis direction is as small as about 20 to 30% of the mobility in the <1-100> and <11-20> directions, and thus 6H—SiC (11 -20) In the growth layer on the plane, anisotropy of 3 to 5 times occurs in the in-plane electrical conduction.
[0011]
The present invention has been made in view of such circumstances, and when used as a semiconductor device, the anisotropy of electron mobility is small, and distortion due to lattice mismatch between the SiC substrate and the SiC epitaxial growth layer can be reduced. An object is to provide a SiC wafer, a semiconductor device including the same, and a method of manufacturing the SiC wafer.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the SiC wafer of the present invention has a plane orientation of (11-20) and is composed of a 4H type polytype or 15R type polytype SiC substrate and SiC formed on the SiC substrate. And a buffer layer.
[0013]
The SiC wafer according to the present invention uses a SiC substrate having a surface orientation of approximately (11-20). Therefore, even if an SiC active layer is epitaxially grown on the SiC wafer of the present invention, the <0001> axis of the SiC substrate Micropipes and screw dislocations extending in the direction do not reach the active layer. In addition, since a 4H-type or 15R-type polytype substrate having a lower anisotropy of electron mobility than a 6H-type polytype SiC substrate is used, the electron mobility in the active layer grown on the SiC wafer is used. Anisotropy is reduced. Furthermore, since the buffer layer made of SiC is formed on the SiC substrate, when the SiC active layer is grown on the SiC wafer of the present invention, distortion due to lattice mismatch between the SiC substrate and the SiC active layer is affected. A situation that occurs in the SiC active layer can be prevented.
[0014]
The buffer layer preferably has a thickness of 0.3 μm or more and 15 μm or less. As a result of diligent research by the present inventors, when an SiC active layer is grown on the buffer layer of the present invention and the thickness of the buffer layer is 0.3 μm or more, distortion based on lattice mismatch is effectively reduced. It has been found that the crystallinity of the SiC active layer can be improved. If the buffer layer is 15 μm or less, the growth time and cost can be reduced.
[0015]
Further, the buffer layer includes at least one of nitrogen, phosphorus, aluminum, or boron as an impurity, and the density of the impurity in the buffer layer is 2 × 10 15 cm -3 3 × 10 or more 19 cm -3 The following is preferable. The impurity density in the buffer layer is set to such a range because the impurity density is 2 × 10 10. 15 cm -3 Is less than 3 × 10, the effect of strain relaxation based on lattice mismatch becomes less. 19 cm -3 This is because the crystallinity of the buffer layer itself deteriorates due to high concentration doping.
[0016]
Moreover, it is preferable that the density of the said impurity in a buffer layer is lower than the density of the impurity in a SiC substrate. By setting the impurity density of the buffer layer in this way, when the SiC active layer is formed on the SiC wafer, the impurity density can be gradually reduced in the order of the SiC wafer, the buffer layer, and the SiC active layer.
[0017]
The SiC wafer of the present invention is further characterized by further comprising an active layer made of SiC on the buffer layer. Further, in this case, it is preferable to reduce the impurity density in the buffer layer from the interface with the SiC substrate toward the interface with the SiC active layer.
[0018]
The SiC semiconductor device of the present invention includes the above-described SiC wafer. As described above, since the SiC wafer has a small anisotropy of electron mobility and hardly causes distortion due to lattice mismatch between the SiC substrate and the SiC active layer, such a semiconductor device is of high quality.
[0019]
The SiC semiconductor device of the present invention may have a Schottky barrier formed of an SiC active layer and a metal layer on the surface, or a pn junction formed by epitaxial growth or ion implantation. Furthermore, it has an oxide film formed by thermal oxidation or chemical vapor deposition as a gate insulating film, or has an oxide film formed by thermal oxidation or chemical vapor deposition as part of the surface protection film. Also good.
[0020]
The SiC wafer manufacturing method of the present invention is characterized in that a buffer layer made of SiC is grown on a SiC substrate of a 4H type polytype or a 15R type polytype having a plane orientation of approximately (11-20). . Further, an active layer made of SiC may be further grown on the buffer layer.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a SiC wafer, a SiC semiconductor device, and a method for producing a SiC wafer according to the present invention will be described in detail with reference to the accompanying drawings. In addition, the same code | symbol shall be used for the same element and the overlapping description is abbreviate | omitted. In the description of the embodiments and examples, the lattice direction and the lattice plane of the crystal may be used, but here, the lattice direction and the symbols of the lattice plane will be described. The individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, as for the negative index, “−” (bar) is attached to the number in terms of crystallography, but a negative sign is attached before the number for the convenience of preparing the specification.
[0022]
FIG. 1 is a side view of the SiC wafer 1 of the present embodiment. The SiC wafer 1 includes a 4H-SiC (11-20) substrate 2 of a 4H type polytype (“H” means a hexagonal system, “4” means a crystal structure in which four atomic layers are stacked and one period). A buffer layer 4 made of SiC formed on the SiC (11-20) substrate 2 and an active layer 6 made of SiC for device fabrication formed on the buffer layer 4. The plane orientation of the 4H—SiC (11-20) substrate 2 may be slightly inclined from (11-20). Further, each of the layers 2 to 6 is all n-type.
[0023]
Next, the manufacturing method of the SiC wafer 1 of this embodiment is demonstrated. The 4H—SiC (11-20) substrate 2 is produced, for example, by slicing an ingot grown on the 4H—SiC (000-1) plane by a modified Rayleigh method in parallel to the growth direction and mirror polishing. At this time, the thickness of the 4H—SiC (11-20) substrate 2 is preferably in the range of about 150 μm to about 400 μm. The effective donor density is about 5 × 10 17 cm -3 ~ About 5 × 10 19 cm -3 It is preferable to be in the range.
[0024]
Next, the 4H—SiC (11-20) substrate 2 is mirror finished, and then the buffer layer 4 is formed by a chemical vapor deposition (CVD) method excellent in film thickness, impurity doping controllability, and growth layer surface flatness. Then, the active layer 6 is epitaxially grown. Specifically, after the 4H—SiC (11-20) substrate 2 is washed with an organic solvent, aqua regia, hydrofluoric acid, etc., it is rinsed with deionized water and installed on a graphite susceptor covered with a SiC film. And set in a CVD growth apparatus. Hydrogen (H for CVD growth) 2 ) Is used as a carrier gas at normal pressure, and the susceptor is heated by high frequency induction heating. After the 4H—SiC (11-20) substrate 2 is placed in the reactor, the gas replacement and the high vacuum evacuation are repeated several times. 2 Carrier gas is introduced to enter the CVD growth program.
[0025]
First, HCl / H at about 1300 ° C. 2 After performing gas phase etching with gas, the temperature of the 4H—SiC (11-20) substrate 2 is raised to about 1500 ° C., and the source gas (silane: SiH Four Propane: C Three H 8 Etc.) and the growth of the buffer layer 4 and the active layer 6 is started. For CVD growth, an effective donor density of about 10 16 cm -3 ~ About 10 19 cm -3 After growing the n-type SiC buffer layer 4 of about 0.3 μm to about 15 μm, the effective donor density is about 10 14 cm -3 ~ About 10 16 cm -3 The n-type active layer 6 is grown from about 5 μm to about 80 μm. Note that n-type conductivity control is performed by adding nitrogen gas during growth.
[0026]
Further, the thickness of the buffer layer 4 is particularly preferably 0.3 μm or more and 15 μm or less. Furthermore, the impurity contained in the buffer layer 4 is preferably any of nitrogen, phosphorus, aluminum, and boron. The impurity density in the buffer layer 4 is preferably gradually decreased from the interface with the 4H—SiC (11-20) substrate 2 toward the interface with the active layer 6.
[0027]
Next, the effect of the SiC wafer 1 of the present embodiment will be described with reference to FIG. Usually, micropipe and screw dislocation exist in the SiC substrate, but the micropipe and the like extend in the <0001> axial direction of the SiC substrate as shown in FIG. However, since the SiC wafer 1 of the present embodiment uses a SiC substrate having a surface orientation of (11-20), the micropipe (indicated by a one-dot chain line) 8 and the screw dislocation (indicated by a broken line) 10 are formed in the active layer 6. Hardly reach. For this reason, the active layer 6 has few defects and excellent flatness.
[0028]
In the present embodiment, since a 4H type polytype substrate having a lower anisotropy of electron mobility than a 6H type polytype SiC substrate or the like is used, the active layer 6 grown on the SiC wafer 1 is used. The anisotropy of electron mobility is reduced. Also, mixing of different polytypes is completely prevented. Furthermore, since the buffer layer 4 made of SiC is formed on the SiC substrate 2, it is possible to prevent the active layer 6 from being distorted due to lattice mismatch between the SiC substrate 2 and the SiC active layer 6.
[0029]
In addition, as a result of diligent research by the present inventors, by setting the thickness of the buffer layer 4 to 0.3 μm or more, distortion based on lattice mismatch can be effectively reduced, and the crystallinity of the active layer 6 is improved. Was found. On the other hand, if the buffer layer 4 is 15 μm or less, growth time and cost can be reduced.
[0030]
Furthermore, the density of impurities contained in the buffer layer 4 is 2 × 10. 15 cm -3 3 × 10 or more 19 cm -3 The following is preferable. The impurity density contained in the buffer layer 4 is set in this range because the impurity density is 2 × 10 6. 15 cm -3 Is less than 3 × 10, the effect of strain relaxation based on lattice mismatch becomes less. 19 cm -3 This is because the crystallinity of the buffer layer 4 itself deteriorates due to high concentration doping.
[0031]
In this embodiment, a 4H type polytype SiC substrate is used, but in addition to this, a 15R type polytype (“R” is a rhombohedral system, “15” is a crystal having 15 atomic layers and one cycle). Even if a 15R-SiC (11-20) substrate (which means a structure) is used, the active layer grown on the SiC wafer does not have micropipes or screw dislocations and has excellent flatness. Become.
[0032]
Moreover, various SiC semiconductor devices can be manufactured using the SiC wafer 1 of the present embodiment. For example, such a SiC semiconductor device can be configured to have a metal / SiC Schottky barrier or a pn junction formed by epitaxial growth or ion implantation on the surface. Further, an oxide film formed by thermal oxidation or chemical vapor deposition is used as a gate insulating film, or an oxide film formed by thermal oxidation or chemical vapor deposition is used as part of the surface protection film. It may be configured.
[0033]
As described above, since the SiC wafer 1 has a small anisotropy of electron mobility and hardly generates distortion due to lattice mismatch between the SiC substrate 2 and the SiC active layer 6, such a semiconductor device has a high quality. It becomes. More specifically, since the surface flatness of the active layer 6 is particularly excellent, electric field concentration at the pn junction formed by epitaxial growth or the Schottky barrier interface formed on the epitaxial growth surface is greatly reduced, and the breakdown voltage of the device is increased. It becomes easy. Furthermore, since SiC (11-20) has fewer atomic bond bonds per unit area than SiC {0001}, the interface state at the oxide / SiC MOS interface is reduced and a high-quality MOS interface can be fabricated. A high-performance MOS transistor can be realized.
[0034]
【Example】
Examples of the above embodiment will be described below. However, the present invention is not limited to the examples.
[0035]
[Example 1]
Example 1 will be described with reference to FIG. In this example, in order to investigate the micropipe and screw dislocation penetration from the SiC substrate to the SiC active layer and the flatness of the surface of the active layer 6, a chemical was formed on the n-type 4H—SiC (11-20) substrate 2. An n-type active layer 6 was grown by vapor deposition (CVD). For comparison, an active layer was simultaneously grown on a substrate whose surface direction was 4H—SiC (1-100) and (0001) 8 degrees off (<11-20> direction) and evaluated. 4H-SiC (11-20) and (1-100) substrates are produced by slicing an ingot grown on the 4H-SiC (000-1) plane by a modified Rayleigh method in parallel to the growth direction and mirror polishing. did. The substrates are all n-type, and the effective donor density obtained from the capacitance-voltage characteristics of the Schottky barrier is 1 × 10 18 cm -3 ~ 2x10 18 cm -3 The thickness was about 380 μm.
[0036]
As a result of etching these substrates with molten potassium hydroxide (KOH) at 500 ° C. for 10 minutes, the micropipe density was 12 cm. -2 ~ 28cm -2 , Screw dislocation density 5 × 10 Three cm -2 ~ 2x10 Four cm -2 It was found that there were some defects. However, with respect to the (11-20) and (1-100) planes, a slant polishing of about 80 degrees is performed on the edge of the substrate to obtain a plane inclined by about 10 degrees from the (0001) plane, and this plane is observed after etching. The defect density was estimated.
[0037]
Next, the substrate subjected to KOH etching was re-polished and mirror-finished to perform CVD growth. These substrates were washed with an organic solvent, aqua regia, and hydrofluoric acid, then rinsed with deionized water, placed on a graphite susceptor covered with a SiC film, and set in a CVD growth apparatus. And after repeating gas substitution and high vacuum exhaust several times, H 2 Carrier gas was introduced to enter the CVD growth program.
[0038]
First, HCl / H at 1300 ° C 2 After performing vapor phase etching with gas, the temperature is raised to 1500 ° C., and the source gas (silane: SiH Four Propane: C Three H 8 Etc.) and started growing. For CVD growth, the effective donor density is 3 × 10. 17 cm -3 ~ 4x10 17 cm -3 After growing an n-type SiC buffer layer of 4.6 μm, an effective donor density of 1 × 10 16 cm -3 ~ 2x10 16 cm -3 The n-type active layer was grown to 12 μm. The main growth conditions at this time are as follows. In general, since the impurity incorporation efficiency differs between the (0001) plane and the (11-20) plane, it is preferable to adjust the doping gas flow rate according to the plane orientation of the substrate.
[0039]
When the surface of the epitaxially grown active layer 6 was observed with a differential interference optical microscope, a mirror surface was obtained on the 4H (11-20) and (0001) 8 degrees off substrates, but on the 4H (1-100) substrate. Particulate irregularities and grooves running partially in the <11-20> direction were observed. This streak defect on the 4H (1-100) plane is also observed in the growth layer on the 6H (1-100) plane, and optimization of the substrate surface treatment method before growth and growth conditions with low supersaturation (for example, When CVD growth is performed at a low raw material gas flow rate, the generation of the streak defects is somewhat reduced, but cannot be completely eliminated. Further, when the surface of the active layer on the 15 mm × 20 mm substrate was observed to estimate the density of surface defects (not necessarily coincident with structural defects such as dislocations), the density of 4H (11-20) substrate was 4 ×. 10 2 cm -2 , (1-100) substrate 8 × 10 Three cm -2 , (0001) 8 degrees off substrate 2 × 10 Three cm -2 The active layer on the 4H (11-20) substrate was the most excellent.
[0040]
FIG. 3 is a graph showing the result of measuring the surface shape profile by performing atomic force microscope (AFM) observation. The surface of the active layer formed on the (1-100) substrate has severe irregularities as shown in FIG. 3B, even if the region without the deep groove (depth of about 100 to 300 nm) is selected. It has become. Further, from FIG. 3C, it was found that the surface of the active layer formed on the (0001) 8 degrees off substrate has stepped irregularities due to atomic step aggregation (step bunching). . In contrast, in the active layer formed on the 4H (11-20) substrate, no grooves, hillocks, steps, etc. are observed as shown in FIG. A good surface was obtained. In addition, the root mean square (Rms) of the surface roughness when AFM observation is performed in the range of 2 μm × 2 μm is 0.18 nm for the active layer formed on the (11-20) substrate, and 6.2 on the (1-100) substrate. The active layer grown on the (11-20) substrate was the most excellent, with 4 nm, 0.24 nm on the (0001) 8 degree off substrate.
[0041]
Next, the grown sample was etched with molten KOH, and structural defects in the active layer 6 were examined. In the active layer on the (0001) 8 degree off substrate, the micropipe density is 18 cm. -2 , Screw dislocation density 8 × 10 Three cm -2 Thus, it was almost the same as the value of the substrate before the growth, and the positions of the pits generated by the etching were in good agreement with those before the growth. When the active layer on the (1-100) substrate is etched, a large number of polygonal pits (1 × 10 6 Five cm -2 In addition to the above, streak defects appearing on the surface of the active layer became deeper. Since these streak-like grooves always extend in the <11-20> direction, it is considered to be caused by stacking faults. The number of grooves deeply etched by the molten KOH is 3-8 cm in the (1-100) substrate before growth. -1 It was 30-200cm after growth -1 It was increasing. Therefore, when an active layer is grown on a (1-100) substrate, it is considered that a stacking fault is newly generated by CVD growth.
[0042]
On the other hand, when the active layer grown on the (11-20) substrate is etched with molten KOH, the density of triangular pits reflecting dislocations is 2 × 10. Three cm -2 Degree, stacking fault density is 5cm -1 It was as small as below. In addition, the micropipe density estimated by etching the obliquely polished surface of this sample is 1 cm. -2 Less than, screw dislocation density is also 100cm -2 Was found to be less than. That is, by using a 4H—SiC (11-20) substrate, it is possible to significantly suppress the penetration of micropipes and screw dislocations from the substrate and to produce a high-quality SiC epitaxial crystal with extremely few stacking faults. This is because, as described above, since micropipes and screw dislocations mainly extend in the <0001> direction of the SiC crystal (see FIG. 2), if the (11-20) plane that is parallel to this orientation is used, This is because micropipes and the like existing in the SiC substrate are not carried over to the active layer above. Even when the active layer on the 15R-SiC (11-20) substrate was epitaxially grown, the active layer had excellent flatness, and there was almost no penetration of micropipes or screw dislocations.
[0043]
[Example 2]
In this example, in order to investigate the influence of the buffer layer on the active layer, after forming the n-type 4H—SiC buffer layer of various thicknesses on the n-type 4H—SiC (11-20) substrate, the active layer A high-purity thick film epitaxially grown layer was formed and its crystallinity was evaluated. The SiC substrate 2 used was n-type 4H—SiC (11-20) produced by slicing a 4H—SiC ingot grown on a 4H—SiC (11-20) seed crystal by a modified Rayleigh method. The effective donor density determined from the capacitance-voltage characteristics of the barrier is 3 × 10 18 cm -3 ~ 4x10 18 cm -3 The thickness was about 340 μm.
[0044]
On this SiC substrate 2, the donor density is 4 × 10. 17 cm -3 ~ 5x10 17 cm -3 After forming an n-type 4H—SiC buffer layer, a high-purity n-type 4H—SiC layer (donor density 4 × 10 15 cm -3 ) Was grown about 24 μm. Note that n-type conductivity control was performed by adding nitrogen gas during growth. Then, an SiC wafer in which the thickness of the buffer layer was changed in the range of 0.1 μm to 22 μm, and an SiC wafer in which a high-purity SiC active layer was directly grown on the substrate without providing the buffer layer for comparison were prepared. . The same CVD apparatus as in Example 1 was used for CVD growth. First, HCl / H at 1400 ° C 2 After performing vapor phase etching with gas, the temperature was raised to 1560 ° C., and a raw material gas was introduced to start growth. The growth conditions at this time are as follows.
[0045]
FIG. 4 is a graph showing the buffer layer thickness dependence of the half-value width (FWHM) of the diffraction peak obtained from the X-ray diffraction rocking curve measurement of the active layer 6 of the SiC wafer having buffer layers of various thicknesses. . For X-ray diffraction, 5-crystal X-ray diffraction using Ge single crystal (400) diffraction was used, and the crystallinity of the sample was evaluated with the half width of the SiC (11-20) diffraction peak (2θ = 60.05 degrees). Note that the half width of the diffraction peak obtained by measuring the 4H—SiC (11-20) substrate before growth was 32 to 38 arcsec (average 35 arcsec).
[0046]
In the active layer 6 of the SiC wafer in which the high-purity n-type SiC layer (24 μm) was directly grown on the substrate without using the buffer layer, the half width of the X-ray rocking curve was 52 arcsec, which was worse than that of the SiC substrate 2 (FIG. 4). Middle, indicated by square marks). This problem could be improved by introducing an n-type buffer layer. That is, when the buffer layer thickness is 0.1 μm, a half-value width (43 arcsec) still slightly worse than that of the substrate is obtained, but when the buffer layer thickness is 0.3 μm or more, the half-value width smaller than the substrate is obtained. It was found that the crystallinity was improved by epitaxial growth. In particular, when the thickness of the buffer layer is about 1.2 μm or more, the full width at half maximum is almost constant at 21 arcsec. When the dislocation density on the (11-20) plane is evaluated by molten KOH etching, 6 × 10 Four cm -2 2 × 10 for active layer grown without buffer layer Five cm -2 In the active layer provided with a buffer layer of 2 μm or more, 3 × 10 Three cm -2 ~ 6 × 10 Three cm -2 After all, the effect of the buffer layer was clearly seen.
[0047]
Thus, the reason why the buffer layer is effective for the production of a high-quality SiC epitaxial growth layer is that the lattice mismatch exists between the SiC substrate doped with a high impurity concentration and the high-concentration SiC active layer doped with a low concentration. This is presumably because the resulting distortion is alleviated by the buffer layer. Generally 10 18 cm -3 In a SiC crystal containing impurities of a degree or more, the lattice constant of the SiC crystal increases or decreases depending on the type of the impurity, and the rate of increase / decrease of the lattice constant is the {0001} plane on the (11-20) plane. Greater than above. Therefore, when epitaxial growth is performed on a 4H—SiC (11-20) substrate, a SiC buffer layer having an impurity density that is an intermediate value between the impurity densities of the substrate and the active layer for device fabrication formed thereon is provided. Therefore, it is effective to relieve lattice distortion caused by lattice mismatch.
[0048]
Normally, when manufacturing a vertical power device, a substrate doped with impurities (donor or acceptor) at a high concentration is used in order to reduce the resistance of the substrate. Therefore, the active layer is lower than the impurity density of this substrate. It is preferable to provide a SiC buffer layer doped with a higher impurity density. In the above examples, nitrogen (N) -doped n-type SiC was used, but experiments were performed using phosphorus (P) -doped n-type SiC, aluminum (Al), and boron (B) -doped p-type SiC. However, the same effect of the buffer layer was observed. Moreover, the same effect was able to be acquired even if it used the 15R-SiC (11-20) board | substrate.
[0049]
[Example 3]
In this example, the effect was examined by changing the impurity density in the buffer layer 4 while keeping the thickness of the buffer layer 4 constant (3 μm). As the substrate, an n-type 15R—SiC (11-20) substrate having a size of 10 mm × 15 mm is used, and an effective donor density is 5 × 10. 18 cm -3 The thickness was 350 μm. Then, after forming a 3 μm thick buffer layer 4 having a nitrogen donor density distribution shown in FIGS. 5A to 5C on this SiC substrate, a donor density of 5 × 10 14 cm -3 A high-purity n-type 15R—SiC active layer 6 having a thickness of 32 μm was epitaxially grown. For comparison, an SiC wafer without the buffer layer 4 (hereinafter referred to as “sample (d)”) was also produced as shown in FIG. In the SiC wafer (sample (a)) shown in FIG. 5A, the donor density in the buffer layer is 5 × 10 5. 17 cm -3 In contrast, the donor density is increased stepwise in the SiC wafer (sample (b)) shown in FIG. 5 (b) and in a gradient in the SiC wafer (sample (c)) shown in FIG. 5 (c). Changed. The main growth conditions are as follows.
[0050]
FIG. 6 shows the results of measuring rocking curves of X-ray diffraction for these samples (a) to (d) in the same manner as in Example 2. In the sample (d) without the buffer layer, the mosaicity of the active layer is increased due to the lattice mismatch between the active layer and the substrate, and the half-value width of the rocking curve is 86 arcsec, which is larger than the substrate (43 arcsec). On the other hand, in the sample (a) having a buffer layer with a constant doping density, the half width is 35 arcsec, and the crystallinity is improved from that of the substrate. Further, in samples (b) and (c) in which the donor density was gradually decreased inside the buffer layer, the half-value width was 28 to 31 arcsec, and a slightly better result was obtained than in sample (a). Thus, it has become clear that it is most effective to provide the buffer layer 4 in which the impurity density is gradually reduced from the SiC substrate 2 to the active layer 6. It should be noted that no significant difference was observed when the impurity density distribution inside the buffer layer 4 was decreased stepwise and continuously (linearly).
[0051]
[Example 4]
In this example, a high breakdown voltage diode shown in FIG. 7 was manufactured using a SiC wafer using a 4H—SiC (11-20) substrate and a (0001) 8 ° off-substrate. The SiC substrate 2 was produced by slicing an ingot grown on a 4H—SiC (000-1) seed crystal by a modified Rayleigh method in parallel to the growth direction and mirror polishing. Both substrates are n-type, and the effective donor density obtained from the capacitance-voltage characteristics of the Schottky barrier is 6 × 10. 18 cm -3 The thickness was about 340 μm. Then, a nitrogen-doped n-type 4H—SiC layer was epitaxially grown on the SiC substrate 2 by the CVD method.
[0052]
Similar to sample (b) of Example 3, 3 × 10 18 cm -3 To 1 × 10 16 cm -3 The buffer layer 4 having a total thickness of about 11.5 μm was formed while changing the donor density stepwise until a total of about 11.5 μm was formed, and then a high-purity n-type 4H—SiC layer serving as the active layer 6 was grown. The donor density of the active layer is 6 × 10 15 cm -3 The film thickness is 16 μm. A sample without a buffer layer was also prepared for comparison. Similarly, a buffer layer and an active layer were grown on a 4H—SiC (0001) 8 ° off-substrate to produce a SiC wafer. The main growth conditions are as follows.
[0053]
Further, the Schottky electrode 12 and the ohmic electrode 14 were formed on each SiC wafer thus produced. The Schottky electrode 12 was formed on the upper surface of the active layer 6, and the ohmic electrode 14 was formed on the lower surface of the SiC substrate 2. Further, titanium (Ti: 180 nm) was used for the Schottky electrode 12, and nickel (Ni: 200 nm) subjected to heat treatment at 1000 ° C. for 20 minutes was used for the ohmic electrode 14 on the back surface. Further, the Schottky electrode 12 was circular and was changed in the range of 100 μm to 3 mm in diameter.
[0054]
Then, in order to alleviate electric field concentration at the end of the Schottky electrode 12, boron (B) ions were implanted to form a high resistance p-type region (guard ring) 16 to complete the Schottky diode. Boron ions are implanted in four stages of 120 keV, 80 keV, 50 keV, and 30 keV, and the total dose is 3 × 10. 13 cm -2 It was. The width of the p-type region 16 forming the guard ring is 100 μm, and the width of the overlapping portion of the p-type region 16 and the Schottky electrode 12 is 10 μm. Further, ion implantation was performed at room temperature, and heat treatment (annealing) for activating the implanted ions was performed in an argon gas atmosphere at 1550 ° C. for 30 minutes. Photolithographic techniques were used for patterning these selective ion implantation masks and electrode metals.
[0055]
FIG. 8 is a graph showing typical current density-voltage characteristics of the manufactured Schottky diode. This is a diode made of a SiC wafer grown by providing a buffer layer on a 4H—SiC (11-20) substrate, and has an electrode diameter of 500 μm. In reverse characteristics, a withstand voltage of 2100 V is achieved, and the leakage current when applying -1000 V is 6 × 10 -6 A / cm 2 And small. In forward characteristics, the on-voltage (current density 100 A / cm 2 Voltage drop) is 1.2V, ON resistance is 4 × 10 -3 Ωcm 2 A very excellent characteristic was obtained. The same diode characteristics were obtained even on a 4H—SiC (0001) 8 ° off-substrate with a small diode with an electrode area of 300 μm or less, but a large difference was observed between the diodes with a large electrode area.
[0056]
FIG. 9 shows SiC with active layers grown on a total of three types of SiC substrates: a 4H—SiC (11-20) substrate (with and without a buffer layer) and a 4H—SiC (0001) 8 ° off substrate. It is a graph which shows the electrode area dependence of the proof pressure (average value) of the Schottky diode produced using the wafer. For each electrode area, at least 12 diodes were measured to determine the average withstand voltage. In the Schottky diode manufactured using the growth layer on the 4H—SiC (0001) 8 ° off substrate, the electrode area is 5 × 10 5. -3 cm 2 ~ 1x10 -2 cm 2 If it exceeds, the pressure resistance will drop rapidly. Even in the case of a 4H—SiC (11-20) substrate, the electrode area is 1 × 10 when the buffer layer is not provided. -2 cm 2 Larger diodes have a lower breakdown voltage.
[0057]
On the other hand, when an epitaxial growth layer produced by providing a buffer layer on a 4H—SiC (11-20) substrate is used, 5 × 10 5 is used. -2 cm 2 Even with an electrode area of about a high pressure resistance, 0.07 cm 2 Even in this case, a breakdown voltage of 1500 V or more was obtained with a yield of 40% or more. Further, when comparing the average value of the leakage current density when applying −1000 V in addition to the withstand voltage with a diode having an electrode diameter of 500 μm, a diode fabricated on a 4H—SiC (0001) 8 degree off substrate has an 8 × 10 8. -Five A / cm 2 6 × 10 with a diode on the (11-20) plane without the buffer layer -Five A / cm 2 In contrast, the diode on the (11-20) plane provided with the buffer layer is 1 × 10 -Five A / cm 2 And was the smallest.
[0058]
This is because the use of the 4H—SiC (11-20) plane suppresses the penetration of micropipes and screw dislocations from the SiC substrate to the active layer, and the use of the buffer layer yields a high-quality SiC crystal. it is conceivable that. Further, the use of the 4H—SiC (11-20) plane improves the flatness of the growth surface, and has the effect of reducing the electric field concentration at the Schottky electrode / SiC interface. In this embodiment, an example of manufacturing a Schottky diode has been described. However, even in the case of a pn junction diode or thyristor formed by epitaxial growth or ion implantation, a 4H-SiC (11-20) substrate or 15R-SiC (11 -20) It is effective to use a substrate.
[0059]
[Example 5]
In this example, an n-channel inversion MOSFET 20 shown in FIG. 10 was produced using a SiC wafer formed of a (11-20) substrate and a (0001) off substrate. The SiC substrate 2 used was prepared by slicing an ingot grown by the modified Rayleigh method and mirror polishing (1) 6H-SiC (0001) 3.5 degree off substrate, (2) 6H-SiC (11- 20) substrate, (3) 4H-SiC (0001) 8 degree off substrate, (4) 4H-SiC (11-20) substrate, (5) 15R-SiC (0001) 3.5 degree off substrate, and (6 ) 15R-SiC (11-20) substrate.
[0060]
The SiC substrate 2 is all p-type, and the effective acceptor density obtained from the capacitance-voltage characteristics of the Schottky barrier is 2 × 10 18 cm -3 ~ 5x10 18 cm -3 The thickness is 320 μm to 340 μm. Then, a boron-doped p-type SiC layer was epitaxially grown on each SiC substrate 2 by the CVD method. First, similarly to the sample (b) of Example 3, 8 × 10 17 cm -3 To 1 × 10 16 cm -3 The buffer layer 4 having a total thickness of about 1.6 μm was formed while changing the acceptor density stepwise until about 0.4 μm for each layer, and then a high-purity p-type SiC layer serving as the active layer 6 was grown. The acceptor density of the active layer 6 is 5 × 10 15 cm -3 The film thickness is 5 μm. The main growth conditions are as follows.
[0061]
The low resistance n-type regions 22 and 24 were formed by implanting nitrogen (N) ions into the SiC wafer thus fabricated in order to form source and drain regions. N ion implantation is performed in four stages of 140 keV, 80 keV, 50 keV, and 25 keV, and the total dose is 8 × 10. 14 cm -2 It was. The ion implantation was performed at room temperature, and the heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1450 ° C. for 30 minutes. Next, the insulating layer 26 was formed on the SiC wafer 1 by dry oxidation. The oxidation conditions are 1150 ° C. for 3 hours when using a SiC (0001) off substrate, 1150 ° C. for 1 hour for a SiC (11-20) sample, and the thickness of the insulating layer 26 is 35 to 46 nm. is there.
[0062]
Next, the source electrode 28 and the drain electrode 30 were formed on the n-type regions 22 and 24, respectively. Aluminum / titanium (Al: 250 nm, Ti: 30 nm) was used for the source electrode 28 and the drain electrode 30 and heat treatment was performed at 800 ° C. for 60 minutes. Further, an Al gate electrode 32 (thickness 200 nm) is formed on the insulating layer 26, and then a forming gas (H 2 / N 2 ) At 450 ° C. for 10 minutes. Photolithographic techniques were used for patterning these selective ion implantation masks and electrode metals.
[0063]
The channel length of the MOSFET 20 is 30 μm and the channel width is 200 μm. Furthermore, in the case of fabricating a MOSFET on the SiC (11-20) plane, the drain current flows in the <0001> direction or the <1-100> direction in consideration of the plane orientation.
[0064]
FIG. 11 is a graph showing typical drain characteristics of the fabricated MOSFET. This is a characteristic of a MOSFET in which an active layer grown on a 4H—SiC (11-20) substrate is used and the channel is parallel to the <0001> axis. A linear region and a saturation region are clearly observed, and the MOSFET operates normally as a normally-off type MOSFET that is turned off at the time of zero gate bias. Even with MOSFETs using other samples, all FET operations were confirmed, but there were differences in channel mobility and threshold voltage.
[0065]
FIG. 12 shows an average value of effective channel mobility obtained from the linear region for each MOSFET. At least 6 MOSFETs or more were evaluated for each sample, channel mobility was measured, and the average was obtained. For MOSFETs fabricated on a SiC (11-20) substrate, the channel mobility (μ //) parallel to <0001> and the <1-100> direction (direction perpendicular to the <0001> axis) The channel mobility (μ⊥) was obtained and the ratio was also shown.
[0066]
As can be seen from FIG. 12, when 6H—SiC, 4H—SiC, and 15R—SiC are compared in μ⊥, the MOSFET fabricated on the (11-20) plane is better than the MOSFET fabricated on the (0001) off-substrate. High channel mobility is obtained. The reason for this is that the (11-20) active layer 6 on the substrate has reduced surface roughness due to step bunching, an extremely flat MOS interface is obtained, and scattering due to surface roughness is reduced. Can be considered. Further, when the (0001) substrate and the (11-20) substrate are compared, the number of SiC bond bonds per unit area is smaller on the (11-20) plane, so that it is formed at the MOS interface when the oxide film is formed. It can be mentioned that the interface state density is smaller in the (11-20) plane.
[0067]
Next, when the characteristics are compared for each polytype, the μ⊥ is 74 cm in the MOSFET on the 6H—SiC (11-20) substrate. 2 / Vs is relatively high, but μ // is 22cm 2 As small as / Vs. This is the same tendency as the anisotropy of the electron mobility in the 6H—SiC bulk, so it is considered that the effective mass and the anisotropy of the scattering factor have an influence. In any case, such a device that exhibits an electrical conductivity anisotropy of 3 times or more in the plane is not desirable. In the case of 4H—SiC, the channel mobility is 8.4 cm in the MOSFET on the (0001) 8 ° off-substrate. 2 / Vs is very small, but on the (11-20) substrate, μ⊥ = 46 cm 2 / Vs, μ // = 55cm 2 / Vs, a relatively good value and a small anisotropy. On the other hand, in the MOSFET on the 15R-SiC (11-20) substrate, μ⊥ = 76 cm. 2 / Vs, μ // = 64cm 2 / Vs, which was higher than 4H—SiC. From the above results, since the MOMOSFET manufactured on the 4H-SiC (11-20) or 15R-SiC (11-20) substrate has high channel mobility and low anisotropy, a high performance MOSFET, IGBT ( Insulated Gate Bipolar Transistor) and MOS gate thyristors are effective.
[0068]
Here, the insulating layer 26 for the gate electrode is formed by thermal oxidation, but SiO 2 is formed by the CVD method. 2 Even when a film is deposited, it is effective to use 4H—SiC or 15R—SiC (11-20). In this example, an inversion type MOSFET was fabricated in order to investigate the characteristics of the MOS interface. However, when 4H—SiC or 15R—SiC (11-20) is used, good oxide film / SiC interface characteristics can be obtained. It can also be applied to device fabrication. For example, when a surface protective film having an oxide film as a first layer is formed on a SiC semiconductor device by thermal oxidation or chemical vapor deposition, it is very stable and interface characteristics with a low carrier generation rate at the interface can be obtained. .
[0069]
【The invention's effect】
As described above, according to the SiC wafer according to the present invention, since the SiC substrate having a plane orientation of (11-20) is used, even if the SiC active layer is epitaxially grown on the wafer, the SiC substrate <0001. > Micropipes and screw dislocations extending in the axial direction do not reach the active layer. In addition, since a 4H-type or 15R-type polytype substrate having a lower anisotropy of electron mobility than a 6H-type polytype SiC substrate is used, the electron mobility in the active layer grown on the SiC wafer is used. Anisotropy is reduced. Furthermore, since the buffer layer made of SiC is formed on the SiC substrate, when the SiC active layer is grown on the wafer, distortion due to lattice mismatch between the SiC substrate and the SiC active layer is caused in the SiC active layer. The situation that occurs can be prevented.
[Brief description of the drawings]
FIG. 1 is a view showing a SiC wafer of the present invention.
FIG. 2 is a diagram showing micropipes and screw dislocations in a SiC substrate.
FIG. 3 is a diagram showing a surface state of an SiC active layer grown on a different SiC substrate.
FIG. 4 is a graph showing the relationship between the buffer layer thickness and the X-ray rocking curve FWHM.
FIG. 5 is a view showing a SiC wafer including buffer layers having different impurity densities.
FIG. 6 is a graph showing an X-ray rocking curve of an SiC active layer formed on a 15R-SiC (11-20) substrate.
FIG. 7 is a diagram showing a SiC Schottky diode of the present invention.
FIG. 8 is a diagram showing current-voltage characteristics of a Schottky diode fabricated using a SiC active layer grown on a 4H—SiC (11-20) substrate.
FIG. 9 is a graph showing the relationship between the electrode area and the breakdown voltage of a 4H—SiC Schottky diode.
FIG. 10 is a diagram showing a MOSFET of the present invention.
FIG. 11 is a diagram showing current-voltage characteristics of a MOSFET fabricated using a SiC active layer grown on a 4H—SiC (11-20) substrate.
FIG. 12 is a table showing channel mobility of MOSFETs fabricated using a plurality of SiC substrates.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... SiC wafer, 2 ... SiC substrate, 4 ... Buffer layer, 6 ... Active layer, 8 ... Micropipe, 10 ... Spiral dislocation, 12 ... Schottky electrode, 14 ... Ohmic electrode, 26 ... Insulating layer, 28 ... Source Electrode, 30 ... drain electrode, 32 ... gate electrode.

Claims (7)

  1. The plane orientation is (11-20) , 4H type polytype or 15R type polytype SiC substrate,
    A buffer layer made of SiC formed on the SiC substrate;
    An active layer made of SiC provided on the buffer layer;
    Equipped with a,
    The buffer layer has a thickness of 0.3 μm or more and 15 μm or less;
    The buffer layer includes at least one of nitrogen, phosphorus, aluminum, or boron as an impurity,
    The density of the impurities in the buffer layer is 2 × 10 15 cm −3 or more and 3 × 10 19 cm −3 or less,
    The density of the impurity in the buffer layer is lower than the density of the impurity in the SiC substrate,
    The density of the impurities in the buffer layer decreases from the interface with the SiC substrate toward the interface with the active layer made of SiC.
    SiC wafer.
  2. A SiC semiconductor device comprising the SiC wafer according to claim 1 .
  3. The SiC semiconductor device according to claim 2 , wherein a metal layer is provided on a surface of the active layer made of SiC, and a Schottky barrier is formed by the active layer and the metal layer.
  4. 3. The SiC semiconductor device according to claim 2, which has a pn junction formed by epitaxial growth or ion implantation.
  5. 3. The SiC semiconductor device according to claim 2, comprising an oxide film formed by thermal oxidation or chemical vapor deposition as a gate insulating film.
  6. 3. The SiC semiconductor device according to claim 2, comprising an oxide film formed by thermal oxidation or chemical vapor deposition as part of the surface protective film.
  7. The 4H polytype or 15R polytype SiC substrate with a plane orientation (11-20), Rukoto grown a buffer layer composed of SiC,
    Further growing an active layer made of SiC on the buffer layer;
    Including
    The buffer layer has a thickness of 0.3 μm or more and 15 μm or less;
    The buffer layer includes at least one of nitrogen, phosphorus, aluminum, or boron as an impurity,
    The density of the impurities in the buffer layer is 2 × 10 15 cm −3 or more and 3 × 10 19 cm −3 or less,
    The density of the impurity in the buffer layer is lower than the density of the impurity in the SiC substrate,
    The density of the impurities in the buffer layer decreases from the interface with the SiC substrate toward the interface with the active layer made of SiC;
    A method for manufacturing a SiC wafer.
JP12747199A 1999-05-07 1999-05-07 SiC wafer, SiC semiconductor device, and method of manufacturing SiC wafer Expired - Lifetime JP4185215B2 (en)

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