JP2002280394A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a satisfactory device the leakage current of which is low, using an epitaxial film on a (11-20) or (1-100) plane of a silicon carbide(SiC) substrate. SOLUTION: The field effect transistor is formed on a p-type silicon carbide substrate 11 or a p-type silicon carbide substrate, having a p-type silicon carbide buffer layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a silicon carbide (SiC)
The present invention relates to a field effect transistor formed on a conductive layer formed on a single crystal substrate by epitaxial growth or ion implantation.

[0002]

2. Description of the Related Art Silicon carbide (SiC) has attracted attention as an environment-resistant semiconductor material because it has excellent heat resistance and mechanical strength and is physically and chemically stable. In recent years, SiC has been used as a substrate wafer for high-frequency high-voltage electronic devices and the like.
Demand for single crystal wafers is increasing.

When a power device, a high-frequency device, or the like is manufactured using a SiC single crystal wafer, a SiC thin film is usually epitaxially grown on the wafer by a method called thermal CVD (thermal chemical vapor deposition). Generally, a dopant is directly implanted by an ion implantation method. At this time, as the plane orientation of the SiC wafer, a (0001) plane or a (000-1) plane is usually used. On these planes, threading dislocations called micropipes are present at about 50 to 100 / cm ^2. In addition, not only in the ion implantation method but also in the epitaxial growth,
The micropipe is taken over as it is.

[0004] It is known that a device formed on a micropipe has deteriorated characteristics (for example, T.I.
Kimoto et al. , IEEE Tran.
Electron. Devices 46 (3)
pp. 471-474, 1999), and reduction of micropipes is urgently needed. On the other hand, Takahashi
Have shown that micropipes do not exist in the SiC crystal grown in the <1-100> direction or the <11-20> direction (J. Takahashi et al.).
l. , J. et al. Cryst. Growth 135,
1994), and furthermore, a prototype of a MOS device is manufactured using an epitaxial thin film grown on a wafer having a (11-20) plane. Electron mobility about 2
0 times (H. Yano et. Al,
Mater. Sci. Forum 338-34
(2, 2000), attention has been paid to an epitaxial thin film grown on a wafer having a (11-20) plane.

However, in the case of 6H-SiC, <1
(1-100) of SiC crystal grown in −100> direction
In the plane, about 1000 times the (000-1) plane, <1
(11-20) of the SiC crystal grown in the <1-20> direction
There is also a defect called stacking fault about 100 times on the surface, and the stacking fault is also present in 4H-SiC, although it is about 1/10 of the case of 6H.

[0006] Even if epitaxial growth is performed on such a wafer, stacking faults are considered to be inherited, and there is a concern that devices formed on these surfaces may be adversely affected. In the case of 6H-SiC, <1-
(1-100) plane of the SiC crystal grown in the <100> direction and (11-100) of the SiC crystal grown in the <11-20> direction.
In the (−20) plane, the current value is anisotropic, and in the direction in which the stacking fault exists (<11−20 in the (1-100) plane).
The current is likely to flow in the <> direction (the <1-100> direction in the (11-20) plane), and the ratio of the current value to the direction perpendicular thereto is about two to three digits.

[0007] This is because stacking faults become linear traps, and when electrons are trapped therein, a depletion layer is formed around them and the potential increases, so that the flow of electrons across the direction of stacking faults is reduced. This is because it is a barrier.

Next, the effect of the stacking fault on the device will be described with reference to FIG. FIG. 1A is a top view of a general field-effect transistor, and FIG. 1B is a cross-sectional view. It is also assumed that it is formed on the (11-20) plane.

In the figure, 1 is a source electrode, 2 is a drain electrode, and 3 is a gate electrode. A current must flow easily between the source and the drain, and the direction (arrow in the figure) is <1-100>. Direction. In the sectional view, reference numeral 4 denotes an SiC wafer, 5 denotes an epitaxially grown SiC buffer layer (non-doped layer), and 6 denotes an epitaxially grown SiC active layer (doped layer).

As can be seen from FIG. 1, a part of the source electrode and a part of the drain electrode are formed on the buffer layer. A current hardly flows in a buffer layer which is usually non-doped, and the source electrode and the drain electrode on the buffer layer must be insulated from each other.

However, in the case of FIG. 1, considering the direction indicated by A, the direction becomes the same <1-100> direction as the direction of the stacking fault. In this case, the electrons trapped by the stacking fault are buffered. The layer functions as a leak path in the layer, and a considerable current flows even in the buffer layer. This phenomenon is
Since the distance between the source and the drain must be in the <1-100> direction, it cannot be avoided. Further, as described above, since the stacking fault is an electron trap, when a high electric field is applied, electrons may be extracted from the trap and avalanche amplification may occur. These become uncontrollable source-drain currents, are observed as leak currents, and degrade device characteristics.

The result of the above-mentioned Yano et al. Is a result of using a (11-20) plane wafer obtained by so-called longitudinally cutting a SiC single crystal grown in the c-axis direction in parallel with the c-axis.
In this case, since there is almost no stacking fault in the wafer, there is no need to consider the effect.

However, a large diameter (1-1)
In order to obtain a wafer having a (00) plane or a (11-20) plane, it is necessary to increase the length of Si in the c-axis direction by at least the same length as the diameter of the wafer.
It is technically difficult to grow C and make it thicker.

Then, the (1-100) plane or (11)
-20) A wafer having a projected surface is used as a seed crystal, and <1-
It is realistic to grow a single crystal by growing the diameter in the 100> direction or the <11-20> direction, and to prepare a wafer from this, but in this case, the problem of stacking faults is inevitable as described above. It is.

Therefore, (1-10) of the SiC crystal grown in the <1-100> direction or the <11-20> direction.
On the (0) plane or the (11-20) plane, and on the plane on which those planes are epitaxially grown, there is no micropipe, the electron mobility of the MOS is improved, and both the yield and the element characteristics are improved. However, the problem is how to avoid the influence of leakage current due to stacking faults.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to provide a SiC field effect transistor which has solved the problem of the leakage current caused by the stacking fault.

[0017]

According to the present invention, there is provided a method for manufacturing a computer comprising:
When a device is formed on the (1-100) plane or the (11-20) plane of the SiC crystal grown in the> direction or the <11-20> direction, and further, on the plane epitaxially grown on those planes, The inventors have found that the above problem can be solved by considering the conductivity type of the buffer layer and have completed the invention.

That is, the present invention relates to (1) a field-effect transistor formed on a p-type silicon carbide substrate or a silicon carbide substrate having a p-type silicon carbide buffer layer, and (2) the p-type silicon carbide substrate. Alternatively, the field effect transistor according to (1), wherein the doping density of the p-type silicon carbide buffer layer is 2 × 10 15 cm −3 or more, and (3) the silicon carbide substrate has a (11-20) plane or ( 1-
100) The field-effect transistor according to (1) or (2), which is a plane.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the (1-100) plane or the (11-20) plane of a SiC crystal grown in the <1-100> or <11-20> direction, When a device is formed on the surface on which epitaxial growth has been performed, a p-type SiC substrate or a p-type SiC buffer layer epitaxially grown is used.

The inventors have found that electrons trapped by stacking faults function as a leak path in the buffer layer, and when a high electric field is applied, the electrons are extracted from the traps and avalanche amplification causes a larger leak. Therefore, it was considered that electrons trapped in stacking faults should be compensated. Therefore, the substrate or the buffer layer grown epitaxially is doped with an impurity which becomes p-type in SiC.

By actually changing the p-type doping density
When the device was prototyped, the doping density was 1
× 10¹⁵cm^-3Below, the leakage current is still large and 2 ×
10 ¹⁵cm^-3As described above, the leakage current becomes the normal (00
01) substrate or epitaxially grown buffer
2 × 10¹⁵cm^-3Works
The lower limit of the carrier density at which fruit was observed was set. Also, the current
The doping density of the flowing layer (n-type) is usually 1 × 10¹⁷
cm^-3Therefore, the p-type doping density is
To the extent that n-type is not compensated, for example, 5 × 10¹⁶cm^-3Is the upper limit
Becomes

[0022]

(Embodiment) FIG. 2 shows a SiC grown in the <11-20> direction to form a field-effect transistor.
It is sectional drawing of the board | substrate which performed epitaxial growth on the (11-20) plane of a wafer. In the figure, 11 is Si
The C wafer 12 is an SiC buffer layer formed by epitaxial growth and prevents the influence of substrate roughness, strain, and the like from being transmitted upward.

This SiC wafer 11 or epitaxy
The SiC buffer layer 12 grown by the char becomes p-type.
Specifically, doping with B (boron) or the like
10 ¹⁵cm^-3It is the above value. 13 is epitaxy
In this example, nitrogen is doped in the SiC active layer
And the current flows.

The procedure for forming a field effect transistor using such a substrate will be described with reference to FIG. First, FIG.
As shown in FIG. 2A, a region where a device is to be formed is covered with a photoresist 14, and other portions are etched to a buffer layer by a method such as reactive ion etching.

Next, as shown in FIG. 3B, a pattern for the source electrode 15 and the drain electrode 16 is formed by a method such as photolithography, and the electrodes are formed by a method such as metal deposition and lift-off. Finally, as shown in FIG. 3C, the gate electrode 17 is formed in the same manner as in FIG. 3B, and the field effect transistor is completed.

FIG. 4 shows the drain voltage-drain current characteristics of the field-effect transistor prepared as described above.
It can be seen that the pinch-off characteristics are good and the influence of the leakage current due to the stacking fault does not appear.

Although the (11-20) plane of the SiC crystal grown in the <11-20> direction has been described in the present embodiment, the (1-20) plane of the SiC crystal grown in the <1-100> direction has been described.
The same was true for the (-100) plane.

Comparative Example As a comparative example, FIG. 5 shows a drain voltage-drain current characteristic of a field-effect transistor in the case of not using a p-type substrate or a buffer layer and performing non-doping.

Even if the absolute value of the gate voltage is increased, the rate of decrease in the source-drain current is small and does not exhibit good pinch-off characteristics. When the source-drain voltage is increased, the source-drain cannot be controlled by the gate.
It can be seen that the drain-to-drain current increases rapidly.
These are determined to be due to the leak current between the source and drain electrodes on the buffer layer due to the influence of stacking faults.

Although the embodiments and examples of the present invention have been described above, the present invention is not limited to these. For example, it is apparent that the present invention can be applied not only to the metal-semiconductor field-effect transistor (MESFET) as in the embodiment but also to a metal-oxide-semiconductor field-effect transistor (MOSFET) and a junction transistor (JFET).

[0031]

As described above, according to the present invention, the (1-100) plane or the (11-100) plane of the SiC crystal grown in the <1-100> or <11-20> direction.
On the -20) plane, and also on the planes on which those planes are epitaxially grown, it is possible to manufacture an electronic device or the like having a small leak current and excellent electric characteristics with a high yield. Furthermore, since these planes are used as wafers, the diameter can be easily increased and the cost is advantageous as compared with the case where planes obtained by vertically cutting crystals grown in the c-axis direction are used as wafers.

[Brief description of the drawings]

FIG. 1 is a top view and a cross-sectional view of a field-effect transistor for describing a problem of a conventional technique.

FIG. 2 is a cross-sectional view of a substrate for a field-effect transistor formed according to the present invention.

FIG. 3 is a process flow chart of a field-effect transistor.

FIG. 4 shows a drain voltage-drain current characteristic of a field effect transistor formed on a substrate according to the present invention.

FIG. 5 shows a drain voltage-drain current characteristic of a field effect transistor formed on a substrate according to a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 SiC wafer 12 SiC buffer layer 14 Photoresist 13 SiC active layer 15 Source electrode 16 Drain electrode 17 Gate electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hirokatsu Yashiro 20-1 Shintomi, Futtsu-shi, Chiba Nippon Steel Corporation Technology Development Division (72) Inventor Tatsuo Fujimoto 20-1 Shintomi, Futtsu-shi, Chiba New Japan (72) Inventor Masakazu Katsuno 20-1 Shintomi, Futtsu-shi, Chiba F-term 5F102 FA00 GA01 GC01 GD01 GD04 GJ02 GK02 GR01 HC01 HC11 HC15 HC19 5F140 AA24 AB04 BA02 BA20 BC12 BC19

Claims (3)

[Claims] 1. A field-effect transistor formed on a p-type silicon carbide substrate or a silicon carbide substrate having a p-type silicon carbide buffer layer. 2. The doping density of the p-type silicon carbide substrate or the p-type silicon carbide buffer layer is 2 × 10 ¹⁵ cm ^−3.
2. The field effect transistor according to claim 1, wherein: 3. The silicon carbide substrate has a plane orientation of (11-2).
The field-effect transistor according to claim 1, wherein the field-effect transistor is a (0) plane or a (1-100) plane.