JP3637052B2 - SiC-MISFET and method for manufacturing the same - Google Patents

Description

  The present invention relates to a SiC-MISFET provided using a SiC body, in particular, a storage-type SiC-MISFET and a method for manufacturing the same.

  Silicon carbide (SiC) is a wide band gap semiconductor material that has a structure in which Si and C are combined at a composition ratio of 1: 1, has a higher hardness and is less susceptible to chemicals than Si, and has a large band gap. It is. Since SiC has higher dielectric breakdown resistance than other wide band gap semiconductor materials, it is expected to be applied to low-loss power devices. SiC has many polytypes such as cubic 3C—SiC, hexagonal 6H—SiC, and 4H—SiC. Among these, 6H—SiC and 4H—SiC are generally used for producing practical SiC-MISFETs. A substrate having a main surface that is substantially coincident with the (0 0 0 1) plane perpendicular to the c-axis crystal axis is widely used.

  The SiC semiconductor element is formed by using an epitaxial growth layer formed on a SiC substrate as an active region and providing a necessary region in the active region according to the type. Among the semiconductor elements, in the case of an FET, a source / drain region and a gate region are provided. Particularly, in a SiC-MISFET which is a MIS (metal / insulating film / semiconductor) type FET, a MOS (metal / oxide film / semiconductor) type MOSFET using an oxide film formed by thermal oxidation as a gate insulating film. Is generally well known.

  A silicon oxide film that becomes a good gate insulating film is formed on the Si layer by thermal oxidation. However, in the case of a SiC layer, since C exists in addition to Si, it is very difficult to form a good oxide film by ordinary thermal oxidation. That is, since C exists in the silicon oxide film formed on the SiC layer, an interface state that traps carriers by fixed charges is formed in a region near the interface between the Si layer and the oxide film. . For this reason, in the inversion type MISFET, only a very low carrier channel mobility is realized in the inversion layer serving as a channel layer through which a current flows, and it is very difficult to flow a large current in the SiC-MISFET. In order to solve this problem, a power SiC-MISFET generally has a structure in which an accumulation type channel layer containing impurities of the same conductivity type as the source / drain regions is provided. Such a MISFET is called a storage type (accumulation type) SiC-MISFET (SiC-ACCUFET).

FIG. 9 is a cross-sectional view showing the structure of a conventional general storage type SiC-MISFET. As shown in the figure, a general storage type SiC-MISFET includes an SiC substrate 101, a first epitaxial growth layer 102a epitaxially grown on the main surface of the SiC substrate 101, and an upper surface of the first epitaxial layer 102a. And a second epitaxial growth layer 102b epitaxially grown. First epitaxial growth layer 102a is formed by implanting n-type body portion 102c containing n-type impurities (dopant) formed on the main surface of SiC substrate 101, and p-type impurity ions in n-type body portion 102c. A p-type well region 103 formed and a high-concentration contact layer 109 containing a p-type impurity at a concentration higher than that of the well region 103 are provided. In addition, a part of the second epitaxial layer 102b is provided across the well region 103 and the n-type body 102c, and serves as a SiC channel layer 105 that is an accumulation channel layer containing n-type impurities. Furthermore, an n-type source region 104 formed by implanting n-type impurity ions into a part of the second epitaxial growth layer 102b and a part of the well region 103 is provided. Also, a gate insulating film 106 provided on the SiC channel layer 105, a gate electrode 113 provided on the gate insulating film 106, a source electrode 111 in ohmic contact with the source region 104 and the high-concentration contact layer 109, and The drain electrode 112 is in ohmic contact with the surface (back surface) opposite to the main surface of the SiC substrate 101. The source region 104 is formed so as to overlap the gate electrode 113 in plan view and to be in contact with the high-concentration contact layer 109 (see, for example, Patent Document 1).
JP 2001-144292 A

  However, the conventional storage type SiC-MISFET has the following problems.

  In the conventional storage type SiC-MISFET as shown in FIG. 9, there is a case where a current flows between the source and the drain in a so-called normally-on state when no voltage is applied to the gate. This problem is that an n-type SiC channel in which the n-type source region 104 and the n-type epitaxial growth layer 102 have the same conductivity type in a state where the voltage applied between the gate electrode 113 and the well region 103 is 0V. This is because the layer 105 becomes conductive. In such a normally-on type storage MISFET, in order to prevent a drain current from flowing at the time of off, a negative bias voltage is applied to the gate electrode at the time of off, so that a depletion layer in the SiC channel layer is formed. Needs to reach the gate insulating film and be in a pinch-off state.

  Therefore, the impurity concentration of the SiC channel layer 105 is lowered (first measure) so that the depletion layer formed in the SiC channel layer reaches the gate insulating film, or conversely, the impurity of the p-type well region 103 The concentration is increased (second countermeasure). However, in the first countermeasure, since the carrier concentration in the SiC channel layer is lowered, only a drain current having a small current density can be realized in an ON state in which a positive voltage is applied to the gate electrode. In the second countermeasure, the influence of impurity scattering increases due to the high impurity concentration in the p-type well region. For this reason, the channel mobility of electrons decreases and the on-resistance increases, and as a result, it becomes difficult to realize a drain current with a high current density. That is, even if the normally-off state is realized by either of the first and second measures, it is very difficult to flow a drain current having a high current density.

  As described above, when the conventional storage SiC-MISFET structure is used, the drain current having a high current density and the normally-off state are in a trade-off relationship and it is very difficult to achieve both. Therefore, in the off state in which no voltage is applied to the gate electrode, a normally-off state in which no current flows between the source and drain, and a drain current having a high current density flows in the on state in which a positive voltage is applied to the gate electrode. Therefore, it is desired to realize a storage type MISFET having a high current drive capability.

  In view of the above-described conventional problems, an object of the present invention is to provide a SiC-MISFET having a high current drive capability while realizing a normally-off state, and a method for manufacturing the same.

  The SiC-MISFET of the present invention includes a portion containing a high-concentration second conductivity type impurity surrounded by a main body portion containing a first conductivity type impurity or a well region containing a second conductivity type impurity in a region immediately below the channel layer. A high concentration injection layer is provided.

  Thereby, when the storage type SiC-MISFET is off, that is, when the voltage between the gate and the well region is 0, the current flowing through the channel layer is suppressed, and when the storage type SiC-MISFET is on, a drain current having a high current density can flow. Nevertheless, a normally-off state is realized. This is considered to be due to the expansion of the depletion layer in a part of the channel layer.

  Here, when the depletion layer formed in the channel layer at the time of OFF reaches the gate insulating film, the current is surely cut off by the depletion layer.

  In the case where the partial high concentration implantation layer is provided by injecting the second conductivity type impurity into the main body, the distance between the partial high concentration implantation layer and the well region is the dimension of the partial high concentration implantation layer in the gate length direction. Since the potential of the partial high concentration injection layer is easily fixed, the depletion layer is expanded more efficiently.

  Since the partial high concentration injection layer is provided in the well region, the potential of the partial high concentration injection layer is fixed, so that it becomes easy to form a depletion layer that completely pinches off the inside of the SiC channel layer. A normally-off SiC-MISFET can be realized without reducing the drain current during the on-operation.

  In particular, when a high-concentration contact layer is provided in a part of the well region, the high-concentration contact layer is formed so as to surround the source region from below, and the partial high-concentration implantation layer is a part thereof. This facilitates manufacturing.

  The length of the partial high concentration injection layer in the gate length direction is 1/10 or less of the length of the channel layer, thereby suppressing the influence of scattering by impurities contained in the partial high concentration injection layer within an allowable range. It becomes possible.

  Since the depth direction dimension of the partial high concentration injection layer is larger than the depth direction dimension of the channel layer, the depletion layer formed in the channel layer at the OFF time reaches the gate insulating film and reliably supplies current. It becomes possible to block.

  When the impurity concentration of the partial high-concentration implanted layer is 10 times or more higher than the impurity concentration of the well region, a depletion layer capable of reliably blocking current at the time of OFF is formed in the channel layer.

  The SiC-MISFET of the present invention can adopt a vertical MISFET structure or a horizontal MISFET structure.

  The SiC-MISFET manufacturing method of the present invention includes a step of injecting a second conductivity type impurity into an SiC body to form a well region, and an implantation of a second conductivity type impurity having a higher concentration than the well region into the SiC body. A step of forming a partial high-concentration implantation layer, and a step of forming a channel layer including a first conductivity type impurity on the main body portion, well region and partial high-concentration implantation layer of the SiC body.

  By this method, the above-described SiC-MISFET structure can be easily obtained.

  In particular, by using a implantation mask provided with an opening including a region where a source region is to be formed, a second high conductivity type impurity is implanted to form a partial high concentration implanted layer so as to be in contact with the source region. Can be facilitated.

  The present invention can provide a normally-off SiC-MISFET capable of flowing a drain current having a high current density.

(First embodiment)
First, the storage type SiC-MISFET according to the first embodiment of the present invention in which a partial high-concentration injection layer containing impurities higher in concentration than the well region is provided in the drift layer will be described.

  FIG. 1 is a cross-sectional view showing the structure of the storage SiC-MISFET according to the first embodiment. As shown in the figure, the storage type SiC-MISFET of this embodiment includes a SiC substrate 1, a first epitaxial growth layer 2a epitaxially grown on the main surface of the SiC substrate 1, and a first epitaxial layer 2a. And a second epitaxial growth layer 2b epitaxially grown thereon. The first epitaxial growth layer 2a includes an n-type drift layer 2c (body portion) containing an n-type impurity (dopant) formed on the main surface of the SiC substrate 1, and p-type impurity ions in the n-type drift layer 2c. P-type well region 3 formed by implanting and high-concentration contact layer 9 containing a p-type impurity at a concentration higher than that of well region 3. A part of the second epitaxial layer 2b is provided across the well region 3 and the n-type drift layer 2c, and serves as a SiC channel layer 5 which is an accumulation channel layer containing n-type impurities. Further, an n-type source region 4 formed by implanting n-type impurity ions into another part of the second epitaxial growth layer 2b and a part of the well region 3 is provided. A gate insulating film 6 provided on the SiC channel layer 5; a gate electrode 13 provided on the gate insulating film 6; a source electrode 11 in ohmic contact with the source region 4 and the high-concentration contact layer 9; A drain electrode 12 is provided in ohmic contact with a surface (back surface) facing the main surface of the SiC substrate 1. The source region 4 is formed so as to overlap the gate electrode 13 in plan view and to be in contact with the high concentration contact layer 9.

  The high-concentration contact layer 9 is not necessarily provided, but it is preferable to have the high-concentration contact layer 9 in order to reliably obtain the ohmic property of the source electrode 11 for applying a bias to the well region 3.

  During operation of the storage type SiC-MISFET of the present embodiment, a current flows from the source region 4 to the SiC substrate 1 (drain region) through the SiC channel layer 5 and the n-type drift layer 2c, so that the storage type SiC- The MISFET has a vertical MISFET structure.

  The structure of the storage type SiC-MISFET of the present embodiment is different from the structure of the conventional storage type SiC-MISFET in that the p-type impurity ions are partially implanted into the upper surface of the n-type drift layer 2c. The high concentration injection layer 7A is provided. In this embodiment, the partial high-concentration implanted layer 7A is adjacent to the well region 3 and has the same conductivity type impurity (p-type in this embodiment) that is 10 times higher than the impurity concentration in the well region 3. Impurities).

  In the present embodiment, the SiC substrate 1 and the epitaxial growth layer 2 including the first epitaxial growth layer 2a and the second epitaxial growth layer 2b function as an SiC body. However, it is also possible to form an n-type accumulation channel layer by ion implantation above the first epitaxial growth layer 2a without providing the second epitaxial growth layer 2b. In that case, the first epitaxial growth layer 2a and the SiC substrate 1 become a SiC body. Further, it is possible to provide a well region, a source region, a storage channel layer, and the like on the SiC substrate 1 without forming any epitaxial growth layer. In this case, the SiC substrate 1 becomes a SiC body.

  Next, a manufacturing method of the storage type SiC-MISFET in this embodiment will be described. 2A to 2D are cross-sectional views showing a manufacturing process of the SiC-MISFET according to this embodiment.

The following steps are performed before the step shown in FIG. First, the SiC substrate 1 is prepared. As the SiC substrate 1, for example, a 4H—SiC substrate having a diameter of 50 mm with an off-angle of 8 degrees in the [1 1-2 0] direction from the (0 0 0 1) main surface is used. The SiC substrate 1 is doped with n-type impurities, and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . Next, the first epitaxial growth layer 2a including the n-type drift layer 2c of the storage SiC-MISFET is epitaxially grown on the SiC substrate 1 by in-situ doping with the n-type impurity by the CVD method. The thickness of the first epitaxial growth layer 2a (the thickness of the n-type drift layer 2c) is about 10 μm, and the carrier concentration in the n-type drift layer 2c is about 5 × 10 ¹⁵ cm ⁻³ . Thereby, a SiC body lower layer composed of SiC substrate 1 and first epitaxial growth layer 2a is formed.

Subsequently, in order to form the well region 3 of the storage SiC-MISFET, an implantation mask (not shown) made of, for example, nickel (Ni) is formed on the surface of the n-type drift layer 2c. This implantation mask covers a part of the n-type drift layer 2 c and has an opening in a region to be the well region 3. Then, multi-stage Al ions are implanted into the n-type drift layer 2c from above the implantation mask, and then activation annealing is performed. Thereby, a part of the n-type drift layer 2c becomes the p-type well region 3 having a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ .

Next, in the step shown in FIG. 2A, after removing the implantation mask made of Ni, an implantation made of Al with openings in the regions where the partial high concentration implantation layer 7A and the high concentration contact layer 9 are to be formed. A mask 21 is formed. Then, multi-stage Al ions are implanted into the n-type drift layer 2c from above the implantation mask 21, and then activation annealing is performed. As a result, a p-type partial high concentration injection layer 7A having a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ is formed so as to be in contact with the well region 3 in the n type drift layer 2c. Further, a high concentration contact layer 9 containing a p-type impurity of the same level as that of the partial high concentration implantation layer 7 A is formed so as to be surrounded by the well region 3.

Next, in the step shown in FIG. 2 (b), a second method including a SiC channel layer 5 having a thickness of 0.3 μm and containing an n-type impurity on the upper surface of the well region 3 and the n-type drift layer 2c is formed by CVD. Epitaxial growth layer 2b (SiC upper layer) is epitaxially grown. The n-type impurity is also introduced into the SiC channel layer 5 by in-situ doping, and its concentration is about 5 × 10 ¹⁷ cm ⁻³ . Thereby, the SiC body which consists of the epitaxial growth layer 2 and the SiC substrate 1 is formed.

Next, in the step shown in FIG. 2C, an implantation mask made of Ni or the like having an opening in the region where the source region 4 is to be formed is formed (not shown), and an n-type impurity is formed from above the implantation mask. After injecting nitrogen ions, which are ions, into the well region 3, activation annealing of nitrogen is performed. Thereby, each part of the SiC channel layer 5 and the well region 3 becomes an n-type source region 4 having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ .

  In the present embodiment, the width of the SiC channel layer 5 formed on the well region 3 is set to about 10 μm by adjusting the dimensions of the implantation mask used in the steps shown in FIGS. The high concentration implantation layer 7A has a width of 0.5 μm and a depth of 0.5 μm.

  Next, in the step shown in FIG. 2D, the exposed surface of the SiC body is thermally oxidized at 1100 ° C. to form a gate insulating film 6 having a thickness of 30 nm on the upper surface of the substrate. Thereafter, a portion of the gate insulating film 6 located on the region where the source electrode is to be formed is removed, and then deposited on the upper surface of the source region 4 and the SiC substrate 1 by vapor deposition using an electron beam (EB) vapor deposition apparatus. A Ni film is formed on the back surface of the substrate. Subsequently, by heating at 1000 ° C. in a heating furnace, the source electrode 11 serving as the first ohmic electrode is formed on the source region 4, and the drain electrode 12 serving as the second ohmic electrode is formed on the back surface of the SiC substrate 1. Respectively. Finally, an aluminum film is formed on the gate insulating film 6 by vapor deposition, and this is patterned to form the gate electrode 13.

  Next, in order to investigate the performance of the storage SiC-MISFET according to the present embodiment, the current-voltage characteristics were measured. The results will be described below.

  For comparison, a conventional storage type SiC-MISFET as shown in FIG. 9 was prepared. The structure is the same as that of the storage type SiC-MISFET of the present embodiment except that the partial high concentration injection layer 7A does not exist.

  Next, the current-voltage characteristics of the present embodiment and the conventional storage type SiC-MISFET were examined. Specifically, the drain current in the state where the voltage applied between the gate electrode and the well region is 0 V was measured and compared.

  As a result, it has been found that in the storage type SiC-MISFET of this embodiment, the drain current is suppressed by nearly two orders of magnitude compared to the conventional storage type SiC-MISFET. It was found that the drain currents of the two regions were almost equal during the on-operation in which a positive voltage was applied to the gate with reference to the well region. The reason is considered as follows.

  First, in the conventional storage SiC-MISFET, when the voltage applied between the gate electrode 13 and the well region 3 is 0 V (off state), the depletion layer formed in the SiC channel layer 5 is gate-insulated. It is easy for the source / drain regions to become conductive without reaching the film 6. In this state, a normally on state occurs, and a drain current flows even when the gate bias is 0V.

  On the other hand, in the storage type SiC-MISFET of this embodiment, the depletion layer formed in the SiC channel layer 5 is gate-insulated by the partial high-concentration implantation layer 7A containing a p-type impurity having a higher concentration than the well region 3. Since the film 6 is almost reached, it is considered that the source / drain region is interrupted. For this reason, it is considered that the normally off state is ensured and the drain current does not flow when the gate bias is 0V.

  Here, in the region where the high-concentration p-type partial high-concentration injection layer 7A exists, there is a possibility that the channel mobility of electrons may decrease due to the influence of impurity scattering, but the partial high-concentration injection layer 7A shown in FIG. By making the width W1 smaller by one digit or more than the width W2 of the SiC channel layer 5, it is considered that the influence on the drain current at the ON operation can be ignored.

  In addition, since the dimension in the depth direction of the partial high concentration implantation layer 7A is larger than the dimension in the depth direction of the SiC channel layer 5, a depletion layer formed in the SiC channel layer 5 is surely formed in the gate insulating film 6. To reach.

  From the above, by providing the p-type partial high-concentration injection layer 7A in contact with the well region 3 in the n-type drift layer 2c, the gate electrode 13 and the well can be formed without reducing the drain current in the ON operation. It was shown that a normally-off type storage SiC-MISFET in which no drain current flows when the voltage applied to the region 3 is 0 V is obtained.

-Modification of the first embodiment-
FIG. 3 is a cross-sectional view showing the structure of a storage SiC-MISFET according to a modification of the first embodiment. In this modification, the partial high concentration injection layer 7B is not in contact with the well region 3 in the n-type drift layer 2c. The structure of other parts is the same as that of the first embodiment. Also in this modification, as in the first embodiment, the drain current flows when the voltage applied between the gate electrode 13 and the well region 3 is 0 V without reducing the drain current in the ON operation. Thus, a normally-off storage type SiC-MISFET is obtained.

  In this example, since the distance between the partial high concentration injection layer 7B and the well region 3 is smaller than the dimension of the partial high concentration injection layer in the gate length direction, the potential of the partial high concentration injection layer is reliably fixed. Therefore, the above-described effects can be surely exhibited.

  In particular, as in the first embodiment, when the partial high concentration injection layer is in contact with the well region 3 in the n-type drift layer 2c, the potential of the partial high concentration injection layer is more reliably fixed. This is preferable in that the SiC channel layer 5 can be pinched off more reliably.

(Second Embodiment)
Next, an accumulation type SiC-MISFET according to a second embodiment of the present invention in which a partial high concentration implantation layer containing impurities higher in concentration than the well region is provided in the well region will be described.

  FIG. 4 is a cross-sectional view showing the structure of the storage-type SiC-MISFET in the second embodiment. As shown in the figure, the storage type SiC-MISFET of this embodiment includes a SiC substrate 1, a first epitaxial growth layer 2a epitaxially grown on the main surface of the SiC substrate 1, and a first epitaxial layer 2a. And a second epitaxial growth layer 2b epitaxially grown thereon. First epitaxial growth layer 2a is formed by implanting n-type drift layer 2c containing n-type impurities (dopant) formed on the main surface of SiC substrate 1 and p-type impurity ions into n-type drift layer 2c. A p-type well region 3 formed and a high-concentration contact layer 9 containing a p-type impurity at a concentration higher than that of the well region 3 are provided. A part of the second epitaxial layer 2b is provided across the well region 3 and the n-type drift layer 2c, and serves as a SiC channel layer 5 which is an accumulation channel layer containing n-type impurities. Further, an n-type source region 4 formed by implanting n-type impurity ions into another part of the second epitaxial growth layer 2b and a part of the well region 3 is provided. A gate insulating film 6 provided on the SiC channel layer 5; a gate electrode 13 provided on the gate insulating film 6; a source electrode 11 in ohmic contact with the source region 4 and the high-concentration contact layer 9; A drain electrode 12 is provided in ohmic contact with a surface (back surface) facing the main surface of the SiC substrate 1. The source region 4 is formed so as to overlap the gate electrode 13 in plan view and to be in contact with the high concentration contact layer 9.

  During operation of the storage type SiC-MISFET of the present embodiment, a current flows from the source region 4 to the SiC substrate 1 (drain region) through the SiC channel layer 5 and the n-type drift layer 2c, so that the storage type SiC- The MISFET has a vertical MISFET structure.

  In the storage type SiC-MISFET of this embodiment, unlike the first embodiment, a partial high-concentration implanted layer 7C formed by partially implanting p-type impurity ions is provided on the upper surface of the well region 3. This is the point. In the present embodiment, the partial high-concentration implanted layer 7 </ b> C contains the same conductivity type impurity (p-type impurity in the present embodiment) that is 10 times or more higher than the impurity concentration in the well region 3.

  Since most of the manufacturing process of the storage-type SiC-MISFET in the present embodiment is almost the same as the manufacturing process of the storage-type SiC-MISFET of the first embodiment, illustration is omitted and only different parts will be described.

  In the manufacturing process of this embodiment, in the process shown in FIG. 2A, ion implantation is performed using an implantation mask having an opening above the well region 3, and the high concentration contact layer 9 and the partial high concentration implantation layer 7C. And form. Other steps are as described in FIGS. 2A to 2D and the description thereof.

  The current-voltage characteristics of the storage type SiC-MISFET of this embodiment and the conventional storage type SiC-MISFET shown in FIG. 9 were examined. Specifically, the drain current in the state where the voltage applied between the gate electrode and the well region is 0 V was measured and compared.

  As a result, in the storage type SiC-MISFET of this embodiment, as in the case of the first embodiment, it has been found that the drain current is suppressed by nearly two orders of magnitude compared to the conventional storage type SiC-MISFET. . It was found that the drain currents of both were substantially equal during the ON operation in the state where a positive voltage was applied to the gate electrode 13 with respect to the well region 3. As this reason, the same reason as the first embodiment can be considered.

  From the above, by providing the p-type partial high concentration injection layer 7C in the well region 3, the voltage applied between the gate electrode 13 and the well region 3 without reducing the drain current in the ON operation. It was shown that a normally-off storage type SiC-MISFET in which no drain current flows in a state of 0 V can be obtained.

-Modification of the second embodiment-
FIG. 5 is a cross-sectional view showing the structure of a storage type SiC-MISFET according to a modification of the second embodiment. In this modification, two partial high-concentration injection layers 7D are provided in the well region 3. The structure of other parts is the same as that of the second embodiment. Also in this modification, as in the second embodiment, the drain current flows when the voltage applied between the gate electrode 13 and the well region 3 is 0 V without reducing the drain current in the on-operation. Thus, a normally-off storage type SiC-MISFET is obtained.

  As in this modification, it is preferable that a plurality of partial high-concentration implantation layers are provided in the well region 3 in that a storage type SiC-MISFET capable of pinching off the SiC channel layer more reliably can be obtained.

(Third embodiment)
Next, an accumulation type SiC-MISFET according to a third embodiment of the present invention in which a partial high-concentration implantation layer containing impurities higher in concentration than the well region is provided in the well region will be described.

  FIG. 6 is a cross-sectional view showing the structure of the storage type SiC-MISFET in the third embodiment. As shown in the figure, the storage type SiC-MISFET of this embodiment includes a SiC substrate 1, a first epitaxial growth layer 2a epitaxially grown on the main surface of the SiC substrate 1, and a first epitaxial layer 2a. And a second epitaxial growth layer 2b epitaxially grown thereon. First epitaxial growth layer 2a is formed by implanting n-type drift layer 2c containing n-type impurities (dopant) formed on the main surface of SiC substrate 1 and p-type impurity ions into n-type drift layer 2c. A p-type well region 3 formed and a high-concentration contact layer 9 containing a p-type impurity at a concentration higher than that of the well region 3 are provided. A part of the second epitaxial layer 2b is provided across the well region 3 and the n-type drift layer 2c, and serves as a SiC channel layer 5 which is an accumulation channel layer containing n-type impurities. Further, an n-type source region 4 formed by implanting n-type impurity ions into another part of the second epitaxial growth layer 2b and a part of the well region 3 is provided. A gate insulating film 6 provided on the SiC channel layer 5; a gate electrode 13 provided on the gate insulating film 6; a source electrode 11 in ohmic contact with the source region 4 and the high-concentration contact layer 9; A drain electrode 12 is provided in ohmic contact with a surface (back surface) facing the main surface of the SiC substrate 1. The source region 4 is formed so as to overlap the gate electrode 13 in plan view and to be in contact with the high concentration contact layer 9.

  During operation of the storage type SiC-MISFET of the present embodiment, a current flows from the source region 4 to the SiC substrate 1 (drain region) through the SiC channel layer 5 and the n-type drift layer 2c, so that the storage type SiC- The MISFET has a vertical MISFET structure.

  In the storage type SiC-MISFET of this embodiment, unlike the first and second embodiments, the high concentration contact layer 9 formed by partially implanting p-type impurity ions into the upper surface of the well region 3. Is that the region located below the SiC channel layer 5 in the high-concentration contact layer 9 is the partial high-concentration implantation layer 9a. In the present embodiment, the partial high-concentration implanted layer 9a is a part of the high-concentration contact layer 9, and therefore has the same conductivity type impurity (in this embodiment, 10 times higher than the impurity concentration in the well region 3). , P-type impurities).

  Next, a manufacturing method of the storage type SiC-MISFET in this embodiment will be described. 7A to 7D are cross-sectional views showing a manufacturing process of the SiC-MISFET according to this embodiment.

Prior to the step shown in FIG. 7A, the following steps are performed. First, the SiC substrate 1 is prepared. As the SiC substrate 1, for example, a 4H—SiC substrate having a diameter of 50 mm with an off-angle of 8 degrees in the [1 1-2 0] direction from the (0 0 0 1) main surface is used. The SiC substrate 1 is doped with n-type impurities, and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . Next, the first growth layer 2a including the n-type drift layer 2c of the storage SiC-MISFET is epitaxially grown on the SiC substrate 1 by in-situ doping with the n-type impurity by the CVD method. The thickness of the first epitaxial growth layer 2a (the thickness of the n-type drift layer 2c) is about 10 μm, and the carrier concentration in the n-type drift layer 2c is about 5 × 10 ¹⁵ cm ⁻³ . Thereby, a SiC body lower layer composed of SiC substrate 1 and first epitaxial growth layer 2a is formed.

Subsequently, in order to form the well region 3 of the storage SiC-MISFET, an implantation mask (not shown) made of, for example, nickel (Ni) is formed on the surface of the n-type drift layer 2c. This implantation mask covers a part of the n-type drift layer 2 c and has an opening in a region to be the well region 3. Then, multi-stage Al ions are implanted into the n-type drift layer 2c from above the implantation mask, and then activation annealing is performed. As a result, a part of the n-type drift layer 2c becomes the well region 3 containing an impurity having a concentration of 1 × 10 ¹⁷ cm ⁻³ .

Next, in the step shown in FIG. 7A, after the implantation mask made of Ni is removed, an implantation mask 22 made of Al having an opening in a region where the high concentration contact layer 9 is to be formed is formed. At this time, the opening of the implantation mask 22 includes the entire opening of the implantation mask that is used to form a source region later. Then, multi-stage Al ions are implanted into the n-type drift layer 2c from above the implantation mask 22, and then activation annealing is performed. Thereby, a high concentration contact layer 9 containing a p-type impurity having a concentration of about 2 × 10 ¹⁸ cm ⁻³ is formed so as to be surrounded by the well region 3 in the n-type drift layer 2 c.

Next, in the step shown in FIG. 7B, the second region including the SiC channel layer 5 having the thickness of 0.3 μm and containing the n-type impurity on the upper surface of the well region 3 and the n-type drift layer 2c is formed by the CVD method. The epitaxial growth layer 2b (SiC upper layer) is epitaxially grown. The n-type impurity is also introduced into the SiC channel layer 5 by in-situ doping, and its concentration is about 5 × 10 ¹⁷ cm ⁻³ . Thereby, the SiC body which consists of the epitaxial growth layer 2 and the SiC substrate 1 is formed.

Next, in the step shown in FIG. 7C, an implantation mask made of Ni or the like having an opening in the region where the source region 4 is to be formed is formed (not shown), and an n-type impurity is formed from above the implantation mask. After injecting nitrogen ions, which are ions, into the well region 3, activation annealing of nitrogen is performed. Thereby, a part of SiC channel layer 5 becomes source region 4 containing an n-type impurity having a concentration of 2 × 10 ¹⁸ cm ⁻³ . In the present embodiment, since the concentration of the p-type impurity in the high-concentration contact layer 9 and the concentration of the n-type impurity in the source region 4 are approximately the same, the region up to the high-concentration contact layer 9 is the source region 4. Although not changed, for convenience, in FIG. 6 and FIGS. 7C and 7D, the lower part of the source region 4 is drawn so as to penetrate into the well region 3.

  Next, in the step shown in FIG. 7D, the exposed surface of the SiC body is thermally oxidized at 1100 ° C. to form a gate insulating film 6 having a thickness of 30 nm on the upper surface of the substrate. Thereafter, a portion of the gate insulating film 6 located on the region where the source electrode is to be formed is removed, and then the surface of the source region 4 and the back surface of the SiC substrate 1 are formed using an electron beam (EB) vapor deposition apparatus. Ni is vapor-deposited. Subsequently, by heating at 1000 ° C. in a heating furnace, the source electrode 9 serving as the first ohmic electrode is formed on the source region 4, and the drain electrode 10 serving as the second ohmic electrode is formed on the back surface of the SiC substrate 1. Respectively. Finally, an aluminum film is formed on the gate insulating film 6 by vapor deposition, and this is patterned to form the gate electrode 8.

  Next, in order to investigate the performance of the storage SiC-MISFET according to the present embodiment, the current-voltage characteristics were measured. The results will be described below.

  For comparison, a conventional storage type SiC-MISFET as shown in FIG. 9 was prepared. The structure is the same as that of the storage type SiC-MISFET of the present embodiment except that the partial high concentration implantation layer 9a does not exist.

  Next, the current-voltage characteristics of the present embodiment and the conventional storage type SiC-MISFET were examined. Specifically, the drain current in the state where the voltage applied between the gate electrode and the well region is 0 V was measured and compared.

  As a result, it has been found that in the storage type SiC-MISFET of this embodiment, the drain current is suppressed by nearly two orders of magnitude compared to the conventional storage type SiC-MISFET. It was found that the drain currents of the two regions were almost equal during the on-operation in which a positive voltage was applied to the gate with reference to the well region. The reason is considered as in the first embodiment.

  From the above, by forming the high-concentration contact layer 9 in the well region 3 so as to surround the source region 4, and making a part of it function as the partial high-concentration injection layer 9a, the drain current in the on operation is reduced. It has been shown that a normally-off storage type SiC-MISFET in which no drain current flows when the voltage applied between the gate electrode 13 and the well region 3 is 0 V is obtained.

  In particular, as compared with the first and second embodiments, the partial high-concentration implantation layer 9a is far from the end of the well region 3, so that the positional deviation between the implantation masks used at the time of ion implantation for forming the both is increased. There is an advantage that can be ignored. In addition, in this structure, since the “punch through” in which the depletion layer due to the pn junction between the well region and the drift layer reaches the source region is less likely to occur, the breakdown voltage is improved.

In the present embodiment, since the concentration of the p-type impurity in the high-concentration contact layer 9 and the concentration of the n-type impurity in the source region 4 are approximately the same, the lower portion of the source region 4 is almost intrinsic. It has become. Therefore, the thickness of the substantial portion of the source region 4 is substantially the same as the thickness of the SiC channel layer 5, but even with such a structure, the function of the source region 4 is not impaired. Similarly, when the concentration of the n-type impurity in the source region 4 is, for example, about 1 × 10 ¹⁸ cm ^−3, which is lower than the concentration of the impurity in the high-concentration contact layer 9, the source region 7 shown in FIG. Although the lower portion becomes the high-concentration contact region 9, even in such a structure, the function of the source region 4 is not impaired. Furthermore, the n-type impurity concentration of the source region 4 may be higher than the p-type impurity concentration of the high-concentration contact layer 9.

(Fourth embodiment)
Next, an accumulation type SiC-MISFET, which is a lateral MISFET according to the fourth embodiment of the present invention, in which a partial high-concentration implantation layer containing impurities higher in concentration than the well region is provided in the well region will be described.

  FIG. 8 is a cross-sectional view showing the structure of the storage type SiC-MISFET in the fourth embodiment. As shown in the figure, the storage type SiC-MISFET of this embodiment includes a SiC substrate 1, a first epitaxial growth layer 2a epitaxially grown on the main surface of the SiC substrate 1, and a first epitaxial layer 2a. And a second epitaxial growth layer 2b epitaxially grown thereon. First epitaxial growth layer 2a is formed by implanting n-type drift layer 2c containing n-type impurities (dopant) formed on the main surface of SiC substrate 1 and p-type impurity ions into n-type drift layer 2c. A p-type well region 3 formed and a high-concentration contact layer 9 containing a p-type impurity at a concentration higher than that of the well region 3 are provided. A part of the second epitaxial layer 2b is provided across the well region 3 and the n-type drift layer 2c, and serves as a SiC channel layer 5 which is an accumulation channel layer containing n-type impurities. Further, an n-type source region 4 formed by implanting n-type impurity ions into another part of the second epitaxial growth layer 2b and a part of the well region 3 is provided. The gate insulating film 6 provided on the SiC channel layer 5, the gate electrode 13 provided on the gate insulating film 6, and the source electrode 11 in ohmic contact with the source region 4 and the high-concentration contact layer 9 are provided. I have. The source region 4 is formed so as to overlap the gate electrode 13 in plan view and to be in contact with the high concentration contact layer 9.

  Further, a drain region 31 formed by introducing an n-type impurity having a concentration similar to that of the source region 4 into the surface portion of the n-type main body 2c and facing the source region 4 with the SiC channel layer 5 interposed therebetween, and a drain A drain electrode 32 that is in ohmic contact with the region 31 is provided.

  During operation of the storage type SiC-MISFET of the present embodiment, a current flows from the source region 4 to the drain region 32 through the SiC channel layer 5, so that the storage type SiC-MISFET of the present embodiment has a lateral MISFET structure. .

  Also in this embodiment, similarly to the first embodiment, by providing the p-type partial high-concentration injection layer 7A in contact with the well region 3 in the n-type drift layer 2c, the drain current in the on operation can be reduced. Without reduction, a normally-off storage SiC-MISFET is obtained in which no drain current flows when the voltage applied between the gate electrode 13 and the well region 3 is 0V.

  The structure of the partial high-concentration implantation layer in the modification of the first embodiment, the second embodiment, the modification of the second embodiment, and the third embodiment is the storage type that is such a lateral MISFET. Even when applied to a SiC-MISFET, the drain current does not flow when the voltage applied between the gate electrode 13 and the well region 3 is 0 V without reducing the drain current in the on operation, and is a normally-off type. The storage type SiC-MISFET is obtained.

(Other embodiments)
In each of the above embodiments, the case where the storage type SiC-MISFET is an n-channel type MISFET has been described. However, even if the storage type SiC-MISFET of the present invention is a p-channel type MISFET, the same as the above embodiments. The effect can be demonstrated.

  In the above embodiment, the partial high concentration injection layer is formed in the storage type SiC-MISFET. However, the same effect as described above can be obtained even if the partial high concentration injection layer is formed in the storage type IGBT using SiC. It is done.

  In the above embodiment, the n-type doped layer having a uniform concentration distribution is used as the SiC channel layer. However, the effect of the present invention can be obtained even when a channel layer having multiple δ-doped layers is used.

  In the above embodiment, 4H—SiC is used as the SiC substrate, but a substrate made of a polytype other than 4H—SiC may be used.

  INDUSTRIAL APPLICABILITY The present invention can be used as a power semiconductor device or a high-frequency semiconductor device provided in various electronic devices and power devices.

It is sectional drawing which shows the structure of accumulation | storage type SiC-MISFET in 1st Embodiment. (A)-(d) is sectional drawing which shows the manufacturing process of SiC-MISFET which concerns on 1st Embodiment. It is sectional drawing which shows the structure of storage type SiC-MISFET which concerns on the modification of 1st Embodiment. It is sectional drawing which shows the structure of storage-type SiC-MISFET in 2nd Embodiment. It is sectional drawing which shows the structure of storage type SiC-MISFET which concerns on the modification of 2nd Embodiment. It is sectional drawing which shows the structure of storage type SiC-MISFET in 3rd Embodiment. (A)-(d) is sectional drawing which shows the manufacturing process of SiC-MISFET which concerns on this embodiment. It is sectional drawing which shows the structure of storage type SiC-MISFET in 4th Embodiment. It is sectional drawing which shows the structure of the conventional storage type SiC-MISFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 N type epitaxial growth layer 3 Well region 4 Source region 5 Gate insulating film 6 SiC channel layer 7 Partial high concentration injection layer 9 High concentration contact layer 11 Source electrode 12 Drain electrode 13 Gate electrode

Claims (12)

A SiC body having a main body portion containing a first conductivity type impurity;
A well region formed by introducing a second conductivity type impurity into a portion of the SiC body excluding the body portion;
A channel layer containing a first conductivity type impurity provided across the well region and the main body of the SiC body in the SiC body;
A gate insulating film formed on the channel layer;
A gate electrode formed on the gate insulating film;
A source region including a first conductivity type impurity provided in a region adjacent to the channel layer in the SiC body so as to be in contact with the well region;
A drain region provided in a region facing the source region across the body portion in the SiC body;
A SiC-MISFET comprising a partial high-concentration injection layer provided by injecting a second conductivity type impurity having a concentration higher than that of the well region into a portion of the SiC body located below the channel. The SiC-MISFET according to claim 1, wherein
A SiC-MISFET in which a depletion layer formed by the partial high concentration injection layer reaches the gate insulating film in a state in which a voltage applied between the gate electrode and the well region is 0V. The SiC-MISFET according to claim 1 or 2,
At least the lower surface of the partial high concentration injection layer is surrounded by the main body,
The SiC-MISFET, wherein a distance between the partial high concentration implantation layer and the well region is smaller than a dimension of the partial high concentration implantation layer in a gate length direction. The SiC-MISFET according to claim 1 or 2,
The partial high concentration implantation layer is a SiC-MISFET surrounded by the well region. The SiC-MISFET according to claim 4,
A high-concentration contact layer containing a second conductivity type impurity at a concentration higher than that of the well region and connected to the partial high-concentration implantation layer;
The high-concentration contact layer is formed so as to surround the source region,
The partial high-concentration implantation layer is a SiC-MISFET formed by an ion implantation process common to the high-concentration contact layer. In SiC-MISFET as described in any one of Claims 1-5,
The SiC-MISFET, wherein a dimension of the partial high concentration implantation layer in a gate length direction is 1/10 or less of a dimension of the channel layer in a gate length direction. In SiC-MISFET as described in any one of Claims 1-6,
The SiC-MISFET, wherein a dimension in the depth direction of the partial high concentration implantation layer is larger than a dimension in the depth direction of the channel layer. In SiC-MISFET as described in any one of Claims 1-6,
The SiC-MISFET, wherein the impurity concentration of the partial high concentration implantation layer is 10 times or more higher than the impurity concentration of the well region. In SiC-MISFET as described in any one of Claims 1-8,
The drain region is provided in the lowermost part of the SiC body, and is a vertical MISFET. SiC-MISFET. In SiC-MISFET as described in any one of Claims 1-8,
The drain region is provided in a surface portion connected to the channel layer of the SiC body, and is a lateral MISFET, SiC-MISFET. A step of forming a well region by implanting a second conductivity type impurity into a portion of the SiC body lower layer containing the first conductivity type impurity except for a main body portion; and
(B) after or before the step (a), implanting a second conductivity type impurity having a concentration higher than that of the well region into the main body to form a partial high concentration implantation layer;
A step (c) of epitaxially growing a SiC body upper layer having a channel layer containing a first conductivity type impurity on the SiC body body, the well region, and the partial high-concentration implanted layer;
A step (d) of implanting a first conductivity type impurity into a part of the SiC upper layer to form a source region;
Forming a gate insulating film on the channel layer (e);
And a step (f) of forming a gate electrode on the gate insulating film. In the manufacturing method of SiC-MISFET of Claim 11,
In the step (b), by using the implantation mask provided with an opening including the region where the source region is to be formed, a second conductivity type impurity is implanted so that the partial height is in contact with the source region. A method for manufacturing a SiC-MISFET, wherein a concentration injection layer is formed.

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