JP2011100964A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a reverse leakage current at a pn junction part without increasing ON resistance. <P>SOLUTION: A semiconductor device such as a 3C-SiC-MOSFET is characterized in that when an n-type SiC epitaxial layer 11 doped with n-type impurity ions is grown on an n+ type 3C-SiC substrate 10, a donor concentration of a surface region of the n-type SiC epitaxial layer 11 is not lowered but held high, and a donor concentration of a pn junction part between a (p) well 12 formed in the n-type SiC epitaxial layer 11 and the n-type SiC epitaxial layer 11 is lowered. A desired donor concentration profile is formed by controlling a dopant gas amount in the growth of the n-type SiC epitaxial layer 11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power semiconductor device (for example, a SiC field effect transistor, hereinafter referred to as “SiC-MOSFET”) using a silicon carbide (SiC) semiconductor, and a manufacturing method thereof.

  The SiC semiconductor is a semiconductor having a larger energy band gap than silicon (Si), and has characteristics such as low loss, miniaturization, high voltage resistance, and high heat resistance compared to Si. Various SiC-pn diodes and SiC-MOSFETs have been proposed.

For example, Patent Documents 1 and 2 below describe vertical SiC-MOSFET technology that can be easily miniaturized. In the vertical SiC-MOSFET, for example, an n-type epitaxial layer is formed on an n-type SiC substrate that is a bulk substrate. A p-well is formed in the n-type epitaxial layer, and an n ⁺ -type source region is formed in the p-well. A gate is formed in the vicinity of the n ⁺ type source region. Furthermore, a drain is formed on the back side of the n-type SiC substrate. A pn junction is formed at the boundary between the p-well and the n-type epitaxial layer.

  In this type of vertical SiC-MOSFET, by applying a predetermined voltage to the gate, electrons flow in a substantially vertical direction from the source to the drain, and the conduction state between the source and the drain is controlled.

  The following Non-Patent Documents 1-5 describe a pn junction technique using a 3C—SiC wafer.

JP 2005-79339 A JP 2009-16530 A

H. Nagasawa, K .; Yagi, T .; Kawahara, N .; Hatta, M .; Abe, Microelectronic Eng. 83, 185 (2006) A. Qteish, V .; Heine, R.A. J. et al. Needs, Phys. Rev. B45, 6534 (1992) H. P. Iwata, U .; Lindefelt, S .; Oberg, P.M. R. Briddon, Phys. Rev B 68, 113202 (2003). G. Blatter, F.A. Greuter, Phys. Rev. B33, 3952 (1986) John Wiley & Sons, “SEMICONDUCTOR DEVICES Physics and Technology” (1985) M.M. SZE, AT & Bell Laboratories, Murray Hill, New Jersey. 71-87

  However, the conventional SiC-MOSFET having a pn junction has the following problems.

  For example, when a SiC-MOSFET having a pn junction is manufactured using a 3C-SiC wafer, when a reverse bias voltage is applied to the pn junction, a reverse leakage current flows, and power consumption during off-state There was a problem that increased. This leakage current is believed to be due to stacking faults across the pn junction.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a pn junction with reduced reverse leakage current and a method for manufacturing the same.

  A semiconductor device of the present invention includes an n-type epitaxial layer doped with n-type impurity ions, a p-type region formed by doping p-type impurity ions in the n-type epitaxial layer, and the p-type region And a pn junction portion that is a boundary between the n-type epitaxial layer and the n-type region of the n-type epitaxial layer, wherein the n-type epitaxial layer is higher than a donor concentration in a surface region of the n-type epitaxial layer. It is characterized by having a donor concentration profile in which the donor concentration in the pn junction portion is low.

  The method for manufacturing a semiconductor device of the present invention includes a growth step of growing an n-type epitaxial layer, a p-type region is formed by doping p-type impurity ions in the n-type epitaxial layer, and the p-type region Forming a pn junction portion that is a boundary with the n-type region of the n-type epitaxial layer, wherein the growth step is a control step of controlling the amount of donor-type dopant gas The n-type epitaxial layer having a desired donor concentration profile is grown by the control, and the control step includes comparing the donor concentration of the n-type impurity ions in the surface region of the n-type epitaxial layer with the pn The donor concentration profile is controlled so as to reduce the donor concentration of the n-type impurity ions at the junction. To.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the donor concentration in the pn junction portion is reduced by, for example, reducing the doping amount of impurity ions in the pn junction portion. Therefore, the reverse leakage current can be reduced.

It is typical sectional drawing which shows the structure of the vertical SiC-MOSFET in Example 1 of this invention. It is a figure which shows the pn junction part in FIG. It is a figure which shows the transistor characteristic in the vertical SiC-MOSFET of FIG. It is a figure which shows the reverse leakage current characteristic in the vertical SiC-MOSFET of FIG. It is a schematic diagram of a 3C-SiC-p ⁺ n diode. It is a figure which shows the temperature (T) dependence of the reverse current density of FIG. It is a figure which shows the EBIC image (bright horizontal line = C-SFs) of FIG. It is a figure which shows the temperature (T) dependence of the reverse current density of FIG. It is a figure which shows the EBIC image (bright vertical line = Si-SFs) of FIG. FIG. 4 shows a diagram of a double Schottky barrier for different external electric fields F. It is a figure which shows the Arrhenius plot of leak current. It is a figure which shows the reference example of the leakage current reduction effect of FIG. It is the figure which showed in detail the example of the donor concentration profile of the epitaxial layer in a pn diode. It is a figure which shows the specific example of the cumulative frequency distribution of the leakage current density in the pn diode which has the electric field relaxation structure by the donor concentration profile of FIG.

The inventors of the present application have analyzed the temperature dependence of the leakage current in the 3C-SiC-p ⁺ n diode, and based on the analysis result, proposed a SiC-MOSFET having such a SiC-p ⁺ n junction. . This will be described below.

5 is a schematic diagram of a 3C-SiC-p ⁺ n diode, FIG. 6 is a diagram showing the temperature (T) dependence of the reverse current density of FIG. 5, and FIG. 7 is an EBIC image (bright horizontal line = C-SFs) of FIG. 8 is a diagram showing the temperature (T) dependence of the reverse current density in FIG. 5, FIG. 9 is a diagram showing the EBIC image (bright vertical line = Si-SFs) in FIG. 5, and FIG. (C) is a diagram showing a diagram of a double Schottky barrier for different external electric fields F, and FIG. 11 is an Arrhenius plot of leakage current.

Because of the high electron mobility and the 2.2 eV band gap, 3C-SiC is a semiconductor suitable as an element that operates in a medium withstand voltage region and a high withstand voltage region (600 V or more). Despite these physical advantages, there are still many crystal defects (for example, stacking faults) in the epitaxial layer of 3C-SiC, and the stacking faults cause deterioration of the blocking characteristics of the pn junction. It is thought that. In order to study carrier transport through stacking faults that are thought to contribute to leakage current, for example, a 3C-SiC-p ⁺ n diode as shown in FIG. 5 is manufactured and the temperature dependence of leakage current is studied. investigated.

In the 3C-SiC-p ⁺ n diode 1 shown in FIG. 5, the p ⁺ layer 2 and the n layer 3 are joined by a pn junction 4, and a depletion layer 5 is generated in the pn junction 4. When a positive voltage V1 is applied to the p ⁺ layer 2 and the n layer 3 is connected to the ground GND, the width of the depletion layer 5 is reduced by the forward bias voltage V1, and a forward current easily flows through the depletion layer 5. . On the other hand, when the p ⁺ layer 2 is connected to the ground GND and the positive voltage V1 is applied to the n layer 3, the width of the depletion layer 5 is widened by the reverse bias voltage V1, and the reverse current hardly flows.

The inventors of the present application used an n-type 3C-SiC epilayer (thickness = 13 μm, [N] = 7 × 10 ¹⁵ cm ⁻³ ) (see Non-Patent Document 1), and 6 guard rings (depth = 1 μm, In order to form a 100 μm-diameter p region surrounded by [Al] = 1 × 10 ¹⁸ cm ⁻³ ), aluminum (Al) ions were implanted. The reverse leakage current characteristics were measured in the temperature range of 100K to 295K. Crystal defects and leak current locations are observed with an electron beam induced current (EBIC) and a photoemission microscope (PEM), respectively.

The leakage current characteristic of the pn junction 4 and its temperature dependence vary greatly depending on the defect density under the p ⁺ layer 2. The leakage current characteristics shown in FIG. 6 hardly change with temperature. This EBIC image of the p ⁺ n diode 1 (see FIG. 7) shows two broad slip bands (C-SFs), which probably cause a short circuit current across the pn junction 4. In the voltage dependency of the leakage current, the leakage current increases rapidly in the low voltage region, but shows a gentle slope as the voltage increases.

FIG. 8 shows a leakage current characteristic having a strong temperature dependency often observed in the p ⁺ n diode 1. The bright vertical lines in the EBIC image of the p ⁺ n diode 1 shown in FIG. 9 correspond to stacking faults (Si-SFs) terminated by Si atoms, and a few dark horizontal lines are stacked by C atoms. It corresponds to the defect. Although not shown, one bright small spot is observed in the p ⁺ n junction region from PEM observation.

  In addition, according to the prediction results of the first principle calculation described in Non-Patent Document 2 and Non-Patent Document 3, the electronic structure of the stacking fault of 3C-SiC on the adjacent basal plane is at a pair of twin interfaces. It has been shown to be replaced, causing a spontaneous polarization of approximately 80 meV. Further, according to Non-Patent Document 4, it can be determined that a charged crystal defect can be regarded as a double Schottky barrier electrically. With an applied electric field F, one side of the double Schottky barrier is connected in the forward direction and the other side is connected in the opposite direction.

  An increase in applied electric field F or temperature rise allows many electrons to exceed the barrier (see the diagram of FIG. 10). The local electric field in the vicinity of the barrier is about 1.3 MV / cm, where electrons can obtain a large kinetic energy, so that the leakage current increases due to an increase in the density of charged carriers due to subsequent collisions. . The current exceeding the barrier is expressed by the thermionic emission theory of the following equation (1).

In this equation (1), A ^* , I _S , A and w are the Richardson constant, the saturation current, the area of the p region, and the length of the space charge region, respectively.

The inventors of the present application obtained a leak current value at a different temperature at a reverse bias voltage of 40 V, and obtained a barrier height Φ _B = 90 ± 8 meV that agrees well with the theoretical prediction by an Arrhenius plot. Furthermore, the present inventor has derived that the voltage at which the barrier disappears becomes 140 V as a result of extrapolating the reverse bias voltage at which the barrier height Φ _B becomes 0 meV using the same method for different voltages. It was. Therefore, at a voltage of 140V, all electrons can pass through the Schottky barrier.

  As described above, the inventors of the present invention have a leak current that strongly depends on temperature and applied electric field, and the physical mechanism is that a double Schottky barrier due to spontaneous polarization of stacking faults is present in the depletion layer 5 of the pn junction 4. It was found that this is because it is formed. That is, it has been found that if there is a stacking fault, spontaneous polarization that promotes an increase in the leak current occurs without applying an electric field from the outside, so that the leak current flows due to the stacking fault. Here, since the leakage current has a strong dependence on the electric field strength, the leakage current can be reduced by reducing the electric field of the depletion layer 5 even with the same reverse bias voltage. In other words, in order to reduce the leakage current, it can be said that it is effective to apply a method for reducing the electric field strength at the pn junction portion.

  According to the equation (18) derived from the Poisson equation of the equation (18) described in the equation (14b) on page 76 in Non-Patent Document 5, the maximum electric field strength is proportional to the donor concentration. Based on this equation, one method for reducing the leakage current is to reduce the impurity concentration of the pn junction portion. By utilizing the fact that the maximum electric field strength is proportional to the donor concentration, for example, if the donor concentration at the pn junction is 3/7, the electric field strength is also 3/7, and the leakage current can be reduced accordingly ( (See FIG. 13 on page 77 regarding impurity concentration and electric field distribution in Non-Patent Document 5)).

FIG. 12 is a diagram illustrating a reference example of the leakage current reduction effect in the p ⁺ n diode 1. The reference example in the figure shows the result of the cumulative frequency distribution of the leakage current density when the donor concentration (dopant is nitrogen) of the epitaxial layer of 3C-SiC is simply reduced. Here, “simply” reducing the donor concentration means that the donor concentration is uniformly reduced in the entire epitaxial layer including the pn junction 4, and the donor concentration after the reduction is reduced in the entire epitaxial layer including the pn junction 4. Means constant. In the figure, the horizontal axis represents the leakage current density, and the vertical axis represents the cumulative frequency of the leakage current density. In addition, the results indicated by diamond-shaped dots in the figure (the graph portion on the right side in the figure) indicate that the donor concentration of the epitaxial layer is N _D = 7.5E15 / cm ³ and the results indicated by square dots (the left side in the figure) In the graph part), the donor concentration is N _D = 1.5E15 / cm ³ . When both results are compared, it can be confirmed that the leakage current density shifts to the low density side as the donor concentration decreases. That is, it can be seen that a decrease in donor concentration has an effect of reducing leakage current.

  However, if the impurity concentration (donor type impurities) of the epitaxial layer is simply lowered, there is a concern about an increase in on-resistance as will be described later. Therefore, the inventors of the present application have come up with the idea of adopting an epitaxial layer donor concentration profile as described below, instead of simply reducing the donor concentration of the epitaxial layer.

FIG. 13 is a diagram showing in detail a specific example of the donor concentration profile of the epitaxial layer in the p ⁺ n diode 1. In the figure, the horizontal axis indicates the depth in the direction of the 3C-SiC substrate, and the vertical axis indicates the impurity concentration of the epitaxial layer.

In the donor concentration profile shown in the figure, the first layer located within a depth of 1 μm or less from the epitaxial surface (epi surface) has a donor concentration (dopant is nitrogen) of N _D = 7E15 / cm ³ . This first layer includes an epi surface which is the “surface region” of the epitaxial layer. N _D = 7E15 / cm ³ corresponds to a general donor concentration in the epitaxial layer. That is, the donor concentration in the surface region of the epitaxial layer remains high without being reduced.

The second layer located within a depth of 10 μm from the first layer has a donor concentration (dopant is nitrogen) of N _D = 3E15 / cm ³ . This second layer includes a pn junction 4 that is a boundary between the p ⁺ layer 2 and the n layer 3. That is, in the region range including the pn junction portion, the donor concentration is reduced as compared with the surface region of the epitaxial layer included in the first layer.

The third layer located within a depth of 3 μm from the second layer has a donor concentration (dopant is nitrogen) of N _D = 7E15 / cm ³ . This third layer includes a substrate side surface which is a “surface region” different from the epi surface in the epitaxial layer. That is, this surface region is also kept high without reducing the donor concentration as compared with the pn junction portion, similarly to the epi surface. As described above, the donor concentration profile in the example has a stepped junction in which the donor concentration is changed stepwise.

FIG. 14 is a diagram showing a specific example of the cumulative frequency distribution of the leakage current density in the p ⁺ n diode 1 having the electric field relaxation structure based on the donor concentration profile of FIG. In the figure, the horizontal axis represents the leakage current density, and the vertical axis represents the cumulative frequency of the leakage current density. Moreover, the result shown by the dot of the US mark in the figure (the graph part of the right side in the figure) is a comparative example with respect to the donor concentration profile of FIG. 13, and the donor concentration of the epitaxial layer (the dopant is nitrogen) is N _D = 7. .5E15 / cm ³ is constant. On the other hand, the results shown by the circled dots in the figure (the graph portion on the left side in the figure) indicate the case of the electric field relaxation structure based on the donor concentration profile in FIG. Comparing the two results, when the stepped junction is adopted, the leakage current density is shifted to the lower density side by about an order of magnitude compared to the case of the constant donor concentration (Standard) as a comparative example. I understand that. That is, if the electric field relaxation structure based on the donor concentration profile of FIG. 13 is adopted, the leakage current can be reduced.

  The embodiment of the present invention is not limited to the electric field relaxation structure in which the donor concentration has a stepped profile as described above. That is, the electric field relaxation structure shown in FIG. 13 is only one specific example of the donor concentration profile conceived by the inventors of the present application, and the profile is such that the donor concentration at the pn junction portion is lower than the surface region of the epitaxial layer. If there is, it does not have to be stepped. For example, even if the profile is such that the donor concentration is gradually reduced from the surface region toward the pn junction, the leakage current can be reduced.

  Based on the above, in the present invention, in order to reduce the reverse leakage current caused by the stacking fault SFs crossing the pn junction 4 of 3C-SiC, the vertical SiC- having the following SiC-pn junction is used. A MOSFET was proposed.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Structure of vertical SiC-MOSFET)
FIG. 1 is a schematic cross-sectional view showing the structure of a vertical SiC-MOSFET in Example 1 of the present invention.

The vertical SiC-MOSFET of the first embodiment has an n ⁺ -type 3C-SiC substrate 10 that is a bulk substrate, and an n-type SiC epitaxial layer 11 is formed thereon. A p-type region 12 is formed in the n-type SiC epitaxial layer 11 by ion implantation of a p-type impurity (for example, Al), and an n-type impurity (for example, nitrogen (for example, nitrogen ( N)) is ion-implanted (doped) to form an n ⁺ -type source region 13. In the vicinity of the n ⁺ -type source region 13, a gate region 15 made of poly-Si is formed via a gate insulating film (for example, gate oxide film) 14, and a metal film 16 is further formed on the gate region 15. Is formed.

  An insulating film 17 is formed on the entire surface including the metal film 16. In the insulating film 17, a contact opening 18 having a depth at which the source region 13 and the metal film 16 are exposed is formed at a position facing the source region 13 and the metal film 16. An adhesion layer 19 is formed on the entire surface including A metal wiring layer made of Al or the like is formed on the entire surface of the adhesion layer 19, and the source electrode 20 and the gate electrode 21 separated from each other are formed by patterning the metal wiring layer. A drain electrode 22 made of a metal film is formed on the back surface of the 3C—SiC substrate 10.

  A pn junction 30 is present at the boundary between the p-well 12 and the n-type SiC epitaxial layer 11, and a JFET region 31 is present in a region sandwiched between the gate oxide film 14 and the P-well.

  According to the above analysis based on the temperature-dependent analysis result of the leakage current and the like, if a stacking fault exists at a location crossing the pn junction 30 in FIG. Leakage current occurs. Since this leakage current shows a strong dependence on the electric field strength at the pn junction portion 30, if the electric field strength at the pn junction portion 30 is reduced, the leakage current at the time of reverse bias application can be reduced.

  However, if the impurity concentration of the epitaxial layer (donor type impurity) is simply lowered in order to reduce the electric field strength at the pn junction portion, the donor concentration in the JFET region also decreases at the same time, so that the resistance of the JFET region 31 increases. When the SiC-MOSFET is on, electrons flow through the JFET region 31. As a result, a new problem arises in that the on-resistance of the SiC-MOSFET increases and the transistor characteristics deteriorate.

  Therefore, in Example 1, in order to reduce the leakage current without increasing the on-resistance (that is, by reducing the on-resistance), the depth direction profile of the impurity concentration in the pn junction portion is controlled, The donor concentration in the pn junction portion 30 is reduced while the donor concentration in the JFET region 31 is kept high without being reduced.

  2A to 2C are diagrams showing a pn junction portion in FIG. 1, and FIG. 2A is a schematic cross-sectional view showing the pn junction portion, and FIGS. 2B and 2C. ) Is a diagram showing an example of impurity concentration in a pn junction portion.

  The horizontal axis in FIG. 2A is the depth from the epitaxial surface (epi surface) in FIG. 1 to the 3C-SiC substrate direction, and the vertical axis is the plane direction in the epitaxial surface (epi surface) in FIG. A depletion layer 32 is generated at the pn junction 30. 2B and 2C, the horizontal axis represents the depth from the epitaxial surface (epi surface) of FIG. 1 toward the 3C-SiC substrate, and the vertical axis represents the impurity concentration of the pn junction portion.

  In the method of FIG. 2B, the donor concentration (N-type epi concentration) is not made constant in the entire pn junction portion, but, for example, the donor concentration in a certain region near the pn junction portion 30 is decreased. Here, the reason why the donor concentration in the upper layer portion and the lower layer portion is not reduced is because the adverse effect (on resistance increases) due to the reduction in the donor concentration is taken into consideration. That is, the n-type SiC epitaxial layer 11 has a donor concentration profile in which the donor concentration in the pn junction 30 is lower than the donor concentration in the upper layer portion and the lower layer portion including the surface region of the n-type SiC epitaxial layer 11. Yes.

  In the method of FIG. 2C, the doping amount on the n-type SiC epitaxial 11 side is gradually reduced from the 3C-SiC substrate 10 side toward the pn junction 30 and the donor concentration (N-type epi concentration). . Also according to this method, the n-type SiC epitaxial layer 11 has a donor at the pn junction 30 compared to the donor concentration in the region including the epi surface of the n-type SiC epitaxial layer 11 and the surface region on the 3C-SiC substrate 10 side. The concentration has a low donor concentration profile.

(Manufacturing example of vertical SiC-MOSFET)
A schematic manufacturing example of the vertical SiC-MOSFET of FIG. 1 will be described.

First, an n ⁺ type 3C—SiC substrate 10 is used, and an n type SiC epitaxial layer 11 is grown thereon. The SiC epitaxial layer 11 is, for example, a vapor phase growth method using SiH ₂ Cl ₂ gas as a Si raw material, C ₂ H ₂ gas as a C raw material, argon or hydrogen as a carrier gas, nitrogen (N ₂ ) as a dopant gas, or the like ( Hereinafter referred to as “CVD method”). At this time, an SiC film having a desired dopant concentration is formed by appropriately changing the gas flow rate during growth.

A resist pattern is formed on SiC epitaxial layer 11 by photolithography, and p-type impurities (for example, Al) are ion-implanted using this resist pattern as a mask to form p-well 12. A resist pattern is formed on the entire surface of the SiC epitaxial layer 11 including the p-well 12 by photolithography, and n ⁺ -type impurities (for example, N) are ion-implanted using the resist pattern as a mask, and n ⁺ impurity diffusion is performed. An n ⁺ type source region 13 composed of layers is formed.

An oxide film is formed on the entire surface of the SiC epitaxial layer 11 including the p-well 12 and the n ⁺ -type source region 13, and a poly-Si layer and a metal layer are further formed thereon. Then, the oxide film is oxidized by a photolithography technique. The film, the poly-Si layer, and the metal layer are patterned to form a gate oxide film 11, a gate region 15 made of a poly-Si layer, and a metal film 16 in the vicinity of the source region 13.

  An insulating film 17 is deposited on the entire surface of the SiC epitaxial layer 11 including the metal film 16 by CVD or the like. A contact opening 18 is formed in the insulating film 17 by photolithography, and the source region 13 and the metal film 16 are exposed. An adhesion layer 19 is formed on the entire surface of the insulating film 17 including the opening 18, and a metal wiring layer such as Al is further formed on the entire surface of the adhesion layer 19. The metal wiring layer is patterned by photolithography technology to form the source electrode 20 and the gate electrode 21 separated from each other. The source electrode 20 is electrically connected to the source region 13 via the opening 18 and the adhesion layer 19, and the gate electrode 21 is connected to the gate region 15 via the opening 18, the adhesion layer 19 and the metal film 16. Electrically connected.

  If the drain electrode 22 made of a metal film or the like is formed on the back surface of the 3C-SiC substrate 10 by sputtering or the like, the manufacture of the vertical SiC-MOSFET of FIG. 1 is completed.

(Operation of vertical SiC-MOSFET)
FIG. 3 shows transistor characteristics of the vertical SiC-MOSFET shown in FIG. 1, in which the drain-source voltage Vds dependence of the drain-source current Ids is measured using the gate-source voltage Vgs as a parameter. Further, FIG. 4 is a diagram showing reverse leakage current characteristics in the vertical SiC-MOSFET of FIG.

  As shown in FIG. 3, in the vertical SiC-MOSFET of FIG. 1, when a gate-source voltage Vgs (for example, 15 V) is applied, if the drain-source voltage Vds increases, an arrow in FIG. As shown, electrons flow from the source region 13 → the p well 12 under the gate oxide film 14 → the JFET region 31 → the 3C-SiC substrate 10 → the drain electrode 22, and the drain-source current Ids increases rapidly. When the gate-source voltage Vgs is 15 V or less, for example, 10 V or 8 V, the drain-source current Ids saturates to a constant value when the drain-source voltage Vds exceeds a predetermined voltage.

  Further, as shown in FIG. 4, in the vertical SiC-MOSFET of FIG. 1, when the reverse-biased drain-source voltage Vds increases, the drain-source leakage in the reverse direction is caused by stacking faults generated in the pn junction 30. The current Ids increases rapidly. In the first embodiment, as assumed from FIGS. 2B and 2C, the donor concentration in the pn junction portion 30 is reduced while the donor concentration in the JFET region 31 is kept high. The electric field relaxation of the pn junction portion is achieved without increasing the on-resistance, and the leakage current Ids is reduced.

(Effect of Example 1)
According to the vertical SiC-MOSFET and the manufacturing method thereof of the first embodiment, the n-type SiC epitaxial layer 11 has an n-type having a desired donor concentration profile by controlling the amount of the donor-type dopant gas such as N ₂ during the growth of the n-type SiC epitaxial layer 11. Since the SiC epitaxial layer 11 is grown, the electric field of the pn junction 30 can be relaxed without increasing the on-resistance, and the leakage current Ids when a reverse bias is applied can be reduced.

(Modification)
The present invention is not limited to the first embodiment, and various usage forms and modifications are possible.
For example, in the first embodiment of the present invention, an n-type SiC-MOSFET is used, but a similar effect can be expected with a p-type SiC-MOSFET.

  Further, the structure and manufacturing method in the vertical SiC-MOSFET of the first embodiment may be changed to a structure and manufacturing method other than those shown in the drawing.

10 n ⁺ type 3C-SiC substrate 11 n type SiC epitaxial layer 12 p well 13 n ⁺ type source region 14 gate oxide film 15 gate region 20 source electrode 21 gate electrode 22 drain electrode 30 pn junction 31 JFET region 32 depletion layer region

Claims (6)

an n-type epitaxial layer doped with n-type impurity ions;
A p-type region formed by doping p-type impurity ions in the n-type epitaxial layer; and a pn junction portion that is a boundary between the p-type region and the n-type region of the n-type epitaxial layer. A semiconductor device,
The n-type epitaxial layer has a donor concentration profile in which the donor concentration of the n-type impurity ions in the pn junction portion is lower than the donor concentration of the n-type impurity ions in the surface region of the n-type epitaxial layer. A semiconductor device.   2. The semiconductor device according to claim 1, wherein the semiconductor device is a SiC field effect transistor having the pn junction portion.   The semiconductor device according to claim 1, wherein the n-type epitaxial layer is formed on a 3C—SiC substrate. a growth step of growing an n-type epitaxial layer;
In the n-type epitaxial layer, p-type impurity ions are doped to form a p-type region, and a pn junction portion that is a boundary between the p-type region and the n-type region of the n-type epitaxial layer is formed. Process,
A method of manufacturing a semiconductor device having
The growth step includes a control step of controlling the amount of donor-type dopant gas, and the control grows the n-type epitaxial layer having a desired donor concentration profile.
In the control step, the donor concentration profile is set such that the donor concentration of the n-type impurity ions in the pn junction portion is reduced compared to the donor concentration of the n-type impurity ions in the surface region of the n-type epitaxial layer. A method of manufacturing a semiconductor device, comprising: controlling the semiconductor device.   The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is a SiC field effect transistor having the pn junction portion.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the n-type epitaxial layer is formed by being grown on a 3C-SiC substrate.