JP2002368015A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SiC field-effect transistor that can avoid anisotropy in device characteristics due to the influence of lamination defects. SOLUTION: The field-effect transistor is formed on a silicon carbide single crystal substrate having lamination defects. It is featured in that the lamination defect line density in the substrate is set to 500/cm or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor formed on a conductive layer formed by epitaxial growth or ion implantation on a silicon carbide (SiC) single crystal substrate.

[0002]

2. Description of the Related Art Silicon carbide (SiC) has attracted attention as an environment-resistant semiconductor material because of its excellent heat resistance and mechanical strength and physical and chemical stability. In recent years, demand for SiC single crystal wafers as substrate wafers for high-frequency high-voltage electronic devices and the like has been increasing.

Power devices using SiC single crystal wafers,
When manufacturing high-frequency devices, SiC is usually formed on a wafer using a method called thermal CVD (thermal chemical vapor deposition).
Generally, a thin film is epitaxially grown or a dopant is directly implanted by an ion implantation method.

[0004] At this time, the (0001) plane or the (000-1) plane is usually used as the plane orientation of the SiC wafer, and threading dislocations called micropipes are present on these planes in an amount of 50 to 100.
Per cm ² , and in the ion implantation method,
The micropipe is inherited as it is in the epitaxial growth. Devices made on micropipes are known to have poor properties (e.g.
Kimoto, et al., IEEE Tran. Electron. Devices 46 (3)
pp.471-477, 1999), the reduction of micropipes is urgently needed. On the other hand, Takahashi et al.
Micropipes do not exist in the SiC single crystal grown in the <11-20> direction (J. Takahashi, et al.,
J. Cryst. Growth 135, 1994), and Yano et al.
A MOS device was prototyped using an epitaxial thin film grown on a wafer with a (1-20) plane.In the case of 4H-SiC, the conventional (00
It shows that the electron mobility is about 20 times higher than when using the (01) plane (H. Yano, et al., Mater. Sci. Forum 338-
342, 2000), attention has been paid to epitaxial thin films grown on wafers having a (11-20) plane.

However, in the case of 6H-SiC, the (1-100) plane of the SiC crystal grown in the <1-100> direction grows about 1000 times the (000-1) plane and grows in the <11-20> direction. (11-20)
There is also a defect called stacking fault about 100 times on the surface, and stacking fault also exists on 4H-SiC, although it is about 1/10 that of 6H. Even if epitaxial growth is performed on such a wafer, stacking faults are considered to be inherited, and there is a concern that devices formed on these surfaces may be adversely affected. Actually, when a SiC crystal with a stacking fault linear density of about 5,000 / cm is used as a substrate, normal device operation is performed when a current flows in a direction that does not cross stacking faults (parallel to stacking faults). However, when a current is passed in a direction that crosses (perpendicular to the stacking fault), the absolute value of the current is 1/100 to 1/100 of that in the direction parallel to the stacking fault.
It has been experimentally confirmed that only about 0 is obtained and the device does not operate normally. That is, if the stacking fault linear density is about 5000 / cm, anisotropy occurs in the device characteristics, and a device in which the current direction is perpendicular to the stacking fault direction cannot be formed, and the degree of freedom in device design is extremely small. Become.

The results of Yano et al. Described above were obtained by cutting a SiC single crystal grown in the c-axis direction in parallel with the c-axis, that is, so-called longitudinal cutting (11-
This is the result of using a wafer having a 20) plane. In this case, since there is no stacking fault in the wafer, it is not necessary to consider the effect. However, large diameter (1-100)
In order to obtain a wafer having a plane or a (11-20) plane, it is necessary to grow SiC in the c-axis direction at least as long as its diameter and to make it thick, which is technically difficult. Therefore, (1-1
Using a wafer with a (00) plane or (11-20) plane as a seed crystal, grow a single crystal by growing the diameter in the <1-100> or <11-20> direction, and create a wafer from this However, in this case, as described above, the problem of stacking faults is inevitable.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a SiC field effect transistor capable of avoiding anisotropy of device characteristics due to the above-mentioned problem of stacking faults.

[0008]

The density of stacking faults is such that a single crystal is grown from a seed crystal, a seed crystal is cut out from the single crystal and a single crystal is grown again. It is known that the value of a single crystal wafer is smaller as it is cut from a portion closer to the seed crystal. Therefore, if the stacking fault linear density is below a certain value, it is conceivable that the anisotropy of the device characteristics as described above may not appear, and it is possible to confirm the possibility, (1-100)
It has become important for practical use of devices on the (11-20) plane.

Therefore, the (1-100) or (11-20) plane of the SiC wafer grown in the <1-100> or <11-20> direction,
Furthermore, micropipes do not exist on those surfaces that have been epitaxially grown on those surfaces, which improves the electron mobility of MOS and is an effective method for improving both yield and device characteristics. The anisotropy of the device characteristics due to the above has been studied diligently.

[0010] Here, the line defect density is a defect density per unit length (normally 1 cm) in a direction perpendicular to the direction of stacking faults.

The present invention relates to a (1-100) or (11-20) plane of a SiC crystal grown in a <1-100> or <11-20> direction,
Further, when forming a device on a surface on which epitaxial growth has been performed on those surfaces, it has been found that the above problem can be solved if the stacking fault density of the substrate is lower than a certain value.

That is, the present invention provides (1) a transistor formed on a silicon carbide single crystal substrate having a stacking fault,
The field effect transistor, wherein the stacking fault linear density existing in the substrate is 500 / cm or less, (2) the plane orientation of the silicon carbide single crystal is (11-20) plane (1) description. (3) The field effect transistor according to (1), wherein a plane orientation of the silicon carbide single crystal is a (1-100) plane.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the effect of stacking faults on device operation will be described. Stacking faults present in the SiC wafer are considered to be linear traps, and when electrons are trapped here, a depletion layer is formed around them, increasing the potential and causing a barrier to the flow of electrons, that is, the current. Conceivable. Therefore, when a device is formed on a substrate having such traps, a current in a direction crossing a stacking fault becomes difficult to flow due to the influence of this potential, and the above-described anisotropy occurs. This anisotropy should not appear if the stacking fault linear density is zero, but it is difficult to grow the crystal. It is important to keep the defect density below that value. Therefore, when considering a field-effect transistor, it was determined that anisotropy could be avoided if the density could be reduced to such an extent that stacking faults did not exist between the source and the drain. This is because the distance between the source and the drain is usually about 10 μm, and if one stacking fault exists between them, the linear density is 1000 μm.
/ Cm, so 1/2 of this value, that is, 500 / cm
If it is below, it is considered that the stacking fault does not actually exist between the source and the drain. In fact, it is possible to create a single crystal with a stacking fault density of about 500 / cm, and when a device is formed on such a single crystal substrate, no anisotropy appears and it is usually prototyped The same characteristics as the device on the (0001) plane were obtained, and it was confirmed that good device characteristics were obtained without being affected by stacking faults. The (1-100) or (11-20) plane of the crystal grown in the <1-100> or <11-20> direction has a larger diameter than the vertical section of the crystal grown in the c-axis direction. The present invention is easy, and therefore the cost of the wafer can be reduced.

[0014]

(Example 1) FIG. 1 shows a substrate obtained by epitaxial growth on the (11-20) plane of a SiC single crystal wafer grown in the <11-20> direction in order to form a field effect transistor. It is sectional drawing. 1 is an SiC wafer, 2 is an SiC buffer layer grown epitaxially, which does not transmit the influence of substrate roughness, strain and the like upward. Reference numeral 3 denotes an epitaxially grown SiC active layer. In this example, nitrogen is doped so that a current flows. here,
The stacking fault linear density in the SiC wafer is 500 / cm or less. Such a SiC wafer cuts a SiC single crystal grown in the c-axis direction parallel to the c-axis, and uses it as a seed crystal <11-20>
By cutting from the SiC single crystal grown in the direction,
Obtainable. For the drain voltage-drain current characteristics of the field-effect transistor created on such a substrate, FIG. 2 (a) shows the case where the direction of current flow is <1-100> direction (parallel to stacking faults). FIG. 2B shows the case of the> direction (perpendicular to the stacking fault). There is no difference in characteristics depending on the direction in which current flows, and the characteristics are the same as those of a field-effect transistor formed on a normal (0001) plane.The pinch-off characteristics are good, and the effect of stacking faults has not appeared. I understand.

(Comparative Example) As a comparative example, regarding the drain voltage-drain current characteristic of a field effect transistor when the stacking fault linear density in a SiC wafer is about 5000 / cm, the current flowing direction is <1-100. Fig. 3 (a) shows the <0001
The case of the> direction is shown in FIG. 3 (b). First, in FIG. 3B, it can be seen that the absolute value of the current is smaller by about two digits. Furthermore, it does not show good pinch-off characteristics, and it is judged that the influence of anisotropy caused by the stacking fault described above appears.

In this embodiment, the (11-20) plane of the SiC crystal grown in the <11-20> direction has been described, but the (1-100) plane of the SiC crystal grown in the <1-100> direction has been described. It was similar. Also,
The metal-semiconductor field effect transistor (ME
It is clear that the present invention can be applied not only to SFETs) but also to metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction transistors (JFETs).

[0017]

As described above, according to the present invention, the (1-100) or (11-20) plane of the SiC crystal grown in the <1-100> or <11-20> direction, Further, an electronic device or the like having no anisotropy and excellent electric characteristics can be manufactured on the surface on which those surfaces are epitaxially grown. These surfaces can increase the production yield because micropipes do not exist. In addition, <1
-100> or <11-20>
The (0) plane or the (11-20) plane is easier to increase the diameter than the vertical cutting of the crystal grown in the c-axis direction, and has an effect of reducing the cost of the wafer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an epitaxial growth substrate to which the present invention is applied.

FIG. 2 shows a drain voltage-drain current characteristic of the field-effect transistor of the present invention.

FIG. 3 shows a drain voltage-drain current characteristic of a field-effect transistor according to a conventional method.

[Explanation of symbols]

 1. SiC wafer 2. epitaxially grown SiC buffer layer 3. epitaxially grown SiC active layer

Continued on the front page (72) Inventor Hirokatsu Yashiro 20-1 Shintomi, Futtsu-shi, Chiba Nippon Steel Corporation Technology Development Division (72) Inventor Tatsuo Fujimoto 20-1 Shintomi, Futtsu-shi, Chiba Nippon Steel Corporation In-house Technology Development Headquarters (72) Inventor Masakazu Katsuno 20-1 Shintomi, Futtsu-shi, Chiba Nippon Steel Corporation In-house Technology Development Headquarters F-term (reference) BA20 BC12

Claims (3)

[Claims] 1. A field effect transistor comprising a transistor formed on a silicon carbide single crystal substrate having stacking faults, wherein a stacking fault linear density existing in the substrate is 500 / cm or less. Transistor. 2. The silicon carbide single crystal has a plane orientation of (11-20).
2. The field effect transistor according to claim 1, which is a surface. 3. The plane orientation of the silicon carbide single crystal is (1-100).
2. The field effect transistor according to claim 1, which is a surface.