JP5810894B2 - semiconductor substrate - Google Patents

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JP5810894B2
JP5810894B2 JP2011280865A JP2011280865A JP5810894B2 JP 5810894 B2 JP5810894 B2 JP 5810894B2 JP 2011280865 A JP2011280865 A JP 2011280865A JP 2011280865 A JP2011280865 A JP 2011280865A JP 5810894 B2 JP5810894 B2 JP 5810894B2
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太郎 西口
太郎 西口
原田 真
真 原田
藤原 伸介
伸介 藤原
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住友電気工業株式会社
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  The present invention relates to a semiconductor substrate, and more particularly to a semiconductor substrate made of single crystal silicon carbide.

  In recent years, silicon carbide substrates have begun to be used for manufacturing semiconductor devices. Silicon carbide has a larger band gap than a general material such as silicon. Therefore, a semiconductor device using a silicon carbide substrate has advantages such as high breakdown voltage, low on-resistance, and small deterioration in characteristics under a high temperature environment.

On the other hand, in order to realize a semiconductor device having excellent characteristics as described above, it has been proposed to use a silicon carbide substrate with a reduced density of crystal defects. For example, US Pat. No. 7,314,520 (Patent Document 1) discloses a silicon carbide substrate in which the density of screw dislocations is 2500 cm −2 or less.

US Pat. No. 7,314,520

  However, even if only the defects disclosed in the above-described prior art documents are suppressed, it is difficult to improve the yield of the semiconductor device formed on the silicon carbide substrate.

  The present invention has been made to solve the above-described problems, and is to provide a silicon carbide semiconductor substrate capable of improving the yield of semiconductor devices.

  As a result of diligent research, the inventor of the present application pays attention to the local dislocation density, not the average dislocation density of the silicon carbide semiconductor substrate, in order to improve the yield of the silicon carbide semiconductor device. It has been found that it is important to reduce the dislocation density in all regions used for manufacturing the device.

Therefore, the semiconductor substrate according to the present invention is a semiconductor substrate having a main surface and made of single crystal silicon carbide. The main surface includes a central region which is a region excluding a region within 5 mm from the outer periphery. When the central area is divided into square areas each having a side of 1 mm 2 , in any square area, the Burgers vector includes a component parallel to the <0001> direction and a component parallel to the <11-20> direction. Is 1 × 10 5 cm −2 or less.

  Thereby, the yield of the semiconductor device manufactured using the said semiconductor substrate can be improved.

  In the semiconductor substrate, preferably, in the central region, the density of dislocations whose Burgers vector is parallel to the <0001> direction is such that the Burgers vector includes dislocations including <0001> direction components and <11-20> direction components. Lower than density.

  Thereby, the yield of the semiconductor device manufactured using the said semiconductor substrate can further be improved.

  In the above semiconductor substrate, preferably, in the central region, the density of dislocations in which the Burgers vector is parallel to the <11-20> direction includes a component in the <0001> direction and a component in the <11-20> direction. Lower than dislocation density.

  Thereby, the yield of the semiconductor device manufactured using the said semiconductor substrate can further be improved.

  In the semiconductor substrate, the semiconductor substrate may be branched into a plurality of dislocation lines, and the Burgers vector may include a dislocation having a component in the <0001> direction and a component in the <11-20> direction. .

  In the above semiconductor substrate, the diameter is preferably 4 inches or more. Thereby, since a large-diameter semiconductor substrate is obtained, a semiconductor device can be manufactured efficiently.

  In the semiconductor substrate described above, the polytype of single crystal silicon carbide constituting the semiconductor substrate is preferably 4H.

  A semiconductor device using a silicon carbide substrate having a polytype of 4H can be suitably used for a power device because of its high mobility.

  According to the semiconductor substrate of the present invention, the yield of semiconductor devices can be improved.

It is a top view which shows roughly the semiconductor substrate in Embodiment 1 of this invention. It is a top view which shows roughly a part of semiconductor substrate in Embodiment 1 of this invention. It is a figure which illustrates roughly the basal plane dislocation and threading dislocation when the off angle is 0. It is a figure which illustrates roughly the basal plane dislocation and threading dislocation at the off angle θ. It is sectional drawing which shows schematically the semiconductor substrate in Embodiment 1 of this invention. It is a schematic diagram which illustrates roughly the apparatus for manufacturing the semiconductor substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a flowchart which shows schematically the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows roughly the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number. The angle is described using a system in which the omnidirectional angle is 360 degrees.

(Embodiment 1)
Referring to FIG. 1, semiconductor substrate 10 of the present embodiment is made of single crystal silicon carbide, and has a main surface 1 and a central region 3. Single crystal silicon carbide has a hexagonal crystal structure. The polytype of single crystal silicon carbide constituting semiconductor substrate 10 is preferably 4H. The normal line of the main surface 1 is inclined, for example, from the <0001> direction by an off angle θ. As a specific example, the main surface 1 is preferably a plane obtained by turning off the (0001) plane by 4 degrees in the <11-20> direction. The aperture of the semiconductor substrate 10 is preferably 4 inches or more.

  The central region 3 is a region excluding a region of, for example, 5 mm (distance indicated by a in FIG. 1) from the outer periphery 2 of the semiconductor substrate 10 toward the center of the semiconductor substrate. As shown in FIG. 1, the case where the center area | region 3 is divided | segmented into many square area | regions 4 whose 1 side is 1 mm is assumed.

  FIG. 2 is an enlarged view of the square region 4 of the semiconductor substrate 10. Referring to FIG. 2, the square region 4 usually contains various types of dislocations. Square region 4 has dislocations 23 in which, for example, the Burgers vector includes a component in the <11-20> direction and a component in the <0001> direction.

  In addition, the square region 4 may have dislocations 22 in which, for example, the Burgers vector is parallel to the <11-20> direction. In this dislocation 22, the Burgers vector is parallel to the <11-20> direction, the dislocation line is in the basal plane, the dislocation line is exposed on the main surface of the semiconductor substrate, and the other dislocation 25. And may be included. The basal plane is the (0001) plane (in other words, the plane having the c-axis as a normal line). Furthermore, the square region 4 may have dislocations 21 whose Burgers vector is parallel to the <0001> direction.

The density of dislocations 23 in which the Burgers vector includes a component in the <11-20> direction and a component in the <0001> direction, which the semiconductor substrate 10 of the present embodiment has, is 1 × 10 5 in any square region 4. cm -2 or less. More preferably, the density of dislocations 23 in which the Burgers vector includes a component in the <11-20> direction and a component in the <0001> direction is 1 × 10 4 cm −2 or less in any square region 4, More preferably, it is 1 × 10 3 cm −2 or less.

Preferably, in any square region 4, the density of dislocations 22 whose Burgers vector is parallel to the <11-20> direction is 1 × 10 5 cm −2 or less, more preferably 1 × 10 4 cm −2. Or less, more preferably 1 × 10 3 cm −2 or less.

Preferably, in any square region 4, the density of dislocations 21 whose Burgers vector is parallel to the <0001> direction is 1 × 10 5 cm −2 or less, more preferably 1 × 10 4 cm −2 or less. More preferably 1 × 10 3 cm −2 or less.

  Preferably, in the central region 3, the density of dislocations 22 whose Burgers vector is parallel to the <11-20> direction is such that the Burgers vector includes a dislocation 23 including a component in the <0001> direction and a component in the <11-20> direction. Is less than the density. More preferably, in any square region 4, the density of dislocations 22 in which the Burgers vector is parallel to the <11-20> direction includes the components in the <0001> direction and the components in the <11-20> direction. It is lower than the density of dislocations 23 included.

  Also preferably, in the central region 3, the density of dislocations 21 whose Burgers vector is parallel to the <0001> direction, and the density of dislocations 23 whose Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction. Lower than. More preferably, in any square region 4, the density of dislocations 21 whose Burgers vector is parallel to the <0001> direction is such that the Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction. The density is lower than 23.

Here, a method for measuring the density of dislocations will be described.
The density of dislocations is obtained by performing etching on the surface of the semiconductor substrate 10 and then counting the number of etch pits on the surface of the semiconductor substrate 10 using, for example, a Nomarski differential interference microscope. The etching process is performed by immersing the semiconductor substrate 10 in a KOH (potassium hydroxide) melt at 500 ° C. for 10 minutes, for example. Further, the etching process may be performed by gas-etching the surface of the semiconductor substrate 10 with a mixed gas of chlorine and oxygen at 1000 ° C. for 1 hour.

Next, the above-described terms will be described with reference to FIGS.
FIG. 3 is a diagram showing dislocations generated in semiconductor substrate 10 made of single-crystal silicon carbide having an off angle of zero. Dislocations are mainly classified into threading dislocations 6 and basal plane dislocations 5. The threading dislocation 6 is a dislocation that extends so as to extend from one main surface 1 of the semiconductor substrate 10 to the other main surface 1. In FIG. 3, the semiconductor substrate 10 extends in the <0001> direction from one main surface 1 to the other main surface 1. When the off angle is 0, the dislocation line of threading dislocation 6 extends in the <0001> direction. The basal plane dislocation 5 is a dislocation having dislocation lines in the basal plane of the crystal. The dislocation line of the basal plane dislocation 5 extends parallel to the basal plane.

  FIG. 4 is a diagram showing dislocations generated in semiconductor substrate 10 made of single crystal silicon carbide having an off angle of θ. As described above, the dislocation line of the basal plane dislocation 5 extends in parallel with the basal plane (c-plane). Therefore, basal plane dislocations 5 may be exposed to main surface 1 when the off-angle of single crystal silicon carbide constituting semiconductor substrate 10 has a finite value θ. Further, when the dislocation line of the basal plane dislocation 5 extends in the <11-20> direction, the basal plane dislocation 5 may be exposed on the side surface of the semiconductor substrate 10. The dislocation 7 is an example of a dislocation in which the dislocation line is in the basal plane and the dislocation line is exposed on the main surface of the semiconductor substrate 10.

  Referring to FIG. 5, semiconductor substrate 10 branches into a plurality of dislocation lines 8 inside semiconductor substrate 10, and the Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction. You may have a dislocation. Further, the branched dislocation lines 8 may be gathered inside the semiconductor substrate 10 to form a dislocation whose Burgers vector is 1c + 1/3 <11-20>.

  Further, the semiconductor substrate 10 may be branched into a plurality of dislocation lines 8 inside the semiconductor substrate 10, and the Burgers vector may have dislocations parallel to the <11-20> direction. For example, when the polytype of silicon carbide forming the semiconductor substrate 10 is 4H, dislocations with a Burgers vector of 1/3 <11-20> are generated, and a Burgers vector within a semiconductor substrate 10 has a 1/3 <10-10. > And 1/3 <01-10>, which is divided into two dislocation lines 8. The two dislocation lines 8 may be gathered inside the semiconductor substrate 10 to form a dislocation whose Burgers vector is 1/3 <11-20>.

  Further, the semiconductor substrate 10 may be branched into a plurality of dislocation lines 8 inside the semiconductor substrate 10, and the Burgers vector may have dislocations parallel to the <0001> direction. For example, when the polytype of silicon carbide forming the semiconductor substrate 10 is 4H, a dislocation whose Burgers vector is 1c (where 1c = <0001>, the same applies hereinafter) is formed inside the semiconductor substrate 10 by Burgers. It is divided into four dislocation lines 8 having a vector of 0.25c. The four dislocation lines 8 may be gathered inside the semiconductor substrate 10 to form a dislocation whose Burgers vector is 1c.

Next, a method for manufacturing the semiconductor substrate 10 of the present embodiment will be described.
Referring to FIG. 6, the semiconductor substrate 10 manufacturing apparatus mainly includes a crucible 11 and a heating unit (not shown). A raw material 12 is accommodated inside the crucible 11. The raw material 12 is a raw material for growing the silicon carbide crystal 14 and is not particularly limited as long as it generates a raw material gas such as SiC 2 gas or Si 2 C gas. For example, it is preferable to use silicon carbide powder as the raw material 12 because of easy handling and easy preparation of the raw material. Silicon carbide powder can be obtained, for example, by pulverizing silicon carbide polycrystal. The heating unit is arranged to surround the outside of the crucible 11 and heats the raw material 12. For example, a high-frequency heating coil is used as the heating unit.

  A seed crystal 13 is arranged inside the crucible 11. A silicon carbide crystal 14 is grown on the seed crystal 13 by sublimating the raw material 12. The seed crystal 13 is a crystal made of silicon carbide, and its crystal structure is preferably a hexagonal system. As for the plane orientation of the surface of the seed crystal substrate, for example, in the case of hexagonal system, {0001} plane, {03-38} plane and the like can be mentioned. Further, it is preferable that an off-angle is formed from these crystal planes. As a specific example, a plane in which the (0001) plane is inclined by 10 degrees or less in the <11-20> direction is preferable. The off angle is more preferably 2 degrees or more and 8 degrees or less, and further preferably 4 degrees or more and 6 degrees or less.

  The surface of seed crystal 13 is preferably subjected to, for example, CMP (Chemical Mechanical Polishing) treatment. As for the roughness of the surface of the seed crystal 13, for example, the root mean square roughness (RMS) is preferably smaller than 1 nm.

  As shown by the arrow in FIG. 6, silicon carbide crystal 14 grows on seed crystal 13 by sublimating raw material 12 and recrystallizing on seed crystal 13. The temperature at which silicon carbide is sublimated and recrystallized is, for example, 2100 ° C. or higher and 2500 ° C. or lower. A temperature gradient is provided so that the temperature decreases from the raw material 12 side to the seed crystal 13 side.

  The inside of the crucible 11 is filled with, for example, a mixed gas of argon and nitrogen. The temperature of the atmosphere inside the crucible 11 becomes a predetermined temperature of, for example, 2000 ° C. or more and 2500 ° C. or less, and the pressure of the atmosphere inside the crucible 11 becomes a predetermined pressure of, for example, 5 kPa or less. When the environment in which the source gas is generated is reached, vapor phase growth of the silicon carbide crystal 14 by the sublimation method starts. The growth rate of silicon carbide at this time is preferably slower than 0.01 mm per hour, for example. The growth pressure during the growth of the silicon carbide crystal is, for example, about 4 kPa (30 torr).

  The seed crystal 13 is provided with an off angle of, for example, 4 degrees. If there is a dislocation on the surface of the seed crystal 13, the silicon carbide crystal 14 grown thereon will also take over the dislocation. Silicon carbide crystal 14 is grown on the surface of seed crystal 13 in a step flow growth mode in which two-dimensional nuclei are not generated with off-angle provided in seed crystal 13. Thereby, some of the dislocations exposed on the surface of the seed crystal 13 can be removed in the lateral direction in the figure without extending toward the main surface. Moreover, generation of new dislocations during the growth of silicon carbide crystal 14 can be suppressed.

  After growing silicon carbide crystal 14 to a predetermined thickness as described above, semiconductor substrate 10 made of silicon carbide is completed by slicing silicon carbide crystal 14.

Next, the effect of the semiconductor substrate 10 of this Embodiment is demonstrated.
Semiconductor substrate 10 according to the present embodiment is fabricated in a direction that allows the dislocations on the surface of seed crystal 13 to escape laterally as described above and suppresses the occurrence of new dislocations during the growth of silicon carbide crystal 14. It is made by slicing silicon carbide crystal 14. As a result, in any square region 4 obtained by dividing the central region 3 into square regions 4 each having a side of 1 mm, the Burgers vector has a component parallel to the <0001> direction and a component parallel to the <11-20> direction. The density of dislocations included is 1 × 10 5 cm −2 or less.

  Thereby, the yield of the semiconductor device manufactured using the said semiconductor substrate 10 can be improved.

  Further, when the Burgers vector has a density of dislocations parallel to the <0001> direction and the Burgers vector is lower than the density of dislocations including a component in the <0001> direction and a component in the <11-20> direction, the semiconductor substrate 10 The yield of semiconductor devices manufactured using can be further improved.

  Furthermore, when the density of dislocations whose Burgers vector is parallel to the <11-20> direction is lower than the density of dislocations where the Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction, the semiconductor The yield of semiconductor devices manufactured using the substrate 10 can be further improved.

  Furthermore, when the diameter of the semiconductor substrate 10 is 4 inches or more, a large-diameter semiconductor substrate can be obtained, and a semiconductor device can be manufactured efficiently.

  Furthermore, when the polytype of the single crystal silicon carbide composing the semiconductor substrate 10 is 4H, a semiconductor device using a silicon carbide substrate having a polytype of 4H has high mobility and can be suitably used for a power device.

(Embodiment 2)
Referring to FIG. 7, the semiconductor device 100 of the present embodiment is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor substrate 10, a buffer layer 121, a breakdown voltage holding layer 122, and a p region 123. N + region 124, p + region 125, oxide film 126, source electrode 111, upper source electrode 127, gate electrode 110, and drain electrode 112.

The semiconductor substrate 10 has n-type conductivity in the present embodiment, and, as described in the first embodiment, the Burgers vector is in the <11-20> direction and the component parallel to the <0001> direction. The density of dislocations including parallel components is 1 × 10 5 cm −2 or less in any square region 4.

Buffer layer 121 has n-type conductivity and has a thickness of 0.5 μm, for example. The concentration of the n-type conductive impurity in the buffer layer 121 is, for example, 5 × 10 17 cm −3 .

The breakdown voltage holding layer 122 is formed on the buffer layer 121 and is made of silicon carbide having an n-type conductivity. For example, the thickness of the breakdown voltage holding layer 122 is 10 μm, and the concentration of the n-type conductive impurity is 5 × 10 15 cm −3 .

  In the region including the surface of the breakdown voltage holding layer 122, a plurality of p regions 123 having a p-type conductivity are formed at intervals. An n + region 124 is formed in the surface layer of the p region 123 inside the p region 123. A p + region 125 is formed at a position adjacent to the n + region 124. On the n + region 124 in one p region 123, from the p region 123, the breakdown voltage holding layer 122 exposed between the two p regions 123, the other p region 123, and the n + region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126. A source electrode 111 is formed on the n + region 124 and the p + region 125. An upper source electrode 127 is formed on the source electrode 111.

The maximum value of the nitrogen atom concentration in the region within 10 nm from the interface between the oxide film 126 and the n + region 124, p + region 125, p region 123 and the breakdown voltage holding layer 122 as the semiconductor layer is 1 × 10 21 cm −3. That's it. As a result, the mobility of the channel region under the oxide film 126 (the portion in contact with the oxide film 126 and the p region 123 between the n + region 124 and the breakdown voltage holding layer 122) can be improved. .

Next, a method for manufacturing the semiconductor device 100 will be described.
First, in the substrate preparation step (step S110: FIG. 8), the semiconductor substrate 10 is prepared by the method described in the first embodiment. The conductivity type of the semiconductor substrate 10 is, for example, n type.

  Referring to FIG. 9, buffer layer 121 and breakdown voltage holding layer 122 are formed as follows by the epitaxial layer forming step (step S120: FIG. 8).

First, the buffer layer 121 is formed on the surface of the semiconductor substrate 10. Buffer layer 121 is made of silicon carbide of n-type conductivity, and is an epitaxial layer having a thickness of 0.5 μm, for example. The concentration of the conductive impurity in the buffer layer 121 is set to 5 × 10 17 cm −3 , for example.

Next, the breakdown voltage holding layer 122 is formed on the buffer layer 121. Specifically, a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method. The thickness of the breakdown voltage holding layer 122 is, for example, 10 μm. The concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 is, for example, 5 × 10 15 cm −3 .

  Referring to FIG. 10, p region 123, n + region 124, and p + region 125 are formed as follows by the implantation step (step S130: FIG. 8).

  First, an impurity having a p-type conductivity is selectively implanted into a part of the breakdown voltage holding layer 122, whereby the p region 123 is formed. Next, n + region 124 is formed by selectively injecting n-type conductive impurities into a predetermined region, and p-type conductive impurities are selectively injected into the predetermined region. As a result, ap + region 125 is formed. The impurity is selectively implanted using a mask made of an oxide film, for example.

  After such an implantation step, an activation annealing process is performed. For example, annealing is performed in an argon atmosphere at a heating temperature of 1700 ° C. for 30 minutes.

  Referring to FIG. 11, a gate insulating film forming step (step S140: FIG. 8) is performed. Specifically, oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125. This formation may be performed by dry oxidation (thermal oxidation). The dry oxidation conditions are, for example, a heating temperature of 1200 ° C. and a heating time of 30 minutes.

  Thereafter, a nitrogen annealing step (step S150: FIG. 8) is performed. Specifically, an annealing process is performed in a nitrogen monoxide (NO) atmosphere. For example, the heating temperature is 1100 ° C. and the heating time is 120 minutes. As a result, nitrogen atoms are introduced near the interface between oxide film 126 and each of breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125.

  Note that an annealing process using an argon (Ar) gas that is an inert gas may be performed after the annealing process using nitrogen monoxide. The conditions for this treatment are, for example, a heating temperature of 1100 ° C. and a heating time of 60 minutes.

  Referring to FIG. 12, source electrode 111 and drain electrode 112 are formed as follows by the electrode formation step (step S160: FIG. 8).

  First, a resist film having a pattern is formed on the oxide film 126 by photolithography. Using this resist film as a mask, portions of oxide film 126 located on n + region 124 and p + region 125 are removed by etching. As a result, an opening is formed in the oxide film 126. Next, a conductor film is formed in contact with each of n + region 124 and p + region 125 in this opening. Next, by removing the resist film, the portion of the conductor film located on the resist film is removed (lifted off). The conductor film may be a metal film, and is made of nickel (Ni), for example. As a result of this lift-off, the source electrode 111 is formed.

  In addition, it is preferable that the heat processing for alloying is performed here. For example, heat treatment is performed for 2 minutes at a heating temperature of 950 ° C. in an atmosphere of argon (Ar) gas that is an inert gas.

  Referring to FIG. 7 again, upper source electrode 127 is formed on source electrode 111. A drain electrode 112 is formed on the back surface of the semiconductor substrate 10. Thus, the semiconductor device 100 is obtained.

  As described above, the silicon carbide substrate of the present invention such as the substrate of the first embodiment is used for the semiconductor device 100 of the present embodiment. As a result, the yield of the semiconductor device 100 can be improved.

  Note that a structure in which the conductivity types in this embodiment are switched, that is, a structure in which the p-type and the n-type are replaced can also be used. In the present embodiment, the DiMOSFET has been described as an example of the semiconductor device 100. However, for example, the semiconductor device 100 may be a trench MOSFET. The above manufacturing method can be used for manufacturing various semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and diodes other than MOSFETs.

Next, examples will be described.
In this embodiment, the average dislocation density is similar, and a vertical DiMOSFET device is fabricated using a semiconductor substrate 10 having a different local dislocation density, and the drain leakage current density is measured. I investigated the yield of.

(Invention Examples 1 to 5)
The semiconductor substrate 10 used in the MOSFET devices of Examples 1 to 5 of the present invention was manufactured according to the manufacturing method described in the first embodiment. Specifically, silicon carbide having a polytype of 4H was used as the seed crystal 13. Next, a silicon carbide crystal was grown on the surface of the seed crystal 13 by a sublimation method (high-frequency heating method) under the conditions of a growth temperature of 2300 ° C. and a growth pressure of about 4 kPa (30 Torr). The crucible 11 of the apparatus used for sublimation of silicon carbide crystals was made of graphite. The outer diameter of the crucible 11 was φ140 cm, the inner diameter of the crucible 11 was φ120 cm, and the height of the crucible 11 was 100 cm. The size of the seed crystal 13 was 6 inches. The off angle with respect to the (0001) plane of the seed crystal 13 was set to 4 degrees. Further, the surface of the seed crystal 13 was subjected to CMP treatment, so that the root mean square roughness (RMS) of the surface of the seed crystal 13 was less than 1 nm. Silicon carbide powder was used as the raw material 12. The growth rate of the silicon carbide crystal 14 was less than 0.01 mm per hour. By measuring the dislocation density of the semiconductor substrate 10 manufactured by the above-described method by the method described in the first embodiment, substrates used in Invention Examples 1 to 5 were obtained. The semiconductor substrate 10 used in the devices of Examples 1 to 5 of the present invention has a Burgers vector component parallel to the <0001> direction and a component parallel to the <11-20> direction in any square region 4 having a side of 1 mm. Is a substrate having a dislocation density of 1 × 10 5 cm −2 or less.

  Using the semiconductor substrate 10 described above, vertical DiMOSFET devices of Examples 1 to 5 of the present invention were manufactured by the method described in the second embodiment.

(Comparative example)
The semiconductor substrate 10 used for the comparative example was produced in the same manner as the inventive examples 1 to 5 except for the following points. The semiconductor substrate 10 used in the comparative example was manufactured under the condition that the off-angle of the seed substrate was 12 degrees. On the other hand, the semiconductor substrates 10 of Invention Examples 1 to 5 were produced under the condition that the off-angle of the seed substrate was 4 degrees.

  A vertical DiMOSFET device of a comparative example was manufactured by using the semiconductor substrate 10 and the method described in the second embodiment.

(Yield measurement method)
The yields of the vertical DiMOSFET devices of Invention Examples 1 to 5 and Comparative Example were measured as follows. The drain leakage current density (I D ) of the vertical DiMOSFET device was measured under the conditions of the drain voltage (V D ) = 1100V and the gate voltage (V G = 0V). A device having a drain leakage current density of 1 μA / mm 2 or more was determined as a defective product, and a device having a drain leakage current density of less than 1 μA / mm 2 was determined as a non-defective product. Yield represents the proportion of non-defective devices among all measured devices.

  (result)

Table 1 shows that, in any square region 4 having a side of 1 mm, the density of dislocations including a component whose Burgers vector is parallel to the <0001> direction and a component parallel to the <11-20> direction is 1 × 10 5 cm. The relationship between the yield of the vertical DiMOSFET device manufactured using the semiconductor substrate 10 which is a substrate of −2 or less and the average dislocation density and local dislocation density of the semiconductor substrate 10 is shown. Here, the local dislocation density is a dislocation density in a region having the highest dislocation density in the square region 4 of the central region 3 of the semiconductor substrate 10.

As shown in Table 1, the yield of the device (comparative example) having a local dislocation density exceeding about 1 × 10 6 cm −2 was as low as 51%. On the other hand, the yield of the device having the local dislocation density of less than 1 × 10 5 cm −2 (Invention Example 1) was 75%, which was higher than the yield of the comparative example. In addition, the local dislocation density and the device yield had a relatively strong correlation, and the device yield improved as the local dislocation density decreased. Further, for example, when the comparative example and the inventive example 3 are compared, the average dislocation density is both about 3 × 10 4 cm −2 , but the yield is greatly different. That is, in order to improve the device yield, this experiment shows that it is effective to reduce the local dislocation density, not just the average dislocation density of the semiconductor substrate 10.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Main surface, 2 outer periphery, 3 center area | region, 4 square area | region, 6 basal plane dislocation, 6 threading dislocation, 7 dislocation, 8 dislocation line, 10 semiconductor substrate, 11 crucible, 12 raw material, 13 seed crystal, 14 silicon carbide crystal, 100 Semiconductor device.

Claims (6)

  1. A semiconductor substrate having a main surface and made of single crystal silicon carbide,
    The main surface includes a central region that is a region excluding a region within 5 mm from the outer periphery,
    When the central region is divided into square regions each having a side of 1 mm 2 , the Burgers vector has a component parallel to the <0001> direction and a component parallel to the <11-20> direction in any of the square regions. A semiconductor substrate having a dislocation density of 1 × 10 5 cm −2 or less.
  2.   The density of dislocations in which the Burgers vector is parallel to the <0001> direction in the central region is lower than the density of dislocations in which the Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction. 2. The semiconductor substrate according to 1.
  3.   In the central region, the density of dislocations in which the Burgers vector is parallel to the <11-20> direction is lower than the density of dislocations in which the Burgers vector includes a component in the <0001> direction and a component in the <11-20> direction. The semiconductor substrate according to claim 1 or 2.
  4.   4. The semiconductor device according to claim 1, wherein the semiconductor substrate branches into a plurality of dislocation lines, and the Burgers vector includes a dislocation having a component in a <0001> direction and a component in a <11-20> direction. The semiconductor substrate according to item.
  5.   The semiconductor substrate of any one of Claims 1-4 whose aperture is 4 inches or more.
  6.   The semiconductor substrate according to claim 1, wherein a polytype of single crystal silicon carbide constituting the semiconductor substrate is 4H.
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