JP4224253B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device formed on a silicon carbide substrate and a method for manufacturing the same.
[0002]
[Prior art]
Silicon carbide (silicon carbide, SiC) is a semiconductor having high insulation resistance because it has a larger band gap than silicon (Si), and is stable even at high temperatures. From such characteristics, SiC is expected to be applied to next-generation power devices, high-frequency devices, high-temperature operation devices, and the like.
[0003]
It is known that SiC can take many crystal structures such as cubic 3C—SiC, hexagonal 6H—SiC, 4H—SiC, or rhombohedral 15R—SiC. Among these, 6H—SiC and 4H—SiC are generally used for producing practical SiC semiconductor devices.
[0004]
In the 6H—SiC and 4H—SiC layers, substrates having a main surface substantially coincident with the (0001) plane perpendicular to the c-axis crystal axis are widely used.
[0005]
An SiC semiconductor device is formed by forming an epitaxial growth layer on a SiC substrate and then processing the layer according to the type of device such as impurity doping or etching. For example, in the case of a diode, a p-type doped layer, an i layer (intrinsic (intrinsic semiconductor) layer), an n-type doped layer, and the like are formed on a substrate. In the case of an FET, a source / drain region, A channel layer or the like is provided on the substrate.
[0006]
High-capacity, high-withstand-voltage power devices have a vertical element structure in which current flows in the vertical direction of the element, that is, from the upper surface to the back surface, or a voltage is applied between the upper surface and the back surface. There are many. Such a vertical semiconductor device has a configuration in which electrodes are provided on the upper surface and the back surface, respectively.
[0007]
FIG. 10 is a cross-sectional view showing a conventional Schottky diode using a SiC substrate. As shown in the figure, when the vertical semiconductor device is a Schottky diode, an epitaxial growth layer 103 having a thickness of 20 μm made of SiC containing n-type impurities is formed on the main surface (upper surface) of the n-type SiC substrate 101. A Schottky electrode 106 made of Au (gold) and a guard ring 105 for preventing electric field concentration are provided on the epitaxial growth layer 103. An ohmic electrode made of Ni (nickel) is provided on the back surface of SiC substrate 101.
[0008]
In the case of a vertical MOSFET, a source electrode and a gate electrode are provided on the upper surface of the substrate, and a drain electrode which is an ohmic electrode is provided on the rear surface.
[0009]
Next, an epitaxial growth technique when manufacturing a vertical semiconductor device using SiC will be described.
[0010]
FIG. 7 is a diagram schematically showing a configuration of a general vertical thin film growth apparatus for forming a silicon carbide film. As shown in the figure, a typical silicon carbide thin film growth apparatus includes a reaction furnace 50, a carbon susceptor 52 for fixing a substrate 51, a support shaft 53, and a coil 54 for heating a sample. A gas supply system 58 for supplying the source gas 55, the dilution gas 56 and the dopant gas 57 to the reaction furnace 50, a gas exhaust system 59 for exhausting the gas from the reaction furnace 50, and pressure adjustment And a valve 60.
[0011]
In this apparatus, the source gas 55, the dilution gas 56, and the dopant gas 57 are supplied from the gas supply system 58 to the reaction furnace 50 as indicated by arrows. The raw material gas 55, the dilution gas 56 and the dopant gas 57 enter the reaction furnace 50, pass through the exhaust pipe 61, and are exhausted by the gas exhaust system 59. The pressure in the reaction furnace 50 is adjusted by a pressure adjusting valve 60. The susceptor 52 supported by the support shaft 53 is heated by high-frequency induction heating using a coil 54 wound around the reaction furnace 50.
[0012]
The procedure for forming an epitaxial growth layer on a SiC substrate using this vertical thin film growth apparatus is as follows.
[0013]
First, a dilution gas (for example, hydrogen gas) is introduced into the reaction furnace 50, and the pressure in the furnace is adjusted to atmospheric pressure or lower than atmospheric pressure. In this state, high frequency power is applied to the coil 54 to heat the substrate 51, and the substrate temperature is set to 1500 ° C. or higher.
[0014]
Next, a gas containing carbon (for example, propane) and a gas containing silicon (for example, silane) are introduced, and at the same time, a dopant gas 57 is supplied from the gas supply system 58, whereby an n-type or a p-type is formed on the substrate 51. A doped epitaxial growth layer can be formed. In the case of n-type doping, for example, nitrogen, and in the case of p-type doping, for example, a gas containing aluminum is used as the dopant gas 57.
[0015]
Next, the supply of the source gas 55 and the dopant gas 57 is stopped, the application of the high frequency power to the coil 54 is stopped, the heating is finished, and the substrate 51 is cooled.
[0016]
By this method, an epitaxial growth layer can be formed on the substrate 51. The thickness and carrier density of this epitaxial growth layer are determined so that the SiC semiconductor device can obtain a desired breakdown voltage and on-current.
[0017]
FIG. 9 is a diagram showing the flow rate of the source gas and the impurity dopant gas and the time change of the substrate temperature in the conventional SiC layer growth method.
[0018]
As shown in the figure, in the conventional SiC layer growth method, the supply of the source gas and the impurity dopant gas is started after the substrate temperature reaches the epitaxial growth temperature (for example, 1500 ° C.). During the epitaxial growth, the flow rates of the source gas and the dopant gas are kept constant. Thereafter, the supply of the source gas and the dopant gas is stopped, and at the same time, the heating of the substrate is stopped, and the growth of the SiC layer is stopped.
[0019]
By using the above method, the SiC layer of the conventional vertical semiconductor device is formed.
[0020]
[Problems to be solved by the invention]
As described above, since a vertical semiconductor device using SiC has low power consumption and high pressure resistance, it is preferably used for various devices as a power device. However, depending on the operating conditions of the device, a high voltage exceeding the rated value may be applied to the semiconductor device, and the conventional Schottky diode as shown in FIG. 10 may temporarily cause dielectric breakdown. .
[0021]
This breakdown occurs when a high reverse bias voltage is applied and the depletion layer that has spread over the epitaxial growth layer of the semiconductor device reaches the SiC substrate. In general, the crystallinity of an SiC substrate is inferior to that of an epitaxial growth layer, and the impurity dopant concentration is high. For this reason, it is considered that the breakdown phenomenon occurs due to the accelerated carriers in the depletion layer formed in the substrate, which causes the breakdown of the semiconductor device.
[0022]
In order to avoid such inconveniences, a measure has been conventionally taken to make the epitaxial growth layer sufficiently thick so that the depletion layer does not reach the substrate even when a voltage exceeding the rated value is applied.
[0023]
However, increasing the thickness of the epitaxially grown layer of the semiconductor device by two times corresponds to increasing the resistance component in this layer by a factor of two, thus causing a new problem of increased power loss in the semiconductor device.
[0024]
As described above, in the prior art, even if an element is manufactured using SiC, it is difficult to obtain characteristics such as high pressure resistance and ultra-low loss as expected from its excellent physical property values.
[0025]
An object of the present invention is to provide a semiconductor device having a high pressure resistance that can withstand use in equipment and a method for manufacturing the same.
[0026]
  The semiconductor device of the present invention includes a first conductivity type impurity.Semiconductor substrateAnd aboveSemiconductor substrateAbove and aboveSemiconductor substrateContains impurities of the first conductivity type at a higher concentration thanFormed by epitaxial growthA first high-concentration impurity doped layer made of a semiconductor and the first high-concentration impurity-doped layer are provided on the first high-concentration impurity-doped layer and contain a first conductivity type impurity at a concentration lower than that of the first high-concentration impurity-doped layer.First semiconductor layerAnd in operation, the carrier is aboveSemiconductor substrateThe first high-concentration impurity doped layer and the aboveFirst semiconductor layerDrive through the road.
[0027]
  As a result, when a reverse bias is applied, the depletion layer extending from above the first high-concentration impurity doped layer is stopped in the first high-concentration impurity doped layer.Semiconductor substrateTherefore, the pressure resistance of the semiconductor device can be improved. in addition,Semiconductor substrateWhenFirst semiconductor layerSince a high-resistance region with a low dopant concentration is not interposed between the two, the electric resistance can be reduced as compared with a conventional semiconductor device.
[0028]
  the aboveSemiconductor substrateIs made of one material selected from Si, SiC, GaN, GaAs, and InP, a high breakdown voltage and low loss semiconductor device can be realized.
[0029]
  the aboveSemiconductor substrateThe first high-concentration impurity doped layer and the aboveFirst semiconductor layerSince both are made of SiC, it is possible to realize a semiconductor device with high breakdown voltage, low loss, and good heat dissipation. For this reason, it can be preferably used in various devices that require pressure resistance as a semiconductor device that consumes less power and does not easily accumulate heat.
[0030]
Since the first high-concentration impurity doped layer is formed by epitaxial growth, the density of crystal defects in the first high-concentration impurity doped layer can be lowered, so that the breakdown voltage of the semiconductor device can be improved. it can.
[0031]
The concentration of impurities contained in the first high-concentration impurity doped layer is 1 × 10¹⁸atoms · cm^-31 × 10 or more²⁰atoms · cm^-3The following is preferable. The concentration of impurities contained in the first high-concentration impurity doped layer is 1 × 10¹⁸atoms · cm^-3As described above, when the reverse bias is applied, a predetermined withstand voltage can be ensured without making the second semiconductor layer thicker than necessary. The concentration of impurities contained in the first high-concentration impurity doped layer is 1 × 10²⁰atoms · cm^-3Since the crystallinity of the first high-concentration impurity doped layer is kept good by the following, the pressure resistance of the semiconductor device can be kept good.
[0032]
The thickness of the first high-concentration impurity doped layer is not less than 10 nm and not more than 1000 nm, thereby preventing the depletion layer from reaching the first semiconductor layer when a reverse bias is applied, and of the semiconductor device during operation. Power loss can be reduced.
[0033]
  UpSince the impurities contained in the first high-concentration impurity doped layer are introduced by in-situ doping, the crystallinity of the first high-concentration impurity doped layer can be kept good.
[0034]
  the aboveFirst semiconductor layerIs formed by epitaxial growth,First semiconductor layerSince the crystallinity of the semiconductor device can be improved, the breakdown voltage of the semiconductor device can be increased.The
[0035]
  the aboveFirst semiconductor layerAbove and aboveFirst semiconductor layerAnd Schottky electrode in contact with SchottkySemiconductor substrateProvided on the back of the aboveSemiconductor substrateAnd an ohmic electrode that is in ohmic contact with each other, a Schottky diode having a high breakdown voltage and a low loss can be realized.
[0036]
  Also, aboveFirst semiconductor layerAnd further comprising a guard ring made of an insulator surrounding the Schottky electrode.First semiconductor layerIt is possible to prevent the occurrence of dielectric breakdown due to electric field concentration at the upper end of the.
[0037]
  the aboveFirst semiconductor layerAnd includes an impurity of the second conductivity type.Second semiconductor layerAnd aboveSecond semiconductor layerAn upper electrode provided above, andSemiconductor substrateAnd a lower electrode provided on the back surface of the semiconductor device, and a semiconductor device functioning as a pn diode can be realized.
[0038]
  In this case, the aboveFirst semiconductor layerAnd aboveSecond semiconductor layerBetween the above andSecond semiconductor layerAnd further comprising a second high-concentration impurity doped layer containing a second conductivity type impurity at a higher concentration thanFirst semiconductor layerWhenSecond semiconductor layerTherefore, the power loss during operation can be further reduced.
[0039]
  the aboveSecond semiconductor layerIs composed of epitaxially grown SiC,Second semiconductor layerSince the crystallinity of is favorable, it is preferable.
[0040]
  the aboveFirst semiconductor layerA first well which is provided by implanting impurity ions of the second conductivity type in a part of the first region and functions as a channel;First semiconductor layerAnd a gate insulating film provided on the first well, a gate electrode provided on the gate insulating film, and a region located on both sides of the gate electrode in the first well. The second well provided by implanting first conductivity type impurity ions; the first electrode provided on the second well;Semiconductor substrateIt is also possible to realize a semiconductor device that further includes a second electrode provided on the back surface of the semiconductor device and functions as a MISFET having a vertical structure.
[0041]
  In the method for manufacturing a semiconductor device of the present invention, a first source gas, a second source gas, and an impurity dopant gas are supplied to a reaction furnace of a thin film growth apparatus, and the semiconductor substrate has a higher concentration than the semiconductor substrate. Impurities of the first conductivity typeAt the position where the constituent elements contained in the first source gas should beIncludeFirst heavily doped layerEpitaxially growing the step (a) and the step (a) after the stepFirst heavily doped layerAbove aboveFirst heavily doped layerAnd a step (b) of epitaxially growing a first semiconductor layer containing a first conductivity type impurity at a lower concentration than the first step, when the step (a) is started, the first step is compared to the start of the step (b). The feed rate of the first source gas and the second feed gas is changed by reducing the feed rate of the source gas of,the aboveIncrease the supply amount of impurity dopant gas.
[0042]
  This wayFirst heavily doped layerIn the first source gasFirst heavily doped layerSince the first conductivity type impurities are likely to be taken into the positions where the constituent elements ofFirst heavily doped layerThe impurity concentration of can be increased.
[0043]
At the start of the step (a), the impurity concentration of the first semiconductor layer can be increased more efficiently by increasing the supply amount of the impurity dopant gas than at the start of the step (b). become.
[0044]
Since the substrate temperature is lowered at the start of the step (a) compared to the start of the step (b), the formation rate of the first semiconductor layer can be made lower than the formation rate of the second semiconductor layer. The impurity concentration contained in the first semiconductor layer can be made higher than the impurity concentration contained in the second semiconductor layer.
[0045]
The step (a) further includes the step (a1) of continuously reducing the supply amount of the impurity dopant gas, thereby moderating the change in the impurity concentration in the depth direction in the first semiconductor layer. Therefore, the electrical resistance of the first semiconductor layer can be reduced.
[0046]
Since the semiconductor substrate is made of SiC, a semiconductor device having a high breakdown voltage and a low loss can be formed.
[0047]
  the aboveFirst high concentration impurityDoped layers andFirst semiconductor layerSince both are made of SiC, a high breakdown voltage and low loss semiconductor device can be formed.
[0048]
Since the impurity dopant gas is nitrogen or phosphine, and the first source gas is a carbon source gas, nitrogen easily enters the position of carbon in the SiC crystal. The first semiconductor layer containing can be efficiently formed.
[0049]
The first source gas is preferably one selected from propane, methane, acetylene, ethane, ethylene, propylene, and butane.
[0050]
Since the impurity dopant gas is trimethylaluminum gas or diborane gas, and the first source gas is a source gas of silicon, Al is likely to enter the position of silicon in the SiC crystal, so that the first semiconductor layer Even if it is a p-type semiconductor, it becomes possible to manufacture efficiently.
[0051]
The first source gas is preferably silane gas or disilane gas
[0052]
DETAILED DESCRIPTION OF THE INVENTION
-Examination of element configuration-
The inventors of the present application have studied a method for improving the withstand voltage without increasing the thickness of the epitaxial growth layer more than necessary in order to improve the withstand voltage of the SiC semiconductor device without increasing the electric resistance.
[0053]
In the course of the study, a plurality of Schottky diodes having different epitaxial growth layers were produced, and the withstand voltage and resistance values were measured.
[0054]
As a result, as expected, the Schottky diode having the epitaxially grown layer thinned to about 10 μm had a lower breakdown voltage and a lower resistance value than the Schottky diode shown in FIG. However, the inventors of the present application have noticed that the resistance value of the Schottky diode is larger than a value predicted by simulation or the like. And when this cause was investigated, it turned out that it is because the area | region where dopant concentration is not contained between SiC substrate 101 and epitaxial growth layer 103, or the area | region where dopant concentration is low exists. Such a low resistance region was considered to be caused by the unstable supply of the dopant gas immediately after the supply of the dopant gas was started. This becomes more remarkable when an epitaxial growth layer having a low dopant concentration is formed.
[0055]
For this reason, in order to fabricate a SiC semiconductor device having good electrical characteristics, a method was sought that not only improved withstand voltage but also reduced electrical resistance.
[0056]
As a result of various studies, the inventors of the present application provide a SiC layer having a higher concentration of impurities and the same conductivity type as that of the substrate on the substrate including impurities, whereby the depletion layer is formed on the substrate during the operation of the semiconductor device. I found that I can prevent it from reaching.
[0057]
It was also confirmed that by providing a SiC layer doped with an impurity at a high concentration, a region having a low impurity concentration existing between the conventional epitaxial growth layer and the substrate can be eliminated. That is, it was found that by providing a doped layer containing impurities at a high concentration (hereinafter referred to as “high concentration impurity doped layer”) on the substrate, the withstand voltage can be improved and the electrical resistance can be reduced. .
[0058]
-Examination of SiC layer growth conditions-
Next, the inventors of the present application examined conditions for growing a high-concentration impurity doped layer more efficiently using the vertical thin film growth apparatus shown in FIG. As a result, the high concentration impurity doped layer was grown by the following procedure.
[0059]
FIG. 2 is a diagram showing the flow rate of the source gas and the impurity dopant gas and the time change of the substrate temperature in the SiC layer growth method of the present invention.
[0060]
Here, in comparison with the conventional epitaxial growth layer forming method shown in FIG. 9, in the SiC layer forming method of the present invention, the supply amount of nitrogen, which is an impurity dopant gas, and the supply amount of propane gas change during the process. I understand that That is, when forming a high concentration impurity doped layer, the flow rate of nitrogen gas is increased to about 1.0 mL / min, and the flow rate of propane gas, which is a carbon source gas, is decreased to about 0.6 mL / min. In the epitaxial growth layer forming step, the flow rate of nitrogen gas is 0.2 mL / min, and the flow rate of propane gas is 3.0 mL / min. In addition, the flow rate of the silane gas, which is the Si source gas, is adjusted to 3.0 mL / min throughout the SiC layer forming process, and the C (carbon) / Si ratio of the source gas is the same as that during the formation of the high concentration impurity doped layer. , 0.6, and 3 in the epitaxial growth layer forming step.
[0061]
Further, the substrate temperature is set to 1500 ° C. in the process of forming the highly doped layer, and is set to 1600 ° C. in the process of forming the epitaxial growth layer.
[0062]
In the step of forming the high-concentration impurity doped layer, introduction of impurities into SiC is attempted by the following three devices.
[0063]
The first contrivance is to increase the supply amount of nitrogen gas in the step of forming the high concentration impurity doped layer. If the nitrogen gas concentration increases on the SiC surface during epitaxial growth, the amount of nitrogen taken into the SiC crystal also increases.
[0064]
The second contrivance is to reduce the supply amount of the carbon source gas in the step of forming the high concentration impurity doped layer. Thereby, nitrogen can easily enter the position where carbon in the SiC crystal should enter, and the concentration of impurities taken into the SiC layer can be increased.
[0065]
It should be noted that the position of carbon or silicon that is likely to enter depending on impurities is somewhat different. Since nitrogen easily enters the carbon position, it is preferable to reduce the supply amount of propane gas when the impurity is nitrogen, and since Al easily enters the silicon position, the supply amount of silane gas is reduced when the impurity is Al. It is preferable to make it smaller.
[0066]
Next, the third idea is that the substrate temperature is set as low as possible in the step of forming the high concentration impurity doped layer. Thereby, since the SiC layer can be grown at a low speed, the amount of impurities taken up can be increased.
[0067]
For the above reasons, when the method for forming a SiC layer of the present invention is used, the impurity concentration is 1 × 10 5.¹⁸atoms · cm^-3It is possible to efficiently form a SiC layer exceeding the thickness.
[0068]
Examples of the SiC semiconductor device and the SiC semiconductor substrate using this method will be described below.
[0069]
(First embodiment)
First, as a first embodiment of the present invention, a method for manufacturing a SiC substrate having a high concentration impurity doped layer having a higher impurity concentration than the substrate between the substrate and the epitaxial growth layer will be described below.
[0070]
1A to 1C are cross-sectional views illustrating a method for manufacturing an SiC substrate according to the first embodiment of the present invention.
[0071]
First, a substrate 1 made of SiC is prepared in the step shown in FIG. As the substrate 1, an n-type (0001) plane SiC substrate (4H-SiC substrate) having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] direction is used. The dopant concentration of the substrate 1 is about 1 × 10¹⁸atoms · cm^-3It is.
[0072]
The substrate 1 is placed in a water vapor atmosphere bubbled with oxygen having a flow rate of 5 L / min, and is subjected to thermal oxidation at 1100 ° C. for about 3 hours. Thereby, a thermal oxide film having a thickness of about 40 nm (400 mm) is formed on the surface of the substrate 1, and then the thermal oxide film is removed by buffered hydrofluoric acid (hydrofluoric acid: ammonium fluoride aqueous solution = 1: 7). To do.
[0073]
Next, in the step shown in FIG. 1B, a high concentration impurity doped layer 2 is formed on the substrate 1 by the CVD method. The specific method is described below.
[0074]
First, the substrate 1 is placed on the susceptor 52 of the vertical thin film growth apparatus shown in FIG.^-FiveThe pressure is reduced until the degree of vacuum is about Pa. Next, hydrogen gas as the dilution gas 56 is supplied from the gas supply system 58 at a flow rate of 2 L / min, and the pressure in the reaction furnace 50 is set to 90 kPa. The pressure in the reaction furnace 50 is controlled by adjusting the valve 60. In a state where the flow rate of hydrogen gas is maintained, a high frequency power of 20.0 kHz and 20 kW is applied to the coil 54 using an induction heating device to heat the susceptor 52. During this step, the temperature of the substrate 1 is controlled to be constant at 1500 ° C.
[0075]
Next, the propane gas and the silane gas of the source gas 55 and the nitrogen gas as the n-type dopant are supplied from the gas supply port of the reaction furnace 50 while keeping the hydrogen gas flow rate constant at 2 L / min. The source gas 55 and the dopant gas 57 are supplied after being diluted with hydrogen gas.
[0076]
The flow rates of silane gas, propane gas, and nitrogen gas immediately after the start of the formation of the high-concentration impurity doped layer 2 are 3.0 mL / min, 0.6 mL / min, and 1.0 mL / min, respectively.
[0077]
Silane gas (monosilane) has 1 Si per molecule, and propane gas has 3 carbons per molecule, so the carbon / silicon ratio of the source gas in this case is 0.6. . In this state, the source gas and nitrogen gas are kept flowing for at least 10 minutes. The carbon / silicon ratio means the ratio of the number of C and Si atoms supplied to the reaction furnace 50 per unit time, that is, the value of (number of carbon atoms) / (number of silicon atoms).
[0078]
Thereafter, as shown in FIG. 2, the flow rate of propane gas is continuously increased and the flow rate of nitrogen gas (impurity dopant gas) is continuously decreased. After 5 minutes, 3.0 mL / min and 0. 2 mL / min. During this time, the flow rate of silane gas is kept constant at 3.0 mL / min.
[0079]
By this step, the thickness is about 100 nm and the dopant concentration is about 1 × 10.¹⁹atoms · cm^-3N-type high concentration impurity doped layer 2 is formed on substrate 1.
[0080]
Next, in the step shown in FIG. 1C, an epitaxial growth layer is subsequently formed on the high-concentration impurity doped layer 2 by the CVD method. A specific method is described below.
[0081]
First, the substrate temperature is raised so as to be constant at 1600 ° C. In this step, the flow rates of silane gas, propane gas, and nitrogen gas are 3.0 mL / min, 3.0 mL / min, and 0.2 mL / min, respectively.
[0082]
The carbon / silicon ratio at this time is 3, which is a higher value than the carbon / silicon ratio when the high concentration impurity doped layer 2 is formed. By this step, the thickness is about 10 μm and the carrier density is about 1 × 10.¹⁶atoms · cm^-3N-type epitaxial growth layer 3 is formed on heavily doped impurity layer 2.
[0083]
The dopant concentration distribution in the depth direction of the SiC thin film formed by this method was measured using a secondary ion mass spectrometer (SIMS). As a result, it was found that in the high concentration impurity doped layer 2, the nitrogen concentration once increased and then gradually decreased upward, and the thickness of the high concentration impurity doped layer 2 was about 100 nm.
[0084]
The SiC substrate of the present embodiment manufactured by the above method was provided on the substrate 1, the high-concentration impurity doped layer 2 having a thickness of 100 nm provided on the substrate 1, and the high-concentration impurity doped layer 2. And an epitaxial growth layer 3 made of n-type SiC having a thickness of 10 μm.
[0085]
Here, the high concentration impurity doped layer 2 in the SiC substrate of the present embodiment has a thickness of 100 nm and an impurity concentration of 1 × 10 6.¹⁹atoms · cm^-3The thickness is preferably at least 10 nm to 1000 nm, and the impurity concentration is 1 × 10 10.¹⁸atoms · cm^-31 × 10 or more²⁰atoms · cm^-3The following is preferable. This is due to the following reason.
[0086]
FIG. 8 is a diagram showing a table summarizing the impurity concentration and resistivity in the 4H—SiC n-type doped layer.
[0087]
Here, the resistance value R (Ω) of a semiconductor having a resistivity ρ (Ω · cm) represents the cross-sectional area through which a current flows, S (cm² ), Where the thickness is L (cm),
[0088]
R = ρ × (L / S) (1)
8 and equation (1), the resistance values of the high-concentration impurity doped layer 2 and the epitaxial growth layer 3 will be compared. The thickness of the high-concentration impurity doped layer 2 is 100 nm and the impurity concentration is 1 × 10¹⁹atoms · cm^-3The thickness of the epitaxial growth layer 3 is 10 μm and the impurity concentration is 1 × 10¹⁶atoms · cm^-3In this case, the resistivity is 0.015 (Ω · cm) and 1 (Ω · cm), respectively, and the thickness ratio is 1: 100. Therefore, the resistance value of the epitaxial growth layer 3 is the same as that of the high-concentration impurity doped layer 2. It becomes almost 4 digits larger than the resistance value. In this case, it can be said that the resistance value of the high-concentration impurity doped layer 2 is negligibly small compared to the resistance value of the epitaxial growth layer 3.
[0089]
Next, the thickness of the high concentration impurity doped layer 2 is 1000 nm, and the impurity concentration is 1 × 10 5.¹⁸atoms · cm^-3The resistivity of the high concentration impurity doped layer 2 is 0.065.
(Ω · cm) Since the ratio of the thickness of the high-concentration impurity doped layer 2 and the epitaxial growth layer 3 is 1:10, the resistance value of the high-concentration impurity doped layer 2 is less than 1% of the resistance value of the epitaxial growth layer 3 (0.65%). If the resistance value of the high-concentration impurity doped layer 2 becomes larger than this, the resistance value cannot be ignored. Therefore, the thickness of the high-concentration impurity doped layer 2 is preferably 1000 nm or less, and the impurity concentration is 1 × 10.¹⁸atoms · cm^-3The above is preferable.
[0090]
Further, when the impurity concentration is high, the resistance value is small, but the impurity concentration is 1 × 10.²⁰atoms · cm^-3If it exceeds 1, the crystallinity of SiC deteriorates and the pressure resistance may be lowered. Therefore, the impurity concentration of the high-concentration impurity doped layer 2 is 1 × 10 6.¹⁸atoms · cm^-31 × 10 or more²⁰atoms · cm^-3The following.
[0091]
The reason why the thickness range of the high-concentration impurity doped layer 2 is 10 nm or more is that if the thickness is less than 10 nm, sufficient pressure resistance may not be obtained.
[0092]
Note that FIG. 8 shows the case of a 4H—SiC layer containing an n-type impurity, and the resistivity differs in the case of a 6H—SiC layer or when the impurity is p-type. However, even in these cases, the inversely proportional relationship between the impurity concentration and the resistivity as shown in FIG. 8 is established. Therefore, the high concentration impurity doped layer 2 has a thickness of 10 nm to 1000 nm and an impurity concentration range of 1 ×. 10¹⁸atoms · cm^-31 × 10 or more²⁰atoms · cm^-3The following may be used.
[0093]
As described above, in the SiC substrate of this embodiment, the breakdown voltage is improved without increasing the resistance value. The pressure resistance of the device using the SiC substrate of this embodiment will be described in the following embodiments.
[0094]
In the SiC layer forming method of the present embodiment, the high-concentration impurity doped layer 2 and the epitaxial growth layer 3 are formed using nitrogen as an impurity dopant gas. Containing phosphine (PH_Three), Dopant gas containing other impurities may be used.
[0095]
In this embodiment, since an n-type SiC substrate is used, nitrogen is used as an impurity dopant gas to form a high concentration impurity doped layer. However, when a p-type SiC substrate is used, p-type impurities are added. Impurity dopant gas containing, for example, TMA (trimethylaluminum) gas or diborane gas is used. At this time, it is more preferable that the flow rate of the silane gas is smaller than the flow rate of the propane gas in the step of forming the high concentration impurity doped layer 2.
[0096]
In the method of the present embodiment, the substrate temperature in the step of forming the high-concentration impurity doped layer 2 shown in FIG. 1B is 1500 ° C., but is 1500 ° C. or higher and lower than the substrate temperature at the time of epitaxial growth layer formation. I just need it.
[0097]
In the method of this embodiment, nitrogen is introduced into the high-concentration impurity doped layer 2 by in-situ doping, but nitrogen ions can also be introduced by ion implantation. However, since the crystal structure is easily damaged when ion implantation is performed, it is preferable to adopt the method of this embodiment.
[0098]
In the step of forming the high concentration impurity doped layer 2 shown in FIG. 2B, the supply amount of propane gas is reduced while the supply amount of silane gas is kept constant. However, by changing the supply amount of silane gas, carbon / The silicon ratio can also be changed.
[0099]
In the semiconductor device manufacturing method of the present embodiment, propane gas is used as the carbon source gas, but methane (CH_Four), Acetylene (C₂H₂), Ethane (C₂H₆), Ethylene (C₂H_Four), Propylene (C_ThreeH₆) And butane (C_FourH_Ten) Can also be used.
[0100]
In addition to silane gas, disilane (Si₂H₆) Can also be used.
[0101]
(Second Embodiment)
As a second embodiment of the present invention, a Schottky diode manufactured using the SiC substrate according to the first embodiment will be described.
[0102]
3A to 3C are cross-sectional views illustrating the manufacturing process of the Schottky diode according to the present embodiment.
[0103]
As shown in FIG. 3C, the Schottky diode of the present embodiment is provided on the main surface of the substrate 11 made of n-type 4H—SiC and has a higher concentration than the substrate 11. On the high-concentration impurity doped layer 12 having a thickness of about 100 nm containing impurities, an epitaxial growth layer 13 having a thickness of 10 μm made of SiC containing n-type impurities, and on the epitaxial growth layer 13. Silicon oxide (SiO2) provided and partially opened₂), A Schottky electrode 16 made of Au provided on a region of the epitaxial growth layer 13 where the guard ring 15 is opened, and an ohmic contact made of Ni formed on the back surface of the substrate 11 by vapor deposition. And an electrode 14. The concentrations of the n-type impurities contained in the substrate 11, the high-concentration impurity doped layer 12, and the epitaxial growth layer 13 are 1 × 10, respectively.¹⁸atoms · cm^-31 × 10¹⁹atoms · cm^-3And 1 × 10¹⁶atoms · cm^-3It is.
[0104]
Next, a method for manufacturing the Schottky diode of this embodiment will be described.
[0105]
First, in the step shown in FIG. 3A, the high concentration impurity doped layer 12 is formed on the substrate 11 by the CVD method. Here, as the substrate 11, an n-type (0001) plane SiC substrate (4H-SiC substrate) having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] direction is used.
[0106]
Hereinafter, a specific method for forming the high concentration impurity doped layer 12 will be described. This procedure is the same as that in the first embodiment.
[0107]
First, the substrate 11 is placed on the susceptor 52 of the vertical thin film growth apparatus shown in FIG.^-FiveThe pressure is reduced until the degree of vacuum is about Pa. Next, hydrogen gas as the dilution gas 56 is supplied from the gas supply system 58 at a flow rate of 2 L / min, and the pressure in the reaction furnace 50 is set to 90 kPa. The pressure in the reaction furnace 50 can be adjusted by a valve 60. Subsequently, a high frequency power of 20.0 kHz and 20 kW is applied to the coil 54 using an induction heating device while maintaining the flow rate of hydrogen gas, and the susceptor 52 is heated. In this step, the temperature of the substrate 11 is controlled to be constant at 1500 ° C.
[0108]
Next, while the hydrogen gas flow rate is kept constant at 2 L / min, propane gas, which is a carbon source gas, silane gas, which is a silicon source gas, and nitrogen gas, which is an n-type dopant, are supplied to the reactor 50. Supply from mouth.
[0109]
The flow rates of silane gas, propane gas, and nitrogen gas immediately after the start of the formation of the high concentration impurity doped layer 12 are 3.0 mL / min, 0.6 mL / min, and 1.0 mL / min, respectively. In this case, the carbon / silicon ratio of the source gas is 0.6. Subsequently, the source gas and the nitrogen gas are kept flowing for at least 10 minutes while keeping these flow rate values constant.
[0110]
Thereafter, with the silane gas flow rate kept constant at 3.0 mL / min, the propane gas flow rate was continuously increased, and the nitrogen gas flow rate was continuously decreased. Min and 0.2 mL / min. Here, since the change in the nitrogen concentration in the high concentration impurity doped layer 12 can be moderated by continuously changing the flow rates of the source gas and the nitrogen gas without suddenly changing, the high concentration impurity doping The resistance value of the layer 12 can be lowered.
[0111]
Through the above steps, the thickness is about 100 nm and the nitrogen concentration is about 1 × 10.¹⁹atoms · cm^-3The n-type heavily doped impurity layer 12 is epitaxially grown on the substrate 11.
[0112]
Next, in the step shown in FIG. 3B, the epitaxial growth layer 13 is formed on the high concentration impurity doped layer 12. A specific method is described below.
[0113]
First, the substrate temperature is raised so as to be constant at 1600 ° C. In this step, the flow rates of silane gas, propane gas, and nitrogen gas are 3.0 mL / min, 3.0 mL / min, and 0.2 mL / min, respectively. The carbon / silicon ratio at this time is 3, which is higher than the carbon / silicon ratio at the time of forming the high concentration impurity doped layer 12. By this step, the thickness is about 10 μm, and the carrier density (nitrogen concentration) is about 1 × 10.¹⁶atoms · cm^-3The epitaxial growth layer 13 is formed on the high concentration impurity doped layer 12.
[0114]
Next, in the step shown in FIG. 3C, after the nickel (Ni) is deposited on the back surface of the substrate 11 using a vacuum deposition apparatus, the ohmic electrode 14 made of Ni is formed by heating at 1000 ° C. .
[0115]
Subsequently, after a silicon oxide film is formed on the epitaxial growth layer 13 by CVD or the like, a part thereof is opened by etching to form a guard ring 15. Next, a Schottky electrode 16 formed by depositing gold (Au) is formed on a region of the epitaxial growth layer 13 where the guard ring 15 is opened.
[0116]
The current-voltage characteristics of the Schottky diode of this embodiment formed as described above were examined. For comparison, a similar Schottky diode was fabricated on a SiC substrate in which an epitaxial growth layer was formed by a conventional method in which a high concentration impurity doped layer was not formed on the substrate, and the current-voltage characteristics were examined. Hereinafter, this Schottky diode manufactured by the conventional method is referred to as “conventional Schottky diode”. Unlike the Schottky diode shown in FIG. 9, the conventional Schottky diode fabricated here has an epitaxial growth layer thickness of about 10 μm and a carrier density of 1 × 10.¹⁶atoms · cm^-3The element configuration is the same as that of the Schottky diode of this embodiment except that the high-concentration impurity doped layer is not provided.
[0117]
The operating characteristics when a voltage was applied to these Schottky diodes were measured.
[0118]
FIG. 4 is a diagram showing current-voltage characteristics of the Schottky diode of this embodiment and the conventional Schottky diode. Here, the voltage applied to the Schottky electrode side is a positive voltage.
[0119]
As shown in the figure, in the Schottky diode of this embodiment, it has been found that the on-current for the same voltage is nearly twice as large as that of the conventional Schottky diode.
[0120]
This is because, in the Schottky diode of this embodiment, a low resistance region with a low impurity concentration does not occur between the substrate 11 and the epitaxial growth layer 13, so that the resistance value becomes small and the on-state when a forward voltage is applied is reduced. This is probably because the current has increased.
[0121]
On the other hand, the on-voltage, which is the forward voltage when the on-current starts to flow, is about 1 V for both diodes, and no difference was observed.
[0122]
Next, in order to compare the breakdown voltage characteristics of both Schottky diodes, the reverse breakdown voltage, which is a voltage that causes breakdown by applying a reverse bias voltage, was measured.
[0123]
As a result, it was found that the breakdown voltage of the Schottky diode of this embodiment is nearly 20% higher than that of the conventional Schottky diode.
[0124]
This is because, in the Schottky diode of this embodiment, a high concentration impurity doped layer having a higher dopant concentration than that of the substrate is provided, and therefore, when a reverse bias voltage is applied, a depletion layer that spreads from the Schottky electrode side. Is considered to be caused by not reaching the substrate.
[0125]
From these results, a high-concentration impurity doped layer having the same conductivity type as the substrate and containing a higher concentration of impurities than the substrate exists between the substrate and the epitaxially grown layer, so that the on-current is large and the reverse breakdown voltage is increased. A large Schottky diode can be fabricated.
[0126]
In the case of the conventional Schottky diode shown in FIG. 10 in which the epitaxial growth layer is formed thick, the on-current is further reduced. Therefore, the Schottky diode of this embodiment can significantly reduce power consumption during operation as compared with the conventional Schottky diode shown in FIG.
[0127]
Since it has the above characteristics, the Schottky diode of this embodiment is preferably used for various electronic devices. For example, when the Schottky diode of the present embodiment is used for a plasma display (PDP), since power consumption is small and heat dissipation is better than Si, generation and accumulation of heat can be suppressed, The number of parts required for heat dissipation can be reduced.
[0128]
In addition, since the Schottky diode of this embodiment has higher breakdown voltage than the conventional Schottky diode, even when the guard ring 15 is not provided, it is difficult for dielectric breakdown to occur during reverse bias application. Thereby, the manufacturing process can be further simplified, and the manufacturing cost can be reduced.
[0129]
In addition, the Schottky diode manufacturing method of the present embodiment also has an advantage that it is possible to easily manufacture a Schottky diode that realizes an increase in on-current and an improvement in breakdown voltage without using a special device. .
[0130]
Note that the thickness of the high-concentration impurity doped layer 12 in the Schottky diode of this embodiment is preferably 10 nm or more and 1000 nm or less, as in the first embodiment, and the impurity concentration range is also 1 × 10 10.¹⁸atoms · cm^-31 × 10 or more²⁰atoms · cm^-3The following is preferable.
[0131]
In the Schottky diode of this embodiment, nitrogen is used as a dopant for the substrate 11, the epitaxial growth layer 13, and the high-concentration impurity doped layer 12 existing between them, but other n-type impurities are used instead. Alternatively, a p-type impurity such as Al may be used. Even in this case, the same effect as in the present embodiment can be obtained.
[0132]
In the Schottky diode of this embodiment, a 4H—SiC substrate is used as a substrate, but a 6H—SiC substrate, a 3C—SiC substrate, a 15R—SiC substrate, or the like can also be used.
[0133]
In the Schottky diode of this embodiment, SiC is used as the material for the substrate and the epitaxial growth layer. Instead, Si, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP) are used. Such semiconductors can also be used. In the case of GaN or InP, Si or the like is used as the impurity. This is common in the following embodiments.
[0134]
(Third embodiment)
As a third embodiment of the present invention, an example of a pn diode using the SiC substrate of the first embodiment will be described.
[0135]
FIGS. 5A to 5C are cross-sectional views showing a process for manufacturing a pn diode according to the third embodiment of the present invention.
[0136]
As shown in FIG. 5C, the pn diode of the present embodiment is provided on a substrate 21 made of n-type 4H—SiC and on the main surface of the substrate 21, for example, SiC having a thickness of 100 nm containing nitrogen. Provided on the high-concentration n-type doped layer 22 and the high-concentration n-type doped layer 22, provided on the n-type SiC layer 23 having a thickness of about 10 μm containing nitrogen, and the n-type SiC layer 23, For example, a high-concentration p-type doped layer 27 having a thickness of 10 nm containing Al, a p-type SiC layer 28 having a thickness of about 2.5 μm, which is provided on the high-concentration p-type doped layer 27, and p-type SiC The upper electrode 26 formed by laminating Ni and Al provided on the layer 28 and the lower electrode 24 formed of Ni provided on the back surface of the substrate 21 are provided.
[0137]
The nitrogen concentration in substrate 21, high concentration n-type doped layer 22 and n-type SiC layer 23 is 1 × 10, respectively.¹⁸atoms · cm^-3, 1 × 10¹⁹atoms · cm^-3And 1 × 10¹⁶atoms · cm^-3The Al concentration contained in the high-concentration p-type doped layer 27 and the p-type SiC layer 28 is 1 × 10 3 respectively.¹⁹atoms · cm^-3, 1 × 10¹⁸atoms · cm^-3It is.
[0138]
The pn diode of this embodiment includes a high-concentration n-type doped layer 22 containing n-type impurities at a higher concentration than the substrate 21 on the main surface of the substrate 21, and an n-type SiC layer 23 and a p-type SiC layer 28. A high-concentration p-type doped layer 27 containing a p-type impurity at a high concentration is provided.
[0139]
For this reason, since there is no region having a large resistance not only in the n-type SiC layer 23 but also in the p-type SiC layer 28, the resistance value of the pn diode of this embodiment is smaller than that of the conventional pn diode.
[0140]
In addition, when a reverse bias is applied, the depletion layer extending from the pn junction is stopped in the high-concentration n-type doped layer 22, so that the withstand voltage is improved as compared with the conventional pn diode.
[0141]
Next, a method for manufacturing the pn diode of this embodiment will be described.
[0142]
First, in the step shown in FIG. 5A, a high-concentration n-type doped layer 22 and an n-type SiC layer 23 are sequentially formed on the main surface of the substrate 21 by the same procedure as in the first and second embodiments. . A specific procedure will be described below.
[0143]
After the substrate 21 is placed on the susceptor 52 of the vertical thin film growth apparatus shown in FIG.^-FiveThe pressure is reduced until the degree of vacuum is about Pa. Next, hydrogen gas as the dilution gas 56 is supplied from the gas supply system 58 at a flow rate of 2 L / min, and the pressure in the reaction furnace 50 is set to 90 kPa.
[0144]
Subsequently, a high frequency power of 20.0 kHz and 20 kW is applied to the coil 54 using an induction heating device while maintaining the flow rate of hydrogen gas, and the susceptor 52 is heated. In this step, the temperature of the substrate 21 is controlled to be constant at 1500 ° C.
[0145]
Next, while the hydrogen gas flow rate is kept constant at 2 L / min, propane gas, which is a carbon source gas, silane gas, which is a silicon source gas, and nitrogen gas, which is an n-type dopant, are supplied to the reactor 50. Supply from mouth.
[0146]
The flow rates of silane gas, propane gas, and nitrogen gas immediately after the start of the formation of the high-concentration n-type doped layer 22 are 3.0 mL / min, 0.6 mL / min, and 1.0 mL / min, respectively. In this case, the carbon / silicon ratio of the source gas is 0.6. Subsequently, the source gas and the nitrogen gas are kept flowing for at least 10 minutes while keeping these flow rate values constant.
[0147]
Thereafter, with the silane gas flow rate kept constant at 3.0 mL / min, the propane gas flow rate was continuously increased, and the nitrogen gas flow rate was continuously decreased. Min and 0.2 mL / min. This procedure resulted in a thickness of about 100 nm and a nitrogen concentration of about 1 × 10¹⁹atoms · cm^-3The n-type high-concentration n-type doped layer 22 is epitaxially grown on the substrate 21.
[0148]
Subsequently, the substrate temperature is raised so as to be constant at 1600 ° C.
[0149]
Here, the flow rates of silane gas, propane gas, and nitrogen gas are 3.0 mL / min, 3.0 mL / min, and 0.2 mL / min, respectively. The carbon / silicon ratio at this time is 3.
[0150]
By this procedure, the thickness is about 10 μm and the carrier density (nitrogen concentration) is about 1 × 10¹⁶ atoms · cm^-3The n-type SiC layer 23 is epitaxially grown on the high-concentration n-type doped layer 22.
[0151]
Next, a high-concentration p-type doped layer 27 and a p-type SiC layer 28 are sequentially formed on the n-type SiC layer 23 in the step shown in FIG. A specific procedure will be described below.
[0152]
First, after the supply of silane gas, propane gas, and nitrogen gas is stopped, the substrate temperature is lowered to 1500 ° C. and held at that temperature. Next, silane gas and propane gas are supplied to the reactor 50 at flow rates of 1.0 mL / min and 3.0 mL / min, respectively. At the same time, TMA gas, which is an Al source gas, is supplied into the reactor 50 at a flow rate of 1 mL / min.
[0153]
After holding in this state for about 10 minutes, the flow rate of silane gas is continuously increased and the flow rate of TMA gas is continuously decreased to reach 3.0 mL / min and 0.5 mL / min, respectively, after 5 minutes. Like that. During this time, the flow rate of propane gas is kept constant at 3.0 mL / min.
[0154]
By such a procedure, the high concentration p-type doped layer 27 is epitaxially grown.
[0155]
Subsequently, the substrate temperature is raised to 1600 ° C. and maintained at this temperature. In this state, the flow rates of propane gas, silane gas, and TMA gas are maintained at 3.0 mL / min, 3.0 mL / min, and 0.2 mL / min, respectively. By this procedure, the thickness is about 2.5 μm and the carrier concentration is about 1 × 10.¹⁸atoms · cm^-3The p-type SiC layer 28 is formed by epitaxial growth.
[0156]
Next, in the step shown in FIG. 5C, Ni / Al and Ni are deposited on the p-type SiC layer 28 and the back surface of the substrate 21 using a vacuum deposition apparatus, respectively, and then heated at 1000 ° C. Thus, the upper electrode 26 and the lower electrode 24 made of Ni / Al and Ni, respectively, are formed.
[0157]
Through the above steps, the pn diode of this embodiment is manufactured.
[0158]
In the manufacturing method of the pn diode of the present embodiment, since the high concentration n-type doped layer 22 is formed before the n-type SiC layer 23 is formed, a decrease in nitrogen concentration in the n-type SiC layer 23 is suppressed. Yes. Therefore, in the pn diode of the present embodiment, the resistance value between the substrate 21 and the n-type SiC layer 23 is reduced.
[0159]
In addition, in the pn diode of this embodiment, by providing the high-concentration p-type doped layer 27, the resistance value in the p-type SiC layer 28 is also reduced.
[0160]
In the step shown in FIG. 5B, when the high-concentration p-type doped layer 27 is formed, by increasing the carbon / silicon ratio of the source gas as compared with the formation of the p-type SiC layer, Increasing incorporation into the concentration p-type doped layer 27 is intended.
[0161]
Next, the current-voltage characteristics were examined for a conventional pn diode in which the high-concentration n-type doped layer 22 and the high-concentration p-type doped layer 27 are not provided and the pn diode of this embodiment. Here, as the conventional pn diode, the same element configuration as that of the pn diode of the present embodiment except for the high-concentration n-type doped layer 22 and the high-concentration p-type doped layer 27 was used.
[0162]
As a result of measuring the operating characteristics when a voltage was applied to both pn diodes, it was confirmed that the on-current for the same voltage was increased in the pn diode of this embodiment compared to the conventional pn diode (not shown). )
[0163]
Further, when the reverse breakdown voltage of both pn diodes was measured, it was confirmed that the reverse breakdown voltage was larger than that of the pn diode of this embodiment.
[0164]
As described above, the pn diode of the present embodiment is preferably used for various devices because it has improved withstand voltage and reduced power consumption. In particular, a pn diode can be designed to have a higher withstand voltage than a Schottky diode, and thus is used in a device that requires a withstand voltage.
[0165]
In the pn diode of this embodiment, the high-concentration n-type doped layer 22 and the high-concentration p-type doped layer 27 are provided. However, even when the high-concentration p-type doped layer 27 is not provided, the breakdown voltage and the current driving capability are improved. Improvements can be made.
[0166]
In addition, although the 4H-SiC substrate was used in the pn diode of this embodiment, a pn diode with high breakdown voltage and reduced power consumption can be manufactured even if a substrate made of other polytypes is used.
[0167]
(Fourth embodiment)
As a fourth embodiment of the present invention, a vertical structure MOSFET (hereinafter abbreviated as a vertical MOSFET) manufactured using the SiC substrate according to the first embodiment will be described below.
[0168]
6A to 6C are cross-sectional views illustrating the manufacturing process of the vertical MOSFET according to the fourth embodiment of the present invention.
[0169]
As shown in FIG. 6C, the vertical MOSFET of this embodiment is provided on a substrate 31 made of SiC containing an n-type impurity and on the main surface of the substrate 31, and has a higher concentration than that of the substrate 31. High-concentration impurity doped layer 32 made of SiC containing n-type impurities, epitaxial growth layer 33 made of SiC containing n-type impurities, and SiO provided on epitaxial growth layer 33₂ Of the gate oxide film 43, the gate electrode 46 provided on the gate oxide film 43, the p-type well 41 provided by ion implantation in a part of the epitaxial growth layer 33, and the gate electrode of the p-type well 41. N-type well 42 provided in regions located on both sides of 46, source electrode 44 made of Ni provided on n-type well 42, and drain electrode made of Ni provided on the back surface of substrate 31. 35.
[0170]
The substrate 31, the high concentration impurity doped layer 32, the epitaxial growth layer 33, and the n-type well each have a concentration of 1 × 10 5.¹⁸atoms · cm^-31 × 10¹⁹atoms · cm^-31 × 10¹⁶atoms · cm^-3And 1 × 10¹⁹atoms · cm^-3N-type impurities such as nitrogen are contained. The p-type well 41 has a concentration of 1 × 10.¹⁷atoms · cm^-3P-type impurities such as Al.
[0171]
Next, a method for manufacturing the vertical MOSFET of this embodiment will be described.
[0172]
First, in the step shown in FIG. 6A, a high concentration impurity doped layer 32 is formed on a substrate 31 made of SiC by a CVD method. As the substrate 1, an n-type (0001) plane SiC substrate (4H-SiC substrate) having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] direction is used. The dopant concentration of this substrate is about 1 × 10¹⁸atoms · cm^-3It is. A specific method is described below.
[0173]
First, the substrate 31 is set on the susceptor 52 of the vertical thin film growth apparatus shown in FIG.^-FiveThe pressure is reduced until the degree of vacuum is about Pa. Next, hydrogen gas is supplied from the gas supply system 58 at a flow rate of 2 L / min, and the pressure in the reaction furnace 50 is set to 90 kPa. The pressure in the reaction furnace 50 is controlled by adjusting the valve 60. In a state where the flow rate of hydrogen gas is maintained, high frequency power is applied to the coil 54 by using an induction heating device to heat the susceptor 52. During this step, the temperature of the substrate 1 is controlled to be constant at 1500 ° C.
[0174]
Next, the propane gas and silane gas of the source gas 55 and the nitrogen gas of the n-type dopant are supplied from the gas supply port of the reaction furnace 50 while keeping the hydrogen gas flow rate constant at 2 L / min. The source gas 55 and the dopant gas 57 are supplied after being diluted with hydrogen gas.
[0175]
The flow rates of silane gas, propane gas, and nitrogen gas immediately after the start of the formation of the high-concentration impurity doped layer 2 are 3.0 mL / min, 0.6 mL / min, and 1.0 mL / min, respectively. In this case, the carbon / silicon ratio of the source gas is 0.6. Then, in this state, the source gas and nitrogen gas continue to flow for at least 10 minutes.
[0176]
Thereafter, as shown in FIG. 2, the flow rate of propane gas is continuously increased and the flow rate of nitrogen gas (impurity dopant gas) is continuously decreased. After 5 minutes, 3.0 mL / min and 0. 2 mL / min. During this time, the flow rate of silane gas is kept constant at 3.0 mL / min.
[0177]
By this step, the thickness is about 100 nm and the dopant concentration is about 1 × 10.¹⁹atoms · cm^-3The n-type high concentration impurity doped layer 32 is formed on the substrate 31.
[0178]
Next, in the step shown in FIG. 6B, the epitaxial growth layer 33 is subsequently formed on the high-concentration impurity doped layer 32 by the CVD method. A specific method is described below.
[0179]
First, the temperature of the SiC substrate 1 on which the high-concentration impurity doped layer 2 is formed is raised so as to be constant at 1600 ° C. In this step, the flow rates of silane gas, propane gas, and nitrogen gas are 3.0 mL / min, 3.0 mL / min, and 0.2 mL / min, respectively.
[0180]
The carbon / silicon ratio at this time is 3, which is a higher value than the carbon / silicon ratio when the high concentration impurity doped layer 2 is formed. By this step, the thickness is about 10 μm and the carrier density is about 1 × 10.¹⁶atoms · cm^-3The n-type epitaxial growth layer is formed on the high concentration impurity doped layer 32.
[0181]
Next, in the step shown in FIG. 6C, after ion implantation of Al ions into the epitaxial growth layer 33, activation annealing is performed.
[0182]
Thereby, a part of the epitaxial growth layer 33 has a dopant concentration of 1 × 10 5.¹⁷atoms · cm^-3Thus, the p-type well 41 functions as a channel of the MOSFET.
[0183]
Next, after implanting nitrogen ions into the p-type well 41, activation annealing is performed.
[0184]
As a result, a part of the p-type well has a dopant concentration of 1 × 10 5.¹⁹atoms · cm^-3Thus, the n-type well 12 functions as a contact layer for the source of the MOSFET.
[0185]
Next, the substrate is thermally oxidized at about 1100 ° C. to form SiO on the substrate.₂A gate oxide film 43 having a thickness of 30 nm is formed.
[0186]
Thereafter, Ni is vapor-deposited on the upper surface of the n-type well 42 and the rear surface of the substrate 31 using an electron beam (EB) vapor deposition apparatus. Subsequently, by heating the substrate to 1000 ° C. in a heating furnace, the source electrode 44 that is an ohmic electrode is formed on the n-type well 42, and the drain electrode 35 that is an ohmic electrode is formed on the back surface of the substrate 31, respectively. Form.
[0187]
Subsequently, Al is evaporated on the gate oxide film 43 to form the gate electrode 46. The gate length is about 2 μm.
[0188]
With the above method, the vertical MOSFET of the present embodiment is manufactured.
[0189]
Next, in order to investigate the performance of the vertical MOSFET according to this embodiment, the relationship between the drain current and the gate voltage of the vertical MOSFET was measured. The results will be described below.
[0190]
First, for comparison, a vertical MOSFET was prepared in which a high-concentration impurity doped layer having a higher dopant concentration than the SiC substrate was not formed on the substrate. The element structure of the vertical MOSFET is the same as that of the vertical MOSFET of the present embodiment except for the high concentration impurity doped layer. This vertical MOSFET is hereinafter referred to as “conventional vertical MOSFET”.
[0191]
Next, the current-voltage characteristics of the present embodiment and the conventional vertical MOSFET were examined. Specifically, the withstand voltage and on-current of both vertical MOSFETs were measured and compared.
[0192]
As a result, it was confirmed that the vertical MOSFET of this embodiment has a withstand voltage nearly twice as high as that of a conventional vertical MOSFET and an on-current is also about 20% higher (not shown). .
[0193]
From this result, in the conventional vertical MOSFET, since the epitaxial growth layer which becomes the active region is formed on the substrate as described above, when a voltage is applied between the source and the drain, the depletion layer spreads from the pn junction. Is likely to reach the substrate and cause dielectric breakdown within the substrate. Further, it is considered that the on-current is reduced because a resistance component exists between the substrate 31 and the epitaxial growth layer 33.
[0194]
On the other hand, in the vertical MOSFET according to the present embodiment, the depletion layer extending from the pn junction remains at the high-concentration impurity doped layer 32 when a voltage is applied, so that the breakdown voltage is considered to be improved. Furthermore, it is considered that the high concentration impurity doped layer 32 is provided between the substrate 31 and the epitaxial growth layer 33, whereby the resistance component is reduced and the on-current is increased.
[0195]
From the above, it can be seen that a vertical MOSFET having a high breakdown voltage and a high gain can be produced by using a SiC substrate having a high impurity concentration doped layer having a higher dopant concentration than the substrate.
[0196]
In the vertical MOSFET of this embodiment, the p-type well is used as a channel. However, the substrate, the n-type doped layer, and the n-type well may be p-type, and the p-type well may be n-type.
[0197]
In the vertical MOSFET of this embodiment, the thickness of the epitaxial growth layer in the active region is 10 μm, but the thickness may be changed as necessary.
[0198]
Also in the vertical MOSFET of this embodiment, a substrate made of a polytype other than 4H—SiC can be used as in the second and third embodiments.
[0199]
In the present embodiment, an example of a vertical MOSFET has been described. However, the SiC substrate according to the first embodiment can exhibit the above-described effect even in an SiC semiconductor device having a vertical structure of any configuration. .
[0200]
【The invention's effect】
The method for manufacturing a semiconductor device according to the present invention includes an impurity having the same conductivity type as that of the SiC substrate between the SiC substrate and the epitaxially grown layer made of SiC, and a high concentration of impurities that are higher in concentration than the SiC substrate. A concentration impurity doped layer is formed. By this method, it is possible to realize a semiconductor device having a higher withstand voltage and a reduced power loss as compared with the prior art.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing an SiC substrate according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a flow rate of a source gas and an impurity dopant gas and a change in substrate temperature with time in a method for growing a SiC layer according to the present invention.
FIGS. 3A to 3C are cross-sectional views showing manufacturing steps of a Schottky diode according to a second embodiment of the present invention. FIGS.
FIG. 4 is a diagram showing current-voltage characteristics of a Schottky diode according to a second embodiment of the present invention and a conventional Schottky diode.
FIGS. 5A to 5C are cross-sectional views showing manufacturing steps of a pn diode according to a third embodiment of the present invention. FIGS.
FIGS. 6A to 6C are cross-sectional views showing a manufacturing process of a vertical MOSFET according to the fourth embodiment of the present invention. FIGS.
FIG. 7 is a diagram schematically showing a configuration of a general vertical thin film growth apparatus used for forming a SiC film.
FIG. 8 is a table showing a summary of impurity concentration and resistivity in an n-type doped layer of 4H—SiC.
FIG. 9 is a diagram showing a flow rate of a source gas and an impurity dopant gas and a change in substrate temperature with time in a conventional SiC layer growth method.
FIG. 10 is a cross-sectional view showing a conventional Schottky diode.
[Explanation of symbols]
1,11,21,31 substrate
2,12,32 Highly doped layer
3,13,33 Epitaxial growth layer
14 Ohmic electrode
15 Guard ring
16 Schottky electrode
22 High-concentration n-type doped layer
23 n-type SiC layer
24 Lower electrode
26 Upper electrode
27 High-concentration p-type doped layer
28 p-type SiC layer
35 Drain electrode
41 p-type well
42 n-type well
43 Gate oxide film
44 Source electrode
46 Gate electrode
50 reactor
51 substrates
52 Susceptor
53 Support shaft
54 coils
55 Source gas
56 Dilution gas
57 Dopant gas
58 Gas supply system
59 Gas exhaust system
60 valves
61 Exhaust pipe

Claims (23)

A semiconductor substrate containing an impurity of a first conductivity type;
The provided semiconductor substrate, a first high concentration impurity doped layer made of a semiconductor which is formed by the epitaxial growth including a first conductivity type impurity at a higher concentration than the semiconductor substrate, the first high concentration impurity doped A first semiconductor layer that is provided on the layer and includes a first conductivity type impurity at a lower concentration than the first high-concentration impurity doped layer;
In operation, a semiconductor device in which carriers travel through the semiconductor substrate , the first high-concentration impurity doped layer, and the first semiconductor layer . The semiconductor device according to claim 1,
The semiconductor device is characterized in that the semiconductor substrate is made of one material selected from Si, SiC, GaN, GaAs and InP. The semiconductor device according to claim 2,
The semiconductor device , the first high-concentration impurity doped layer, and the first semiconductor layer are all made of SiC. In the semiconductor device according to any one of claims 1 to 3 ,
A semiconductor device, wherein a concentration of impurities contained in the first high-concentration impurity doped layer is 1 × 10 ¹⁸ atoms · cm ^{−3 to} 1 × 10 ²⁰ atoms · cm ⁻³ . In the semiconductor device according to any one of claims 1 to 4 ,
The thickness of the said 1st high concentration impurity dope layer is 10 nm or more and 1000 nm or less, The semiconductor device characterized by the above-mentioned. In the semiconductor device according to any one of claims 1 to 5 ,
On SL impurity contained in the first high concentration impurity doped layer, a semiconductor device which is characterized in that which has been introduced by in-situ doping. In the semiconductor device according to any one of claims 1 to 6 ,
The semiconductor device, wherein the first semiconductor layer is formed by epitaxial growth. In the semiconductor device according to any one of claims 1 to 7 ,
Provided on the first semiconductor layer, and the Schottky electrode in contact the first semiconductor layer and the Schottky,
The provided semiconductor substrate on the back surface, the semiconductor device further comprising a ohmic electrode in contact the semiconductor substrate and ohmic. The semiconductor device according to claim 8 ,
A semiconductor device, further comprising a guard ring made of an insulator provided on the first semiconductor layer and surrounding the Schottky electrode. In the semiconductor device according to any one of claims 1 to 7 ,
Provided above the first semiconductor layer, a second semiconductor layer containing an impurity of the second conductivity type,
An upper electrode provided on the second semiconductor layer ;
A lower electrode provided on the back surface of the semiconductor substrate ,
A semiconductor device which functions as a pn diode. The semiconductor device according to claim 10 .
A second high-concentration impurity doped layer which is provided between the first semiconductor layer and the second semiconductor layer and contains a second conductivity type impurity at a higher concentration than the second semiconductor layer; A semiconductor device characterized by that. The semiconductor device according to claim 10 or 11 ,
The semiconductor device, wherein the second semiconductor layer is made of epitaxially grown SiC. In the semiconductor device according to any one of claims 1 to 7 ,
A first well which is provided by implanting impurity ions of the second conductivity type into a part of the first semiconductor layer and functions as a channel;
A gate insulating film provided on the first semiconductor layer and the first well;
A gate electrode provided on the gate insulating film;
The second well provided by implanting impurity ions of the first conductivity type in regions located on both sides of the gate electrode in the first well;
A first electrode provided on the second well;
A second electrode provided on the back surface of the semiconductor substrate ,
A semiconductor device which functions as a MISFET having a vertical structure. The first source gas, the second source gas, and the impurity dopant gas are supplied to the reaction furnace of the thin film growth apparatus, so that the first conductivity type impurity is more concentrated on the semiconductor substrate than the semiconductor substrate . A step (a) of epitaxially growing a first high-concentration impurity-doped layer included at a position where a constituent element contained in the source gas should be ;
Epitaxially growing a first semiconductor layer comprising the above step (a) the first of the first conductivity type impurity at a low concentration than the first high concentration impurity doped layer on the high concentration impurity doped layer after the (B)
At the start of the step (a), the supply amount of the first source gas is made smaller than that at the start of the step (b), and the ratio of the supply amounts of the first source gas and the second source gas is compared. The method for manufacturing a semiconductor device is characterized in that the supply amount of the impurity dopant gas is increased . In the manufacturing method of the semiconductor device according to claim 14 ,
A method of manufacturing a semiconductor device, wherein the supply amount of the impurity dopant gas is larger at the start of the step (a) than at the start of the step (b). In the manufacturing method of the semiconductor device according to claim 14 or 15 ,
A method of manufacturing a semiconductor device, characterized in that the substrate temperature is lowered at the start of the step (a) as compared to the start of the step (b). In the manufacturing method of the semiconductor device according to any one of claims 14 to 16 ,
The method (a) further includes a step (a1) of continuously reducing the supply amount of the impurity dopant gas. In the manufacturing method of the semiconductor device as described in any one of Claims 14-17 ,
A method of manufacturing a semiconductor device, wherein the semiconductor substrate is made of SiC. In the manufacturing method of the semiconductor device according to claim 18 ,
The method for manufacturing a semiconductor device, wherein both the first high-concentration impurity doped layer and the first semiconductor layer are made of SiC. In the manufacturing method of the semiconductor device as described in any one of Claims 14-19 ,
The semiconductor device manufacturing method, wherein the impurity dopant gas is nitrogen or phosphine, and the first source gas is a carbon source gas. In the manufacturing method of the semiconductor device according to claim 20 ,
The method of manufacturing a semiconductor device, wherein the first source gas is one selected from propane, methane, acetylene, ethane, ethylene, propylene, and butane. In the manufacturing method of the semiconductor device as described in any one of Claims 14-19 ,
The impurity dopant gas is trimethylaluminum gas or diborane,
The method of manufacturing a semiconductor device, wherein the first source gas is a source gas of silicon. In the manufacturing method of the semiconductor device according to claim 22 ,
The method of manufacturing a semiconductor device, wherein the first source gas is silane gas or disilane gas.

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